Generate digital clocks for systems with RF circuits

Abstract

The present invention provides an integrated circuit, comprising a receiver radio frequency circuit, a transmitter radio frequency circuit, a carrier signal generator and a clock generator. The carrier signal generator comprises an oscillator. The oscillator is used to provide a carrier signal for the receiver radio frequency circuit or the transmitter radio frequency circuit. The clock generator is used to generate a clock signal based on a signal output by the oscillator. The clock generator generates a clock signal based on the same oscillator as the carrier signal, and the frequency of the clock signal is generated from the frequency of the radio frequency circuit, so that interference with the RF circuit will only occur at specific frequencies. These interferences can be more easily compensated, or can be arranged to have a frequency far enough away from the useful part of the RF signal so that it can be more easily filtered out.

Description

Technical Field

[0001] The present invention relates to a circuit, which is used in any one of a transceiver, a receiver and a transmitter. Background Art

[0002] The rapid spread of modern cellular communication systems around the world is driven primarily by three factors: standardization, cost, and performance. The availability of common communication standards promulgated by organizations such as 3GPP enables manufacturers to produce a single product for the global market. The low cost of cellular communications is primarily due to the high level of functional integration achievable with modern microchip technology and the large economies of scale that the size of the global market brings to manufacturers. The high performance of cellular communications has been achieved by exploiting the functional capabilities of modern semiconductor technology.

[0003] Functional integration in radio transceivers has increased, resulting in the analog and digital functions of the radio transceivers being placed close to each other. It is well known in the prior art that the reduction in physical isolation between radio circuit components can cause increased mutual self-interference. Typically, digital clocks are composed of a series of rectangular pulses and are rich in harmonics. Therefore, at the harmonic frequencies of the digital clock, digital cable components that utilize the digital clock can cause radio frequency (RF) interference when integrated. Typically, a transceiver is most susceptible to this type of interference when it attempts to receive a low power signal at an RF frequency that is at or near a harmonic of any digital clock used in the transceiver.

[0004] Modern cellular radio transceivers are required to operate in multiple frequency bands. Modern transceivers must also meet the expected performance levels required by standards such as 3GPP, so modern transceivers must have excellent digital signal processing capabilities. In addition, since radio transceivers are expensive and time consuming to develop in advanced semiconductor manufacturing processes, it is expected that radio transceivers are flexible enough to operate in some frequency bands that may be designated as cellular bands by standardization authorities in the future.

[0005] US 5,926,514 discloses changing a clock signal used by a microcontroller unit in a radio transceiver in response to changes in the operating frequency of the radio transceiver.

[0006] US 7,103,342 discloses varying the clock signal used by a microcontroller unit in a radio transceiver in order to minimize interference at a selected operating frequency of the radio transceiver.

[0007] US 6,898,420 discloses switching the clock signal used by a microcontroller between two possible frequencies.

[0008] US 7,676,192 discloses a technique for changing the operating frequency of a device and the signal frequency of a co-located signal source, thereby minimizing interference introduced on the wireless interface of the device.

[0009] There remains a need for techniques that can be used to address the effects of clock harmonic interference in radio transceivers. Summary of the invention

[0010] It is an object of the present invention to provide an alternative circuit for a radio system, in particular a transceiver for a radio system, having an enhanced immunity to clock harmonic interference.

[0011] According to a first aspect of the present invention, there is provided a circuit, which is used for any one of a transceiver, a transmitter and a receiver, and has an RF circuit, a digital circuit, a carrier signal generator and a clock generator, the clock generator being used to generate a digital clock for timing at least some of the digital circuits, the RF circuit being susceptible to harmonics generated by timing the digital circuits, the carrier signal generator being coupled to provide a carrier signal to the RF circuit, and the clock generator being arranged to obtain a frequency of the digital clock based on a frequency generated by dividing down the frequency of the carrier signal, so that interference with the RF circuit occurs at a specific frequency, which is a harmonic of the carrier signal.

[0012] Since any interference from harmonics of the digital clock is at a specific frequency, which is a harmonic of the carrier, these interferences can be more easily compensated, or can be arranged to have a frequency far enough away from the useful part of the RF signal so that it can be more easily filtered out. For example, in a receiver or transmitter chain, the digital circuit may include an ADC or DAC or digital processing circuit. The digital reference may include, for example, a discrete time timing analog. For example, an example of a transceiver is used in communication applications, but a one-way radio application includes a GPS receiver.

[0013] Embodiments of the invention may have any additional features added, or any additional features not claimed. Some such additional features are set out in the dependent claims and are described in detail below.

[0014] On the other hand, a corresponding method of generating a digital clock is provided, wherein the digital clock is used to time a digital circuit associated with any one of a transceiver, a transmitter, and a receiver, and the method has the following steps: generating a carrier signal for an RF circuit, wherein the RF circuit is susceptible to harmonics generated by clocking the digital circuit; and obtaining the frequency of the digital clock based on a frequency generated by dividing down the frequency of the carrier signal, so that interference with the RF circuit occurs at a specific frequency, wherein the specific frequency is a harmonic of the carrier signal.

[0015] Embodiments of the present invention can provide novel implementations of radio communication systems. Its advantages are particularly useful for communication systems involving simultaneous transmission and reception of RF signals.

[0016] Some additional features are as follows.

[0017] A clock generator may have one or more programmable dividers to generate a digital clock. Figure 3 or Figure 4 or Figure 5 , which allows the design and operation of digital circuits to be more flexible and can be tuned to reduce actual interference.

[0018] The clock generator may have two or more oscillators to generate carrier signals at different carrier frequencies, and the clock generator may have a selector to select which of the carrier frequencies is used as a source for generating a digital clock. Figure 5 , which makes the selection of digital clock frequency more flexible and can therefore improve, for example, the trade-off between maximum output power and receiver noise. In some cases, oscillators can be used for reception and transmission separately, or can be used for multiple protocols or standards for the reception process or the transmission process. The digital circuit timed by the digital clock can include any one or more of the following items: an analog-to-digital conversion circuit for the received signal, a digital-to-analog conversion circuit for the transmitted signal, a digital processing circuit for processing the received signal or the transmitted signal, and a digital part of the clock generator.

[0019] The circuit may have a fallback oscillator for generating a fallback reference frequency, and the clock generator may have a fallback selector to select the fallback reference frequency as a source for generating a digital clock when the carrier frequency is not suitable. Figures 3 to 6 , which can help improve reliability, which is especially useful at higher frequencies such as 11GHz when reliable carrier signals are difficult to obtain. It also allows digital circuits to be more independent, which is useful, for example, in the case of an operational layer that can run software without considering the clock rate.

[0020] The fallback selector may have a monitor for monitoring the stability of the carrier signal, and the fallback selector may be operable to select the fallback reference frequency based on the output of the monitor. Figure 6 , Figure 7 and Figure 8 , which can further improve the reliability of the clock generator.

[0021] The clock generator may have a controller for selecting a frequency change of the digital clock based on the quality of the digitally processed output of the received signal or the transmitted signal clocked by the digital clock and the disturbance caused by the timing. Figure 2 , Fig.12 and Fig.13 , which can help achieve a better balance between the increased performance of fast digital processing and the increased interference of fast digital clocks.

[0022] The controller may be arranged to estimate the digital clock rate required for a corresponding type of digital receiver processing in order to achieve a predetermined minimum signal-to-noise ratio for the received signal, and to determine whether interference caused by the estimated digital clock rate is within an acceptable threshold, which will serve as a basis for selecting a frequency change of the digital clock. This is useful, for example, where downstream processing depends on a given minimum noise. Consider the case where error-free decoding of high-order modulation requires a specific SINAD from the transceiver, and reassigning the SINAD contribution of clock-related interference to be relatively high in order to increase processing speed.

[0023] The circuit may have a digital compensation circuit to digitally compensate at least some of the digital processing circuits clocked by the digital clock based on changes in the frequency of the digital clock. Fig.15 and Fig.16 , which can help design digital processing to be more independent of changes in clock rate. In some cases, the digital compensation circuit can include a digital resampling circuit to perform resampling at a rate that is inversely proportional to the frequency change of the digital clock. This allows the clock rate to be decoupled from the sampling rate so that they can be optimized separately, which means, for example, that processing requirements can be reduced by returning to the optimal sampling rate.

[0024] The circuit may be part of an integrated circuit. This may reduce costs through more integration, but interference will be more severe. The circuit or integrated circuit may be part of a mobile device such as a mobile phone or a handheld computing device.

[0025] The method may have additional steps corresponding to the additional features set forth above. There may be steps of programming one or more programmable frequency dividers to change the frequency of the digital clock. The method may have steps of generating two or more carrier signals at different carrier frequencies and selecting which of the carrier frequencies to use as a source for generating the digital clock. There may be steps of estimating the digital clock frequency required for processing by a corresponding type of digital receiver to achieve a predetermined minimum signal-to-noise ratio for the received signal; determining whether interference caused by the estimated digital clock frequency is within an acceptable threshold range; and selecting a frequency change of the digital clock based on this determination. There may be steps of resampling a digital signal used by a digital circuit at a rate that is inversely proportional to the frequency change of the digital clock. Another step may be compensating for interference to the RF circuit caused by harmonics generated by clocking the digital circuit.

[0026] The present invention provides an integrated circuit, comprising a receiver radio frequency circuit, a transmitter radio frequency circuit, a carrier signal generator and a clock generator. The carrier signal generator comprises an oscillator. The oscillator is used to provide a carrier signal for the receiver radio frequency circuit or the transmitter radio frequency circuit. The clock generator is used to generate a clock signal based on a signal output by the oscillator. The clock generator generates a clock signal based on the same oscillator as the carrier signal, and the frequency of the clock signal is generated from the frequency of the radio frequency circuit, so that interference with the RF circuit will only occur at specific frequencies. These interferences can be more easily compensated, or can be arranged to have a frequency far enough away from the useful part of the RF signal so that it can be more easily filtered out.

[0027] Any additional features may be combined together and in combination with any aspect. Other advantages, especially advantages over other prior art, will be readily apparent to those skilled in the art. Various changes and modifications may be made without departing from the claims of the present invention. Therefore, it should be clearly understood that the form of the present invention is merely illustrative and is not intended to limit the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] How the invention may be put into practice will now be described by way of example with reference to the accompanying drawings, in which:

[0029] FIG. 1 shows a schematic diagram corresponding to a known layout,

[0030] Figure 2 shows a schematic diagram of a transceiver with a circuit according to a first embodiment,

[0031] Figure 3 , Figure 4 and Figure 5Schematic diagrams showing clock generators and other parts of other embodiments,

[0032] Figure 6 shows a schematic diagram of a fallback control part used in some embodiments,

[0033] Figure 7 A diagram showing the timing of a clock signal,

[0034] Figure 8 shows the steps for entering fallback mode in some embodiments,

[0035] Fig. 9 and Fig.10 shows steps for leaving fallback mode in some embodiments,

[0036] Fig.11 The steps of controlling a programmable frequency divider according to one embodiment are shown.

[0037] Fig.12 A diagram showing the spectrum of the received signal at different times,

[0038] Fig.13 A diagram showing the spectrum of the transmitted signal,

[0039] Fig.14 A graph showing the ADC noise spectrum for two different sampling frequencies,

[0040] Fig.15 A schematic diagram showing a circuit for resampling after the ADC and before the DAC, and

[0041] Fig.16 The steps of changing the resampling rate according to one embodiment are shown. DETAILED DESCRIPTION

[0042] The present invention will be described in conjunction with specific embodiments and with reference to specific drawings, but the present invention is not limited thereto, but only by the claims. The drawings described are merely illustrative and non-restrictive. In the drawings, for illustrative purposes, the sizes of some elements may be exaggerated and not drawn to scale. Where the term "comprising" is used in this specification and claims, other elements or steps are not excluded. Where an indefinite or definite article is used when referring to a singular noun, for example, "a" or "the", this includes the plural form of the noun unless otherwise stated.

[0043] The term "comprising" used in the claims should not be understood as being limited to the components listed thereafter, and the term does not exclude other elements or steps. Therefore, the scope of the expression "the device comprises components A and B" should not be limited to the device consisting of only components A and B. This means that with respect to the present invention, the relevant components of the device are only A and B.

[0044] In addition, the terms "first", "second", "third", etc. in the specification and claims are used to distinguish similar elements and are not necessarily used to describe a sequential or chronological order. It should be understood that the terms so used are interchangeable under appropriate circumstances, and the embodiments of the invention described in this text are capable of operating in other sequences than those described or illustrated in this text.

[0045] Furthermore, the terms "top", "bottom", "above", "below", etc. in the specification and claims are used for descriptive purposes and not necessarily for describing relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances, and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.

[0046] It should be noted that the term "comprising" used in the claims should not be understood as being limited to the components listed thereafter, and the term does not exclude other elements or steps. Therefore, it should be understood as explicitly stating the existence of the features, wholes, steps or components involved, but does not exclude the existence or addition of one or more other features, wholes, steps or components or combinations of the above. Therefore, the scope of the expression "the device comprises components A and B" should not be limited to the device consisting only of components A and B. This means that with respect to the present invention, the relevant components of the device are only A and B.

[0047] References to "one embodiment" or "an embodiment" throughout this specification mean that the specific features, structures, or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily all refer to the same embodiment, but may refer to the same embodiment. In addition, it will be readily apparent to those skilled in the art from this disclosure that these features, structures, or characteristics may be combined in any appropriate manner in one or more embodiments.

[0048] Similarly, it should be understood that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof in order to make the invention flow and to aid in the understanding of one or more of the multiple inventive aspects. However, this approach to the invention should not be interpreted as reflecting an intent that the claimed invention requires more features than those expressly recited in each claim. In fact, as reflected in the following claims, inventive aspects lie in less than all the features of a single preceding embodiment. Therefore, the claims that follow the detailed description are hereby expressly incorporated into this detailed description, with each claim independently serving as a separate embodiment of the invention.

[0049] In addition, those skilled in the art will appreciate that, although some embodiments described in this document include some features but do not include other features included in other embodiments, the combination of features of different embodiments is intended to fall within the scope of the present invention and form different embodiments. For example, in the appended claims, any claimed embodiment can be used in any combination.

[0050] In the description provided in this text, many specific details are set forth. However, it should be understood that multiple embodiments of the present invention can be practiced without these specific details. In other cases, well-known methods, structures, and techniques are not shown in detail to avoid obscuring the understanding of this description.

[0051] The present invention will now be described by a specific description of several embodiments of the present invention. Obviously, other embodiments of the present invention can be configured according to the knowledge of those skilled in the art without departing from the technical teachings of the present invention, and the present invention is only limited by the terms of the attached claims.

[0052] Introduction, Figure 1, known layout

[0053] By way of introduction to a number of embodiments, a layout corresponding to a known system will be described with reference to FIG. 1 . In the prior art, a typical transceiver includes components for generating a desired RF signal by generating a carrier signal at a selected radio frequency using one or more VCOs and one or more PLLs. The generated carrier signal is used in the following processes: converting a baseband signal to an RF signal to be transmitted and converting a received RF signal to a corresponding baseband signal. FIG. 1 illustrates a frequency generation subsystem 100 of a typical modern wireless communication transceiver. A reference clock generator 110 delivers a reference clock signal to a VCO frequency control section 180, which includes a hybrid phase-locked loop (PLL) circuit 120 and a voltage-controlled oscillator (VCO) 130. Connection 125 provides the necessary feedback signal to lock the loop. Signal 135 is an output signal from VCO 130, and signal 135 oscillates at a selected VCO frequency. A divider network 140 generates an output signal 145, and signal 145 oscillates at a frequency that is a divisor of the frequency of signal 135. Signal 145 is often referred to as a carrier signal or LO (local oscillator) signal and is often used by a radio transceiver for up-conversion and down-conversion processes. A divider network 150 is used to generate a plurality of output signals 151, 152, and 153. Signals 151, 152, and 153 oscillate at a frequency that is one or more factors of the frequency of input signal 145. A microcontroller 160 often controls and programs each of PLL 120, VCO 130, and divider networks 140 and 150.

[0054] Figure 2 , a transceiver having a circuit according to a first embodiment

[0055] Some embodiments of the present invention help enable a radio transceiver to operate in the presence of harmonic interference from one or more clock signals without degrading performance when the clock harmonic interference is not present. In the presence of such interference, the radio transceiver can be robust enough to maintain a desired performance level. Figure 2 A schematic diagram of a transceiver with circuitry according to a first embodiment is shown. A receive antenna 71 is coupled to a receiver RF circuit 70, which feeds a receiver baseband circuit 60. This outputs an analog signal, which is converted to digital form by an ADC 260. The digital signal is processed by a digital processor 30, which is implemented in a variety of ways to perform a variety of conventional signal processing tasks on the received signal.

[0056] The carrier signal generating section 80 feeds the local carrier signal 47 to the receiver RF circuit 70. The carrier signal generating section 80 also generates the local carrier signal 46 for the transmitter side of the transceiver. A selected one of the carrier signals is also sent to the clock generator section 90 to generate one or more digital clocks, which are obtained by dividing down the selected carrier frequency. In the example shown, the digital clocks obtained in this way are used for analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and digital processors. In some cases, other digital circuits in the radio transceiver can be clocked in this way by one or other carrier signals from the transmitter or receiver carrier signal. Generating digital clocks in this way (respectively 152, 153 and 151) ensures that any clock harmonic interference that occurs will be located at the same frequency as the selected carrier signal. Interference occurring at this location is similar to a DC offset in a baseband signal, for which many compensation techniques are known in the prior art. By extension, the method can also be used for clock harmonic interference at specific frequencies that are benign from a radio perspective, for example due to sequential location of filtering attenuation in the system and / or due to more relaxed spectrum restrictions, without loss of generality.

[0057] There is also a reference clock section 110 for generating a reference clock to provide a stable frequency reference source 011 for carrier generation and to provide a backup signal 111 for the clock generator 90. The transmitter side includes a DAC 250, a transmitter baseband circuit 50, and a transmitter RF circuit 40, which uses a transmitter local carrier 46 and feeds a transmit antenna 72. Figures 3 to 5 An embodiment of the carrier signal generating section 80 and the clock generator section 90 will be described.

[0058] Figure 3 , a clock generator and other parts according to one embodiment

[0059] Figure 3 A more detailed illustration of the Figure 2 This portion 200 of the circuit has a reference clock 110, a carrier generator 80, and a clock generator 90 and some digital parts, such as ADC and DAC.

[0060] The reference clock generator 110 delivers the reference clock signal to the input of the VCO1 frequency control section 180, which can be implemented by the PLL circuit 120 and the VCO 130 as shown in FIG1 , wherein the PLL circuit 120 and the VCO 130 can be implemented by circuits known in the art. The VCO1 divider network 140 performs frequency division on the output signal from the VCO frequency control section 180 to generate a local carrier signal 145, which oscillates at a certain frequency, which is a frequency factor of the signal 135. The carrier signal 145 can be generated in the same manner as shown in FIG1 , and is a signal used to generate a receiver or transmitter carrier signal.

[0061] LO divider units 210, 220 and 230 are attached components of LO distributor network 150, where intermediate signals 205 and 215 are available, as shown here. Carrier signal 145 is divided using LO1 divider 210, thereby generating intermediate signal 205. Signal 205 is further divided using LO2 divider 220, thereby generating intermediate signal 215. Finally, signal 215 is divided using LO3 divider 230, thereby generating final digital clock signals 151, 152 and 153, which do not need to be of the same frequency, but are all derived from the carrier. In this figure, 153 is an example of a digital clock signal sent to a digital circuit associated with a receiver, transmitter or transceiver. Examples of such digital circuits are DAC 250 and ADC 260. Another example of a digital clock is signal 152, which is a digital clock signal for ADC 260. Digital clock signal 151 is sent to fallback control unit 240. The fallback control unit 240 also receives the signal 111 from the reference clock generator. Signal 241 is the output of the fallback control unit 240, which is used as a clock signal for the microcontroller 160. Figures 6 to 10 1 and 2 to describe the implementation details of the fallback control section. The microcontroller 160 is used to control and code other parts, such as the VCO1 frequency control section 180, the VCO1 divider network 140, and the divider networks 210, 220, and 230. The microcontroller 160 uses a control bus 161 to control the VCO frequency control unit 180, and uses a control bus 162 to control the LO divider units 210, 220, and 230.

[0062] Signal 151 is used as a clock for microprocessor 160 and other digital logic within the transceiver, signal 152 is used as a sampling clock for ADC 260, and signal 153 is used as a sampling clock for DAC 250. Signals 151, 152, and 153 are all derived from signal 145, which is also used by the transceiver as an RF carrier signal, so that all factors implemented in blocks 140, 210, 220, and 230 are independent integers rather than fractions, so that any clock harmonic interference caused by signals 151, 152, or 153 will be considered to be below the RF carrier frequency. This relationship between clock harmonic interference and the carrier signal frequency remains even if the frequency of the carrier signal changes. Therefore, it is possible to change the carrier signal frequency and still compensate for clock carrier interference in the same manner.

[0063] Figure 4 , another embodiment

[0064] Figure 4 Shows something like Figure 3 The circuit portion 300 is shown in FIG. Figure 3 362. An expansion of the clock generation system shown is shown. DAC 250 now uses signal 353 as a clock signal. Signal 353 is generated by applying signal 145 to a set of LO dividers 310, 320 and 330. Intermediate signals 305 and 315 are also shown. LO dividers 310, 320 and 330 are controlled by microcontroller 160 using control bus 362. Signal 353 is generated using a set of LO3 dividers (310, 320 and 330) that function the same as the set of LO2 dividers (210, 220 and 230), but can be independently programmed by microcontroller 160. This permits signals 152 and 353 to be programmed to have different frequencies and to be changed independently, but both are derived from signal 145.

[0065] Figure 5 , another embodiment with selectable carrier

[0066] Figure 5 Shows something like Figure 4 The circuit portion 400 is shown in FIG. Figure 41 and 1 . An extension of the clock generation system shown in FIG. 1 is shown. Switch 410 is used to connect the VCO1 divider network 140 or the VCO2 divider network 440 to the LO1 divider 210. Switch 410 is also used to connect the VCO1 divider network 140 or the VCO2 divider network to the LO2 divider 310. The LO dividers 210 and 310 are driven by signals 415 and 445 from switch 410, respectively. The VCO2 divider network 440 is fed by a VCO2 frequency control unit 480, which is controlled by the microcontroller 160 using a control bus 461. In another variant (not shown), the digital clock signal 151 can also be obtained from either of the intermediate signals 205 and 215.

[0067] Figures 6 to 10 , implementation of fallback control

[0068] Figure 6 A portion 500 of a circuit is shown for implementing the fallback control unit 240. The fallback logic subunit 520 uses the states of the input signals 111 and 151 to determine how to control the switch subunit 510. The fallback switch subunit 510 can be used to connect the output signal 241 to the input signal 111 or to the input signal 151.

[0069] Figure 7 A graph 600 is shown, which illustrates the waveforms of signals 151, 111, and 241 over time during typical operation of the fallback control unit 240. As a result of reprogramming the VCO frequency control 170, the clock signal 151 may enter an unknown state 630. In this case, the fallback control unit 240 is used to ensure that the digital clock signal 241 remains in a known state so that the microcontroller 160 can continue to operate correctly. Prior to time 610, the signal 151 and the fallback output signal 241 are the same. At time 610, the signal 151 enters an undefined state 630 until time 620. After time 610, the fallback control subunit 520 can no longer detect or count clock cycles of the signal 151. If this condition lasts longer than a preset amount of time (time interval 640) of reference block 111, the fallback control subunit 510 will connect the fallback output signal 241 to the signal 111.

[0070] Figure 8A sequence of steps 700 is shown to illustrate a typical decision process performed in the fallback control subunit 520 when determining whether to enter fallback mode. If the VCO 130 is retuned, the signal 135 and all derived signals will become unstable until the signal 135 at the output of the VCO 130 returns to a stable state. As shown in steps 720, 730 and 770, the fallback logic subunit 520 monitors the stability and presence of the clock 151 during each cycle of the reference clock 111 by detecting at least one edge of the input clock 151. After starting at terminal 710, the fallback counter is cleared in step 770. The process is paused at step 720, where the subunit 520 waits until it detects a clock edge of the reference clock signal 111. In the next step, the subunit 520 determines whether it has detected a clock edge of the signal 151. If the subunit detects a clock edge, the fallback counter is cleared in step 770 and the subunit 520 returns to step 720. In the time period 630, when the signal 151 enters the unknown state, the fallback logic subunit 520 will perform steps 740 and 750. If a clock edge of the signal 151 is not detected, the fallback counter is incremented in step 740. In step 750, the value of the fallback counter is compared to a preset threshold. If the value of the fallback counter is below the preset threshold, the subunit 520 returns to step 720, otherwise, it enters the fallback mode in step 760. If the clock signal 151 is not detected for the preset amount of time 640 of the reference clock 111, the fallback logic subunit 520 configures the fallback switch subunit 510 to connect the input signal 111 to the output signal 241.

[0071] Fig. 9 A sequence of steps 800 is shown illustrating a typical decision process performed in the fallback control subunit 520 when determining whether to leave the fallback mode. In a first embodiment, after starting at the terminal step 800, the fallback counter is cleared in step 770. At time 620, which occurs at the end of the time period 630, the signal 151 returns to a stable state, and the fallback control subunit 520 may reconfigure the fallback switch subunit 510 to connect the input signal 151 to the output signal 241. Steps 820, 830, and 840 combine to count the reference clock signal and compare the count result to a preset threshold. When the preset threshold is exceeded, the subunit 520 instructs the subunit 510 to reconnect the signal 241 to the signal 151 in step 850. Therefore, the fallback control subunit 510 performs this reconfiguration after the preset amount of time of the reference clock 111 has passed, which is due to entering the fallback mode in step 760.

[0072] Fig.10 An alternative sequence of steps is shown. After starting at terminal step 815, subunit 520 determines in step 825 whether signal 151 is stable, and if the determination is positive, the fallback control unit leaves the fallback mode in step 835. In an alternative variation, fallback logic subunit 520 monitors the stability and presence of input clock 151 by detecting at least one edge of clock 151 during a predefined time interval.

[0073] Fig.11 , select the clock frequency

[0074] Fig.11 A sequence of steps 900 is shown, illustrating an example of a portion of a program executed in the microprocessor 160 to select the clock frequencies of the ADC 260, the DAC 250, and the digital clock 151. The microprocessor 160 determines how to code the dividers 210, 220, and 230 and the dividers 310, 320, and 330 to obtain clock frequencies of the ADC sampling clock 152, the DAC sampling clock 353, and the digital clock 151 that are at or above the corresponding target frequencies. The setting of the target frequencies may use criteria including, but not limited to, satisfying the Nyquist first sampling theorem, power minimization, and maximization of oversampling noise reduction gain.

[0075] After starting at terminal step 910, step 920 determines the current frequency of LO signal 145. In step 930, the target clock frequencies of ADC 152, DAC 353, and digital clock 151 are read. In step 940, the divider setting Nadc is selected to satisfy the constraints in step 940, i.e., Nadc can be implemented as a factor from the combination of dividers 210, 220, and 230. In step 950, the divider setting Ndac is selected to satisfy the constraints in step 950, i.e., Ndac can be implemented as a factor from the combination of dividers 310, 320, and 330. In step 960, the divider setting Ndig is selected to satisfy the constraints in step 960, i.e., Ndig can be implemented as a factor from the combination of dividers 210, 220, and 230.

[0076] In some cases, the microcontroller 160 takes into account link layer parameters, such as data rate, modulation order, channel coding strength, etc., to optimize the clock frequencies of the ADC sampling clock 152, the DAC sampling clock 353, and the digital clock 151. The generation of the clocks can take into account the required input SNR according to the link layer control parameters. For example, the following situation can be considered, where error-free decoding of high-order modulation requires a specific SINAD from the transceiver, and the SINAD contribution of clock-related interference is re-specified to be relatively high in order to increase processing speed.

[0077] Fig.12 , select the clock frequency to reduce interference

[0078] Fig.12 The spectrum of the received signal at two different moments is shown and three possible clock harmonic interference signals are shown. In a receiver, there are three options {clock1, clock2, clock3} available for selecting the digital clock frequency at time 0. Each of the clock frequency options generates an interference signal in a set of corresponding interference signals A, B and C. At time 0, only one of these possible interference signals is located in the desired signal frequency band, that is, interference signal B. Therefore, at time 0, one of the digital clock frequencies clock1 or clock3 can be selected without generating an interference signal in the desired signal frequency band. At time 1, the frequency position of the desired signal changes so that it now overlaps with interference signal A. Therefore, at time 1, one of the clock frequencies clock2 or clock3 is selected.

[0079] Fig.13 , the spectrum of the transmitted signal

[0080] Fig.13 The spectrum of the transmitted signal at two different times and two possible clock harmonic interference signals are shown. In a transmitter, there are two options {clock1, clock2} that can be used to select the digital clock frequency. Each of the two clocks has a corresponding interference signal {X, Y}, which is generated as a by-product of the clock generation process. In the figure, only the interference signal Y is within the licensed bandwidth. A typical cellular transmitter has a SAW bandpass filter (BPF) centered on the licensed bandwidth. Therefore, the self-generated interference signal outside the licensed bandwidth will be weakened by bandpass filtering. Therefore, in this case, it is advantageous to select the clock frequency clock1 so that the corresponding interference signal X is outside the licensed bandwidth. Therefore, in a multi-band transceiver, it is also advantageous to be able to change the clock frequency when switching between two different licensed bands.

[0081] Fig.14, the emission signal spectrum

[0082] Fig.14 A diagram showing the ADC noise spectrum for two different sampling frequencies is shown. In the first case at the top of the figure, the ADC is initially running at the maximum possible sampling rate. The sampling rate far exceeds the bandwidth of the desired signal. Through the process of digital downsampling, the ADC noise located in the shaded area of ​​the figure is removed. This results in a 14 / 15 reduction in noise power. In the second case at the bottom of the figure, the ADC sampling rate is reduced by 50%. In this mode, digital downsampling now only reduces the ADC noise to a lesser extent, i.e., by 13 / 30.

[0083] If the received power level of the desired signal is high, the effect of ADC noise on the receiver's ability to recover information from the desired signal will be less. Therefore, in this case, the ADC sampling rate can be reduced with little or no effect on the receiver performance. This can provide certain benefits, namely, reduced power consumption of the ADC, thereby providing longer battery life for the portable device. When the received power level of the desired signal is low, that is, in conditions generally referred to as sensitive conditions, the effect of ADC noise on receiver performance is relatively more significant. Therefore, in this case, it is desirable to operate the ADC at the highest sampling rate.

[0084] Fig.15 and Fig.16 , resampling after the ADC and before the DAC

[0085] Fig.15 A portion 1000 of a circuit is shown according to one embodiment, illustrating digital resampling performed in each transmit and receive signal path to compensate for changes in signals 152 and 353 due to changes in LO signal 145. In response to the actual clock frequencies obtained for ADC sampling clock 152 and DAC sampling clock 353, microcontroller 160 sets resampling control signals 1011 and 1051 so that the output sampling rate of digital receiver 1080 and the input sampling rate of digital transmitter 1090 can remain unchanged during the continuous change of carrier signal 145.

[0086] ADC 260 converts analog signal 1001 into a digital signal using sampling clock 152. Digital filter 1010 performs digital filtering operations at the same sampling rate as ADC 260. Resampling filter 1020 resamples the output of filter 1010 to form a new signal 1031. The sampling rate adjustment process affected by resampling filter 1020 is controlled by signal 1011 from microcontroller 160. Digital filter 1030 performs digital filtering operations at the same sampling rate as signal 1031. DAC 250 generates analog signal 1061 from the digital signal using sampling clock 353. Digital filter 1060 performs digital filtering operations at the same sampling rate as DAC 250. Resampling filter 1050 resamples the output of filter 1040 to form a new signal 1041. The sampling rate adjustment process affected by resampling filter 1050 is controlled by signal 1051 from microcontroller 160. Digital filter 1040 performs a digital filtering operation at the same sampling rate as signal 1071 .

[0087] Fig.16 A sequence of steps 1100 is shown illustrating the process used by the microcontroller 160 to program the resampling filters 1020 and 1050. The frequencies of the sampling clock 152 of the ADC 260, the sampling clock 353 of the DAC 250, and the frequency of the digital clock 151 may be selected as preparatory steps performed by the microcontroller 160 following the process of steps 910 to 960. Typically, in a communication system, the sampling rate of the signal 1021 at the output of the digital receiver 1080 and the sampling rate of the signal 1071 at the input of the digital transmitter 1090 need to remain constant and independent of changes in the frequency of the carrier signal 145. To achieve this result, the microcontroller 160 adjusts the resampling rates applied by the resampling filters 1020 and 1050 in a manner that is inversely proportional to changes in the ADC sampling clock signal 152 and the DAC sampling clock signal 353, respectively. The microcontroller 160 controls the digital resampling filters 1020 and 1050 through programming steps 1110 to 1195 using control signals 1011 and 1051, respectively. Step 1110 is the start step, while step 1120 involves reading the programmed frequency of the signal 145. At steps 1130 and 1140, the frequency of the DAC clock 353 and the sampling rate of the signal 1071 are read in. At step 1150, the ratio of the DAC sampling rate to the sampling rate of the signal 1071 is calculated. At step 1160, the resampling filter 1050 is programmed using the control signal 1051.

[0088] At step 1165, the frequency of the ADC clock 152 is read in. At step 1175, the sampling rate of the signal 1031 is read in. At step 1185, the ratio of the ADC sampling rate to the sampling rate of the signal 1031 is calculated. At step 1195, the resampling filter 1020 is programmed using the control signal 1011.

[0089] Numerous modifications, changes, variations, substitutions and equivalents will occur to those skilled in the art without departing from the scope of the claims.

Claims

1. An integrated circuit, characterized in that: The invention comprises an oscillator circuit, a first frequency divider circuit, a second frequency divider circuit, a first circuit and a second circuit, wherein the first frequency divider circuit and the second frequency divider circuit are coupled to the oscillator circuit, the first frequency divider circuit is used to provide a clock signal to the first circuit based on a signal output by the oscillator, the second frequency divider circuit is used to provide a clock signal to the second circuit based on a signal output by the oscillator circuit, the first circuit and the second circuit operate based on the clock signals provided by the first frequency divider and the second frequency divider, respectively, and the oscillator circuit is used to generate a signal output by the oscillator according to a reference signal provided by a reference clock; The integrated circuit also includes a controller; the controller being configured to select a frequency variation of the clock signal provided by the first frequency divider, the selection being based on a quality of a digitally processed output of a signal timed by the clock signal provided by the first frequency divider and interference caused by the clock signal provided by the first frequency divider; The controller is also used to select a frequency change of the clock signal provided by the second divider, based on the quality of the digitally processed output of the signal timed by the clock signal provided by the second divider and interference caused by the clock signal provided by the second divider.

2. The integrated circuit according to claim 1, wherein: The first circuit is a digital circuit.

3. The integrated circuit according to claim 1, wherein: The second circuit is a digital circuit.

4. The integrated circuit according to claim 2, wherein: The first circuit includes a digital-to-analog conversion circuit.

5. The integrated circuit according to claim 3, characterized in that The second circuit includes an analog-to-digital conversion circuit.

6. The integrated circuit according to any one of claims 1 to 5, characterized in that: The oscillator circuit includes a first oscillator and a second oscillator, and the integrated circuit further includes a signal switch, and the signal switch is used to select the first oscillator or the second oscillator to be coupled with the first frequency divider circuit or the second frequency divider circuit.

7. The integrated circuit according to any one of claims 1 to 5, characterized in that: The oscillator circuit includes a first oscillator and a second oscillator, the first oscillator and the second oscillator being coupled to the first frequency divider circuit and the second frequency divider circuit, respectively.

8. The integrated circuit according to claim 5, characterized in that It also includes a receiver RF circuit, which is used to couple the signal of the receiving antenna, and the receiver RF circuit is coupled to the analog-to-digital conversion circuit ADC through a receiver baseband circuit.

9. The integrated circuit according to claim 8, characterized in that The receiver RF circuit is used to implement down-conversion according to the signal provided by the reference clock.

10. The integrated circuit according to claim 4, characterized in that It also includes a transmitter baseband circuit and a transmitter RF circuit, wherein the transmitter RF circuit is used for coupling with a transmitting antenna, and the transmitter RF circuit is coupled to the digital-to-analog conversion circuit DAC through the transmitter baseband circuit.

11. The integrated circuit according to claim 10, wherein: The transmitter RF circuit is also used to implement up-conversion according to the signal provided by the reference clock.

12. A method for generating a digital clock, characterized in that: generating a reference clock signal; Generate a first clock signal based on the reference clock signal after frequency division by a first frequency divider circuit; Generate a second clock signal based on the reference clock signal after frequency division by a second frequency divider circuit; The first clock signal is used to provide to a first digital circuit; The second clock signal is used to provide to the second digital circuit; wherein the frequency variation of the first clock signal is selected based on the quality of the digitally processed output of the signal clocked by the first clock signal and the interference caused by the clocking of the first clock signal; The frequency variation of the second clock signal is selected based on the quality of the digitally processed output of the signal clocked by the second clock signal and interference caused by the clocking of the second clock signal.

13. The method for generating a digital clock according to claim 12, characterized in that: The first digital circuit includes an ADC.

14. The method for generating a digital clock according to any one of claims 12 to 13, characterized in that: The second digital circuit includes a DAC.

15. The method for generating a digital clock according to claim 12, characterized in that: A first oscillation signal generated by a first oscillator based on the reference clock signal; A second oscillator generates a second oscillation signal based on the reference clock signal.

16. The method for generating a digital clock according to claim 15, characterized in that: The first oscillation signal and the second oscillation signal are used to be provided to the first frequency divider circuit and the second frequency divider circuit respectively.

17. The method for generating a digital clock according to any one of claims 15 to 16, characterized in that: The first oscillation signal and the second oscillation signal are selected by a selector and provided to the first frequency divider circuit and the second frequency divider circuit respectively.

18. The method for generating a digital clock according to claim 13, characterized in that: The RF transceiver circuit includes a receiver RF circuit, which is used to couple the signal of the receiving antenna. The receiver RF circuit is coupled to the analog-to-digital conversion circuit ADC through a receiver baseband circuit. The receiver RF circuit is used to achieve down-conversion according to the reference clock signal.

19. The method for generating a digital clock according to claim 14, characterized in that: The RF transceiver circuit includes a transmitter RF circuit, which is used to couple the signal of the transmitting antenna. The transmitter RF circuit is coupled to the digital-to-analog conversion circuit DAC through a transmitter baseband circuit, and the transmitter RF circuit is used to achieve up-conversion according to the reference clock signal.

20. A digital resampling circuit, characterized in that : An ADC circuit is included, wherein the ADC circuit converts an analog signal into a digital signal using a first sampling clock; A digital filter, wherein the digital filter uses the first sampling clock to digitally filter the digital signal; A resampling filter for resampling the signal after the digital filter; A controller is configured to select a frequency change of the first sampling clock based on a quality of a digitally processed output of a signal clocked by the first sampling clock and interference caused by the first sampling clock.

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