An electrostatic protection circuit

Abstract

The embodiment of the present invention relates to an electrostatic protection circuit design, and discloses an electrostatic protection circuit, including: an electrostatic protection module; an input and output terminal, a power supply terminal, and a ground terminal; the electrostatic protection module includes a first NMOS transistor, a first capacitor, and a first resistor, the source and substrate of the first NMOS transistor are both connected to the input and output terminal, and the drain is connected to the ground terminal; the first end of the first capacitor is connected to the ground terminal, and the second end is connected to the gate of the first NMOS transistor; the first end of the first resistor is connected to the input and output terminal, and the second end is connected to the gate of the first NMOS transistor. In the present invention, the electrostatic protection circuit can effectively realize the electrostatic protection of the internal circuit without affecting the operation of the internal circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an electrostatic protection circuit. Background Art

[0002] Integrated circuits are easily damaged by electrostatic discharge (ESD) during manufacturing, packaging, testing and application. The voltage of ESD can usually reach several thousand volts and the current can reach several amperes. ESD test models are usually divided into three categories. The first category is caused by contact between people and ICs. Usually, HBM (human body model) type ESD protection circuits can be made for this type of ESD. The rise time of HBM type ESD pulse is about 10ns; the second category is caused by contact between mechanical equipment and ICs. Usually, MM (machine model) type ESD protection circuits can be made for this type of ESD; the third category is caused by the charge of the IC itself, and its discharge can occur through a single pin of the IC. This type of ESD can be made into CDM (charged-device-model) type ESD protection circuits for discharge protection, and the rise time of CDM type ESD pulse is even less than 1ns.

[0003] The inventors have found that there are at least the following problems in the prior art: the operating voltage of the input, output and power pads of semiconductor integrated circuit products is usually greater than or equal to 0 volts during normal operation, and there are corresponding electrostatic protection circuits to protect the pads. However, for some special applications, some pads have a negative voltage during normal operation, and there is no corresponding electrostatic protection circuit to protect the pads. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide an electrostatic protection circuit, which can effectively implement electrostatic protection of an internal circuit without affecting the operation of the internal circuit.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides an electrostatic protection circuit, comprising:

[0006] An electrostatic protection module; an input / output terminal, a power supply terminal and a ground terminal; the electrostatic protection module comprises a first NMOS transistor, a first capacitor and a first resistor, the source and substrate of the first NMOS transistor are both connected to the input / output terminal, and the drain is connected to the ground terminal; the first terminal of the first capacitor is connected to the ground terminal, and the second terminal is connected to the gate of the first NMOS transistor; the first terminal of the first resistor is connected to the input / output terminal, and the second terminal is connected to the gate of the first NMOS transistor.

[0007] Specifically, the working state of the electrostatic protection module can be divided into two states: normal operation and ESD occurrence. In normal operation, the input-output terminal VBBSVT is a negative voltage and serves as the gate of the first NMOS transistor. Since the source and substrate of the first NMOS transistor are both connected to the input-output terminal VBBSVT, the source and substrate are both negative voltages of the same magnitude as the input-output terminal voltage VBBSVT. At this time, the drain of the first NMOS transistor is grounded, the first NMOS transistor is turned off, and the electrostatic protection module does not affect the operation of the internal circuit, ensuring the normal operation of the internal circuit. When ESD occurs, it is divided into two situations. One is that a positive electrostatic pulse is generated from the input-output terminal VBBSVT to the ground terminal VSS. At this time, the voltage of the input-output terminal VBBSVT will continue to increase until the parasitic diode of the first NMOS transistor is turned on, thereby discharging the electrostatic current to the ground terminal VSS through the parasitic diode; the other is that a positive electrostatic pulse is generated from the ground terminal VSS to the input-output terminal VBBSVT. In the rising stage of the electrostatic pulse at the ground terminal VSS, it is equivalent to adding a fast rising voltage to the ground terminal VSS. In this stage, the first capacitor is equivalent to a wire, and the gate voltage of the first NMOS transistor will change with the change of the ground terminal VSS voltage (because the voltage of the ground terminal VSS is constantly increasing, the gate voltage of the first NMOS transistor is also constantly increasing). When the electrostatic pulse rises to a certain value (for example, Vth), the first NMOS transistor is turned on, and the first NMOS transistor begins to discharge electrostatic charge. Since the first NMOS transistor is initially on at a relatively weak level, the first NMOS transistor has a relatively weak electrostatic discharge capability, and the charge accumulated on the ground terminal VSS is greater than the charge discharged, causing the voltage of the ground terminal VSS to continue to rise, making the gate voltage of the first NMOS transistor higher, thereby making the first NMOS transistor more conductive and capable of discharging charges stronger, until the charge discharge capability of the first NMOS transistor is equal to the charge accumulation capability on the ground terminal VSS, the voltage of the ground terminal VSS changes from an increasing trend to a decreasing trend, and the voltage of VSS continues to decrease until the voltage of VSS drops to 0, and the entire ESD process ends, thereby effectively realizing electrostatic protection of the internal circuit without affecting the operation of the internal circuit. In addition, since the first capacitor is in a conducting state during the electrostatic discharge process of the entire circuit, by setting the first resistor between the ground terminal VSS and the input / output terminal VBBSVT, the ground terminal VSS and the input / output terminal VBBSVT are effectively prevented from being short-circuited due to direct connection, thereby improving the reliability of the electrostatic protection circuit.

[0008] In addition, it also includes a second electrostatic protection circuit connected to the power supply end and the ground end; the second electrostatic protection circuit includes a second capacitor, a second resistor, a second NMOS transistor and a third NMOS transistor, the first end of the second capacitor is connected to the power supply end, the second end of the second capacitor is connected to the drain of the second NMOS transistor, the first end of the second resistor is connected to the gate of the second NMOS transistor, the second end of the second resistor is connected to the power supply end, the gate of the third NMOS transistor is connected to the drain of the second NMOS transistor, and the drain and source of the third NMOS transistor are respectively connected to the power supply end and the ground end. By setting the second electrostatic protection circuit, the electrostatic current between the power supply end and the ground end in the entire circuit can be discharged, further ensuring the electrostatic protection of the internal circuit. In this way, the electrostatic current is discharged through the third NMOS transistor, thereby achieving the discharge of the electrostatic current between the power supply end and the ground end of the entire circuit.

[0009] In addition, the electrostatic protection module includes a semiconductor substrate and a P-well located on the semiconductor substrate, the first NMOS transistor is located on the P-well, the source and drain of the first NMOS transistor are located in the P-well on both sides of the gate, the P-well also has a first P-type doped region, and the source is electrically connected to the first P-type doped region.

[0010] In addition, a deep N well is included, the deep N well is located on the semiconductor substrate, and the P well is located in the deep N well. Since a large current will be generated when the ESD device discharges static electricity, in order not to affect other circuits, the deep N well is used to isolate it from other circuits, thereby improving the reliability of the electrostatic protection circuit.

[0011] In addition, the deep N-well has an N-type doped region, and the N-type doped region is connected to the power supply terminal.

[0012] In addition, a diode is also included, wherein the anode of the diode is connected to the input / output end, and the cathode of the diode is connected to the power supply end.

[0013] In addition, the total channel width of the first NMOS transistor is greater than 300 microns.

[0014] In addition, a channel length of the first NMOS transistor is less than or equal to a channel length of the third NMOS transistor.

[0015] In addition, the capacitance value of the first capacitor is between 1 and 10 pF.

[0016] In addition, the resistance of the first resistor is between 1 kiloohm and 10,000 ohms.

[0017] In addition, the drain of the first NMOS transistor does not include a lightly doped drain structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0019] Figure 1 is a circuit diagram of an electrostatic protection circuit provided according to a first embodiment of the present invention;

[0020] Figure 2 is a cross-sectional view of an electrostatic protection module provided according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the following will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present invention, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0022] The first embodiment of the present invention relates to an electrostatic protection circuit 100, the specific structure of which is as follows: Figure 1 As shown, including:

[0023] Electrostatic protection module 1; input and output terminal VBBSVT, power supply terminal VDD and ground terminal VSS; electrostatic protection module 1 includes a first NMOS transistor 11, a first capacitor 12 and a first resistor 13, the source and substrate of the first NMOS transistor 11 are connected to the input and output terminal VBBSVT, and the drain is connected to the ground terminal VSS; the first end of the first capacitor 12 is connected to the ground terminal VSS, and the second end is connected to the gate of the first NMOS transistor 11; the first end of the first resistor 13 is connected to the input and output terminal VBBSVT, and the second end is connected to the gate of the first NMOS transistor 11.

[0024] In practical applications, the above circuit structure can be applied to the electrostatic protection of input and output pads of integrated circuits, and can be applied to the electrostatic protection of various semiconductor integrated circuits such as logic, analog and various memory chips.

[0025] Compared with the prior art, the electrostatic protection module 1 of the embodiment of the present invention is used to provide electrostatic protection for the internal circuit. Specifically, the working state of the electrostatic protection module 1 can be divided into two states: normal operation and ESD occurrence. In normal operation, the input-output terminal VBBSVT is a negative voltage and serves as the gate of the first NMOS transistor 11. Since the source and substrate of the first NMOS transistor 11 are both connected to the input-output terminal VBBSVT, the source and substrate are both negative voltages of the same magnitude as the input-output terminal voltage VBBSVT. At this time, the drain of the first NMOS transistor 11 is grounded, and the first NMOS transistor 11 is turned off. The electrostatic protection module 1 does not affect the operation of the internal circuit 4, ensuring the normal operation of the internal circuit 4. When ESD occurs, there are two situations. One is that a positive electrostatic pulse is generated from the input-output terminal VBBSVT to the ground terminal VSS. At this time, the voltage of the input-output terminal VBBSVT will continue to increase until the parasitic diode of the first NMOS transistor 11 is turned on, thereby discharging the electrostatic current to the ground terminal VSS through the parasitic diode; the other is that a positive electrostatic pulse is generated from the ground terminal VSS to the input-output terminal VBBSVT. In the rising stage of the electrostatic pulse at the ground terminal VSS, it is equivalent to adding a fast rising voltage to the ground terminal VSS. In this stage, the first capacitor 12 is equivalent to a wire, and the gate voltage of the first NMOS transistor 11 will change with the change of the ground terminal VSS voltage (because the voltage of the ground terminal VSS is constantly increasing, the gate voltage of the first NMOS transistor 11 is also constantly increasing). When the electrostatic pulse rises to a certain value (for example, Vth), the first NMOS transistor 11 is turned on, and the first NMOS transistor 11 starts to discharge electrostatic charge. Since the first NMOS transistor 11 is initially on at a relatively weak level, the first NMOS transistor 11 has a relatively weak electrostatic discharge capability, and the charge accumulated on the ground terminal VSS is greater than the charge discharged, causing the voltage of the ground terminal VSS to continue to rise, making the gate voltage of the first NMOS transistor 11 higher, thereby making the first NMOS transistor 11 more conductive and capable of discharging charges stronger, until the charge discharge capability of the first NMOS transistor 11 is equal to the charge accumulation capability on the ground terminal VSS, the voltage of the ground terminal VSS changes from an increasing trend to a decreasing trend, and the voltage of VSS continues to decrease until the voltage of VSS drops to 0, and the entire ESD process ends, thereby effectively realizing electrostatic protection of the internal circuit 4 without affecting the operation of the internal circuit 4. In addition, since the first capacitor 12 is in a conducting state during the entire circuit electrostatic discharge process, by setting the first resistor 13 between the ground terminal VSS and the input / output terminal VBBSVT, the ground terminal VSS and the input / output terminal VBBSVT are effectively prevented from being short-circuited due to direct connection, thereby improving the reliability of the electrostatic protection circuit 100.

[0026] In this embodiment, a second electrostatic protection circuit 2 connected to the power supply terminal VDD and the ground terminal VSS is also included; the second electrostatic protection circuit 2 includes a second capacitor 21, a second resistor 22, a second NMOS transistor Mr, and a third NMOS transistor Mesd. The first end of the second capacitor 21 is connected to the power supply terminal VDD, the second end of the second capacitor 21 is connected to the drain of the second NMOS transistor Mr, the first end of the second resistor 22 is connected to the gate of the second NMOS transistor Mr, the second end of the second resistor 22 is connected to the power supply terminal VDD, the gate of the third NMOS transistor Mesd is connected to the drain of the second NMOS transistor Mr, and the drain and source of the third NMOS transistor Mesd are respectively connected to the power supply terminal VDD and the ground terminal VSS. The second protection circuit 2 can be arranged near the power supply terminal VDD and the ground terminal VSS to discharge the electrostatic current between the power supply terminal VDD and the ground terminal VSS of the entire chip. Specifically, in normal operation, the gate of the second NMOS transistor Mr is connected to the VDD terminal via the second resistor 22. At this time, the second NMOS transistor Mr is in the on state, and the impedance of the capacitor 21 is much greater than the impedance of the second NMOS transistor Mr. Therefore, the gate voltage of the third NMOS transistor Mesd is small, so that the third NMOS transistor Mesd is in the off state. At this time, the third NMOS transistor Mesd does not affect the operation of the circuit; when an electrostatic pulse is generated, resulting in When the potential of the power supply terminal VDD increases, the gate voltage of the third NMOS transistor Mesd increases accordingly, triggering the third NMOS transistor Mesd to turn on. Since the conduction degree of the third NMOS transistor Mesd is relatively weak, the discharge capacity is relatively weak, and the charge accumulated on VDD is greater than the charge discharged, causing the voltage of VDD to continue to rise, making the gate voltage of the third NMOS transistor Mesd higher, thereby making the conduction capacity and charge discharge capacity of the third NMOS transistor Mesd stronger, until the charge discharge capacity of the third NMOS transistor Mesd is equal to the charge accumulation capacity on VDD, and the voltage of VDD changes from an increasing trend to a decreasing trend. The voltage of VDD continues to decrease until the voltage of VDD drops to 0, thereby achieving the discharge of the electrostatic current between the power supply terminal VDD and the ground terminal VSS of the entire circuit.

[0027] Optionally, a diode Dp is further included, the anode of the diode Dp is connected to the input / output terminal VBBSVT, and the cathode of the diode Dp is connected to the power supply terminal VDD. In normal operation, since the potential of the power supply terminal VDD is higher than the potential of the ground terminal VSS, the voltage of the positive electrode of the first diode Dp is not higher than the voltage of the negative electrode, so that the first diode Dp is in a disconnected state, and at this time, the diode Dp does not affect the operation of the circuit; when a positive electrostatic pulse is generated from VBBSVT to VDD, causing the potential of the ground terminal VBBSVT to increase, the electrostatic pulse turns on the diode Dp, so that the electrostatic current is discharged through the diode Dp, and the electrostatic current between the input / output terminal VBBSVT and the power supply terminal VDD of the entire electrostatic protection circuit 100 is discharged.

[0028] Specifically, in this embodiment, the total channel width of the first NMOS transistor 11 is greater than 300 microns; the channel length of the first NMOS transistor 11 is less than or equal to the channel length of the third NMOS transistor Mesd; the capacitance of the first capacitor 12 is between 1 and 10 pF; the resistance of the first resistor 13 is between 1 kiloohm and 10,000 ohms. Under the premise of meeting the electrostatic protection requirements, the area of ​​the electrostatic protection circuit is reduced as much as possible.

[0029] The second embodiment of the present invention relates to an electrostatic protection module 200, such as Figure 2 As shown, it includes: a semiconductor substrate 3, a P-well 4 located on the semiconductor substrate 3, a first NMOS transistor located on the P-well 4, a source and a drain of the first NMOS transistor located in the P-well 4 on both sides of the gate, a first P-type doped region in the P-well 4, and the source of the first NMOS transistor is electrically connected to the first P-type doped region.

[0030] Compared with the prior art, the electrostatic protection module 200 of the embodiment of the present invention is used to provide electrostatic protection for the internal circuit. Specifically, the working state of the electrostatic protection module can be divided into two states: normal operation and ESD occurrence. In normal operation, the input-output terminal VBBSVT is a negative voltage and serves as the gate of the first NMOS transistor. Since the source and substrate of the first NMOS transistor are both connected to the input-output terminal VBBSVT, the source and substrate are both negative voltages of the same magnitude as the input-output terminal voltage VBBSVT. At this time, the drain of the first NMOS transistor is grounded, and the first NMOS transistor is turned off. The electrostatic protection module does not affect the operation of the internal circuit, ensuring the normal operation of the internal circuit. When ESD occurs, it is divided into two situations. One is that a positive electrostatic pulse is generated from the input-output terminal VBBSVT to the ground terminal VSS. At this time, the voltage of the input-output terminal VBBSVT will continue to increase until the parasitic diode of the first NMOS transistor is turned on, thereby discharging the electrostatic current to the ground terminal VSS through the parasitic diode; the other is that a positive electrostatic pulse is generated from the ground terminal VSS to the input-output terminal VBBSVT. In the rising stage of the electrostatic pulse at the ground terminal VSS, it is equivalent to adding a fast rising voltage to the ground terminal VSS. In this stage, the first capacitor is equivalent to a wire, and the gate voltage of the first NMOS transistor will change with the change of the ground terminal VSS voltage (because the voltage of the ground terminal VSS is constantly increasing, the gate voltage of the first NMOS transistor is also constantly increasing). When the electrostatic pulse rises to a certain value (for example, Vth), the first NMOS transistor is turned on, and the first NMOS transistor begins to discharge electrostatic charge. Since the first NMOS transistor is initially on at a relatively weak level, the first NMOS transistor has a relatively weak electrostatic discharge capability, and the charge accumulated on the ground terminal VSS is greater than the charge discharged, causing the voltage of the ground terminal VSS to continue to rise, making the gate voltage of the first NMOS transistor higher, thereby making the first NMOS transistor more conductive and capable of discharging charges stronger, until the charge discharge capability of the first NMOS transistor is equal to the charge accumulation capability on the ground terminal VSS, the voltage of the ground terminal VSS changes from an increasing trend to a decreasing trend, and the voltage of VSS continues to decrease until the voltage of VSS drops to 0, and the entire ESD process ends, thereby effectively realizing electrostatic protection of the internal circuit without affecting the operation of the internal circuit. In addition, since the first capacitor is in a conducting state during the electrostatic discharge process of the entire circuit, by setting the first resistor between the ground terminal VSS and the input / output terminal VBBSVT, the ground terminal VSS and the input / output terminal VBBSVT are effectively prevented from being short-circuited due to direct connection, thereby improving the reliability of the electrostatic protection circuit.

[0031] It is worth mentioning that the electrostatic protection module 200 also includes a deep N-well 5, which is located on the semiconductor substrate 3, and the P-well 4 is located in the deep N-well 5. Since a large current will flow when the ESD device discharges static electricity, in order not to affect other circuits, the deep N-well 5 is used to isolate it from other circuits, thereby improving the reliability of the electrostatic protection module 200.

[0032] Preferably, the deep N-well 5 has an N-type doped region, and the N-type doped region is connected to the power supply terminal. In this way, the N-type doped region forms a charged wall, and the circuits on both sides of the charged wall do not affect each other.

[0033] Specifically, the drain of the first NMOS transistor does not include a lightly doped drain structure, and the source of the first NMOS transistor includes a lightly doped drain structure. The drain of the first NMOS transistor does not include a lightly doped drain structure, which can reduce its on-resistance and improve its current discharge capability.

[0034] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present invention, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present invention.

Claims

1. An electrostatic protection circuit, characterized in that: include: Electrostatic protection module; Input and output terminals, power supply terminals and ground terminals; The electrostatic protection module comprises a first NMOS transistor, a first capacitor and a first resistor, wherein the source and substrate of the first NMOS transistor are both connected to the input and output terminals, and the drain is connected to the ground terminal; A first end of the first capacitor is connected to the ground end, and a second end of the first capacitor is connected to the gate of the first NMOS transistor; A first end of the first resistor is connected to the input / output end, and a second end of the first resistor is connected to the gate of the first NMOS transistor; Among them, the electrostatic protection module includes a semiconductor substrate and a P-well located on the semiconductor substrate, the first NMOS transistor is located on the P-well, the source and drain of the first NMOS transistor are located in the P-well on both sides of the gate, the P-well also has a first P-type doped region, and the source is electrically connected to the first P-type doped region.

2. The electrostatic protection circuit according to claim 1, characterized in that: It also includes a second electrostatic protection circuit connected to the power supply end and the ground end; the second electrostatic protection circuit includes a second capacitor, a second resistor, a second NMOS transistor and a third NMOS transistor, the first end of the second capacitor is connected to the power supply end, the second end of the second capacitor is connected to the drain of the second NMOS transistor, the first end of the second resistor is connected to the gate of the second NMOS transistor, the second end of the second resistor is connected to the power supply end, the gate of the third NMOS transistor is connected to the drain of the second NMOS transistor, and the drain and source of the third NMOS transistor are respectively connected to the power supply end and the ground end.

3. The electrostatic protection circuit according to claim 1, characterized in that: It also includes a deep N-well, wherein the deep N-well is located on the semiconductor substrate, and the P-well is located in the deep N-well.

4. The electrostatic protection circuit according to claim 3, characterized in that: The deep N-well has an N-type doping region therein, and the N-type doping region is connected to the power supply end.

5. The electrostatic protection circuit according to claim 2, characterized in that: It also includes a diode, wherein the anode of the diode is connected to the input and output terminals, and the cathode of the diode is connected to the power supply terminal.

6. The electrostatic protection circuit according to claim 5, characterized in that: The total channel width of the first NMOS transistor is greater than 300 microns.

7. The electrostatic protection circuit according to claim 6, characterized in that: A channel length of the first NMOS transistor is less than or equal to a channel length of the third NMOS transistor.

8. The electrostatic protection circuit according to claim 1, characterized in that: The capacitance value of the first capacitor is between 1 and 10 pF.

9. The electrostatic protection circuit according to claim 1, characterized in that: The resistance of the first resistor is between 1 kiloohm and 10,000 ohms.

10. The electrostatic protection circuit according to claim 1, characterized in that: The drain of the first NMOS transistor does not include a lightly doped drain structure.

11. An electrostatic protection circuit, characterized in that: include: Electrostatic protection module; Input and output terminals, power supply terminals and ground terminals; The electrostatic protection module comprises a first NMOS transistor, a first capacitor and a first resistor, wherein the source and substrate of the first NMOS transistor are both connected to the input and output terminals, and the drain is connected to the ground terminal; A first end of the first capacitor is connected to the ground end, and a second end of the first capacitor is connected to the gate of the first NMOS transistor; A first end of the first resistor is connected to the input / output end, and a second end of the first resistor is connected to the gate of the first NMOS transistor; A second electrostatic protection circuit connected to the power supply terminal and the ground terminal; The second electrostatic protection circuit includes a second capacitor, a second resistor, a second NMOS transistor and a third NMOS transistor, wherein a first end of the second capacitor is connected to the power supply terminal, a second end of the second capacitor is connected to the drain of the second NMOS transistor, a first end of the second resistor is connected to the gate of the second NMOS transistor, a second end of the second resistor is connected to the power supply terminal, a gate of the third NMOS transistor is connected to the drain of the second NMOS transistor, and a drain and a source of the third NMOS transistor are respectively connected to the power supply terminal and the ground terminal.

Images