Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device includes: forming vertically spaced first active patterns on a first active fin of a substrate and forming vertically spaced second active patterns on a second active fin of the substrate, the substrate having a first region on which the first active fin is formed and a second region on which the second active fin is formed; forming a first electrode layer on the first active fin and the second active fin and the first active pattern and the second active pattern; forming a first mask pattern overlapping the first electrode layer on the first region; forming a second mask pattern overlapping the first electrode layer on the second region; and etching the first mask pattern and the first electrode layer on the first region using the second mask pattern as an etching mask to form the first electrode pattern on the second region.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having improved reliability and a method of manufacturing the same. Background Art

[0002] Semiconductor devices are beneficial in the electronics industry due to their small size, versatility and / or low manufacturing cost. Semiconductor devices may include semiconductor memory devices that store logic data, semiconductor logic devices that process logic data, and hybrid semiconductor devices having both storage elements and logic elements. With the rapid development of the electronics industry, semiconductor devices have been increasingly manufactured for high integration. For example, semiconductor devices have been increasingly required to have high reliability, high speed and / or versatility. In order to meet these required characteristics, semiconductor devices have gradually become more and more complex and more integrated. Summary of the invention

[0003] Some example embodiments of the inventive concepts provide methods of fabricating semiconductor devices having improved reliability.

[0004] Some example embodiments of the inventive concepts provide semiconductor devices having improved reliability.

[0005] According to some example embodiments of the inventive concept, a method for manufacturing a semiconductor device may include: forming a plurality of first active patterns on a first active fin of a substrate so that the plurality of first active patterns are spaced apart from each other by a first distance in a direction perpendicular to the substrate; and forming a plurality of second active patterns on a second active fin of the substrate so that the plurality of second active patterns are spaced apart from each other by a second distance in a direction perpendicular to the substrate. The substrate includes a first region on which the first active fin is formed and a second region on which the second active fin is formed. The method includes: forming a first electrode layer extending on top surfaces and sidewalls of the first and second active fins and extending on surfaces of the first and second active patterns; forming a first mask pattern extending on the first electrode layer formed on the first region of the substrate; forming a second mask pattern extending on the first electrode layer formed on the second region of the substrate; and etching the first mask pattern and the portion of the first electrode layer on the first region of the substrate using the second mask pattern as an etching mask to form the first electrode pattern on the second region of the substrate.

[0006] According to some example embodiments of the inventive concept, a method for manufacturing a semiconductor device may include: forming a plurality of first active patterns on a first active fin of a substrate so that the plurality of first active patterns are spaced apart from each other by a first distance in a direction perpendicular to the substrate; and forming a plurality of second active patterns on a second active fin of the substrate so that the plurality of second active patterns are spaced apart from each other by a second distance in a direction perpendicular to the substrate. The substrate includes a first region on which the first active fin is formed and a second region on which the second active fin is formed. The method includes: forming a first electrode layer extending on a top surface and a sidewall of the first and second active fins and extending on a surface of the first and second active patterns; forming a first mask pattern extending on the first electrode layer formed on the second region of the substrate; and etching a portion of the first electrode layer formed on the first region using the first mask pattern as an etching mask to form the first electrode pattern on the second region of the substrate. The sidewall of the first mask pattern may have an angle relative to the top surface of the substrate. The sidewall of the first mask pattern may be adjacent to the first region of the substrate. The angle relative to the top surface of the substrate may be in a range from 91° to 100°.

[0007] According to some example embodiments of the present inventive concept, a semiconductor device may include: a device isolation layer between a first active region and a second active region of a substrate; a first active fin on the first active region and a second active fin on the second active region; a first electrode pattern on the first active fin and the second active fin; and a second electrode pattern between the first electrode pattern and the second active fin. The second electrode pattern may extend on the device isolation layer and may have an end adjacent to the first active region of the substrate. The sidewall of the end of the second electrode pattern may have an angle relative to the top surface of the substrate. The angle relative to the top surface of the substrate may be in a range from 91° to 100°. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A A top view of a semiconductor device according to some example embodiments of the inventive concepts is shown.

[0009] Figure 1B FIG. 1 shows a semiconductor device according to some example embodiments of the present inventive concept. Figure 1A Cross-sectional views taken along lines II', II-II' and III-III'.

[0010] Figure 1C FIG. 1 shows a semiconductor device according to some example embodiments of the present inventive concept. Figure 1B Magnified view of part A in FIG.

[0011] Figure 2A , Figure 3A , Figure 4A, Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig. 9A A top view illustrating a method of fabricating a semiconductor device according to some example embodiments of the inventive concepts.

[0012] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B and Fig.10 A method of manufacturing a semiconductor device according to some example embodiments of the present inventive concept is shown along the Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig. 9A Cross-sectional views taken along lines II', II-II' and III-III'.

[0013] Fig.11A , Fig. 12A , Fig.13A and Fig.14A A top view illustrating a method of fabricating a semiconductor device according to some example embodiments of the inventive concepts.

[0014] Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B A method of manufacturing a semiconductor device according to some example embodiments of the present inventive concept is shown along the FIG. 11A to FIG. 14A Cross-sectional views taken along lines II', II-II' and III-III'. DETAILED DESCRIPTION

[0015] Figure 1A A top view of a semiconductor device according to some example embodiments of the inventive concepts is shown. Figure 1B FIG. 1 shows a semiconductor device according to some example embodiments of the present inventive concept. Figure 1A Cross-sectional views taken along lines II', II-II' and III-III'. Figure 1C FIG. 1 shows a semiconductor device according to some example embodiments of the present inventive concept. Figure 1B Magnified view of part A in FIG.

[0016] Reference Figure 1A and Figure 1B, a device isolation layer 101 may be disposed in the substrate 100. The device isolation layer 101 may define a first active region 100a and a second active region 100b of the substrate 100. The first active fin AF1 may be disposed on the first active region 100a of the substrate 100, and the second active fin AF2 may be disposed on the second active region 100b of the substrate 100. The first active fin AF1 and the second active fin AF2 may protrude in a vertical direction from a top surface of the substrate 100. The first active fin AF1 and the second active fin AF2 may extend in a second direction Y and may be spaced apart from each other in a first direction X intersecting the second direction Y. In some embodiments, the first active fin AF1 may have a width greater than a width of the second active fin AF2.

[0017] The first active pattern 114 may be disposed on the first active fin AF1. The first active pattern 114 may be spaced apart from each other in the vertical direction on the top surface of the first active fin AF1. The second active pattern 124 may be disposed on the second active fin AF2. The second active pattern 124 may be spaced apart from each other in the vertical direction on the top surface of the second active fin AF2. In some embodiments, the first active pattern 114 may have a width greater than that of the second active pattern 124.

[0018] The second electrode pattern 152a may be disposed on the first active fin AF1, the second active fin AF2, the first active pattern 114, and the second active pattern 124. The second electrode pattern 152a may extend across the first active fin AF1 and the second active fin AF2 in the first direction X. The second electrode pattern 152a may fill or at least partially fill or occupy the space between the first active patterns 114. The first electrode pattern 142a may be disposed between the second electrode pattern 152a and the second active fin AF2 and between the second electrode pattern 152a and the second active pattern 124. The first electrode pattern 142a may cover or overlap the top surface, sidewall, and / or bottom surface of the second active pattern 124. The first electrode pattern 142a may cover or overlap the top surface and / or sidewall of the second active fin AF2. The first electrode pattern 142a may fill or at least partially fill or occupy the space between the second active patterns 124. A portion of the first electrode pattern 142a on the uppermost one of the second active patterns 124 may extend onto a portion of a sidewall of the second electrode pattern 152a. The portion of the first electrode pattern 142a on the uppermost second active pattern 124 may have a U-shape relative to the substrate. In some embodiments, the first electrode pattern 142a at least partially filling or occupying the space between the second active pattern 124 and the second electrode pattern 152a may have an inverted U-shape relative to the substrate. The first electrode pattern 142a may extend onto the top surface of the device isolation layer 101 adjacent to the second active fin AF2 and the second active pattern 124. Referring together Figure 1C , a sidewall of an end portion EP of the first electrode pattern 142a adjacent to the first active region 100a of the substrate 100 may define a boundary between the first active region 100a and the second active region 100b. The sidewall of the end portion EP of the first electrode pattern 142a may have an angle θ with respect to the top surface of the substrate 100. According to some embodiments, the angle θ may be in a range from 91° to 100°.

[0019] The gate dielectric pattern 140a may be interposed between the second electrode pattern 152a and the first active pattern 114, between the second electrode pattern 152a and the first active fin AF1, between the first electrode pattern 142a and the second active pattern 124, and between the first electrode pattern 142a and the second active fin AF2. The gate dielectric pattern 140a may surround the top surface, bottom surface, and / or sidewall of the first active pattern 114 and the second active pattern 124 in a cross-sectional view, and may also surround the top surface and sidewall of the first active fin AF1 and the second active fin AF2 in a cross-sectional view. The gate dielectric pattern 140a may extend onto the sidewall of each of the first electrode pattern 142a and the second electrode pattern 152a.

[0020] The gate capping pattern 154 may be disposed on the top surface of the second electrode pattern 152a. The gate capping pattern 154 may cover or overlap the top surface of the second electrode pattern 152a. The spacer SP may be disposed on the sidewalls of the first electrode pattern 142a, the sidewalls of the second electrode pattern 152a, and / or the sidewalls of the gate capping pattern 154. The spacer SP may extend in the first direction X on the sidewalls of the first electrode pattern 142a, the sidewalls of the second electrode pattern 152a, and / or the sidewalls of the gate capping pattern 154.

[0021] The source / drain pattern SDP may be disposed on the substrate 100 at the opposite side of the second electrode pattern 152a. The source / drain pattern SDP may be an epitaxial layer grown from the substrate 100 used as a seed layer. The source / drain pattern SDP may have a top surface coplanar with a top surface of the uppermost first active pattern 114 and / or a top surface of the uppermost second active pattern 124. An inner spacer IS may be disposed between each source / drain pattern SDP and the gate dielectric pattern 140a between the first active patterns 114, and may also be disposed between each source / drain pattern SDP and the gate dielectric pattern 140a between the second active patterns 124. The inner spacer IS may be disposed in a space between the first active patterns 114 and in a space between the second active patterns 124. The inner spacer IS may be in contact with a sidewall of the source / drain pattern SDP.

[0022] The interlayer dielectric layer ILD1 may be disposed on the source / drain pattern SDP. The interlayer dielectric layer ILD1 may cover or overlap the top surface of the source / drain pattern SDP. The interlayer dielectric layer ILD1 may have a top surface coplanar with the top surface of the gate cap pattern 154. The contact plug CP may be disposed on the source / drain pattern SDP. The contact plug CP may penetrate the interlayer dielectric layer ILD1 to contact the source / drain pattern SDP.

[0023] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig. 9A A top view illustrating a method of fabricating a semiconductor device according to some example embodiments of the inventive concepts. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B and Fig.10 A method of manufacturing a semiconductor device according to some example embodiments of the present inventive concept is shown along the Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig. 9A Cross-sectional views taken along lines II', II-II' and III-III'.

[0024] Reference Figure 2A and Figure 2B , the first sacrificial pattern 112 and the first active pattern 114 may be alternately and repeatedly stacked on the top surface of the first active fin AF1. The second sacrificial pattern 122 and the second active pattern 124 may be alternately and repeatedly stacked on the top surface of the second active fin AF2. The formation of the first sacrificial pattern 112 and the second sacrificial pattern 122, the first active pattern 114 and the second active pattern 124, and the first active fin AF1 and the second active fin AF2 may include: forming a sacrificial layer and an active layer alternately and repeatedly stacked on the substrate 100; and performing a patterning process on the sacrificial layer, the active layer, and the upper portion of the substrate 100. The sacrificial layer (i.e., the sacrificial pattern) may be formed of a material having an etching selectivity relative to the active layer (i.e., the active pattern). The first sacrificial pattern 112 and the second sacrificial pattern 122 may include, for example, silicon germanium (SiGe). The first active pattern 114 and the second active pattern 124 may include, for example, silicon (Si).

[0025] A device isolation layer 101 may be formed in the substrate 100. The device isolation layer 101 may be formed by filling or at least partially filling a recessed area formed after a patterning process for forming the first sacrificial pattern 112 and the second sacrificial pattern 122 and the first active pattern 114 and the second active pattern 124. The device isolation layer 101 may define a first active area 100a and a second active area 100b of the substrate 100. For example, the first active area 100a may be an NMOS region in which an NMOS transistor is formed, and the second active area 100b may be a PMOS region in which a PMOS transistor is formed. For another example, the first active area 100a may be an NMOS region, and the second active area 100b may be an NMOS region. For another example, the first active area 100a may be a PMOS region, and the second active area 100b may be a PMOS region. As another example, the first active area 100a may be a PMOS region in which a PMOS transistor is formed, and the second active area 100b may be an NMOS region in which an NMOS transistor is formed. The first active fin AF1 may be formed on the first active region 100a of the substrate 100, and the second active fin AF2 may be formed on the second active region 100b of the substrate 100. The first active fin AF1 and the second active fin AF2 may protrude in a vertical direction from the top surface of the substrate 100. The first active fin AF1 and the second active fin AF2 may be spaced apart from each other in a first direction X, and may extend in a second direction Y intersecting the first direction X. Relative to the substrate, the first active fin AF1 and the second active fin AF2 may have a top surface at a height higher than that of the top surface of the device isolation layer 101. The first active fin AF1 may have a width greater than that of the second active fin AF2. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon on insulator (SOI) substrate. The device isolation layer 101 may include a dielectric material (e.g., a silicon oxide layer or a silicon nitride layer).

[0026] Reference Figure 3A and Figure 3B, a sacrificial gate pattern SGE and a sacrificial cap pattern 130 may be sequentially formed on the substrate 100. The sacrificial gate pattern SGE and the sacrificial cap pattern 130 may extend across the first active fin AF1 and the second active fin AF2 in the first direction X. The formation of the sacrificial gate pattern SGE and the sacrificial cap pattern 130 may include: forming a sacrificial gate layer (not shown) to cover the device isolation layer 101, the first sacrificial pattern 112 and the second sacrificial pattern 122, and the first active pattern 114 and the second active pattern 124; forming the sacrificial cap pattern 130 on the sacrificial gate layer; and then performing a patterning process on the sacrificial gate layer using the sacrificial cap pattern 130 as an etching mask. The sacrificial gate pattern SGE may partially cover or partially overlap the sidewalls of the first sacrificial pattern 112 and the second sacrificial pattern 122, the sidewalls of the first active pattern 114 and the second active pattern 124, the top surface of the uppermost first active pattern 114, and / or the top surface of the uppermost second active pattern 124. The sacrificial gate pattern SGE may be formed of a material having an etch selectivity relative to the materials of the first and second sacrificial patterns 112 and 122 and the first and second active patterns 114 and 124. The sacrificial gate pattern SGE may include, for example, polysilicon. The sacrificial capping pattern 130 may include a dielectric material (eg, a silicon nitride layer).

[0027] The spacer SP may be formed on the sidewalls of the sacrificial gate pattern SGE and the sidewalls of the sacrificial cap pattern 130. The formation of the spacer SP may include: forming a spacer layer (not shown) to conformally cover the top surface of the sacrificial cap pattern 130, the sidewalls of the sacrificial gate pattern SGE, the sidewalls of the first sacrificial pattern 112 and the second sacrificial pattern 122 exposed by the sacrificial gate pattern SGE, and the top surface of the uppermost first active pattern 114 and the second active pattern 124; and then performing an etching process on the spacer layer. For example, the etching process may include an etch-back process. The spacer SP may include, for example, a silicon oxide layer.

[0028] Reference Figure 4A and Figure 4B , an etching process may be performed to etch the first and second active fins AF1 and AF2, the first and second active patterns 114 and 124, and upper portions of the first and second sacrificial patterns 112 and 122 exposed by the sacrificial gate pattern SGE and the spacer SP, thereby forming a source / drain recess region SDR. The substrate 100 may be exposed on the bottom surface of the source / drain recess region SDR. The etching process may include a dry etching process.

[0029] An etching action may be performed on portions of the first sacrificial pattern 112 and the second sacrificial pattern 122 exposed to the source / drain recess region SDR. Therefore, the first sacrificial pattern 112 and the second sacrificial pattern 122 may have a reduced width in the second direction Y. Removing portions of the first sacrificial pattern 112 and the second sacrificial pattern 122 may form an empty space between the first active patterns 114 adjacent to each other in a vertical direction relative to the substrate and between the second active patterns 124 adjacent to each other in the vertical direction.

[0030] The inner spacer IS may be formed in the empty space. The inner spacer IS may be formed by filling or at least partially filling the empty space with a dielectric layer covering or overlapping the sidewalls of the source / drain recess region SDR, and then performing an etching process on the dielectric layer to leave the dielectric layer in the empty space. The inner spacer IS may include, for example, a silicon oxide layer.

[0031] The source / drain pattern SDP may be formed by performing an epitaxial growth process in which the substrate 100 exposed by the source / drain recess region SDR is used as a seed crystal. The source / drain pattern SDP may be formed to fill the source / drain recess region SDR. The source / drain pattern SDP may be formed so that its top surface is substantially coplanar with the top surface of the uppermost first active pattern 114 and the second active pattern 124. The source / drain pattern SDP may include the same material as that of the substrate 100. The source / drain pattern SDP may include, for example, silicon. An ion implantation process may be performed on the source / drain pattern SDP. The source / drain pattern SDP may include impurities. The impurities may be, for example, boron (B) or phosphorus (P).

[0032] The interlayer dielectric layer ILD1 may be formed on the source / drain pattern SDP. The interlayer dielectric layer ILD1 may be formed by forming a dielectric layer to cover or overlap the top surface of the sacrificial cap pattern 130 and the top surface of the source / drain pattern SDP, and then performing a polishing process on the dielectric layer. The polishing process may continue until the top surface of the sacrificial cap pattern 130 is exposed. A chemical mechanical polishing process may be used as the polishing process. The interlayer dielectric layer ILD1 may be, for example, a silicon oxide layer.

[0033] Reference Figure 5A and Figure 5B , the sacrificial cap pattern 130 may be removed, and the upper portion of the interlayer dielectric layer ILD1 may be partially removed. Thus, the top surface of the sacrificial gate pattern SGE may be exposed. The sacrificial cap pattern 130 may undergo an etching process to expose the top surface of the sacrificial gate pattern SGE. The etching process may include a chemical mechanical polishing (CMP) process or an etch-back process.

[0034] The sacrificial gate pattern SGE may be removed to form a gate recess region GRR. The gate recess region GRR may be a region defined by the spacer SP. The gate recess region GRR may extend in the first direction X. The gate recess region GRR may partially expose the sidewalls of the first sacrificial pattern 112 and the second sacrificial pattern 122, the sidewalls of the first active pattern 114 and the second active pattern 124, the top surface of the uppermost first active pattern 114, the top surface of the uppermost second active pattern 124, the sidewalls of the first active fin AF1, the sidewalls of the second active fin AF2, and / or the top surface of the device isolation layer 101. The gate recess region GRR may expose the inner sidewalls of the spacer SP. The sacrificial gate pattern SGE may be selectively removed by using an etching recipe having an etching selectivity with respect to the first sacrificial pattern 112 and the second sacrificial pattern 122, the first active pattern 114 and the second active pattern 124, and / or the spacer SP.

[0035] Reference Fig. 6A and Figure 6B , an etching process may be performed to remove the first sacrificial pattern 112 and the second sacrificial pattern 122 exposed to the gate recess region GRR. The first sacrificial pattern 112 and the second sacrificial pattern 122 may be selectively removed by using an etching recipe having an etching selectivity with respect to the first active pattern 114 and the second active pattern 124 and the source / drain pattern SDP. The first sacrificial pattern 112 and the second sacrificial pattern 122 may be removed to form a space between the first active patterns 114 adjacent to each other in the vertical direction and a space between the second active patterns 124 adjacent to each other in the vertical direction. The space may expose the top and bottom surfaces of the first active pattern 114 and the second active pattern 124. The etching process may be a wet etching process using an etching recipe having an etching selectivity with respect to the first active pattern 114 and the second active pattern 124, the source / drain pattern SDP and / or the spacer SP.

[0036] The gate dielectric layer 140 may be formed in the gate recess region GRR. The gate dielectric layer 140 may conformally cover the surfaces of the first active pattern 114 and the second active pattern 124 exposed in the gate recess region GRR, the top surface and sidewalls of the first active fin AF1 and the second active fin AF2 exposed in the gate recess region GRR, the top surface of the device isolation layer 101 exposed in the gate recess region GRR, the inner sidewall of the spacer SP exposed in the gate recess region GRR, and / or the top surface of the interlayer dielectric layer ILD1. The gate dielectric layer 140 may include one or more of a silicon oxide layer and a high-k dielectric layer (e.g., one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and zinc lead niobate).

[0037] The first electrode layer 142 may be formed on the gate dielectric layer 140. The first electrode layer 142 may conformally cover or overlap the top surface of the gate dielectric layer 140, and may be formed to fill or at least partially fill the space between the first active patterns 114 adjacent to each other in the vertical direction with respect to the substrate and may also fill or at least partially fill the space between the second active patterns 124 adjacent to each other in the vertical direction. The first electrode layer 142 may include one or more of TiN, TaN, AlN, WN, and MoN.

[0038] The first mask pattern 144 and the second mask pattern 146 may be formed on the first active region 100a of the substrate 100. The formation of the first mask pattern 144 and the second mask pattern 146 may include: forming a first mask layer (not shown) on the first active region 100a and the second active region 100b of the substrate 100 on which the first electrode layer 142 is formed; forming a second mask pattern 146 covering or overlapping a top surface of the first mask layer on the first active region 100a of the substrate 100; and patterning the first mask layer (not shown) using the second mask pattern 146 as an etching mask to form the first mask pattern 144. On the second active region 100b of the substrate 100, the first mask pattern 144 and the second mask pattern 146 may expose the first electrode layer 142 partially covering or overlapping a top surface and a sidewall of the second active fin AF2 and a surface of the second active pattern 124. The first mask pattern 144 may have a sidewall adjacent to the second active region 100b of the substrate 100, and the sidewall of the first mask pattern 144 may have a first angle θ1 relative to the top surface of the substrate 100. The first angle θ1 may be, for example, in the range of 80° to 89°. The first mask pattern 144 may include, for example, a bottom anti-reflective coating (BARC) layer. The second mask pattern 146 may include a TiO 2 .

[0039] Reference Fig. 7A and Figure 7B , a third mask layer 148 may be formed on the first active region 100a and the second active region 100b of the substrate 100. The third mask layer 148 may cover or overlap the first electrode layer 142 formed on the second active region 100b of the substrate 100, and may also cover or overlap the sidewalls of the first mask pattern 144 and the sidewalls and top surfaces of the second mask pattern 146. The third mask layer 148 may be formed of a material having an etching selectivity relative to the first mask pattern 144. Among them, the third mask layer 148 and the first mask pattern 144 include carbon. The third mask layer 148 may be a silicon-based spin-on hard mask (Si-SOH) layer or a bottom anti-reflective coating (BARC) layer including impurities. The impurity may be, for example, silicon.

[0040] Reference Fig. 8A and Figure 8B , an upper portion of the third mask layer 148 may be etched to form a third mask pattern 150 on the second active region 100b of the substrate 100. The third mask pattern 150 may be formed by etching an upper portion of the third mask layer 148 to expose a top surface of the second mask pattern 146 and sequentially etching the exposed second mask pattern 146. Thus, a top surface of the first mask pattern 144 may be exposed. A top surface of the first mask pattern 144 may be coplanar with a top surface of the third mask pattern 150. The etching process may include an etch-back process and may use an etching recipe containing fluorine (e.g., CF 4 ). For example, the third mask pattern 150 may have a sidewall adjacent to the first active region 100a of the substrate 100, and the sidewall of the third mask pattern 150 may have a second angle θ2. The second angle θ2 may be in the range from 91° to 100°.

[0041] Reference Fig. 9A and Fig. 9B , a removal process may be performed to remove the first mask pattern 144 exposed by the third mask pattern 150 and also remove the first electrode layer 142 from the first active region 100a of the substrate 100. Thus, the removal process may expose the gate dielectric layer 140 covering or overlapping a portion of the top surface and / or sidewall of the first active fin AF1 on the first active region 100a and also covering or overlapping a portion of the surface of the first active pattern 114. Removing the first electrode layer 142 formed on the first active region 100a of the substrate 100 may form a first electrode pattern 142a on the second active region 100b of the substrate 100. The first mask pattern 144 may be removed by using H 2 / N 2The first electrode pattern 142a may be selectively removed by an ashing process. The first electrode layer 142 exposed by the third mask pattern 150 may be formed by performing a wet etching process on the first electrode layer 142. In some embodiments, the wet etching process may continue to completely remove the first electrode layer 142 formed on the first active region 100a of the substrate 100. When the first mask pattern 144 and a portion of the first electrode layer 142 are etched, the third mask pattern 150 having an etching selectivity with respect to the first mask pattern 144 and the first electrode layer 142 may not be removed.

[0042] According to some embodiments of the inventive concept, after the first mask pattern 144 is formed on the first active region 100a of the substrate 100 from which the first electrode layer 142 is to be removed, the third mask pattern 150 is formed, which is used as an etching mask to pattern the first electrode layer 142. The first mask pattern 144 may define a region in which the third mask pattern 150 is formed. The first mask pattern 144 may be used to allow the third mask pattern 150 to have an optimal interval or spacing with the first active fin AF1 formed on the first active region 100a of the substrate 100, and as a result, damage to the first electrode pattern 142a formed on the second active region 100b of the substrate 100 may be prevented and the first electrode pattern 142a is prohibited from remaining on the first active region 100a of the substrate 100.

[0043] Reference Fig.10 , the third mask pattern 150 may be removed to expose the first electrode pattern 142a. The third mask pattern 150 may be removed by a wet etching process. An etching process may be performed to partially etch the first electrode pattern 142a formed on the interlayer dielectric layer ILD1. Therefore, the first electrode pattern 142a may be partially retained in the gate recess region GRR. The first electrode pattern 142a may be located on the second active region 100b of the substrate 100 and may partially expose the gate dielectric layer 140 covering or overlapping the inner sidewall of the spacer SP. The partial etching of the first electrode pattern 142a may be completed by using one or more of an ashing process and a stripping process. The second electrode layer 152 may be formed on the first active region 100a and the second active region 100b of the substrate 100. The second electrode layer 152 may be formed to cover or overlap the top surface of the gate dielectric layer 140 and the top surface of the first electrode pattern 142a and fill the gate recess region GRR. The second electrode layer 152 may fill or at least partially fill a space between the first active fin AF1 and the lowermost first active pattern 114 and a space between the first active patterns 114. The second electrode layer 152 may include one or more of TiN, TaN, AlN, WN, and MoN.

[0044] Return to reference Figure 1A and Figure 1B , the second electrode layer 152 and the gate dielectric layer 140 may be subjected to an etching process to form a second electrode pattern 152a and a gate dielectric pattern 140a in the gate recess region GRR. The gate dielectric pattern 140a and the second electrode pattern 152a may be partially formed in the gate recess region GRR. The gate dielectric pattern 140a and the second electrode pattern 152a may be formed to be recessed from the top surface of the interlayer dielectric layer ILD1. The top surface of the interlayer dielectric layer ILD1 may be exposed by the gate dielectric pattern 140a and the second electrode pattern 152a. The etching process may include a dry etching process or a wet etching process.

[0045] The gate cap pattern 154 may be formed in the upper portion of the gate recess region GRR. The gate cap pattern 154 may be formed by forming a dielectric layer to fill or at least partially fill the upper portion of the gate recess region GRR and cover or overlap the top surface of the interlayer dielectric layer ILD1; and then performing a planarization process on the dielectric layer. The planarization process may be continued until the top surface of the interlayer dielectric layer ILD1 is exposed. The planarization process may include an etch-back process or a chemical mechanical polishing process. The gate cap pattern 154 may include a dielectric material (e.g., a silicon nitride layer).

[0046] The contact plug CP may be formed on the source / drain pattern SDP. The contact plug CP may be formed by forming a through hole to penetrate the interlayer dielectric layer ILD1 and expose the top surface of the source / drain pattern SDP, and then filling the through hole with a conductive material. The contact plug CP may include, for example, one or more of a metal nitride (e.g., TiN, TaN, AlN, WN, or MoN), a metal (e.g., W, Al, or Cu), and a semiconductor silicide.

[0047] Semiconductor devices according to some embodiments of the inventive concept may include a tunneling field effect transistor, a transistor including a nanowire, a transistor including a nanosheet (or a multi-bridge channel field effect transistor (MBCFET)), or a three-dimensional (3D) transistor.

[0048] Fig.11A , Fig. 12A , Fig.13A and Fig.14A A top view illustrating a method of fabricating a semiconductor device according to some example embodiments of the inventive concepts. Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B A method of manufacturing a semiconductor device according to some example embodiments of the present inventive concept is shown along the Fig.11A , Fig. 12A , Fig.13A and Fig.14ACross-sectional views taken along lines II', II-II' and III-III'.

[0049] Reference Fig.11A and Fig. 11B Together with Fig. 8A and Figure 8B , an etching process may be performed on the first mask pattern 144 and the first electrode layer 142 formed on the first active region 100a of the substrate 100. Thus, a residual electrode pattern 142b may be formed on the first active region 100a of the substrate 100, and the first electrode pattern 142a may be formed on the second active region 100b of the substrate 100. The residual electrode pattern 142b may be formed in a space between the first active fin AF1 and the lowermost first active pattern 114 adjacent to each other in a vertical direction with respect to the substrate and in a space between the first active patterns 114 adjacent to each other in the vertical direction. The first mask pattern 144 may be formed by using H 2 / N 2 The first electrode pattern 142a and the residual electrode pattern 142b may be formed by partially etching the first electrode layer 142, which is exposed by the third mask pattern 150 and covers or overlaps the sidewalls of the first active fins AF1, the sidewalls of the first active pattern 114, the top surface of the device isolation layer 101, and / or the top surface of the uppermost first active pattern 114. The etching process for the first electrode layer 142 may be a wet etching process, and the etching time may be controlled so that the first electrode layer 142 may be partially etched to leave a portion of the first electrode layer 142.

[0050] Reference Fig. 12A and Fig. 12B , the third mask pattern 150 may be removed. Thus, the first electrode pattern 142a may be exposed.

[0051] A fourth mask pattern 160 and a fifth mask pattern 162 may be formed on the first active region 100a of the substrate 100. The fourth mask pattern 160 may fill or at least partially fill the gate recess region GRR formed on the first active region 100a of the substrate 100, and may cover the top surface of the gate dielectric layer 140 formed on the first active region 100a of the substrate 100. The fifth mask pattern 162 may be formed on the top surface of the fourth mask pattern 160. The formation of the fourth mask pattern 160 and the fifth mask pattern 162 may include: forming a fourth mask layer (not shown) on the first active region 100a and the second active region 100b of the substrate 100; forming the fifth mask pattern 162 on the first active region 100a of the substrate 100 to cover or overlap the top surface of the fourth mask layer; and patterning the fourth mask layer using the fifth mask pattern 162 as an etching mask. The fourth mask pattern 160 may completely expose the first electrode pattern 142a. The fourth mask pattern 160 may be formed to be physically spaced apart from the first electrode pattern 142a. The fourth mask pattern 160 may have a sidewall adjacent to the second active region 100b of the substrate 100, and the sidewall of the fourth mask pattern 160 may have a third angle θ3 relative to the top surface of the substrate 100. The third angle θ3 may be in a range from 80° to 89°. The fourth mask pattern 160 may include a bottom anti-reflective coating (BARC) layer. The fifth mask pattern 162 may include, for example, TiO 2 .

[0052] Reference Fig.13A and Fig. 13B , a sixth mask pattern 164 may be formed on the second active region 100b of the substrate 100. The sixth mask pattern 164 may be formed to completely cover or overlap the first electrode pattern 142a formed on the second active region 100b of the substrate 100. The sixth mask pattern 164 may be a silicon-based spin-on hard mask (Si-SOH) layer or a bottom anti-reflective coating (BARC) layer including impurities (e.g., silicon). The sixth mask pattern 164 may be formed by forming a sixth mask layer (not shown) to cover or overlap the first electrode pattern 142a, the sidewalls of the fourth mask pattern 160, and / or the sidewalls and top surface of the fifth mask pattern 162, and then etching the upper portion of the sixth mask layer. The fifth mask pattern 162 may be successively removed by etching the upper portion of the sixth mask layer. The etching process for the upper portion of the sixth mask layer and the fifth mask pattern 162 may include an etch-back process and may use a fluorine-containing etching recipe (e.g., CF 4). The fifth mask pattern 162 may be removed to expose a top surface of the fourth mask pattern 160, and the top surface of the fourth mask pattern 160 may be coplanar with a top surface of the sixth mask pattern 164. The sixth mask pattern 164 may have a sidewall adjacent to the first active region 100a of the substrate 100, and the sidewall of the sixth mask pattern 164 may have a fourth angle θ4 with respect to the top surface of the substrate 100. The fourth angle θ4 may be in a range from 91° to 100°.

[0053] Reference Fig.14A and Fig. 14B , the fourth mask pattern 160 may be removed. Thus, the gate dielectric layer 140 formed on the first active region 100a of the substrate 100 may be exposed, and the sidewall of the sixth mask pattern 164 adjacent to the first active region 100a of the substrate 100 may be exposed. The fourth mask pattern 160 may be removed by using H 2 / N 2 The gate dielectric layer 140 may be selectively removed by an ashing process of the sixth mask pattern 164. An etching process may be performed to remove the residual electrode pattern 142b exposed by the sixth mask pattern 164. Removal of the residual electrode pattern 142b may expose the gate dielectric layer 140 covering or overlapping the top surface and sidewall of the first active fin AF1 and also covering or overlapping the top surface and bottom surface of the first active pattern 114. The etching process may include one or more of a wet etching process, an ashing process, and a stripping process.

[0054] Subsequent processes will be omitted as they are related to the above reference Fig. 9A , Fig. 9B and Fig.10 The process discussed is the same.

[0055] According to some embodiments of the present inventive concept, after a first mask pattern is formed on a first region of a substrate from which a first electrode layer is to be removed, a second mask pattern may be formed that serves as an etching mask to pattern the first electrode layer. The first mask pattern may define a region in which the second mask pattern is formed. The first mask pattern may be used to allow the second mask pattern to have an optimal spacing or pitch with the first active fin formed on the first region of the substrate, and as a result, damage to the first electrode pattern formed on the second region of the substrate may be prevented or reduced and the possibility of the first electrode pattern remaining on the first region of the substrate may be inhibited or reduced.

[0056] Although the present invention has been described in conjunction with some example embodiments of the inventive concept shown in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential features of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the inventive concept.

[0057] This application claims the priority of Korean Patent Application No. 10-2019-0104026 filed on August 23, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a plurality of first active patterns on the first active fin of the substrate, wherein the plurality of first active patterns are spaced apart from each other by a first distance in a direction perpendicular to the substrate; forming a plurality of second active patterns on the second active fin of the substrate, wherein the plurality of second active patterns are spaced apart from each other by a second distance in the direction perpendicular to the substrate, wherein the substrate includes a first region on which the first active fin is formed and a second region on which the second active fin is formed; forming a first electrode layer extending on top surfaces and sidewalls of the first active fin and the second active fin and extending on surfaces of the first active pattern and the second active pattern; forming a first mask pattern extending on the first electrode layer formed on the first region of the substrate; forming a second mask pattern extending on the first electrode layer formed on the second region of the substrate; as well as The first mask pattern and portions of the first electrode layer on the first area of ​​the substrate are etched using the second mask pattern as an etching mask, and a first electrode pattern is formed on the second area of ​​the substrate by partially etching the first electrode layer formed on the first area of ​​the substrate to form a plurality of residual electrode patterns between the first active patterns and between the first active fins and a lowermost one of the first active patterns.

2. The method according to claim 1, wherein the first mask pattern and the second mask pattern include carbon, and The first mask pattern and the second mask pattern include materials having an etching selectivity relative to each other.

3. The method according to claim 1, wherein the first mask pattern comprises a bottom anti-reflective coating (BARC) layer, and The second mask pattern includes a silicon-based spin-on hard mask (Si-SOH) layer. 4 . The method according to claim 1 , wherein widths of the first active fin and the first active pattern are respectively greater than widths of the second active fin and the second active pattern.

5. The method according to claim 1, wherein forming the first active fin, the first active pattern, the second active fin, and the second active pattern comprises: forming a plurality of sacrificial layers and a plurality of active layers alternately and repeatedly stacked on the substrate; patterning the sacrificial layer and the active layer to form a plurality of first sacrificial patterns and the plurality of first active patterns alternately stacked on the first active fins and to form a plurality of second sacrificial patterns and the plurality of second active patterns alternately stacked on the second active fins; as well as The first sacrificial pattern and the second sacrificial pattern are selectively removed.

6. The method according to claim 1, wherein a sidewall of the first mask pattern has an angle relative to a top surface of the substrate, wherein the sidewall of the first mask pattern is adjacent to the second region of the substrate, and Wherein the angle relative to the top surface of the substrate is in a range from 80° to 89°. 7 . The method of claim 1 , wherein forming the first electrode pattern on the second region of the substrate comprises completely removing the first electrode layer formed on the first region.

8. The method according to claim 1, further comprising: removing the second mask pattern to expose the first electrode pattern; forming a third mask pattern on the first area of ​​the substrate, the third mask pattern exposing the first electrode pattern; forming a fourth mask pattern on the second area of ​​the substrate, wherein the fourth mask pattern extends on the first electrode pattern; as well as The third mask pattern and the residual electrode pattern are removed using the fourth mask pattern as an etching mask. 9 . The method of claim 8 , wherein the fourth mask pattern is formed to extend entirely on the first electrode pattern.

10. The method according to claim 1, further comprising: forming a sacrificial gate pattern on the first active fin, the first active pattern, the second active fin, and the second active pattern; forming a plurality of spacers on sidewalls of the sacrificial gate pattern; as well as removing the sacrificial gate pattern to form a gate recess region, The first electrode layer is formed to extend on the top surface and the sidewall of the first active fin and the second active fin and on the surface of the first active pattern and the second active pattern, and the top surface and the sidewall of the first active fin and the second active fin and the surface of the first active pattern and the second active pattern are exposed to the gate recess area.

11. The method according to claim 1, further comprising: removing the second mask pattern; as well as A second electrode layer extending on the first electrode pattern, the first active fin, and the first active pattern is formed on the first region and the second region of the substrate.

12. A method for manufacturing a semiconductor device, the method comprising: forming a plurality of first active patterns on the first active fin of the substrate, wherein the plurality of first active patterns are spaced apart from each other by a first distance in a direction perpendicular to the substrate; forming a plurality of second active patterns on the second active fin of the substrate, wherein the plurality of second active patterns are spaced apart from each other by a second distance in the direction perpendicular to the substrate, wherein the substrate includes a first region on which the first active fin is formed and a second region on which the second active fin is formed; forming a first electrode layer extending on top surfaces and sidewalls of the first active fin and the second active fin and on surfaces of the first active pattern and the second active pattern; forming a first mask pattern extending on the first electrode layer formed on the second region of the substrate; as well as etching a portion of the first electrode layer on the first region using the first mask pattern as an etching mask to form a first electrode pattern on the second region of the substrate, wherein a sidewall of the first mask pattern has an angle relative to a top surface of the substrate, wherein the sidewall of the first mask pattern is adjacent to the first region of the substrate, wherein the angle relative to the top surface of the substrate is in the range from 91° to 100°, and Wherein forming the first electrode pattern on the second area of ​​the substrate includes completely removing the first electrode layer formed on the first area.

13. The method of claim 12 , wherein forming the first electrode pattern on the second area of ​​the substrate comprises partially etching the first electrode layer extending on a top surface of an uppermost one of the first active patterns, sidewalls of the first active pattern, and the sidewalls of the first active fin to form a plurality of residual electrode patterns between the first active patterns and between the first active fin and a lowermost one of the first active patterns.

Images