A method for producing NLDMOS device and NLDMOS device

Abstract

The embodiment of the present invention provides a method for producing an NLDMOS device, and also provides an NLDMOS device obtained by the method. The method comprises first providing a low-resistance P+ type substrate, then forming a BN region, two STI regions and an Nwell layer on the low-resistance P+ type substrate, then etching PB regions respectively inside the STI regions, then growing gate oxide and forming a gate on the low-resistance P+ type substrate, generating a source region in the PB region, and finally etching a deep hole region between the PB regions, and after filling the deep hole region, metal deposition and etching are performed to form a drain region. The area of ​​the NLDMOS device produced by the method provided by the present invention is greatly reduced, so that the device with current detection function can be integrated.

Description

Technical Field

[0001] The present invention relates to the field of lithium battery protection, and in particular to a method for producing an NLDMOS device, and an NLDMOS device obtained by the method. Background Art

[0002] Traditional lithium battery protection devices are just conventional power devices. In actual application scenarios, a high-precision sampling resistor must be installed externally. Only by sampling the voltage on the sampling resistor can precise control of the circuit be achieved.

[0003] However, for a large-capacity battery, the resistance value of the sampling resistor will greatly increase the total resistance value in the entire loop, thereby increasing the power consumption of the system and greatly reducing the standby time of the entire machine. Therefore, how to improve the NLDMOS device and provide a smaller NLDMOS device so that a power device with a current detection function can be integrated, thereby avoiding the use of a sampling resistor and solving the current problem is a problem that the present invention needs to solve. Summary of the invention

[0004] The present invention provides a device for lithium battery protection, which solves the problem in the prior art that the resistance value of a sampling resistor affects the total resistance value in a loop, thereby causing a decrease in the standby time of the whole device.

[0005] In order to solve the above technical problems, a technical solution adopted by the present invention is to provide a method for producing an NLDMOS device, comprising:

[0006] First, a low-resistance P+ substrate is provided;

[0007] Forming a BN region, two STI regions and a Nwell layer on the low-resistance P+ type substrate;

[0008] Etching a PB region between the two STI regions respectively;

[0009] Growing gate oxide on the low-resistance P+ substrate to form a gate;

[0010] generating a source region in the PB region;

[0011] A deep hole region is etched between the PB regions, and after the deep hole region is filled, metal is deposited and etched to form a drain region.

[0012] Furthermore, the step of forming a BN region, two STI regions and an Nwell layer on a low-resistance P+ substrate includes:

[0013] The element antimony is selectively implanted into the low-resistance P+ substrate and undergoes a thermal process to form a BN region;

[0014] Etching STI regions at both sides of the low-resistance P+ substrate, filling the STI regions, and performing CMP polishing;

[0015] Nwell is injected into the low-resistance P+ substrate, and diffuses through a thermal process to form an Nwell layer.

[0016] Furthermore, in the step of selectively implanting antimony into the low-resistance P+ substrate, the dose of antimony implanted is X / cm 2 , the value of X is: 1e12≦X≦1e14.

[0017] Furthermore, in the step of injecting Nwell into the low-resistance P+ substrate, the dose of Nwell is N / cm 2 , the value of N is: 1e12≦N≦1e14.

[0018] Furthermore, the step of respectively etching a PB region between two STI regions includes:

[0019] Using a photomask to etch out preliminary PB regions respectively between the two STI regions;

[0020] Implant B ions, the dose of implanted B ions is M / cm 2 , the value of M is: 1e12≦M≦1e14, forming the final PB region;

[0021] Furthermore, the step of growing gate oxide on the low-resistance P+ type substrate and forming a gate includes:

[0022] Growing a gate oxide on the upper surface of the low-resistance P+ substrate, wherein the thickness of the gate oxide is about 100 Å-150 Å;

[0023] Polysilicon is then deposited on the gate oxide, and the polysilicon is etched using a gate photomask to form the final gate.

[0024] Furthermore, the step of generating a source region in the PB region includes:

[0025] Using N+ and P+ photomasks, metals are respectively implanted into the PB region to form an active region N+ region P+ type contact region, and then undergo RTA activation;

[0026] Holes are drilled in the active area N+ region and the active area P+ region, and metal is deposited and etched to form source contacts.

[0027] Furthermore, the step of etching a deep hole region between the PB regions and filling the deep hole region, and then depositing and etching metal to form a drain region comprises:

[0028] Etching a deep hole region between the PB regions, wherein one end of the deep hole region is aligned with the top of the low-resistance P+ type substrate, and the other end is in contact with the BN region;

[0029] Filling the deep hole area with metal;

[0030] Then metal deposition and etching are performed to form electrical connections;

[0031] Lead out the drain.

[0032] In order to solve the above technical problems, another technical solution adopted by the present invention is to provide an NLDMOS device, wherein the NLDMOS device is obtained by any of the above methods for producing the NLDMOS device, and the NLDMOS device comprises:

[0033] BN area;

[0034] an N-type well region located above the BN region;

[0035] A deep hole region is located in the N-type well region, the deep hole region is connected to the BN region, and a metal lead-out drain is filled in the deep hole region, so that the drain N+ region is conductive with the BN region.

[0036] Furthermore, the current of the NLDMOS device flows out from the active region N+ area and directly flows into the BN terminal, and then flows out through the drain hole of the BN terminal.

[0037] The beneficial effects of the present invention are as follows: the present invention provides a method for producing an NLDMOS device, and also provides an NLDMOS device obtained by the method. The method comprises first providing a low-resistance P+ type substrate, then forming a BN region, two STI regions and an Nwell layer on the low-resistance P+ type substrate, then etching PB regions respectively inside the STI regions, then growing gate oxide and forming a gate on the low-resistance P+ type substrate, generating a source region in the PB region, and finally etching a deep hole region between the PB regions, and after filling the deep hole region, metal deposition and etching are performed to form a drain region. The area of ​​the NLDMOS device produced by the method provided by the present invention is greatly reduced, so that the device with current detection function can be integrated. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the structure of a traditional NLDMOS device;

[0039] Figures 2 to 7 It is a schematic diagram of the structure of the NLDMOS device presented in each step of the method for producing the NLDMOS device of the present invention;

[0040] Figure 8It is a schematic diagram of the structure of the NLDMOS device in the present invention. DETAILED DESCRIPTION

[0041] In order to facilitate the understanding of the present invention, the present invention is described in more detail below in conjunction with the accompanying drawings and specific embodiments. Preferred embodiments of the present invention are provided in the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0042] It should be noted that, unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more related listed items.

[0043] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a traditional NLDMOS device. In the traditional NLDMOS device structure, Nwell is used as the withstand voltage area and PB is used as the channel area. Electrons flow out from the N+ in the PB and then flow into the N+ area of ​​the Drain. For integrated devices, the resistance of the N+ lead-out area will seriously restrict the on-resistance of the entire device, and the area of ​​the N+Drain area needs to be expanded. However, as the area increases, the area of ​​the device will also increase, so there is a restriction relationship.

[0044] See also Figures 2 to 7 , which is a schematic diagram of the structure of the NLDMOS device presented in each step of the method for producing the NLDMOS device in this embodiment.

[0045] exist Figure 2 In the process, a low-resistance P+ substrate wafer is first provided as a substrate.

[0046] Then, a BN region, two STI regions and an Nwell layer are formed on the low-resistance P+ substrate. The device structure formed finally is as follows: Figure 3 As shown. Specifically:

[0047] First, the element antimony is selectively implanted into the low-resistance P+ substrate and undergoes a thermal process to form a BN region; the dose of the implanted element antimony is X / cm 2 , the value of X is: 1e12≦X≦1e14;

[0048] The steps of forming the STI region are: etching the STI region at both sides of the low-resistance P+ substrate, filling the STI region, and performing CMP polishing;

[0049] The steps of forming the Nwell layer are: injecting P ions into the low-resistance P+ substrate, and then diffusing to form the Nwell layer after a thermal process. The dose of the injected Nwell is N / cm 2 , the value of N is: 1e12≦N≦1e14.

[0050] exist Figure 3 Based on the above, a preliminary PB region is etched on the inner side of each STI region using a photoresist, and then B ions are implanted into the preliminary PB region. The dose of implanted B ions is M / cm 2 , the value of M is: 1e12≦M≦1e14, forming the final PB region; the final device structure is as follows Figure 4 shown.

[0051] exist Figure 4 On the basis of the structure, an oxide layer is grown on the side wall of the Trench area as the gate oxide, and the thickness of the gate oxide ranges from 100A to 150A. Then, polysilicon is deposited on the gate oxide, and the polysilicon is etched using the gate photomask to form the final gate. Then, metal is injected into the PB areas on both sides using the N+ and P+ photomasks to form the active area N+ area P+ type contact area, and undergo RTA activation. Then, holes are punched in the active area N+ area P+ type contact area, and the metal is deposited and etched to form the source contact. The final device structure is as follows: Figure 5 shown.

[0052] exist Figure 5 On the basis of , a deep hole area is etched in the middle of the PB area on both sides. One end of the deep hole area is aligned with the top of the low-resistance P+ type substrate, and the other end is in contact with the BN area. The device structure finally formed is as follows Figure 6 shown.

[0053] exist Figure 6 On the basis of the , the deep hole area is filled with metal. The metal used for filling can be aluminum, or it can be tungsten or nickel. Then metal deposition and etching are performed to form electrical connections, and the drain is led out to form electrical connections; then the source is led out from the active area N+ area P+ type contact area of ​​the PB area on both sides to form electrical connections. The final device structure is as follows Figure 7 shown.

[0054] A method for producing an NLDMOS device provided in this embodiment provides a low-resistance P+ type substrate, forms a BN region, two STI regions and an Nwell layer on the low-resistance P+ type substrate, opens a deep hole region in the drain region, fills the deep hole region with metal leads, so that the current flows directly into the BN terminal after flowing out of the N+PB, and then is led out through the drain hole at the BN terminal; the NLDMOS device produced by the method in this embodiment not only greatly reduces the area of ​​the device, but also expands the lead-out area of ​​the current for the BN region of the drain lead-out, reduces the on-resistance, and improves the current density of the device.

[0055] like Figure 8 As shown, a novel NLDMOS device proposed in the present invention includes a BN region, an N-type well region is injected and diffused through a thermal process to form a final N-type well region, and the N-type well region is located above the BN region; the NLDMOS device also includes a drain region arranged in the N-type well region, a deep hole region is opened in the drain region, connected to the BN region, and a metal lead is filled in the deep hole region, so that the current flows out of the N+PB and directly flows into the BN end, and then is led out through the drain hole at the BN end.

[0056] The NLDMOS device in this embodiment includes a first P-type well region 101 and a second P-type well region 102, wherein the first P-type well region 101 and the second P-type well region 102 are respectively located on both sides of the deep hole region. The first P-type well region 101 includes a first N-type source region 103 and a first P+ type contact region 104, wherein the first N-type source region 103 and the first P+ type contact region 104 are arranged side by side; the second P-type well region 102 includes a second N-type source region 105 and a second P+ type contact region 106, wherein the second N-type source region 105 and the second P+ type contact region 106 are arranged side by side.

[0057] The NLDMO device further includes a first source 107, which is led out from the first N-type source region 103 and the first P+ type contact region 104; a second source 108, which is led out from the second N-type source region 105 and the second P+ type contact region 106. A first gate 109, which is located between the first source 107 and the drain; and a second gate 110, which is located between the second source 108 and the drain.

[0058] The NLDMO device in this embodiment opens a deep hole area in the drain area of ​​the device and fills the deep hole area with metal leads, so that the current flows out of N+PB and directly flows into the BN terminal, and then is led out through the drain hole at the BN terminal. This reduces the area of ​​the device, but for the BN area of ​​the drain lead, the current lead-out area is expanded and the on-resistance is reduced.

[0059] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for producing an NLDMOS device, characterized in that: The method comprises: First, a low-resistance P+ substrate is provided; Forming a BN region, two STI regions and a Nwel l layer on the low-resistance P+ type substrate; Etching a PB region between the two STI regions respectively; Growing gate oxide on the low-resistance P+ substrate to form a gate; Generating a source region in the PB region, wherein the source region includes an active N+ region and a P+ type contact region; A deep hole region is etched between the PB regions, the deep hole region is connected to the BN region, and after the deep hole region is filled, metal deposition and etching are performed to form a drain region, so that the current of the NLDMOS device flows out from the active area N+ region and then flows into the drain region, and then flows out through the drain hole of the BN region.

2. The method according to claim 1, characterized in that The step of forming a BN region, two STI regions and a Nwel l layer on a low-resistance P+ type substrate comprises: The element antimony is selectively implanted into the low-resistance P+ substrate and undergoes a thermal process to form a BN region; Etching STI regions at both sides of the low-resistance P+ substrate, filling the STI regions, and performing CMP polishing; Nwel l is injected into the low-resistance P+ type substrate, and diffused through a thermal process to form a Nwel l layer.

3. The method according to claim 2, characterized in that The dosage of the antimony element injected in the step of selectively injecting antimony element into the low-resistance P+ substrate is X / cm 2 , the value of X is: 1e12≦X≦1e14.

4. The method according to claim 2, characterized in that: In the step of injecting Nwel l into the low-resistance P+ type substrate, the dose of Nwel l is N / cm 2 , the value of N is: 1e12≦N≦1e14.

5. The method according to claim 2, characterized in that: The step of respectively etching a PB region between two STI regions comprises: Using a photomask to etch out preliminary PB regions respectively between the two STI regions; Implant B ions, the dose of implanted B ions is M / cm 2 , the value of M is: 1e12≦M≦1e14, forming the final PB area.

6. The method according to claim 5, characterized in that The step of growing gate oxide and forming a gate on the low-resistance P+ type substrate comprises: Growing a gate oxide on the upper surface of the low-resistance P+ substrate, wherein the thickness of the gate oxide is 100 Å-150 Å; Polysilicon is then deposited on the gate oxide, and the polysilicon is etched using a gate photomask to form the final gate.

7. The method according to claim 5, characterized in that The step of generating a source region in the PB region further comprises: Using N+ and P+ photomasks, metals are respectively implanted into the PB region to form an active region N+ region P+ type contact region, and then undergo RTA activation; Holes are drilled in the active area N+ region and the active area P+ region, and metal is deposited and etched to form source contacts.

8. The method according to claim 7, characterized in that The step of etching a deep hole region between the PB regions and filling the deep hole region, and then depositing and etching metal to form a drain region comprises: Etching a deep hole region between the PB regions, wherein one end of the deep hole region is aligned with the top of the low-resistance P+ type substrate, and the other end is in contact with the BN region; Filling the deep hole area with metal; Then metal deposition and etching are performed to form electrical connections; Lead out the drain.

9. An NLDMOS device, characterized in that: The NLDMOS device is produced by any one of the production methods described in claim 1 to claim 8, and the NLDMOS device comprises: BN area; an N-type well region located above the BN region; A deep hole region located in the N-type well region, the deep hole region is connected to the BN region, and a metal is filled in the deep hole region to lead out the drain, so that the drain N+ region is conductive with the BN region; The current of the NLDMOS device flows out from the active region N+ region, flows into the drain region, and then flows out through the drain hole of the BN region.

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