Semiconductor device, power module, and method for manufacturing semiconductor device

Abstract

The invention comprises: a conductive semiconductor substrate (10) having a first main surface (11) and a second main surface (12) facing each other, and a groove formed on the first main surface (11); and a plurality of conductive layers stacked along the surface normal direction of the side surface of the groove, namely a first conductive layer (2A) and a second conductive layer (2B); dielectric layers (30) respectively arranged between the conductive layer closest to the side surface of the groove and the side surface of the groove, and between the plurality of conductive layers; a first electrode (41) arranged outside the groove and electrically connected to the first conductive layer (2A); and a second electrode (42) arranged outside the groove and electrically connected to the second conductive layer (2B), wherein the first conductive layer (2A) is electrically insulated from the semiconductor substrate (10), and the semiconductor substrate (10) electrically connected to the second conductive layer (2B) inside the groove is electrically connected to the second electrode (42).

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a semiconductor capacitor, a power module, and a method for manufacturing the semiconductor device. Background Art

[0002] As a semiconductor capacitor, a capacitor structure is used in which a capacitor structure is formed inside a groove formed on the surface of a semiconductor substrate. For example, a capacitor structure in which conductive layers and dielectric layers are alternately stacked inside a groove is disclosed (see Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application No. 2009-515353

[0006] However, the capacitor structure described in Patent Document 1 is configured such that a portion of the conductive layer formed inside the groove is extended to the surface of the semiconductor substrate, and positive and negative electrodes are respectively provided on the conductive layer on the surface of the semiconductor substrate. That is, when the charge is charged from the electrode to the conductive layer formed along the inner wall surface of the groove, the current path flowing through the conductive layer becomes longer before the charge is filled to the entire conductive layer. Therefore, there is a problem of an increase in the equivalent series resistance (ESR) between the conductive layer and the electrode at the portion where the conductive layer is formed thinner inside the groove. Summary of the invention

[0007] An object of the present invention is to provide a semiconductor device, a power module, and a method for manufacturing a semiconductor device, which can suppress an increase in the equivalent series resistance of a capacitor structure formed inside a groove of a semiconductor substrate.

[0008] The gist of a semiconductor device of one embodiment of the present invention is that it comprises: a first conductive layer and a second conductive layer, which are stacked via a dielectric layer inside a groove formed on a first main surface of a conductive semiconductor substrate, a first electrode, which is electrically connected to the first conductive layer; and a second electrode, which is electrically connected to the second conductive layer. The first conductive layer is electrically insulated from the semiconductor substrate, and the semiconductor substrate electrically connected to the second conductive layer inside the groove is electrically connected to the second electrode.

[0009] The main purpose of a power module in another embodiment of the present invention is to form a combination of a semiconductor device and a power semiconductor element electrically connected to a main electrode and a first electrode or a second electrode of the semiconductor device, wherein the semiconductor device forms a capacitor structure by stacking a first conductive layer and a second conductive layer inside a groove formed on a first main surface of a conductive semiconductor substrate via a dielectric layer, and comprises: a first electrode electrically connected to the first conductive layer, and a second electrode electrically connected to the second conductive layer and the semiconductor substrate.

[0010] The gist of a method for manufacturing a semiconductor device in another embodiment of the present invention is to include: a process of stacking a first conductive layer and a second conductive layer inside a groove on a first main surface of a conductive semiconductor substrate via a dielectric layer; a process of removing the first conductive layer and the dielectric layer formed at the bottom of the groove in order to electrically connect the second conductive layer to the semiconductor substrate at the bottom of the groove, and after covering the outside of the groove on the first main surface with an insulating protective film, removing the first conductive layer and the dielectric layer formed at the bottom of the groove.

[0011] Effects of the Invention

[0012] According to the present invention, it is possible to provide a semiconductor device, a power module, and a method for manufacturing a semiconductor device that can suppress an increase in the equivalent series resistance of a capacitor structure formed inside a groove of a semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic cross-sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention.

[0014] Figure 2 It is a schematic cross-sectional view showing the structure of a semiconductor device according to a comparative example.

[0015] Figure 3 This is a schematic cross-sectional view for explaining a current path of the semiconductor device according to the first embodiment of the present invention.

[0016] Figure 4 This is a schematic cross-sectional view (part 1) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0017] Figure 5 This is a schematic cross-sectional view (part 2) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0018] Figure 6 This is a schematic cross-sectional view (part 3) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0019] Figure 7 This is a schematic cross-sectional view (part 4) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0020] Figure 8 This is a schematic cross-sectional view (part 5) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0021] Fig. 9 This is a schematic cross-sectional view (part six) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0022] Fig.10This is a schematic cross-sectional view (part 7) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0023] Fig.11 This is a schematic cross-sectional view (eighth) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0024] Fig.12 This is a schematic cross-sectional view (part 9) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0025] Fig.13 This is a schematic cross-sectional view (the tenth) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0026] Fig.14 This is a schematic cross-sectional view (No. 11) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0027] Fig.15 This is a schematic cross-sectional view (part 12) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0028] Fig.16 This is a schematic cross-sectional view (part 13) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

[0029] Fig.17 It is a schematic perspective view showing the structure of a cooling device in which the semiconductor device according to the first embodiment of the present invention is arranged.

[0030] Fig.18 This is a schematic perspective view showing another structure of the cooling device in which the semiconductor device according to the first embodiment of the present invention is arranged.

[0031] Fig.19 This is a schematic perspective view showing a power module using the semiconductor device according to the first embodiment of the present invention.

[0032] Fig. 20 yes Fig.19 The circuit diagram of the power module is shown.

[0033] Fig.21 It is a schematic cross-sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.

[0034] Fig. 22 This is a schematic cross-sectional view (part 1) for explaining a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

[0035] Fig.23 This is a schematic cross-sectional view (part 2) for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

[0036] Fig.24 This is a schematic cross-sectional view (part 3) for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

[0037] Fig.25 This is a schematic cross-sectional view (part 4) for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

[0038] Fig.26 This is a schematic cross-sectional view (part 5) for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

[0039] Fig. 27 This is a schematic cross-sectional view (part six) for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

[0040] Fig.28 It is a schematic cross-sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention.

[0041] Fig.29 This is a schematic cross-sectional view (part 1) for explaining a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[0042] Fig.30 This is a schematic cross-sectional view (part 2) for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

[0043] Fig.31 This is a schematic cross-sectional view (part 3) for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

[0044] Fig.32 This is a schematic cross-sectional view (fourth) for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0045] The following is an explanation of the embodiments with reference to the accompanying drawings. In the description of the drawings, the same symbols are used for the same parts and the description is omitted. However, the drawings are schematic, and the relationship between the thickness and the plane size, the ratio of the thickness of each layer, etc., contain parts that are different from the actual. In addition, the drawings also contain parts with different size relationships and ratios.

[0046] (First Embodiment)

[0047] Figure 1 The semiconductor device 1 of the first embodiment of the present invention shown has a first main surface 11 and a second main surface 12 facing each other, and includes: a conductive semiconductor substrate 10 with a groove formed on the first main surface 11, and a plurality of conductive layers stacked along the surface normal direction of the side surface of the groove. Figure 1It is a cross-sectional view along the short-side direction of the groove formed in the first main surface 11 .

[0048] The plurality of conductive layers disposed inside the groove are either the first conductive layer 2A or the second conductive layer 2B. Hereinafter, the first conductive layer 2A and the second conductive layer 2B are collectively referred to as "conductive layer 20". Figure 1 In the semiconductor device 1 shown, the conductive layer on the side of the groove in the conductive layer 20 is the first conductive layer, and the odd-numbered conductive layers in the conductive layer 20 are the first conductive layers 2A. That is, the conductive layers 21 and 23 are the first conductive layers 2A. On the other hand, the even-numbered conductive layers in the conductive layer 20 are the second conductive layers 2B. That is, the conductive layer 22 is the second conductive layer 2B.

[0049] like Figure 1 As shown in FIG. 1 , dielectric layers 31 to 33 (hereinafter collectively referred to as “dielectric layers 30”) are respectively arranged between the conductive layer closest to the side of the groove in the conductive layer 20 and the side of the groove, and between the conductive layers 20. That is, the dielectric layer 31 is arranged between the side of the groove and the conductive layer 21, the dielectric layer 32 is arranged between the conductive layer 21 and the conductive layer 22, and the dielectric layer 33 is arranged between the conductive layer 22 and the conductive layer 23. The stacking of the first conductive layer 2A, the dielectric layer 30, and the second conductive layer 2B forms a capacitor.

[0050] The first conductive layer 2A is electrically insulated from the semiconductor substrate 10 by the dielectric layer 30. On the other hand, the second conductive layer 2B is electrically connected to the semiconductor substrate 10 inside the groove. Figure 1 As shown, at the bottom of the groove, the lower end of the second conductive layer 2B contacts the semiconductor substrate 10 .

[0051] The semiconductor device 1 further includes a first electrode 41 electrically connected to the first conductive layer 2A and a second electrode 42 electrically connected to the second conductive layer 2B. The first electrode 41 and the second electrode 42 are arranged outside the groove.

[0052] exist Figure 1 In the semiconductor device 1 shown, a first electrode 41 is arranged on the first main surface 11 of the semiconductor substrate 10, and the first electrode 41 and the first conductive layer 2A are connected outside the groove. That is, a part of the first conductive layer 2A formed inside the groove extends to the first main surface 11, and the first conductive layer 2A is electrically connected to the first main surface 11. Figure 1 The first main surface 11 of the semiconductor device 1 shown in the figure is further provided with a dielectric layer 30 extending from the inside of the groove to the first main surface 11, and an insulating protective film 51 and an insulating protective film 52 formed on the outside of the groove. The first electrode 41 is connected to the first conductive layer 2A at the opening provided in the dielectric layer 30, the insulating protective film 51 and the insulating protective film 52. The details of the insulating protective film 51 and the insulating protective film 52 will be described later.

[0053] The second electrode 42 is disposed on the second main surface 12 of the semiconductor substrate 10 . Since the second conductive layer 2B is electrically connected to the semiconductor substrate 10 inside the groove, the second electrode 42 is electrically connected to the second conductive layer 2B via the conductive semiconductor substrate 10 .

[0054] The following explains Figure 1 The operation of the semiconductor device 1 shown. When a positive voltage is applied to the first electrode 41 and a negative voltage is applied to the second electrode 42, positive charges charge the first conductive layer 2A, and negative charges charge the side walls of the grooves formed on the semiconductor substrate 10 and the second conductive layer 2B. Then, polarization occurs inside the dielectric layer 30, generating electrostatic capacitance. At this time, the conductive layer 21 of the first conductive layer 2A is electrically connected to the conductive layer 23, and the conductive layer 22 of the second conductive layer 2B is electrically connected to the semiconductor substrate 10. Therefore, the semiconductor device 1 is a structure in which three capacitors having the dielectric layer 31, the dielectric layer 32, and the dielectric layer 33 are connected in parallel. In this way, according to Figure 1 The semiconductor device 1 shown can realize a capacitor structure having a significantly improved capacitance density per unit area.

[0055] In addition, according to the semiconductor device 1, the equivalent series resistance (ESR) of the capacitor structure can be reduced. Figure 2 The reduction in ESR of the semiconductor device 1 will be described by comparison with the semiconductor device of the comparative example shown.

[0056] Figure 2 The semiconductor device shown has a structure in which a conductive layer 20a and a conductive layer 20b are stacked inside a groove formed on the first main surface 11 of a conductive semiconductor substrate 10. A dielectric layer 30a is located between the side of the groove and the conductive layer 20a, and a dielectric layer 30b is located between the conductive layer 20a and the conductive layer 20b. The remaining area of ​​the groove is buried by a dielectric layer 30c. In this way, Figure 2 The semiconductor device shown has a capacitor structure in which conductive layers and dielectric layers are alternately stacked in a groove formed in first main surface 11 of semiconductor substrate 10. The ends of conductive layers 20a and 20b extend to the main surface of semiconductor substrate 10 where the groove is formed.

[0057] exist Figure 2 In the semiconductor device of the comparative example shown, for example, in order to charge the conductive layer 20b, as shown by the dashed arrow indicating the current path, the current Ia needs to flow between the two ends of the conductive layer 20b respectively arranged on the main surface of the semiconductor substrate 10. That is, the current needs to flow to the conductive layer inside the groove at a distance of more than twice the groove depth. Since there is a limit to increasing the thickness of the conductive layer arranged on the side of the groove, Figure 2The semiconductor device of the comparative example shown has a large ESR.

[0058] In contrast, Figure 1 In the semiconductor device 1 shown in FIG. 1 , the second conductive layer 2B and the semiconductor substrate 10 are electrically connected at the bottom of the groove. Therefore, in order to charge the second conductive layer 2B with negative charges, as shown in FIG. Figure 3 As shown by the dotted line in FIG. 1 , the transient current I only needs to flow from the second electrode 42 disposed on the second main surface 12 to the upper end of the second conductive layer 2B. Figure 2 Compared with the current path of the semiconductor device of the comparative example shown, the current path of the semiconductor device 1 is linear and extremely short, and the ESR can be reduced.

[0059] Hereinafter, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to the drawings. The method for manufacturing the semiconductor device 1 described below is an example, and the method can be realized by various other manufacturing methods including the modified examples.

[0060] First, a groove is formed in the first main surface 11 of the conductive semiconductor substrate 10. For example, a semiconductor substrate 10 having a resistivity of 1E-4 to 1E-5 cm is used. 2 A silicon substrate with a high impurity concentration of about 1000 nm or more may be used. The semiconductor substrate 10 may be a p-type semiconductor substrate or an n-type semiconductor substrate.

[0061] For example, Figure 4 As shown, the mask material 111 formed on the first main surface 11 of the semiconductor substrate 10 is used as an etching mask to form the groove 100 on the first main surface 11. That is, after the mask material 111 is formed on the entire surface of the first main surface 11, the mask material 111 is patterned to expose the area where the groove 100 is formed. Then, the first main surface 11 of the semiconductor substrate 10 is etched by dry etching using the mask material 111 as an etching mask to form the groove 100.

[0062] In addition, in the patterning of the mask material 111, for example, the following process is used. That is, a silicon oxide film as the mask material 111 is formed by using a thermal CVD method or a plasma CVD method. Then, a photoresist film (not shown) is arranged on the mask material 111. Using photolithography technology, the patterned photoresist film is used as an etching mask, and the mask material 111 is etched by wet etching using fluoric acid or dry etching such as reactive ion etching. Thereafter, the photoresist film is removed by using oxygen plasma or sulfuric acid, and the patterning of the mask material 111 is completed.

[0063] After removing the mask material 111, as Figure 5As shown, a dielectric layer 31 is formed on the surface of the semiconductor substrate 10. For example, a silicon oxide film is used for the dielectric layer 31. At this time, as a method for forming the silicon oxide film, a thermal oxidation method and a thermal CVD method can be used. In addition, by using the thermal CVD method under reduced pressure conditions, the silicon oxide film can be effectively formed even when the groove 100 is deep.

[0064] Then, if Figure 6 As shown, the conductive layer 21 is formed in a manner covering the dielectric layer 31. For example, a polysilicon film can be used for the conductive layer 20 such as the conductive layer 21. The polysilicon film is formed by a reduced pressure CVD method or the like. In addition, after the polysilicon film is formed, an n-type polysilicon film is formed by performing an annealing treatment at 950° C. in phosphorus oxychloride (POCl3), so that the conductive layer 20 can have conductivity.

[0065] Then, if Figure 7 As shown, an insulating protective film 51 is formed on the first main surface 11 to cover the conductive layer 21 formed outside the groove 100. The insulating protective film 51 is formed for the purpose of protecting the conductive layer 21 formed outside the groove 100 in the subsequent etching process. For example, a silicon oxide film formed by plasma CVD or thermal CVD can be used for the insulating protective film 51.

[0066] Then, if Figure 8 As shown, the dielectric layer 31 and the conductive layer 21 formed at the bottom of the groove 100 are selectively removed by dry etching, and the semiconductor substrate 10 is exposed at the bottom of the groove 100. At this time, by making the etching direction directional, the dielectric layer 31 and the conductive layer 21 formed on the side of the groove 100 can be suppressed from being etched.

[0067] Then, if Fig. 9 As shown, a dielectric layer 32 is formed so as to cover the surface of the semiconductor substrate 10. For example, a silicon oxide film is formed as the dielectric layer 32 by using a thermal oxidation method or a thermal CVD method.

[0068] Then, after forming the insulating protection film 52 to cover the dielectric layer 32 formed outside the groove 100, as shown in FIG. Fig.10 As shown, the dielectric layer 32 formed at the bottom of the groove 100 is selectively removed by dry etching. As a result, the semiconductor substrate 10 is exposed at the bottom of the groove 100. The insulating protection film 52 is formed for the purpose of protecting the dielectric layer 32 formed outside the groove 100 during the etching process. The insulating protection film 52 can be made of a silicon oxide film or the like, similarly to the insulating protection film 51.

[0069] Then, if Fig.11As shown, the conductive layer 22 is formed to cover the dielectric layer 32. The conductive layer 22 can be made of a polysilicon film or the like as the conductive layer 21. Since the semiconductor substrate 10 is exposed at the bottom of the groove 100, the conductive layer 22 and the semiconductor substrate 10 are electrically connected at the bottom of the groove 100.

[0070] Then, if Fig.12 As shown, the conductive layer 22 formed outside the groove 100 and at the bottom of the groove 100 is selectively removed by dry etching. In addition, it is necessary to prevent the conductive layer 22 formed outside the groove 100 from remaining on the first main surface 11, but the conductive layer 22 may remain at the bottom of the groove 100. In the etching process of the conductive layer 22, by making the etching direction have directivity, the etching of the conductive layer 22 formed on the side of the groove 100 can be suppressed.

[0071] Then, if Fig.13 As shown in FIG. 1 , a dielectric layer 33 is formed so as to cover the surface of the semiconductor substrate 10. The dielectric layer 33 can be made of, for example, a silicon oxide film.

[0072] Then, if Fig.14 As shown in FIG. 1 , the conductive layer 23 is formed so as to fill the groove 100. As with the conductive layer 21 or the conductive layer 22, the conductive layer 23 can be made of a polysilicon film or the like.

[0073] Next, on the first main surface 11, a portion of the conductive layer 21 is exposed at a predetermined position outside the groove 100. Fig.15 As shown, the mask material 112 is used as an etching mask to form a contact hole 120 that penetrates the insulating protection film 51, the conductive layer 23, the insulating protection film 52, the dielectric layer 33, and the conductive layer 23 formed on the first main surface 11. For example, a photoresist film is used in the mask material 112, and the mask material 112 is patterned by photolithography technology. Then, the contact hole 120 is formed by dry etching.

[0074] After removing the mask material 112, as Fig.16 As shown, a conductive contact film 60 is formed on the first main surface 11 of the semiconductor substrate 10 and arranged inside the contact hole 120. The contact film 60 can reliably make electrical connections between the conductive layer 21, the conductive layer 23 and the first electrode 41. The contact film 60 can be made of a polysilicon film or the like.

[0075] Then, the contact film 60 is covered, the first electrode 41 is formed on the first main surface 11, and the second electrode 42 is formed on the second main surface 12. Thus, the Figure 1 The semiconductor device shown.

[0076] In addition, the material of the first electrode 41 and the second electrode 42 is generally a metal. For example, a metal material such as titanium (Ti), nickel (Ni), and manganese (Mo) or a stacked film such as titanium / nickel / silver (Ti / Ni / Ag) can be used for the first electrode 41 and the second electrode 42. The first electrode 41 and the second electrode 42 are formed, for example, by etching a metal film. That is, after forming a metal film by a spray method or an electron beam (EB) evaporation method, the metal film is etched by dry etching using a mask material formed by photolithography technology, thereby forming the first electrode 41 and the second electrode 42.

[0077] In the above manufacturing method, Figure 8 and Fig.10 As shown, after the outside of the groove 100 is covered with the insulating protection film 51 and the insulating protection film 52, the conductive layer 20 and the dielectric layer 30 formed at the bottom of the groove 100 are etched away. Therefore, the conductive layer 20 and the dielectric layer 30 formed outside the groove 100 on the first main surface 11 and not necessary to be removed are protected. Thus, the conductive layer 20 formed outside the groove 100 can be used for wiring on the surface of the semiconductor substrate 10.

[0078] In addition, if Figure 8 and Fig.10 As shown in FIG. 1 , the insulating protective film 51 or the insulating protective film 52 may be formed in a shape in which the end portion thereof protrudes inwardly at the opening of the groove 100 more than the side surface of the groove 100. Thus, in the process of removing the conductive layer 20 and the dielectric layer 30 formed at the bottom of the groove 100 by etching using plasma, even when the depth of the groove 100 is deep, the conductive layer 20 and the dielectric layer 30 formed on the side surface of the groove 100 can be protected. In addition, when the conductive layer 20 is a polycrystalline silicon film, the conductive layer 20 is formed by a reduced pressure CVD method or the like. In this case, the polycrystalline silicon film is formed from the side surface of the groove 100, and therefore, even if the insulating protective film 51 or the insulating protective film 52 is in a shape in which the end portion protrudes inwardly at the opening of the groove 100, the conductive layer 20 can be easily formed.

[0079] In the semiconductor device 1, the contact film 60 disposed inside the contact hole 120 can reliably connect the layers of the first conductive layer 2A and the first electrode 41. For example, when the number of layers increases and the contact hole 120 becomes deeper, it may be difficult to completely bury the contact hole 120 due to the material used for the first electrode 41. However, by forming the contact film 60 inside the contact hole 120, the layers of the first conductive layer 2A and the first electrode 41 are electrically connected to each other on the first main surface 11. However, when the number of layers of the conductive layer 20 and the dielectric layer 30 is small and the contact hole 120 is deep enough to be reliably buried through the first electrode 41, the contact film 60 may not be formed.

[0080] For example, a single crystal silicon substrate can be used as the semiconductor substrate 10. Thus, it is possible to apply to a common semiconductor process and to easily manufacture the semiconductor device 1. Furthermore, as the dielectric layer 30, a high-quality silicon oxide film generated by oxidizing the semiconductor substrate 10 can be formed with high uniformity on the entire surface of the semiconductor substrate 10. In addition, a polycrystalline silicon substrate can also be used as the semiconductor substrate 10. Thus, the cost of the semiconductor substrate 10 can be reduced.

[0081] In the above description, the case where the dielectric layer 30 is a silicon oxide film is exemplified. However, a material other than a silicon oxide film may be used for the dielectric layer 30. For example, a silicon nitride film may be used for the dielectric layer 30. By making the dielectric layer 30 a silicon oxide film or a silicon nitride film commonly used in a semiconductor process, a high-quality dielectric layer can be formed.

[0082] Alternatively, the dielectric layer 30 may be a structure formed by stacking a plurality of dielectric films composed of different materials. For example, by stacking dielectric films having different strain directions due to stress, the strain caused by stress in the entire dielectric layer 30 can be suppressed. In addition, by stacking a dielectric film having a large insulation breakdown electric field and a dielectric film having a low insulation breakdown electric field but a high dielectric constant, the balance of the insulation breakdown electric field and the dielectric constant of the entire dielectric film 30 can be set to an optimal value corresponding to the characteristics required by the capacitor structure. For example, the dielectric layer 30 may be a stacked structure including a silicon nitride film and a silicon oxide film.

[0083] In the above, the case where the total number of layers of the conductive layer 20 is 3 layers is exemplified. However, the number of layers of the conductive layer 20 stacked inside the groove of the semiconductor substrate 10 is not limited to 3 layers. For example, the first conductive layer 2A and the second conductive layer 2B can be one layer respectively. Thus, the manufacturing process can be shortened. On the other hand, the more layers of the stacked conductive layer 20, the greater the capacitance density per unit area. Therefore, the total number of layers of the conductive layer 20 can also be 4 or more layers.

[0084] In addition, Figure 1 In the semiconductor device 1 shown, the conductive layer closest to the side surface of the groove is used as the first conductive layer, the odd-numbered first conductive layers 2A are electrically connected to each other, and the even-numbered second conductive layers 2B are electrically connected. In this way, the first conductive layers 2A and the second conductive layers 2B are alternately stacked via the dielectric layer 30, so that the capacitance density per unit area can be maximized.

[0085] Furthermore, since the stacked structure of the conductive layer 20 and the dielectric layer 30 fills the groove 100 without any gap, the cross-sectional area of ​​the conductive layer 20 is increased compared to a stacked structure having the same number of layers but without the groove 100. This can reduce the ESR of the capacitor structure.

[0086] As described above, in the semiconductor device 1 according to the first embodiment of the present invention, the second conductive layer 2B and the conductive semiconductor substrate 10 are electrically connected inside the groove, and the second electrode 42 electrically connected to the semiconductor substrate 10 is arranged on the second main surface 12. Therefore, the electric charge is charged to the second conductive layer 2B through the short current path through the semiconductor substrate 10. Therefore, the ESR of the capacitor structure can be reduced.

[0087] Furthermore, a cooling device for cooling the semiconductor device 1 may be disposed on at least one of the first main surface 11 and the second main surface 12 of the semiconductor substrate 10 . Fig.17 This is an embodiment in which the cooling device 300 is arranged on the second main surface 12 side of the semiconductor substrate 10 via the insulator 200 between the semiconductor substrate 10 and the second electrode 42. Fig.18 This is an embodiment in which the cooling device 300 is arranged on the first main surface 11 side of the semiconductor substrate 10 via the insulator 200 between the first electrode 41. By arranging the cooling device 300 opposite to the first main surface 11 or the second main surface 12 of the semiconductor substrate 10, it is possible to suppress the increase in the ESR of the capacitor structure caused by the temperature rise of the conductive layer 20. For example, a cooling fin made of a material with high thermal conductivity such as aluminum can be used in the cooling device 300.

[0088] Furthermore, the semiconductor device 1 can be combined with a power semiconductor element to form a power module. Fig.19 An example of a power module composed of a semiconductor device 1, a first power semiconductor element T1, and a second power semiconductor element T2 is shown. The drain electrode D1 of the first power semiconductor element T1 is connected to the second electrode 42 of the semiconductor device 1, and the source electrode S2 of the second power semiconductor element T2 is connected to the first electrode 41. Then, the source electrode S1 of the first power semiconductor element T1 is electrically connected to the drain electrode D2 of the second power semiconductor element T2.

[0089] The first power semiconductor element T1 and the second power semiconductor element T2 are, for example, MOS transistors. Fig. 20 Shown by Fig.19 The circuit diagram of a power module composed of the semiconductor device 1, the first power semiconductor element T1 and the second power semiconductor element T2 is shown in FIG. The power module operates as an inverter module as shown below.

[0090] That is, the first power semiconductor element T1 of the upper arm of the inverter is arranged on the second electrode 42 of the semiconductor device 1, and the drain electrode D1 of the first power semiconductor element T1 is electrically connected to the second electrode 42. Then, the second power semiconductor element T2 of the lower arm of the inverter is arranged on the first electrode 41, and the source electrode S2 of the second power semiconductor element T2 is electrically connected to the first electrode 41. The source electrode S1 of the first power semiconductor element T1 of the upper arm is electrically connected to the drain electrode D2 of the second power semiconductor element T2 of the lower arm through the intermediate electrode Vm. A positive potential is applied to the positive electrode Vp connected to the drain electrode D1 of the first power semiconductor element T1 and the second electrode 42, and a negative potential is applied to the negative electrode Vn connected to the source electrode S2 of the second power semiconductor element T2 and the first electrode 41. As a result, Fig.19 The power module shown operates as an inverter module.

[0091] exist Fig.19 In the power module shown, the heat generated when the power semiconductor element is in operation is dissipated via the capacitor structure of the semiconductor device 1. In addition, since the electrodes of the capacitor structure are directly connected to the electrodes of the power semiconductor element, the internal parasitic inductance of the power module is reduced. Therefore, the surge component generated when the power semiconductor element is switched can be reduced, and a low-loss power module can be realized.

[0092] (Second Embodiment)

[0093] Fig.21 A semiconductor device 1 according to a second embodiment of the present invention is shown. Fig.21 In the semiconductor device 1 shown in FIG. 1 , the number of layers of the conductive layer 20 and the dielectric layer 30 formed inside the groove is 2.3 times that of the dielectric layer 30 formed inside the groove. Figure 1 There are many semiconductor devices 1 shown. Therefore, it is possible to increase the capacitance of the capacitor structure formed in the semiconductor device 1. The other structures are the same as those of the first embodiment.

[0094] exist Fig.21 In the semiconductor device 1 shown in FIG. 1 , seven conductive layers 20 and seven dielectric layers 30 are alternately arranged inside the groove. Fig.21 As shown, the conductive layer closest to the side surface of the groove is the first conductive layer, and the odd-numbered conductive layers are electrically connected to each other and to the first electrode 41. That is, the conductive layers 21, 23, 25, and 27 as the odd-numbered conductive layers are the first conductive layers 2A. On the other hand, the even-numbered conductive layers are electrically connected to each other and to the second electrode 42 via the semiconductor substrate 10. That is, the conductive layers 22, 24, and 26 as the even-numbered conductive layers are the second conductive layers 2B.

[0095] like Fig.21As shown, each layer of the first conductive layer 2A is electrically connected to the first electrode 41 arranged on the first main surface 11 via the contact film 60 or the like in the region extending to the first main surface 11. Each layer of the second conductive layer 2B is connected to the semiconductor substrate 10 at the bottom of the groove, and is electrically connected to the second electrode 42 arranged on the second main surface 12 via the semiconductor substrate 10. A dielectric layer 31 is arranged between the side surface of the groove and the conductive layer 21, and dielectric layers 32 to 37 are arranged between the conductive layers 21 to 27.

[0096] As mentioned above, Fig.21 The semiconductor device 1 shown has a structure in which seven capacitors are connected in parallel. Hereinafter, an example of a method for manufacturing the semiconductor device 1 according to the second embodiment will be described with reference to the drawings.

[0097] First, with reference Figures 4 to 13 The method described above is the same. After the conductive layers 21-22 and the dielectric layers 31-33 are formed inside the groove 100, as shown in FIG. Fig. 22 As shown, the conductive layer 23 is formed so as to cover the dielectric layer 33 .

[0098] Next, after forming an insulating protective film 53 to cover the conductive layer 23 formed outside the groove 100, as shown in FIG. Fig.23 As shown in FIG. 1 , the dielectric layer 33 and the conductive layer 23 formed at the bottom of the groove 100 are removed by dry etching. Thus, the semiconductor substrate 10 is exposed at the bottom of the groove 100. The insulating protection film 53 is formed for the purpose of protecting the conductive layer 23 formed outside the groove 100 during the etching process. The insulating protection film 53 can use a silicon oxide film or the like like other insulating protection films.

[0099] like Fig.24 As shown, after the dielectric layer 34 is formed, an insulating protective film 54 is formed outside the groove 100 in a manner covering the dielectric layer 34, and the dielectric layer 34 formed at the bottom of the groove 100 is etched away. Then, a conductive layer 24 is formed, as shown in FIG. Fig.25 As shown, the conductive layer 24 outside the groove 100 and at the bottom of the groove 100 is removed by dry etching. At this time, the conductive layer 24 cannot remain outside the groove 100, but the conductive layer 24 may remain at the bottom of the groove 100.

[0100] Below, repeat reference Figure 22 to Figure 25 The process described above forms dielectric layers 35 to 37 and conductive layers 25 to 27, thereby obtaining Fig.26 In addition, the conductive layer 20 and the dielectric layer 30 formed outside the groove 100 are protected by the insulating protective films 55 and 56, and the conductive layer 20 and the dielectric layer 30 formed at the bottom of the groove 100 are removed.

[0101] Then, a contact hole is formed at a predetermined position outside the groove 100 so that the upper surface of the conductive layer 21 is exposed on the conductive layer 20, the dielectric layer 30 and the insulating protection films 51 to 56 arranged on the first main surface 11. Fig. 27 As shown, a contact film 60 is formed in a manner covering the inner wall surface of the contact hole. Through the contact film 60, the conductive layers 21, 23, 25, and 27 are electrically connected to each other. Then, the contact film 60 is covered in a manner of burying the contact hole to form the first electrode 41, and the second electrode 42 is formed on the second main surface 12. Thus, the Fig.21 The semiconductor device shown.

[0102] In the above, although an example of laminating 7 layers of conductive layer 20 and dielectric layer 30 is shown, it is also possible to repeat the same process to laminate 8 or more layers of conductive layer 20 and dielectric layer 30, so that the semiconductor device 1 has a structure in which 8 or more capacitors are connected in parallel. By increasing the number of layers of conductive layer 20 and dielectric layer 30, the capacity of the capacitor structure can be increased. The rest is substantially the same as the first embodiment, so repeated description is omitted.

[0103] (Third Embodiment)

[0104] like Fig.28 As shown in FIG. 1 , in the semiconductor device 1 according to the third embodiment of the present invention, the upper end position of the second conductive layer 2B is farther from the first main surface 11 than the upper end position of the first conductive layer 2A connected to the first electrode 41 disposed on the first main surface 11. Then, the first electrode 41 and the first conductive layer 2A are directly stacked over the entire surface of the first main surface 11. That is, Figure 1 The semiconductor device 1 shown has the same structure as the case where the contact hole 120 is formed on the entire surface of the first main surface 11, and the dielectric layer 30 and the insulating protection films 51 and 52 are not arranged on the conductive layer 20 on the first main surface 11 outside the groove. The other structures are the same as those of the first embodiment.

[0105] exist Fig.28 In the semiconductor device 1 shown, the first electrode 41 and the first conductive layer 2A are electrically connected over the entire surface of the first main surface 11. Therefore, the ESR of the capacitor structure can be reduced. Furthermore, the patterning step for forming the contact hole 120 on the first main surface 11 is omitted, and the manufacturing process can be shortened.

[0106] Hereinafter, referring to the accompanying drawings Fig.28 The method for manufacturing the semiconductor device 1 shown in FIG. Figures 4 to 11 The method of explanation is the same, such as Fig.29 As shown, a dielectric layer 31 , a conductive layer 21 , a dielectric layer 32 , and a conductive layer 22 are stacked on the side of the groove 100 .

[0107] Next, the conductive layer 22 formed at the bottom of the groove 100 is removed by dry etching. Fig.30 As shown, the upper end position of the conductive layer 22 is lower than the upper end position of the conductive layer 21.

[0108] Then, if Fig.31 As shown in FIG. 1 , a dielectric layer 33 and a conductive layer 23 are sequentially formed to bury the interior of the groove 100. Then, as shown in FIG. Fig.32 As shown, the entire first main surface 11 of the semiconductor substrate 10 is etched by dry etching, so that the conductive layers 21 and 23 are exposed on the first main surface 11 .

[0109] Then, the first electrode 41 is formed on the first main surface 11, and the second electrode 42 is formed on the second main surface 12. Fig.28 The semiconductor device 1 is shown.

[0110] (Other embodiments)

[0111] As described above, although the embodiments of the present invention have been described, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. Based on this disclosure, various alternative embodiments, examples, and application techniques will be apparent to those skilled in the art.

[0112] For example, in the above example, an example in which the first conductive layer 2A and the second conductive layer 2B are alternately arranged is shown, but the arrangement of the conductive layer 20 is not limited to this structure. For example, there may be a portion where the first conductive layer 2A and the first conductive layer 2A are adjacent to each other via the dielectric layer 30, or there may be a portion where the second conductive layer 2B and the second conductive layer 2B are adjacent to each other via the dielectric layer 30.

[0113] In addition, the second conductive layer 2B can be electrically connected to the semiconductor substrate 10 not only at the bottom of the groove but also at the side surface of the groove.

[0114] In addition, although the example in which the second electrode 42 is arranged on the second main surface 12 of the semiconductor substrate 10 is shown, the second electrode 42 may also be arranged on the first main surface 11 of the semiconductor substrate 10. By reducing the resistivity of the semiconductor substrate 10, Figure 2 Compared with the case where the conductive layer formed inside the groove is used as the current path as in the semiconductor device of the comparative example shown, the ESR when the semiconductor substrate 10 is used as the current path can be reduced.

[0115] In addition, although the conductive layer 20 is described as a polysilicon film, the conductive layer 20 may be other conductive semiconductor films or metal films. For example, conductive polycrystalline silicon carbide or silicon germanium (SiGe), aluminum, etc. may be used as the material of the conductive layer 20. In addition, in the process of etching the conductive layer 20 or the dielectric layer 30, wet etching using fluoric acid or hot phosphoric acid may be used instead of dry etching.

[0116] In the above, an example in which the semiconductor device 1 is combined with a power semiconductor element to form an inverter module is shown, but the power module using the semiconductor device 1 is not limited to the inverter module. Since a capacitor element of a smaller size can be provided by the semiconductor device 1, the size of the power module can be reduced by applying the semiconductor device 1 to the power module.

[0117] Industrial Applicability

[0118] The semiconductor device, power module, and method for manufacturing a semiconductor device of the present invention can be used in the electronic equipment industry including the manufacturing industry of a semiconductor device that forms a semiconductor capacitor on a semiconductor substrate.

[0119] Explanation of symbols

[0120] 1: Semiconductor devices

[0121] 10: Semiconductor substrate

[0122] 11: First main surface

[0123] 12: Second main surface

[0124] 21~27: Conductive layer

[0125] 2A: First conductive layer

[0126] 2B: Second conductive layer

[0127] 31~37: Dielectric layer

[0128] 41: First electrode

[0129] 42: Second electrode

[0130] 51~56: Insulation protective film

[0131] 100: Slot

[0132] 200: Insulator

[0133] 300: Cooling device

[0134] T1: First power semiconductor element

[0135] T2: Second power semiconductor element

Claims

1. A semiconductor device, characterized in that: have: A conductive semiconductor substrate having a first main surface and a second main surface facing each other, wherein a groove is formed on the first main surface; A plurality of conductive layers, which are either the first conductive layer or the second conductive layer, and are stacked along the surface normal direction of the side surface of the groove; a dielectric layer, which is respectively arranged between a conductive layer closest to a side surface of the groove among the plurality of conductive layers and the side surface of the groove, and between the plurality of conductive layers; A first electrode, which is arranged outside the groove and contacts and is electrically connected to the first conductive layer outside the groove in a plan view; a second electrode, which is disposed outside the groove and is in contact with and electrically connected to the second conductive layer; The first conductive layer is electrically insulated from the semiconductor substrate, The semiconductor substrate electrically connected to the second conductive layer inside the groove is electrically connected to the second electrode, The first electrode is arranged on the first main surface, and the second electrode is arranged on the second main surface. The first conductive layer includes one first conductive layer and other first conductive layers, and the first electrode only penetrates the one first conductive layer among the first conductive layers and extends into the contact hole.

2. The semiconductor device according to claim 1, wherein The groove is buried by a stacked structure of the plurality of conductive layers and the dielectric layer.

3. The semiconductor device according to claim 1 or 2, wherein: The first conductive layer and the second conductive layer together have four or more conductive layers.

4. The semiconductor device according to claim 1 or 2, wherein: The conductive layer closest to the side of the groove among the plurality of conductive layers is used as the first conductive layer, The odd-numbered conductive layers of the plurality of conductive layers are electrically connected to each other, Even-numbered conductive layers of the plurality of conductive layers are electrically connected to each other.

5. The semiconductor device according to claim 1 or 2, wherein: The dielectric layer has a structure in which a plurality of dielectric films made of different materials are stacked.

6. The semiconductor device according to claim 1 or 2, wherein: The upper end of the second conductive layer is located farther from the first main surface than the upper end of the first conductive layer to which the first electrode is connected. The first electrode and the first conductive layer are directly stacked over the entire first main surface.

7. The semiconductor device according to claim 1 or 2, wherein: A cooling device is further provided, which is arranged to face at least one of the first main surface and the second main surface of the semiconductor substrate.

8. The semiconductor device according to claim 1 or 2, wherein: The semiconductor substrate is a single crystal silicon substrate.

9. The semiconductor device according to claim 1 or 2, wherein: The semiconductor substrate is a polycrystalline silicon substrate.

10. The semiconductor device according to claim 1 or 2, wherein: The dielectric layer includes at least one of a silicon oxide film or a silicon nitride film.

11. A power module, characterized in that: have: The semiconductor device according to any one of claims 1 to 10, A first power semiconductor element, a drain electrode of which is connected to the second electrode; a second power semiconductor element, whose source electrode is connected to the first electrode; The source electrode of the first power semiconductor element is electrically connected to the drain electrode of the second power semiconductor element.

12. A method for manufacturing a semiconductor device, characterized in that: The process includes the following: forming a groove on a first main surface of a conductive semiconductor substrate; stacking a plurality of conductive layers, which are either the first conductive layer or the second conductive layer, along a surface normal direction of the side surface of the groove, and forming a dielectric layer between a conductive layer closest to the side surface of the groove among the plurality of conductive layers and the side surface of the groove, and between the plurality of conductive layers; In order to electrically connect the second conductive layer to the semiconductor substrate at the bottom of the groove, the first conductive layer and the dielectric layer formed at the bottom of the groove are removed. After covering the outside of the groove of the first main surface with an insulating protective film, removing the first conductive layer and the dielectric layer formed at the bottom of the groove, A first electrode is formed on the first main surface, and a second electrode is formed on a second main surface of the semiconductor substrate opposite to the first main surface. The first electrode is in contact with and electrically connected to the first conductive layer, and the second electrode is in contact with and electrically connected to the second conductive layer. The first conductive layer includes one first conductive layer and other first conductive layers, and the first electrode only penetrates the one first conductive layer among the first conductive layers and extends into the contact hole.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The insulating protection film is formed into a shape in which an end portion protrudes inward from a side surface of the groove.

14. A semiconductor device, characterized in that: have: A conductive semiconductor substrate having a first main surface and a second main surface facing each other, wherein a groove is formed on the first main surface; A plurality of conductive layers, which are either the first conductive layer or the second conductive layer, and are stacked along the surface normal direction of the side surface of the groove; a dielectric layer, which is respectively arranged between a conductive layer closest to a side surface of the groove among the plurality of conductive layers and the side surface of the groove, and between the plurality of conductive layers; A first electrode, which is arranged outside the groove and contacts and is electrically connected to the first conductive layer via a contact film outside the groove in a plan view; a second electrode, which is disposed outside the groove and is in contact with and electrically connected to the second conductive layer; The first conductive layer is electrically insulated from the semiconductor substrate, The semiconductor substrate electrically connected to the second conductive layer inside the groove is electrically connected to the second electrode, The first electrode is arranged on the first main surface, and the second electrode is arranged on the second main surface. The first conductive layer includes one first conductive layer and other first conductive layers, and the first electrode only penetrates the one first conductive layer among the first conductive layers and extends into the contact hole.

Images