Display device and driving method thereof

Abstract

A display device includes: a substrate; and a transistor placed on the substrate, wherein the transistor includes: a semiconductor layer; a gate electrode overlapping the semiconductor layer; a first gate contact overlapping layer overlapping a channel region and contacting the gate electrode, the gate electrode and the semiconductor layer overlap at the channel region; and a semiconductor contact overlapping layer overlapping the channel region and contacting the semiconductor layer, and the first gate contact overlapping layer and the semiconductor contact overlapping layer are physically separated by a gap in the channel region.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a driving method thereof. More particularly, the present invention relates to a display device including a transistor having improved characteristics and a driving method thereof. Background Art

[0002] A display device is a device for displaying an image, and recently, an organic light emitting diode display has attracted attention.

[0003] Organic light emitting diode displays have self-emission characteristics and, unlike liquid crystal displays, do not require a separate light source, so their thickness and weight can be reduced. In addition, organic light emitting diode displays exhibit high quality characteristics such as low power consumption, high brightness, and high response speed.

[0004] Generally, an organic light emitting diode display includes a substrate, a plurality of transistors disposed on the substrate, and an organic light emitting element connected to the transistor. The transistor is a switching element and is a basic configuration of a display device.

[0005] A transistor having characteristics such as a large data range and a large current flowing in an on-state is advantageous for improving the display quality of a display device.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Summary of the invention

[0007] Embodiments of the present invention provide a display device including a transistor having characteristics such as a large data range and a large current flowing in an on-state, and a driving method thereof.

[0008] A display device according to an embodiment of the present invention includes: a substrate; and a transistor placed on the substrate, wherein the transistor includes: a semiconductor layer; a gate electrode overlapping the semiconductor layer; a first gate contact overlapping layer overlapping the channel region and in contact with the gate electrode, the gate electrode and the semiconductor layer overlap at the channel region; and a semiconductor contact overlapping layer overlapping the channel region and in contact with the semiconductor layer, and the first gate contact overlapping layer and the semiconductor contact overlapping layer are physically separated by a gap in the channel region.

[0009] The transistor may further include a second gate contact overlapping layer overlapping the channel region and contacting the gate electrode, and the semiconductor contact overlapping layer is disposed between the first gate contact overlapping layer and the second gate contact overlapping layer in plane.

[0010] On a plane, a width of the entire region including the first gate contact overlapping layer, the semiconductor contact overlapping layer, the second gate contact overlapping layer, and the gap may be greater than a width of the channel region.

[0011] On a plane, a width of the entire region including the first gate contact overlapping layer, the semiconductor contact overlapping layer, the second gate contact overlapping layer, and the gap may be smaller than a width of the channel region.

[0012] The transistor may further include a floating overlapping layer overlapping the channel region and insulated from and not connected to the semiconductor layer and the gate electrode.

[0013] The semiconductor contact overlapping layer may include: a first overlapping portion overlapping the channel region; a second overlapping portion overlapping the channel region; a contact portion contacting the semiconductor layer without overlapping the gate electrode; and an extension portion connecting the first overlapping portion, the second overlapping portion and the contact portion to each other.

[0014] The first gate contact overlapping layer may be disposed between the first overlapping portion and the second overlapping portion.

[0015] On a plane, a width of the entire region including the first gate contact overlapping layer, the first overlapping portion, the second overlapping portion, and the gap may be greater than a width of the channel region.

[0016] On a plane, a width of the entire region including the first gate contact overlapping layer, the first overlapping portion, the second overlapping portion, and the gap may be smaller than a width of the channel region.

[0017] The transistor may further include a floating overlapping layer overlapping the channel region and insulated from and not connected to the semiconductor layer and the gate electrode.

[0018] The width of the first gate contact overlapping layer may be the same as the width of the semiconductor contact overlapping layer.

[0019] A width of the first gate contact overlapping layer and a width of the semiconductor contact overlapping layer may be different from each other.

[0020] According to another embodiment of the present invention, a display device includes a plurality of pixels, wherein each of the plurality of pixels includes: a light emitting diode (LED); and a driving transistor that controls the amount of current flowing from a first power supply voltage to the light emitting diode (LED), and the driving transistor includes: a gate electrode connected to a first node; a first electrode to which a first power supply voltage is applied; a second electrode electrically connected to the light emitting diode (LED); a gate contact overlapping layer that overlaps with a channel region of the driving transistor and is connected to the gate electrode; and a semiconductor contact overlapping layer that overlaps with the channel region and is connected to the first electrode, and the gate contact overlapping layer and the semiconductor contact overlapping layer are physically separated by a gap.

[0021] Each of the plurality of pixels may further include a switching transistor connected between the data line and the driving transistor, and the switching transistor includes: a gate electrode connected to the first gate line; and a gate contact overlapping layer overlapping a channel region of the switching transistor and connected to the gate electrode of the switching transistor.

[0022] Each of the plurality of pixels may further include a compensation transistor connected between the second electrode and the gate electrode of the driving transistor, and the compensation transistor includes: a gate electrode connected to the first gate line; and a gate contact overlapping layer overlapping a channel region of the compensation transistor and connected to the gate electrode of the compensation transistor.

[0023] Each of the plurality of pixels may further include an initialization transistor that applies an initialization voltage to a gate electrode of the driving transistor, and the initialization transistor may include: a gate electrode connected to the second gate line; and a gate contact overlapping layer overlapping a channel region of the initialization transistor and connected to the gate electrode of the initialization transistor.

[0024] According to another embodiment of the present invention, a driving method of a display device including a driving transistor that controls the amount of current flowing from a first power supply voltage to a light emitting diode (LED), a switching transistor that transmits a data voltage applied to a data line to the driving transistor according to a first gate signal applied to a first gate line, a compensation transistor that diode-connects the driving transistor according to the first gate signal, and an initialization transistor that applies an initialization voltage to a gate electrode of the driving transistor according to a second gate signal applied to a second gate line includes: applying the first power supply voltage to a first electrode of the driving transistor; causing current to flow from the first power supply voltage to the light emitting diode (LED) in response to a voltage of a first node to which the gate electrode of the driving transistor is connected; applying the first power supply voltage to a semiconductor contact overlapping layer that overlaps with a channel region of the driving transistor and is connected to the first electrode of the driving transistor; and applying the voltage of the first node to a gate contact overlapping layer that overlaps with the channel region of the driving transistor and is connected to the gate electrode of the driving transistor.

[0025] It may further include: applying a first gate signal as a gate-on voltage to a gate electrode of the switching transistor to turn on the switching transistor; and applying the first gate signal to a gate contact overlapping layer overlapping a channel region of the switching transistor and connected to the gate electrode of the switching transistor.

[0026] This may further include: applying a first gate signal as a gate-on voltage to a gate electrode of the compensation transistor to turn on the compensation transistor; and applying the first gate signal to a gate contact overlapping layer overlapping a channel region of the compensation transistor and connected to the gate electrode of the compensation transistor.

[0027] The method may further include: applying a second gate signal as a gate-on voltage to a gate electrode of the initialization transistor to turn on the initialization transistor; and applying the second gate signal to a gate contact overlapping layer overlapping a channel region of the initialization transistor and connected to the gate electrode of the initialization transistor.

[0028] The data range of a transistor used in a display device and the current flowing in an on-state can be increased, and thus the display quality of the display device can be improved.

[0029] By increasing the data range of the driving transistor, more grayscale images can be displayed. By increasing the current flowing through the transistor used as a switching element, the charging efficiency of the voltage can be improved, and high-speed driving of the display device can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a top view showing a transistor according to an embodiment of the present invention.

[0031] Figure 2 is along Figure 1 A cross-sectional view of the transistor taken along line II-II'.

[0032] Figure 3 It shows that the modified Figure 1 Top view of a transistor of some configuration embodiments.

[0033] Figure 4 It shows that the modified Figure 1 Top view of a transistor of some configuration embodiments.

[0034] Figure 5 It shows that the modified Figure 1 Top view of a transistor of some configuration embodiments.

[0035] Figure 6 is a top view showing a transistor according to another embodiment of the present invention.

[0036] Figure 7 is along Figure 6 A cross-sectional view taken along line VII-VII'.

[0037] Figure 8 It shows that the modified Figure 6 Top view of a transistor of some configuration embodiments.

[0038] Fig. 9 It shows that the modified Figure 6 Top view of a transistor of some configuration embodiments.

[0039] Fig.10 It shows that the modified Figure 6 Top view of a transistor of some configuration embodiments.

[0040] Fig.11 is a top view showing a transistor according to another embodiment of the present invention.

[0041] Fig.12 is a top view showing a transistor according to another embodiment of the present invention.

[0042] Fig.13 is a block diagram of a display device according to an embodiment.

[0043] Fig.14 is a circuit diagram showing one pixel of a display device according to an embodiment of the present invention.

[0044] Fig.15 is a cross-sectional view showing the structure of a display device according to an embodiment of the present invention.

[0045] Fig.16 is a timing diagram illustrating a driving method of a display device according to an embodiment.

[0046] Fig.17 is a graph showing characteristics of a transistor according to an embodiment of the present invention.

[0047] Fig.18 is a circuit diagram showing a pixel according to the embodiment. DETAILED DESCRIPTION

[0048] Embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present invention are shown. As those skilled in the art will realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

[0049] In order to clearly illustrate the present invention, throughout the specification, parts that are not directly related to the present disclosure are omitted, and the same reference numerals are attached to the same or similar constituent elements.

[0050] In addition, for better understanding and ease of description, the size and thickness of each configuration shown in the drawings are arbitrarily shown, but the present invention is not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thickness of some layers and regions are exaggerated for better understanding and ease of description.

[0051] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, the terms "on" or "over" mean placed on or over an object part, and do not necessarily mean placed on the upper side of the object part based on the direction of gravity.

[0052] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprising” or “including”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0053] Furthermore, in the specification, the phrase "in a plan view" means when an object portion is viewed from above, and the phrase "in a cross-sectional view" means when a cross section taken by vertically cutting the object portion is viewed from the side.

[0054] Now, refer to Figure 1 and Figure 2 A transistor included in a display device according to an embodiment of the present invention is described.

[0055] Figure 1 is a top view showing a transistor according to an embodiment of the present invention. Figure 2 is along Figure 1 A cross-sectional view of the transistor taken along line II-II'.

[0056] See also Figure 1 and Figure 2 , the display device includes a plurality of transistors placed on a substrate 110. The plurality of transistors include an overlapping layer ML, a semiconductor layer 120, a gate electrode 130, a first electrode 151, and a second electrode 153, respectively.

[0057] The substrate 110 may include a material such as glass, plastic, or polyimide (PI). The barrier layer 111 is placed on the substrate 110 , and the overlapping layer ML made of a conductive metal or a semiconductor material having conductive properties equivalent thereto is placed on the barrier layer 111 .

[0058] The overlapping layer ML includes gate contact overlapping layers MG1 and MG2 and a semiconductor contact overlapping layer MS1. The gate contact overlapping layers MG1 and MG2 may include: a first gate contact overlapping layer MG1 partially overlapping the semiconductor layer 120 and contacting the gate electrode 130 through the first gate contact hole CG1; and a second gate contact overlapping layer MG2 partially overlapping the semiconductor layer 120 and contacting the gate electrode 130 through the second gate contact hole CG2.

[0059] like Figure 1As shown in , the gate electrode 130 extends in a first direction D1, and the semiconductor layer 120 extends in a second direction D2, thereby partially overlapping the gate electrode 130. The second direction D2 may intersect with the first direction D1. The second direction D2 may be orthogonal to the first direction D1. For example, the first direction D1 may be a row direction, and the second direction D2 may be a column direction. However, according to the embodiment, the arrangement direction and arrangement shape of the transistor may be changed differently, and the first direction D1 and the second direction D2 are neither always orthogonal nor always row and column directions. The portion of the semiconductor layer 120 that overlaps with the gate electrode 130 becomes the channel region of the transistor. The channel region of the transistor corresponds to the channel portion 121 of the semiconductor layer 120, and the channel region of the transistor may be referred to as the channel region of the semiconductor layer 120.

[0060] The first gate contact overlapping layer MG1 extends in the first direction D1 along one side of the gate electrode 130 to overlap the channel region. The first gate contact overlapping layer MG1 includes a first extension portion MG1-1 that extends further than the semiconductor layer 120 in the first direction D1 and does not overlap the semiconductor layer 120 but overlaps the gate electrode 130. The first gate contact hole CG1 is placed at a position overlapping the first extension portion MG1-1, and the first gate contact overlapping layer MG1 may be directly connected to the gate electrode 130 through the first gate contact hole CG1.

[0061] The second gate contact overlapping layer MG2 extends in the first direction D1 along the other side of the gate electrode 130 to overlap the channel region. The second gate contact overlapping layer MG2 includes a second extension portion MG2-1 that extends further than the semiconductor layer 120 in the first direction D1 and does not overlap the semiconductor layer 120 but overlaps the gate electrode 130. The second gate contact hole CG2 is placed at a position overlapping the second extension portion MG2-1, and the second gate contact overlapping layer MG2 can be directly connected to the gate electrode 130 through the second gate contact hole CG2.

[0062] The semiconductor contact overlapping layer MS1 includes a first overlapping portion MS1-1, an extension portion MS1-2, and a contact portion MS1-3. The first overlapping portion MS1-1 extends parallel to the first gate contact overlapping layer MG1 and the second gate contact overlapping layer MG2 on a plane, and may overlap the semiconductor layer 120 and the gate electrode 130. The first overlapping portion MS1-1 overlaps the channel region of the semiconductor layer 120. On a plane, the first overlapping portion MS1-1 may be placed between the first gate contact overlapping layer MG1 and the second gate contact overlapping layer MG2. The contact portion MS1-3 does not overlap the gate electrode 130, but overlaps the semiconductor layer 120. The semiconductor contact hole CS1 is placed at a position overlapping with the contact portion MS1-3, and the contact portion MS1-3 may contact the semiconductor layer 120 through the semiconductor contact hole CS1. The extension portion MS1-2 has a structure that connects the first overlapping portion MS1-1 and the contact portion MS1-3 to each other. The extension portion MS1-2 may not overlap the semiconductor layer 120.

[0063] On a plane, the first gate contact overlapping layer MG1 and the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 are arranged to be separated from each other by a gap GP. The first gate contact overlapping layer MG1 and the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 are physically separated by the gap GP in the channel region. On a plane, the second gate contact overlapping layer MG2 and the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 are separated from each other by the gap GP. The second gate contact overlapping layer MG2 and the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 are physically separated by the gap GP in the channel region.

[0064] The first gate contact overlapping layer MG1, the second gate contact overlapping layer MG2, and the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 overlap the channel region of the semiconductor layer 120. The overlapping layer ML does not overlap the channel region of the semiconductor layer 120 in the gap GP. That is, the gap GP is a region where the overlapping layer ML does not overlap the channel region of the semiconductor layer 120.

[0065] On a plane, the width Wg1 of the first gate contact overlapping layer MG1, the width Wg2 of the second gate contact overlapping layer MG2, and the width Ws1 of the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 may be the same. In addition, on a plane, the width WT of the entire region including the first gate contact overlapping layer MG1, the second gate contact overlapping layer MG2, the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1, and the plurality of gaps GP may be greater than the width W130 of the channel region of the semiconductor layer 120 overlapping the gate electrode 130. Each size of the plurality of gaps GP may be approximately 0.1 μm to 10 μm.

[0066] Here, the widths Wg1, Wg2, Ws1, WT and W130 may be lengths in the second direction D2 crossing the first direction D1, and the first gate contact overlapping layer MG1, the second gate contact overlapping layer MG2, the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 and the gate electrode 130 extend in the first direction D1.

[0067] See also Figure 2 , the buffer layer 112 is disposed on the overlapping layer ML. The semiconductor contact hole CS1 is formed in the buffer layer 112. A portion of the contact portion MS1-3 of the semiconductor contact overlapping layer MS1 may be exposed through the semiconductor contact hole CS1. The barrier layer 111 and the buffer layer 112 may include inorganic insulating materials such as silicon oxide, silicon nitride, and aluminum oxide. In addition, the barrier layer 111 and the buffer layer 112 may include organic insulating materials such as polyimide and polyacrylate (added with epoxy resin). The semiconductor layer 120 is placed on the buffer layer 112. The semiconductor layer 120 includes a channel portion 121 and doping portions 122 placed on both sides of the channel portion 121. The channel portion 121 may correspond to a channel region of a transistor, and the doping portion 122 may correspond to a source region and a drain region of the transistor. Any one doping portion 122 of the semiconductor layer 120 may be connected to the contact portion MS1-3 of the semiconductor contact overlapping layer MS1 through the semiconductor contact hole CS1. The first gate insulating layer 141 is disposed on the semiconductor layer 120, and the gate electrode 130 is disposed on the first gate insulating layer 141. The gate electrode 130 overlaps a channel region of the semiconductor layer 120.

[0068] Despite Figure 2 1 , but a first gate contact hole CG1 and a second gate contact hole CG2 are formed in the buffer layer 112 and the first gate insulating layer 141. A portion of the first gate contact overlapping layer MG1 is exposed by the first gate contact hole CG1. The gate electrode 130 overlaps with the first gate contact hole CG1 and may be connected to the first gate contact overlapping layer MG1 through the first gate contact hole CG1. A portion of the second gate contact overlapping layer MG2 is exposed by the second gate contact hole CG2. The gate electrode 130 may overlap with the second gate contact hole CG2 and may be connected to the second gate contact overlapping layer MG2 through the second gate contact hole CG2.

[0069] The second gate insulating layer 142 may be placed on the gate electrode 130, and the first electrode 151 and the second electrode 153 may be placed on the second gate insulating layer 142. The first electrode 151 may overlap one doped portion 122 of the semiconductor layer 120, and may be connected to the one doped portion 122 of the semiconductor layer 120 through a first electrode contact hole CE1 formed in the first gate insulating layer 141 and the second gate insulating layer 142. The second electrode 153 may overlap another doped portion 122 of the semiconductor layer 120, and may be connected to the other doped portion 122 of the semiconductor layer 120 through a second electrode contact hole CE2 formed in the first gate insulating layer 141 and the second gate insulating layer 142.

[0070] Depending on the direction of applied voltage or current, one of the first electrode 151 and the second electrode 153 may be a source electrode of the transistor, and the other may be a drain electrode. That is, the semiconductor contact overlapping layer MS1 may be connected to the source electrode or the drain electrode of the transistor.

[0071] As described above, the overlapping layer ML is composed of two or more separated structures within the channel region of the semiconductor layer 120, and the channel region may include an area (e.g., gap GP) that does not overlap with the overlapping layer ML. A portion of the overlapping layer ML (e.g., gate contact overlapping layers MG1 and MG2) may be connected to the gate electrode 130 of the transistor, while another portion (e.g., semiconductor contact overlapping layer MS1) may be connected to the source electrode or drain electrode of the transistor. According to this configuration, the data range of the transistor may be increased, and the current that may flow while the transistor is turned on may be increased. This will be described later.

[0072] In the following, see Figure 3 Description of the invention wherein the transistor is modified Figure 1 Some configurations of embodiments of the transistor.

[0073] Figure 3 It shows that the modified Figure 1 A top view of a transistor of some configuration embodiments. Focus on the above Figure 1 and Figure 2 The differences compared with the embodiments.

[0074] See also Figure 3, the width Ws1 of the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 may be greater than the width Wg1 of the first gate contact overlapping layer MG1. In addition, the width Ws1 of the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 may be greater than the width Wg2 of the second gate contact overlapping layer MG2. That is, on a plane, the width Ws1 of the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 may be different from the width Wg1 of the first gate contact overlapping layer MG1 and the width Wg2 of the second gate contact overlapping layer MG2. The width Wg1 of the first gate contact overlapping layer MG1 and the width Wg2 of the second gate contact overlapping layer MG2 may be the same or different. Even in this case, on a plane, the width WT of the entire region including the first gate contact overlapping layer MG1, the second gate contact overlapping layer MG2, the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1, and the plurality of gaps GP may be greater than the width W130 of the channel region of the semiconductor layer 120.

[0075] At the same time, Figure 3 In contrast to the example of , the width Ws1 of the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 may be smaller than the width Wg1 of the first gate contact overlapping layer MG1, and may be smaller than the width Wg2 of the second gate contact overlapping layer MG2. At this time, on a plane, the width WT of the entire region including the first gate contact overlapping layer MG1, the second gate contact overlapping layer MG2, the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1, and the plurality of gaps GP may be greater than the width W130 of the channel region of the semiconductor layer 120.

[0076] Apart from these differences, see Figure 1 and Figure 2 The features of the described embodiments can be applied to Figure 3 All embodiments described herein are described, and repeated descriptions between the embodiments are omitted.

[0077] In the following, see Figure 4 Describe the Figure 1 The transistor of the transistor of the embodiment is modified in some configurations.

[0078] Figure 4 It shows that the modified Figure 1 A top view of a transistor of some configuration embodiments. Focusing on the above Figure 1 and Figure 2 The differences compared with the embodiments.

[0079] See also Figure 4, on a plane, a width WT of the entire region including the first gate contact overlapping layer MG1, the second gate contact overlapping layer MG2, the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1, and the plurality of gaps GP may be smaller than a width W130 of the channel region of the semiconductor layer 120. In this case, a width Ws1 of the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 may be larger than a width Wg1 of the first gate contact overlapping layer MG1 and a width Wg2 of the second gate contact overlapping layer MG2, respectively. Alternatively, a width Ws1 of the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 may be equal to or smaller than a width Wg1 of the first gate contact overlapping layer MG1 and a width Wg2 of the second gate contact overlapping layer MG2, respectively.

[0080] In addition to these differences, see Figure 1 and Figure 2 The features of the described embodiments can all be applied to Figure 4 The embodiments are described in detail, and therefore repeated descriptions between the embodiments are omitted.

[0081] In the following, see Figure 5 Describe the Figure 1 The transistor of the transistor of the embodiment is modified in some configurations.

[0082] Figure 5 It shows that the modified Figure 1 A top view of a transistor of some configuration embodiments. Focus on the above Figure 1 and Figure 2 The differences compared with the embodiments.

[0083] See also Figure 5 The overlapping layer ML may further include a floating overlapping layer MF which is not connected to the semiconductor layer 120 and the gate electrode 130 and overlaps the channel region of the semiconductor layer 120. The floating overlapping layer MF is insulated from other conductors, and no voltage is applied to the floating overlapping layer MF.

[0084] The floating overlap layer MF may be disposed on the same layer as the gate contact overlap layers MG1 and MG2 and the semiconductor contact overlap layer MS1. In addition, on a plane, the floating overlap layer MF may be disposed close to at least one of the gate contact overlap layers MG1 and MG2 and the first overlap portion MS1-1 of the semiconductor contact overlap layer MS1 via the gap GP.

[0085] Figure 5The floating overlap layer MF is shown to be adjacent to the first gate contact overlap layer MG1. The floating overlap layer MF and the first gate contact overlap layer MG1 are disposed to be separated from each other by a gap GP, and the floating overlap layer MF and the first gate contact overlap layer MG1 are physically separated by the gap GP. The floating overlap layer MF may overlap the channel region of the semiconductor layer 120 and extend in parallel with the first gate contact overlap layer MG1 in the first direction D1.

[0086] The width Wf of the floating overlap layer MF may be the same as at least any one of the width Wg1 of the first gate contact overlap layer MG1, the width Wg2 of the second gate contact overlap layer MG2, and the width Ws1 of the first overlap portion MS1-1 of the semiconductor contact overlap layer MS1. Alternatively, the width Wf of the floating overlap layer MF may be different from the width Wg1 of the first gate contact overlap layer MG1, the width Wg2 of the second gate contact overlap layer MG2, and the width Ws1 of the first overlap portion MS1-1 of the semiconductor contact overlap layer MS1, respectively. At this time, the width Wg1 of the first gate contact overlap layer MG1, the width Wg2 of the second gate contact overlap layer MG2, and the width Ws1 of the first overlap portion MS1-1 of the semiconductor contact overlap layer MS1 may be the same as or different from each other. Moreover, the width WT' of the entire region including the floating overlap layer MF, the first gate contact overlap layer MG1, the second gate contact overlap layer MG2, the first overlap portion MS1-1 of the semiconductor contact overlap layer MS1, and the plurality of gaps GP may be equal to, greater than, or less than the width W130 of the channel region of the semiconductor layer 120.

[0087] In addition to these differences, see Figure 1 and Figure 2 The features of the described embodiments can all be applied to Figure 5 The embodiments are described in detail, and therefore repeated descriptions between the embodiments are omitted.

[0088] Next, see Figure 6 and Figure 7 A transistor of another embodiment is described.

[0089] Figure 6 is a top view showing a transistor according to another embodiment of the present invention. Figure 7 is along Figure 6 Focus on the cross-sectional view taken along the line VII-VII'. Figure 1 and Figure 2 The differences compared with the embodiments.

[0090] See also Figure 6 and Figure 7The overlapping layer ML includes a first gate contact overlapping layer MG1 and a semiconductor contact overlapping layer MS1. The first gate contact overlapping layer MG1 partially overlaps the semiconductor layer 120 and contacts the gate electrode 130 through the first gate contact hole CG1.

[0091] The first gate contact overlapping layer MG1 is placed at the central portion of the gate electrode 130 and extends in the first direction D1 to overlap the channel region. The first gate contact overlapping layer MG1 includes a first extension portion MG1-1 that extends farther than the semiconductor layer 120 in the first direction D1 and does not overlap the semiconductor layer 120 but overlaps the gate electrode 130. The first gate contact hole CG1 is placed at a position overlapping the first extension portion MG1-1, and the first gate contact overlapping layer MG1 may be directly connected to the gate electrode 130 through the first gate contact hole CG1.

[0092] The semiconductor contact overlapping layer MS1 may include a first overlapping portion MS1-1a, a second overlapping portion MS1-1b, an extension portion MS1-2, and a contact portion MS1-3. The first overlapping portion MS1-1a extends along one side of the gate electrode 130 in the first direction D1 to overlap with the channel region. The first overlapping portion MS1-1a may overlap the semiconductor layer 120 and the gate electrode 130. The second overlapping portion MS1-1b extends along the other side of the gate electrode 130 in the first direction D1 to overlap with the channel region. The second overlapping portion MS1-1b may overlap the semiconductor layer 120 and the gate electrode 130. The contact portion MS1-3 does not overlap with the gate electrode 130, but overlaps with the semiconductor layer 120. The semiconductor contact hole CS1 is placed in the contact portion MS1-3, and the contact portion MS1-3 may contact the semiconductor layer 120 through the semiconductor contact hole CS1. The extension portion MS1-2 has a structure that connects the first overlapping portion MS1-1a, the second overlapping portion MS1-1b, and the contact portion MS1-3 to each other. The extension portion MS1 ​​- 2 may not overlap with the semiconductor layer 120 .

[0093] On a plane, the first gate contact overlap layer MG1 may be disposed between the first overlap portion MS1 ​​- 1 a and the second overlap portion MS1 ​​- 1 b of the semiconductor contact overlap layer MS1 and parallel to the first overlap portion MS1 ​​- 1 a and the second overlap portion MS1 ​​- 1 b .

[0094] On a plane, the first gate contact overlapping layer MG1 and the first overlapping portion MS1-1a of the semiconductor contact overlapping layer MS1 are arranged to be separated by a gap GP. Moreover, the first gate contact overlapping layer MG1 and the second overlapping portion MS1-1b of the semiconductor contact overlapping layer MS1 are separated from each other by the gap GP. The first gate contact overlapping layer MG1 and the first overlapping portion MS1-1a of the semiconductor contact overlapping layer MS1 are physically separated by the gap GP in the channel region. In addition, the first gate contact overlapping layer MG1 and the second overlapping portion MS1-1b of the semiconductor contact overlapping layer MS1 are physically separated by the gap GP in the channel region.

[0095] The first gate contact overlapping layer MG1 , the first overlapping portion MS1 ​​- 1 a , and the second overlapping portion MS1 ​​- 1 b of the semiconductor contact overlapping layer MS1 overlap the channel region of the semiconductor layer 120 , and the overlapping layer ML does not overlap the channel region of the semiconductor layer 120 in the gap GP.

[0096] The width Wg1 of the first gate contact overlap layer MG1, the width Ws1 of the first overlap portion MS1-1a of the semiconductor contact overlap layer MS1, and the width Ws2 of the second overlap portion MS1-1b of the semiconductor contact overlap layer MS1 may be the same as each other. Moreover, the width WT of the entire region including the first gate contact overlap layer MG1, the first overlap portion MS1-1a of the semiconductor contact overlap layer MS1, the second overlap portion MS1-1b of the semiconductor contact overlap layer MS1, and the plurality of gaps GP may be greater than the width W130 of the channel region of the semiconductor layer 120.

[0097] Despite Figure 7 Although not shown in the figure, the first gate contact hole CG1 is formed in the buffer layer 112 and the first gate insulating layer 141. A portion of the first gate contact overlapping layer MG1 is exposed by the first gate contact hole CG1. The gate electrode 130 overlaps with the first gate contact hole CG1 and may be connected to the first gate contact overlapping layer MG1 through the first gate contact hole CG1. Figure 6 and Figure 7 In, not required Figure 1 and Figure 2 The second gate contact hole CG2 described in .

[0098] In addition to these differences, see Figure 1 and Figure 2 The features of the described embodiments can all be applied to Figure 6 and Figure 7 The embodiments are described in detail, and therefore repeated descriptions between the embodiments are omitted.

[0099] In the following, see Figure 8 Describe the Figure 6 The transistor of the transistor of the embodiment is modified in some configurations.

[0100] Figure 8 It shows that the modified Figure 6 A top view of a transistor of some configuration embodiments of the present invention. Figure 6 and Figure 7 The differences compared with the embodiments.

[0101] See also Figure 8 , the width Wg1 of the first gate contact overlapping layer MG1 may be greater than the width Ws1 of the first overlapping portion MS1-1a of the semiconductor contact overlapping layer MS1. Moreover, the width Wg1 of the first gate contact overlapping layer MG1 may be greater than the width Ws2 of the second overlapping portion MS1-1b of the semiconductor contact overlapping layer MS1. That is, the width Wg1 of the first gate contact overlapping layer MG1 may be different from the width Ws1 of the first overlapping portion MS1-1a of the semiconductor contact overlapping layer MS1 and the width Ws2 of the second overlapping portion MS1-1b of the semiconductor contact overlapping layer MS1. The width Ws1 of the first overlapping portion MS1-1a of the semiconductor contact overlapping layer MS1 and the width Ws2 of the second overlapping portion MS1-1b of the semiconductor contact overlapping layer MS1 may be the same or different. Even in this case, the width WT of the entire region including the first gate contact overlapping layer MG1, the first overlapping portion MS1-1a of the semiconductor contact overlapping layer MS1, the second overlapping portion MS1-1b of the semiconductor contact overlapping layer MS1, and the plurality of gaps GP may be greater than the width W130 of the channel region of the semiconductor layer 120.

[0102] At the same time, Figure 8 In contrast to the example of , the width Wg1 of the first gate contact overlapping layer MG1 may be smaller than the width Ws1 of the first overlapping portion MS1-1a of the semiconductor contact overlapping layer MS1, and may be smaller than the width Ws2 of the second overlapping portion MS1-1b of the semiconductor contact overlapping layer MS1. At this time, on a plane, the width WT of the entire region including the first gate contact overlapping layer MG1, the first overlapping portion MS1-1a of the semiconductor contact overlapping layer MS1, the second overlapping portion MS1-1b of the semiconductor contact overlapping layer MS1, and the plurality of gaps GP may be greater than the width W130 of the channel region of the semiconductor layer 120.

[0103] In addition to these differences, see Figure 6 and Figure 7 The features of the described embodiments can all be applied to Figure 8 The embodiments are described in detail, and therefore repeated descriptions between the embodiments are omitted.

[0104] In the following, see Fig. 9 Describe the Figure 6 The transistor of the transistor of the embodiment is modified in some configurations.

[0105] Fig. 9 It shows that the modified Figure 6 A top view of a transistor of some configuration embodiments of the present invention. Figure 6 and Figure 7 The differences compared with the embodiments.

[0106] See also Fig. 9 , the width WT of the entire region including the first gate contact overlapping layer MG1, the first overlapping portion MS1-1a of the semiconductor contact overlapping layer MS1, the second overlapping portion MS1-1b of the semiconductor contact overlapping layer MS1, and the plurality of gaps GP may be smaller than the width W130 of the channel region of the semiconductor layer 120. At this time, the width Wg1 of the first gate contact overlapping layer MG1 may be larger than the width Ws1 of the first overlapping portion MS1-1a of the semiconductor contact overlapping layer MS1 and the width Ws2 of the second overlapping portion MS1-1b of the semiconductor contact overlapping layer MS1. Alternatively, the width Wg1 of the first gate contact overlapping layer MG1 may be equal to or smaller than the width Ws1 of the first overlapping portion MS1-1a of the semiconductor contact overlapping layer MS1 and the width Ws2 of the second overlapping portion MS1-1b of the semiconductor contact overlapping layer MS1.

[0107] In addition to these differences, see Figure 6 and Figure 7 The features of the described embodiments can all be applied to Fig. 9 The embodiments are described in detail, and therefore repeated descriptions between the embodiments are omitted.

[0108] In the following, see Fig.10 Describe the Figure 6 The transistor of the transistor of the embodiment is modified in some configurations.

[0109] Fig.10 It shows that the modified Figure 6 A top view of a transistor of some configuration embodiments of the present invention. Figure 6 and Figure 7 The differences compared with the embodiments.

[0110] See also Fig.10 , the overlapping layer ML may further include a floating overlapping layer MF overlapping the channel region without being connected to the semiconductor layer 120 and the gate electrode 130. The floating overlapping layer MF is insulated from other conductors, and no voltage is applied to the floating overlapping layer MF.

[0111] The floating overlap layer MF may be placed on the same layer as the first gate contact overlap layer MG1 and the semiconductor contact overlap layer MS1. On a plane, the floating overlap layer MF may be spaced apart from at least one of the first gate contact overlap layer MG1, the first overlap portion MS1-1a of the semiconductor contact overlap layer MS1, and the second overlap portion MS1-1b of the semiconductor contact overlap layer MS1 by a gap GP.

[0112] Fig.10 The floating overlap layer MF is shown to be close to the first overlap portion MS1-1a of the semiconductor contact overlap layer MS1. The floating overlap layer MF and the first overlap portion MS1-1a of the semiconductor contact overlap layer MS1 are spaced apart from each other by a gap GP, and the floating overlap layer MF and the first overlap portion MS1-1a of the semiconductor contact overlap layer MS1 are physically separated by the gap GP. The floating overlap layer MF may overlap the channel region of the semiconductor layer 120 and may extend in parallel with the first overlap portion MS1-1a of the semiconductor contact overlap layer MS1 in the first direction D1.

[0113] The width Wf of the floating overlap layer MF may be the same as at least any one of the width Wg1 of the first gate contact overlap layer MG1, the width Ws1 of the first overlap portion MS1-1a of the semiconductor contact overlap layer MS1, and the width Ws2 of the second overlap portion MS1-1b of the semiconductor contact overlap layer MS1. Alternatively, the width Wf of the floating overlap layer MF may be different from the width Wg1 of the first gate contact overlap layer MG1, the width Ws1 of the first overlap portion MS1-1a of the semiconductor contact overlap layer MS1, and the width Ws2 of the second overlap portion MS1-1b of the semiconductor contact overlap layer MS1, respectively. At this time, the width Wg1 of the first gate contact overlap layer MG1, the width Ws1 of the first overlap portion MS1-1a of the semiconductor contact overlap layer MS1, and the width Ws2 of the second overlap portion MS1-1b of the semiconductor contact overlap layer MS1 may be the same or different. In addition, the width WT' of the entire area including the floating overlapping layer MF, the first gate contact overlapping layer MG1, the first overlapping portion MS1-1a of the semiconductor contact overlapping layer MS1, the second overlapping portion MS1-1b of the semiconductor contact overlapping layer MS1 and the plurality of gaps GP may be equal to or greater than the width W130 of the channel region of the semiconductor layer 120, or may be less than the width W130 of the channel region.

[0114] In addition to these differences, see Figure 6 and Figure 7 The features of the described embodiments can all be applied to Fig.10 The embodiments are described in detail, and therefore repeated descriptions between the embodiments are omitted.

[0115] In the above Figures 1 to 4 and Figures 6 to 9In the embodiment of FIG. 1 , the overlapping layer ML in the channel region of the semiconductor layer 120 is composed of three separate structures separated by two gaps GP, while in the above Figure 5 and Fig.10 In the embodiment of the present invention, the overlapping layer ML in the channel region of the semiconductor layer 120 is composed of four separation structures separated by three gaps GP. In this way, the overlapping layer ML can be formed by a plurality of separation structures in the channel region of the semiconductor layer 120. The number of separation structures of the overlapping layer ML in the channel region of the semiconductor layer 120 is not limited.

[0116] In the following, see Fig.11 An embodiment of two separated structures in which the overlapping layer ML is separated by a gap GP is described.

[0117] Fig.11 FIG. 1 is a top view of a transistor according to another embodiment of the present invention. Figure 1 and Figure 2 The differences compared with the embodiments.

[0118] See also Fig.11 ,and Figure 1 Compared with the embodiment of the present invention, the second gate contact overlapping layer MG2 is omitted. The first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 extends in the first direction D1 along the other side of the gate electrode 130. The first gate contact overlapping layer MG1 and the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 are spaced apart from each other by the gap GP, and the first gate contact overlapping layer MG1 and the first overlapping portion MS1-1 of the semiconductor contact overlapping layer MS1 can be physically separated by the gap GP.

[0119] Apart from these differences, see Figure 1 and Figure 2 The features of the described embodiments can all be applied to Fig.11 Furthermore, the embodiment described herein is modified as shown in Figures 3 to 5 The features of some of the described embodiments may all be applied to Fig.11 Therefore, repeated descriptions between the embodiments are omitted.

[0120] Now, see Fig.12 An embodiment in which the overlapping layer ML is formed as one is described.

[0121] Fig.12 1 is a top view of a transistor according to another embodiment of the present invention. Figure 1 and Figure 2 The differences compared with the embodiments.

[0122] See also Fig.12, the overlapping layer ML may include only the first gate contact overlapping layer MG1, but not Figure 1 and Figure 2 The semiconductor contact overlapping layer MS1 described in the embodiment of the present invention is formed. The width Wg1 of the first gate contact overlapping layer MG1 may correspond to the width WT of the entire overlapping layer ML. The width Wg1 of the first gate contact overlapping layer MG1 may be greater than the width W130 of the gate electrode 130. That is, the first gate contact overlapping layer MG1 may overlap the entire channel region of the transistor.

[0123] In addition to these differences, see Figure 1 and Figure 2 The features of the described embodiments can all be applied to Fig.11 The embodiments are described in detail, and therefore repeated descriptions between the embodiments are omitted.

[0124] In the following, see Fig.13 A display device according to an embodiment is described, and referring to Fig.14 A pixel according to an embodiment of the present invention included in a display device is described.

[0125] Fig.13 is a block diagram of a display device according to an embodiment.

[0126] See also Fig.13 , the display device includes a signal controller 100 , a gate driver 200 , a data driver 300 , a light emission control driver 400 , a power supply unit 500 , and a display unit 600 .

[0127] The signal controller 100 receives image signals R, G, and B input from an external device and an input control signal for controlling the display thereof. The image signals R, G, and B store brightness information of each pixel PX, and the brightness has a predetermined number of gray levels. Examples of the input control signal include a data enable signal DE, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a main clock signal MCLK, etc.

[0128] The signal controller 100 appropriately processes the input image signals R, G, and B according to the operating conditions of the display unit 600 and the data driver 300 based on the input image signals R, G, and B and the input control signal, and generates a first control signal CONT1, a second control signal CONT2, an image data signal DAT, and a third control signal CONT3. The signal controller 100 transmits the first control signal CONT1 to the gate driver 200, transmits the second control signal CONT2 and the image data signal DAT to the data driver 300, and transmits the third control signal CONT3 to the light emission control driver 400.

[0129] The display unit 600 includes a plurality of gate lines SL1-SLn, a plurality of data lines DL1-DLm, a plurality of light emitting control lines EL1-ELn and a plurality of pixels PX. A plurality of pixels PX are connected to a plurality of gate lines SL1-SLn, a plurality of data lines DL1-DLm and a plurality of light emitting control lines EL1-ELn, and may be arranged in a suitable matrix form. A plurality of gate lines SL1-SLn may extend in a roughly row direction and may be parallel to each other. A plurality of light emitting control lines EL1-ELn may extend in a roughly row direction and may be parallel to each other. A plurality of data lines DL1-DLm may extend in a roughly column direction and may be parallel to each other. The display unit 600 may correspond to a display area in which a plurality of pixels PX are placed and an image is displayed.

[0130] The gate driver 200 is connected to the plurality of gate lines SL1-SLn and transmits a gate signal consisting of a combination of a gate-on voltage and a gate-off voltage to the plurality of gate lines SL1-SLn according to the first control signal CONT1. The gate driver 200 may sequentially apply the gate signal of the gate-on voltage to the plurality of gate lines SL1-SLn.

[0131] The gate driver 200 may be placed in a non-display area around the display area. That is, the gate driver 200 may be placed on the substrate 110 included in the display device in the non-display area. The gate driver 200 includes a plurality of transistors for sequentially applying a gate signal of a gate-on voltage to a plurality of gate lines SL1-SLn, and at least one of the plurality of transistors may include the above Figures 1 to 12 Any of the transistors described in .

[0132] The data driver 300 is connected to the plurality of data lines DL1-DLm and samples and holds the image data signal DAT according to the second control signal CONT2 and applies the data voltage to the plurality of data lines DL1-DLm. The data driver 300 may apply the data voltage having a predetermined voltage range to the plurality of data lines DL1-DLm in response to the gate signal of the gate-on voltage.

[0133] The light emission control driver 400 is connected to the plurality of light emission control lines EL1-ELn and may apply a light emission control signal consisting of a combination of a gate-on voltage and a gate-off voltage to the plurality of light emission control lines EL1-ELn according to a third control signal CONT3. The light emission control driver 400 may sequentially apply the light emission control signal of the gate-on voltage to the plurality of light emission control lines EL1-ELn.

[0134] The light emission control driver 400 may be placed on the substrate 110 included in the display device in the non-display area. The light emission control driver 400 includes a plurality of transistors for sequentially applying a light emission control signal of a gate-on voltage to a plurality of light emission control lines EL1-ELn, and at least one of the plurality of transistors may include the above Figures 1 to 12 Any of the transistors described in .

[0135] The power supply unit 500 supplies a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage Vint to the plurality of pixels PX. The first power supply voltage ELVDD may be a high level voltage supplied to an anode of a light emitting diode LED included in each of the plurality of pixels PX. The second power supply voltage ELVSS may be a low level voltage supplied to a cathode of a light emitting diode LED included in each of the plurality of pixels PX. The first power supply voltage ELVDD and the second power supply voltage ELVSS are driving voltages for causing the plurality of pixels PX to emit.

[0136] Fig.14 1 is a circuit diagram showing one pixel of a display device according to an embodiment of the present invention. Fig.13 A pixel PX placed in an n-th pixel row and an m-th pixel column among a plurality of pixels PX included in a display device.

[0137] See also Fig.14 , the pixel PX includes a light emitting diode LED and a pixel circuit 10 for controlling a current flowing from a first power supply voltage ELVDD to the light emitting diode LED. A first gate line SLn, a second gate line SLIn, a third gate line SLBn, a data line DLm and a light emitting control line ELn may be connected to the pixel circuit 10. The second gate line SLIn may be a gate line to which a gate signal is applied by a pixel row before the first gate line SLn. The third gate line SLBn may be a gate line to which a gate signal is applied by a pixel row before the second gate line SLIn, a gate line to which the same gate signal as the second gate line SLIn is applied, a gate line to which the same gate signal as the first gate line SLn is applied, or a gate line to which a gate signal is applied by a pixel row later than the first gate line SLn. The gate signal applied to the third gate line SLBn may be changed differently according to a driving method of the display device.

[0138] The pixel circuit 10 may include a driving transistor TR11 , a switching transistor TR12 , a compensation transistor TR13 , a first light emission control transistor TR14 , a second light emission control transistor TR15 , an initialization transistor TR16 , a reset transistor TR17 , and a storage capacitor Cst.

[0139] The driving transistor TR11 includes a gate electrode connected to the first node N11, a first electrode connected to the third node N13, and a second electrode connected to the second node N12. The driving transistor TR11 is connected between the first power supply voltage ELVDD and the light emitting diode LED, and controls the amount of current flowing from the first power supply voltage ELVDD to the light emitting diode LED in response to the voltage of the first node N11. The driving transistor TR11 may further include a gate contact overlapping layer MG connected to the gate electrode and a semiconductor contact overlapping layer MS1 connected to the second electrode. The gate contact overlapping layer MG of the driving transistor TR11 may be electrically connected to the first node N11, and the semiconductor contact overlapping layer MS1 of the driving transistor TR11 may be electrically connected to the second node N12. The gate contact overlapping layer MG and the semiconductor contact overlapping layer MS1 of the driving transistor TR11 overlap with the channel region of the driving transistor TR11. The gate contact overlapping layer MG may include the above Figures 1 to 4 The first gate contact overlapping layer MG1 and the second gate contact overlapping layer MG2 described in the embodiment of the present invention are shown in FIG. Figures 6 to 9 In addition, according to an embodiment, the driving transistor may be formed by Figures 1 to 5 The transistor structure described in is formed.

[0140] The switching transistor TR12 includes a gate electrode connected to the first gate line SLn, a first electrode connected to the data line DLm, and a second electrode connected to the second node N12. The switching transistor TR12 is connected between the data line DLm and the driving transistor TR11, and is turned on according to a first gate signal of a gate-on voltage applied to the first gate line SLn to transmit the data voltage Vdat applied to the data line DLm to the second node N12. The switching transistor TR12 may further include a gate contact overlapping layer MG connected to the gate electrode. The gate contact overlapping layer MG of the switching transistor TR12 overlaps with a channel region of the switching transistor TR12. The gate contact overlapping layer MG of the switching transistor TR12 may be electrically connected to the first gate line SLn. The switching transistor TR12 may be composed of Fig.12 The transistor structure shown in is formed.

[0141] The compensation transistor TR13 includes a first compensation transistor TR13-1 and a second compensation transistor TR13-2. The first compensation transistor TR13-1 includes a gate electrode connected to a first gate line SLn, a first electrode connected to a second electrode of the second compensation transistor TR13-2, and a second electrode connected to a first node N11. The second compensation transistor TR13-2 includes a gate electrode connected to the first gate line SLn, a first electrode connected to a third node N13, and a second electrode connected to the first electrode of the first compensation transistor TR13-1. The first compensation transistor TR13-1 and the second compensation transistor TR13-2 are connected between the first electrode and the gate electrode of the driving transistor TR11, and are turned on according to a first gate signal of a gate-on voltage applied to the first gate line SLn. The first compensation transistor TR13-1 and the second compensation transistor TR13-2 may diode-connect the driving transistor TR11 to compensate for the threshold voltage of the driving transistor TR11. The first compensation transistor TR13-1 and the second compensation transistor TR13-2 may further include a gate contact overlapping layer MG, respectively. Each gate contact overlapping layer MG of the first compensation transistor TR13-1 and the second compensation transistor TR13-2 may be electrically connected to the first gate line SLn. Each gate contact overlapping layer MG of the first compensation transistor TR13-1 and the second compensation transistor TR13-2 overlaps with each channel region of the first compensation transistor TR13-1 and the second compensation transistor TR13-2. The first compensation transistor TR13-1 and the second compensation transistor TR13-2 may be formed by Fig.12 The transistor structure shown in is formed. Fig.14 , it is shown that the compensation transistor TR13 includes a first compensation transistor TR13 - 1 and a second compensation transistor TR13 - 2 , but according to an embodiment, the compensation transistor TR13 may be formed as one.

[0142] The first light emission control transistor TR14 includes a gate electrode connected to the light emission control line ELn, a first electrode connected to the first power supply voltage ELVDD, and a second electrode connected to the second node N12. The first light emission control transistor TR14 is connected between the first power supply voltage ELVDD and the driving transistor TR11, and is turned on according to the light emission control signal of the gate-on voltage applied to the light emission control line ELn to transfer the first power supply voltage ELVDD to the driving transistor TR11.

[0143] The second light emission control transistor TR15 includes a gate electrode connected to the light emission control line ELn, a first electrode connected to the third node N13, and a second electrode connected to the anode of the light emitting diode LED. The second light emission control transistor TR15 is connected between the driving transistor TR11 and the light emitting diode LED, and is turned on according to the light emission control signal of the gate-on voltage applied to the light emission control line ELn to transmit the current flowing through the driving transistor TR11 to the light emitting diode LED.

[0144] The initialization transistor TR16 includes a first initialization transistor TR16-1 and a second initialization transistor TR16-2. The first initialization transistor TR16-1 includes a gate electrode connected to the second gate line SLIn, a first electrode connected to the second electrode of the second initialization transistor TR16-2, and a second electrode connected to the first node N11. The second initialization transistor TR16-2 includes a gate electrode connected to the second gate line SLIn, a first electrode connected to the initialization voltage Vint, and a second electrode connected to the first electrode of the first initialization transistor TR16-1. The first initialization transistor TR16-1 and the second initialization transistor TR16-2 are connected between the gate electrode of the driving transistor TR11 and the initialization voltage Vint, and are turned on according to the second gate signal of the gate-on voltage applied to the second gate line SLIn to transmit the initialization voltage Vint to the first node N11, thereby initializing the gate voltage of the driving transistor TR11 to the initialization voltage Vint. The first initialization transistor TR16-1 and the second initialization transistor TR16-2 may further include a gate contact overlapping layer MG connected to the gate electrode, respectively. Each gate contact overlapping layer MG of the first initialization transistor TR16-1 and the second initialization transistor TR16-2 may be electrically connected to the second gate line SLIn. Each gate contact overlapping layer MG of the first initialization transistor TR16-1 and the second initialization transistor TR16-2 overlaps with each channel region of the first initialization transistor TR16-1 and the second initialization transistor TR16-2. The first initialization transistor TR16-1 and the second initialization transistor TR16-2 may be formed by Fig.12 The transistor structure shown in is formed. Fig.14 It is illustrated that the initialization transistor TR16 includes a first initialization transistor TR16 - 1 and a second initialization transistor TR16 - 2 , but according to an embodiment, the initialization transistor TR16 may be formed as one.

[0145] The reset transistor TR17 includes a gate electrode connected to the third gate line SLBn, a first electrode connected to the initialization voltage Vint, and a second electrode connected to the anode of the light emitting diode LED. The reset transistor TR17 is connected between the anode of the light emitting diode LED and the initialization voltage Vint, and is turned on by a third gate signal of the gate-on voltage applied to the third gate line SLBn. The reset transistor TR17 can transmit the initialization voltage Vint to the anode of the light emitting diode LED to reset the light emitting diode LED to the initialization voltage Vint. According to an embodiment, the reset transistor TR17 can be omitted.

[0146] The driving transistor TR11, the switching transistor TR12, the compensating transistor TR13, the first light emission control transistor TR14, the second light emission control transistor TR15, the initialization transistor TR16 and the reset transistor TR17 may each be a p-channel electric field effect transistor. The gate-on voltage for turning on the p-channel electric field effect transistor is a low-level voltage, and the gate-off voltage for turning it off is a high-level voltage.

[0147] According to an embodiment, at least one of the driving transistor TR11, the switching transistor TR12, the compensation transistor TR13, the first light emission control transistor TR14, the second light emission control transistor TR15, the initialization transistor TR16, and the reset transistor TR17 may be an n-channel electric field effect transistor. A gate-on voltage for turning on the n-channel electric field effect transistor is a high-level voltage, and a gate-off voltage for turning it off is a low-level voltage.

[0148] The storage capacitor Cst includes a first electrode connected to the first power voltage ELVDD and a second electrode connected to the first node N11. The data voltage compensating the threshold voltage of the driving transistor TR11 is transmitted to the first node N11, and the storage capacitor Cst serves to maintain the voltage of the first node N11.

[0149] The light emitting diode LED includes an anode connected to the second electrode of the second light emitting control transistor TR15 and a cathode connected to the second power supply voltage ELVSS. The light emitting diode LED is connected between the pixel circuit 10 and the second power supply voltage ELVSS so as to emit light with a brightness corresponding to the current supplied from the pixel circuit 10. The light emitting diode LED may include an emission layer, which includes at least one of an organic light emitting material and an inorganic light emitting material. Holes and electrons are injected into the organic emission layer from the anode and the cathode, and when the excitons, which are a combination of the injected holes and electrons, fall from an excited state to a ground state, emission of light from the organic emission layer occurs. The light emitting diode LED may emit one of the primary colors and white. For example, the primary colors may be three primary colors of red, green and blue. Another example of the primary colors may be yellow, cyan, magenta, etc.

[0150] Now, see Fig.15 The description includes the following: wherein the driving transistor TR11 is composed of Figure 6 and Figure 7 The transistor structure shown in the figure forms a structure of a pixel display device.

[0151] Fig.15 is a cross-sectional view showing the structure of a display device according to an embodiment of the present invention.

[0152] See also Fig.15 , the organic layer 161 may be disposed on the first electrode 151 , the second electrode 153 , and the second gate insulating layer 142 .

[0153] The pixel electrode 171 may be disposed on the organic layer 161, and the pixel electrode 171 may be electrically connected to the first electrode 151 of the driving transistor TR11 through a contact hole (not shown) passing through the organic layer 161. That is, the first electrode 151 of the driving transistor TR11 may be electrically connected to the light emitting diode LED through the second light emission control transistor TR15, and in this case, the pixel electrode 171 (e.g., an anode) of the light emitting diode LED may be connected to the second electrode of the second light emission control transistor TR15 through the contact hole of the organic layer 161.

[0154] The emission layer 172 is placed on the pixel electrode 171, and the power electrode 173 is disposed on the emission layer 172. The power electrode 173 may be formed of a transparent conductor such as ITO, IZO, etc. The pixel electrode 171, the emission layer 172, and the power electrode 173 form a light emitting diode LED.

[0155] A defining layer 162 defining an area of ​​the light emitting diode may be provided around the pixel electrode 171. An encapsulation layer 180 for protecting the light emitting diode LED may be placed on the light emitting diode LED. The encapsulation layer 180 may be formed of an inorganic layer and an organic layer stacked alternately. According to an embodiment, the encapsulation layer 180 may be provided with an encapsulation member such as transparent glass or plastic, and the encapsulation member is bonded to the insulating substrate 110 using a sealant (not shown), thereby sealing the internal space and protecting the light emitting diode LED.

[0156] Because of the above Figure 6 and Figure 7 The features of the described embodiments can all be applied to Fig.15 The embodiments are described in detail, and therefore repeated descriptions between the embodiments are omitted.

[0157] Now, we will see Fig.16 Description based on Fig.14 A method for driving a display device including a pixel according to an embodiment of the present invention, and referring to Fig.17and Fig.18 Characteristics of a transistor according to an embodiment of the present invention are described.

[0158] Fig.16 is a timing diagram illustrating a driving method of a display device according to an embodiment. Fig.17 is a graph showing characteristics of a transistor according to an embodiment of the present invention. Fig.18 is a circuit diagram showing a pixel according to the embodiment.

[0159] See also Fig.16 and Fig.17 , the driving method of the display device according to the embodiment may include an initialization period T1, a data writing period T2, a reset period T3, and a light emitting period T4.

[0160] During the initialization period T1, the second gate signal SLI[n] is applied as the gate-on voltage On. In this case, the first gate signal SL[n], the third gate signal SLB[n] and the light emitting control signal E[n] are applied as the gate-off voltage Off. The first initialization transistor TR16-1 and the second initialization transistor TR16-2 are turned on by the second gate signal SLI[n] of the gate-on voltage On, and the initialization voltage Vint is transmitted to the first node N11. The gate voltage of the driving transistor TR11 can be initialized by the initialization voltage Vint.

[0161] Each of the first initialization transistor TR16-1 and the second initialization transistor TR16-2 includes a gate contact overlapping layer MG. The second gate signal SLI[n] is applied to each gate contact overlapping layer MG of the first initialization transistor TR16-1 and the second initialization transistor TR16-2. Thus, when the first initialization transistor TR16-1 and the second initialization transistor TR16-2 are fully turned on, the current flowing through the first initialization transistor TR16-1 and the second initialization transistor TR16-2 increases. Fig.17 and Fig.18 Describe this.

[0162] Fig.17 2 is a graph showing characteristic curves of a general transistor TR_N and a transistor TR_S including a gate contact overlapping layer MG and a semiconductor contact overlapping layer MS1 according to an embodiment of the present invention. Fig.18 The pixel circuit 20 illustrated in FIG. Fig.18 In the pixel circuit 20, Fig.14 Compared with the pixel circuit 10, all transistors included in the pixel circuit 20 do not have Fig.14 A general transistor TR_N having a gate contact overlapping layer MG and a semiconductor contact overlapping layer MS1 described in FIG.

[0163] exist Fig.17 , the horizontal axis represents the gate-source voltage difference Vgs of the transistor, and the vertical axis represents the current Ids flowing to the transistor.

[0164] Since the gate contact overlapping layer MG is included in the transistor TR_S according to the embodiment of the present invention, the current flowing through the transistor TR_S according to the embodiment of the present invention increases more than the current flowing through the general transistor TR_N due to the gate-source voltage difference Vgs of the fully turned-on transistor. The gate-source voltage difference Vgs of the fully turned-on transistor may represent the gate-source voltage difference Vgs through which the transistor can flow the maximum current. In other words, the voltage required to increase the current through the transistor TR_S according to the present embodiment is lower than the voltage required to increase the current through the general transistor TR_N.

[0165] See again Fig.16 In other words, since each of the first initialization transistor TR16-1 and the second initialization transistor TR16-2 includes the gate contact overlapping layer MG, when the first initialization transistor TR16-1 and the second initialization transistor TR16-2 are fully turned on, the current flowing through the first initialization transistor TR16-1 and the second initialization transistor TR16-2 increases.

[0166] During the data writing period T2, the first gate signal SL[n] is applied as the gate-on voltage On. In this case, the second gate signal SLI[n], the third gate signal SLB[n] and the light emitting control signal E[n] are applied as the gate-off voltage Off. The switching transistor TR12, the first compensation transistor TR13-1 and the second compensation transistor TR13-2 are turned on by the first gate signal SL[n] of the gate-on voltage On. The data voltage Vdat is transmitted to the second node N12 through the turned-on switching transistor TR12. When the first compensation transistor TR13-1 and the second compensation transistor TR13-2 are turned on, the driving transistor TR11 is diode-connected, and the data voltage in which the threshold voltage of the driving transistor TR11 is compensated is transmitted to the first node N11. The voltage transmitted to the first node N11 can be charged in the storage capacitor Cst.

[0167] The switching transistor TR12 includes a gate contact overlapping layer MG, and a first gate signal SL[n] is applied to the gate contact overlapping layer MG of the switching transistor TR12. Since the switching transistor TR12 includes the gate contact overlapping layer MG, when the switching transistor TR12 is fully turned on, the current flowing through the switching transistor TR12 increases. Moreover, each of the first compensation transistor TR13-1 and the second compensation transistor TR13-2 includes a gate contact overlapping layer MG, and a first gate signal SL[n] is applied to each gate contact overlapping layer MG of the first compensation transistor TR13-1 and the second compensation transistor TR13-2. Since each of the first compensation transistor TR13-1 and the second compensation transistor TR13-2 includes a gate contact overlapping layer MG, when the first compensation transistor TR13-1 and the second compensation transistor TR13-2 are fully turned on, the current flowing through the first compensation transistor TR13-1 and the second compensation transistor TR13-2 increases. In addition, since the driving transistor TR11 includes the gate contact overlapping layer MG, the current flowing through the driving transistor TR11 may also increase.

[0168] The data voltage Vdat applied to the data line DLm may be transmitted to the first node N11 more quickly through the switching transistor TR12, the first compensation transistor TR13-1, and the second compensation transistor TR13-2, and the data voltage in which the threshold voltage of the driving transistor TR11 is compensated may be charged in the storage capacitor Cst more quickly.

[0169] During the reset period T3, the third gate signal SLB[n] of the gate-on voltage On is applied to the third gate line SLBn. In this case, the first gate signal SL[n] applied to the first gate line SLn, the second gate signal SLI[n] applied to the second gate line SLIn, and the light-emitting control signal E[n] applied to the light-emitting control line ELn are applied as the gate-off voltage Off. The reset transistor TR17 is turned on by the third gate signal SLB[n] of the gate-on voltage On, and the initialization voltage Vint is transmitted to the anode of the light-emitting diode LED. The light-emitting diode LED can be reset by the initialization voltage Vint.

[0170] During the light emission period T4, the light emission control signal E[n] is applied as a gate-on voltage On. In this case, the first gate signal SL[n], the second gate signal SLI[n], and the third gate signal SLB[n] are applied as gate-off voltages Off. The first light emission control transistor TR14 and the second light emission control transistor TR15 are turned on by the light emission control signal E[n] of the gate-on voltage On. The first power supply voltage ELVDD is transmitted to the second node N12 through the turned-on first light emission control transistor TR14, and the driving transistor TR11 and the light emitting diode LED can be electrically connected by the turned-on second light emission control transistor TR15. A current corresponding to the voltage of the first node N11 flows from the first power supply voltage ELVDD to the light emitting diode LED through the driving transistor TR11, and the light emitting diode LED can emit at a brightness corresponding to the amount of current. In this case, the voltage of the first node N11 is applied to the gate contact overlapping layer MG of the driving transistor TR11 connected to the first node N11. Moreover, the first power supply voltage ELVDD is applied to the semiconductor contact overlapping layer MS1 of the driving transistor TR11 connected to the second node N12. Since the driving transistor TR11 includes the semiconductor contact overlapping layer MS1, the data range of the driving transistor TR11 is increased. Fig.17 and Fig.18 Describe this.

[0171] exist Fig.17 , V0 and V255 represent the positions of the current value representing the minimum grayscale (0 grayscale) and the current value representing the maximum grayscale (255 grayscale) based on 256 grayscales. Since the transistor TR_S according to the embodiment of the present invention includes the semiconductor contact overlapping layer MS1, as the gate-source voltage difference Vgs increases within the range of the displayed grayscale, compared with the general transistor TR_N (for example, Fig.18 Compared with the characteristic curve of the transistor included in the pixel circuit 20 of the embodiment, the slope of the characteristic curve of the transistor TR_S changes more gently. Thus, the data range DR2 of the transistor TR_S according to the present embodiment becomes larger than the data range DR1 of the general transistor TR_N. The data range is the interval between the gate-source voltage difference Vgs for providing the current value representing the minimum grayscale and the gate-source voltage difference Vgs for providing the current value representing the maximum grayscale. In other words, the driving range in which the transistor TR_S according to the present embodiment is driven to display the minimum grayscale and the maximum grayscale is increased.

[0172] As described above, as the data range of the driving transistor TR11 increases, the output of the driving transistor TR11 changes less sensitively to the change of the gate-source voltage difference Vgs, and as a result, the output change according to the characteristics included in the driving transistor TR11 also becomes less sensitive. Thus, the characteristic change between the plurality of pixels PX that emit light in the light emission period T4 is reduced, so that the display quality can be uniform and the display quality can be improved. In addition, since the data range of the driving transistor TR11 increases, images with more grayscales can be displayed.

[0173] The above detailed description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of the embodiments of the present invention as defined by the claims and their equivalents. It includes various specific details to assist in understanding, but these are considered as examples only. Therefore, it will be appreciated by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention should be determined solely in accordance with the appended claims and their equivalents.

[0174] <symbol description>

[0175] 110: Substrate

[0176] 120: Semiconductor layer

[0177] 130: Gate electrode

[0178] ML: Overlapping Layers

Claims

1. A display device, comprising: substrate; and A transistor is placed on the substrate, The transistor comprises: Semiconductor layer; a gate electrode overlapping the semiconductor layer; a first gate contact overlapping layer overlapping the channel region and contacting the gate electrode below the channel region, the gate electrode and the semiconductor layer overlapping at the channel region; and a semiconductor contact overlapping layer overlapping with the channel region and contacting with the semiconductor layer below the channel region, and The first gate contact overlapping layer and the semiconductor contact overlapping layer are physically separated by a gap in the channel region, and Wherein, the transistor further comprises: a second gate contact overlapping layer overlapping the channel region and contacting the gate electrode, and In a plane, the semiconductor contact overlapping layer is disposed between the first gate contact overlapping layer and the second gate contact overlapping layer.

2. The display device according to claim 1, wherein: On a plane, a width of the entire region including the first gate contact overlapping layer, the semiconductor contact overlapping layer, the second gate contact overlapping layer and the gap is greater than a width of the channel region.

3. The display device according to claim 1, wherein: On a plane, a width of the entire region including the first gate contact overlapping layer, the semiconductor contact overlapping layer, the second gate contact overlapping layer and the gap is smaller than a width of the channel region.

4. The display device according to claim 1, wherein: The transistor further includes a floating overlapping layer overlapping the channel region and insulated from and not connected to the semiconductor layer and the gate electrode.

5. The display device according to claim 1, wherein: The width of the first gate contact overlapping layer is the same as the width of the semiconductor contact overlapping layer.

6. The display device according to claim 1, wherein: A width of the first gate contact overlapping layer and a width of the semiconductor contact overlapping layer are different from each other.

7. A display device, comprising: substrate; and A transistor is placed on the substrate, The transistor comprises: Semiconductor layer; a gate electrode overlapping the semiconductor layer; a first gate contact overlapping layer overlapping the channel region and contacting the gate electrode below the channel region, the gate electrode and the semiconductor layer overlapping at the channel region; and a semiconductor contact overlapping layer overlapping with the channel region and contacting with the semiconductor layer below the channel region, and The first gate contact overlapping layer and the semiconductor contact overlapping layer are physically separated by a gap in the channel region, and wherein, The semiconductor contact overlapping layer comprises: a first overlapping portion overlapping the channel region; a second overlapping portion overlapping the channel region; a contact portion that contacts the semiconductor layer but does not overlap the gate electrode; and An extending portion connecting the first overlapping portion, the second overlapping portion, and the contact portion to each other.

8. The display device according to claim 7, wherein: The first gate contact overlapping layer is disposed between the first overlapping portion and the second overlapping portion.

9. The display device according to claim 7, wherein: On a plane, a width of the entire region including the first gate contact overlapping layer, the first overlapping portion, the second overlapping portion, and the gap is greater than a width of the channel region.

10. The display device according to claim 7, wherein: On a plane, a width of the entire region including the first gate contact overlapping layer, the first overlapping portion, the second overlapping portion, and the gap is smaller than a width of the channel region.

11. The display device according to claim 7, wherein: The transistor further includes a floating overlapping layer overlapping the channel region and insulated from and not connected to the semiconductor layer and the gate electrode.

12. A display device, comprising: Multiple pixels, Wherein, each of the plurality of pixels comprises: light emitting diodes; and a driving transistor to control the amount of current flowing from the first power supply voltage to the light emitting diode, and The driving transistor comprises: a gate electrode connected to the first node; a first electrode to which the first power supply voltage is applied; A second electrode electrically connected to the light emitting diode; A first gate contact overlapping layer under the channel region of the driving transistor overlapping the channel region and connected to the gate electrode; and a semiconductor contact overlapping layer overlapping with the channel region below the channel region and connected to the first electrode, and The first gate contact overlapping layer and the semiconductor contact overlapping layer are physically separated by a gap, and The driving transistor further comprises: a second gate contact overlapping layer overlapping with the channel region of the driving transistor and contacting with the gate electrode of the driving transistor, and In a plane, the semiconductor contact overlapping layer is disposed between the first gate contact overlapping layer and the second gate contact overlapping layer.

13. The display device according to claim 12, wherein: Each of the plurality of pixels further comprises: a switching transistor connected between the data line and the driving transistor, and The switching transistor comprises: a gate electrode connected to the first gate line, and A gate contact overlapping layer overlaps the channel region of the switching transistor and is connected to the gate electrode of the switching transistor.

14. The display device according to claim 12, wherein: Each of the plurality of pixels further comprises: a compensation transistor connected between the second electrode and the gate electrode of the driving transistor, and The compensation transistor comprises: a gate electrode connected to the first gate line; and A gate contact overlapping layer overlaps the channel region of the compensation transistor and is connected to the gate electrode of the compensation transistor.

15. The display device according to claim 12, wherein: Each of the plurality of pixels further comprises: an initializing transistor applying an initializing voltage to the gate electrode of the driving transistor, and The initialization transistor comprises: a gate electrode connected to a second gate line; and A gate contact overlapping layer overlaps the channel region of the initialization transistor and is connected to the gate electrode of the initialization transistor.

16. A method for driving a display device, the display device comprising a driving transistor for controlling the amount of current flowing from a first power supply voltage to a light emitting diode, a switching transistor for transmitting a data voltage applied to a data line to the driving transistor according to a first gate signal applied to a first gate line, a compensation transistor for diode-connecting the driving transistor according to the first gate signal, and an initialization transistor for applying an initialization voltage to a gate electrode of the driving transistor according to a second gate signal applied to a second gate line, the driving method comprising: applying the first power supply voltage to a first electrode of the drive transistor, causing current to flow from the first power supply voltage to the light emitting diode in response to a voltage of a first node to which the gate electrode of the drive transistor is connected; applying the first power supply voltage to a semiconductor contact overlapping layer under the channel region of the drive transistor, overlapping the channel region and connected to the first electrode of the drive transistor; and applying the voltage of the first node to a first gate contact overlapping layer overlapping with the channel region below the channel region of the driving transistor and connected to the gate electrode of the driving transistor, and The driving transistor further comprises: a second gate contact overlapping layer overlapping with the channel region of the driving transistor and contacting with the gate electrode of the driving transistor, and In a plane, the semiconductor contact overlapping layer is disposed between the first gate contact overlapping layer and the second gate contact overlapping layer.

17. The method for driving a display device according to claim 16, further comprising: applying the first gate signal as a gate-on voltage to a gate electrode of the switching transistor to turn on the switching transistor; and The first gate signal is applied to a gate contact overlapping layer overlapping a channel region of the switching transistor and connected to the gate electrode of the switching transistor.

18. The method for driving a display device according to claim 16, further comprising: applying the first gate signal as a gate-on voltage to a gate electrode of the compensation transistor to turn on the compensation transistor; and The first gate signal is applied to a gate contact overlapping layer overlapping a channel region of the compensation transistor and connected to the gate electrode of the compensation transistor.

19. The method for driving a display device according to claim 16, further comprising: applying the second gate signal as a gate-on voltage to a gate electrode of the initialization transistor to turn on the initialization transistor; and The second gate signal is applied to a gate contact overlapping layer overlapping a channel region of the initialization transistor and connected to the gate electrode of the initialization transistor.

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