A surge current suppression device

Abstract

The present invention discloses a surge current suppression device, comprising: an AC input port, a load access port, a power supply circuit, a bidirectional thyristor DA, a current limiting resistor RA, a first relay, a thyristor drive circuit and a timing control circuit. After power-on startup, the technical solution uses the thyristor drive circuit to control the conduction moment of the bidirectional thyristor DA, and uses the thyristor drive circuit to set the conduction moment of the bidirectional thyristor DA according to the connected load type, thereby reducing the surge current generated when power is on; the technical solution performs a delay operation after power-on startup, and short-circuits the live input port and the first access port after a first delay period, so that the bidirectional thyristor DA and the current limiting resistor RA are short-circuited, thereby reducing power loss.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and more particularly to a surge current suppression device. Background Art

[0002] Common electrical equipment in life is an inductive load or a capacitive load. Therefore, it will generate surge current when powered on. This surge current will not only cause the line protection device to malfunction, but also endanger the expected life and reliable operation of the equipment itself.

[0003] In order to suppress the surge current of electrical equipment in the prior art, a combination of NTC thermistor (or power resistor) and relay is used to suppress the large surge current encountered by the electrical equipment when it is powered on. That is, the prior art specifically connects an NTC thermistor or power resistor in series between the load and the input power supply, and uses the impedance of the NTC thermistor or power resistor to suppress the large surge current generated at the moment of power-on. Then, the NTC thermistor or power resistor is short-circuited through the relay about 1S after power-on. This technical solution is relatively simple and low in cost, but the main defect of this technical solution is that it cannot control the power-on time and cannot suppress the surge current to the maximum extent according to the characteristics of loads of different properties. For example, for inductive loads such as motors or toroidal transformers, the surge current generated by powering on at the zero-crossing moment of the AC input voltage (near the phase angle of 0° or 180°) reaches the maximum under the condition of certain residual magnetism, and under the same conditions, the surge current generated by powering on at the peak moment of the AC input voltage (near the phase angle of 90° or 270°) is the smallest. For capacitive loads, it is exactly the opposite. The above defects require the use of multiple NTCs in parallel or large and expensive power resistors with metal casings to suppress large surge currents in high-power applications. Summary of the invention

[0004] The object of the present invention is to provide a surge current suppression device to solve one or more technical problems existing in the prior art and at least provide a beneficial choice or create conditions.

[0005] The technical solutions adopted to solve the above technical problems are:

[0006] A surge current suppression device, comprising:

[0007] An AC input port, the AC input port comprising a live wire input port and a neutral wire input port;

[0008] A load access port, wherein the load access port includes a first access port and a second access port;

[0009] A power supply circuit, connected to the live line input port and the neutral line input port respectively, and used for converting the input alternating current into a plurality of direct currents with different amplitudes;

[0010] A bidirectional thyristor DA, a current-limiting resistor RA and a first relay, wherein the bidirectional thyristor DA and the current-limiting resistor RA are connected in series between the live input port and the first access port, the second access port is connected to the neutral input port, and the first relay is used to control the on / off of the live input port and the first access port;

[0011] a thyristor drive circuit, connected to the live input port, the neutral input port and the control electrode of the bidirectional thyristor DA respectively, and the thyristor drive circuit is used to control the moment when the bidirectional thyristor DA is turned on according to the load type connected to the surge current suppression device;

[0012] A timing control circuit is connected to the control end of the first relay. The timing control circuit is configured to delay a first time period after the surge current suppression device is powered on and started, and short-circuit the live wire input port and the first access port through the first relay. The timing control circuit is connected to the power supply circuit.

[0013] As a further improvement of the above technical solution, the timing control circuit is connected to the thyristor drive circuit, and the timing control circuit is configured to control the start of the thyristor drive circuit after the surge current suppression device is powered on and started, delay the first time period, short-circuit the live wire input port and the first access port through the first relay, and then control the thyristor drive circuit to stop after delaying the second time period.

[0014] As a further improvement of the above technical solution, the timing control circuit is also configured to delay for a third time period after the surge current suppression device is powered on and started, control the thyristor drive circuit to start, and after further delaying the first time period, short-circuit the live wire input port and the first access port through the first relay, and after further delaying for a second time period, control the thyristor drive circuit to stop.

[0015] As a further improvement of the above technical solution, the thyristor drive circuit includes a second relay, a resistor R1 and a capacitor C1, the timing control circuit is connected to the control end of the second relay, the resistor R1 and the capacitor C1 are connected in series between an output contact of the second relay and the live wire input port, the other output contact of the second relay is connected to the neutral wire input end, and the control electrode of the bidirectional thyristor DA is connected to the connection point between the resistor R1 and the capacitor C1;

[0016] The resistance value of the resistor R1 and / or the capacitance value of the capacitor C1 are adjustable, and the resistance value of the resistor R1 and / or the capacitance value of the capacitor C1 are set according to the type of load connected to the surge current suppression device.

[0017] As a further improvement of the above technical solution, the second relay is an optocoupler relay.

[0018] As a further improvement of the above technical solution, the timing control circuit includes a first-level delay module for implementing the first time period delay, a second-level delay module for implementing the second time period delay, a third-level delay module for implementing the third time period delay, and a first driving module for driving the first relay;

[0019] The power supply circuit is connected to the three-stage delay module, the three-stage delay module is connected to the two-stage delay module, the two-stage delay module is respectively connected to the thyristor drive circuit and the one-stage delay module, and the one-stage delay module is connected to the first relay through the first drive module;

[0020] After the surge current suppression device is powered on and started, the three-stage delay module starts the delay function. After delaying the third time period, the thyristor drive circuit is controlled to start, and the second-stage delay module and the first-stage delay module are controlled to start the delay function. After delaying the first time period, the live wire input port and the first access port are short-circuited through the first relay. After delaying the second time period, the thyristor drive circuit is controlled to stop.

[0021] As a further improvement of the above technical solution, the timing control circuit also includes a switch module, and the secondary delay module is connected to the primary delay module through the switch module.

[0022] As a further improvement of the above technical solution, the timing control circuit further includes a second driving module, and the secondary delay module is connected to the thyristor driving circuit through the second driving module.

[0023] As a further improvement of the above technical solution, the current limiting resistor RA is an NTC thermistor.

[0024] The beneficial effects of the present invention are as follows: after power-on, the present technical solution uses a thyristor drive circuit to control the conduction moment of the bidirectional thyristor DA, and uses the thyristor drive circuit to set the conduction moment of the bidirectional thyristor DA according to the connected load type, thereby reducing the surge current generated when power is turned on; the present technical solution performs a delay operation after power-on, and short-circuits the live wire input port and the first access port after a first delay period, so that the bidirectional thyristor DA and the current-limiting resistor RA are short-circuited, thereby reducing power loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention will be further described below in conjunction with the accompanying drawings and embodiments;

[0026] Figure 1 is a schematic diagram of a circuit module of the present invention;

[0027] Figure 2 It is the principle diagram of the thyristor driving circuit of the present invention;

[0028] Figure 3 The timing control circuit schematic diagram of the present invention. DETAILED DESCRIPTION

[0029] This section will describe in detail the specific embodiments of the present invention. The preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the accompanying drawings is to supplement the description of the text part of the specification with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of the present invention, but it cannot be understood as a limitation on the scope of protection of the present invention.

[0030] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0031] In the description of the present invention, if there are words such as "several", it means one or more, "more" means more than two, greater than, less than, exceed, etc. are understood as not including the number, and above, below, within, etc. are understood as including the number.

[0032] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0033] Reference Figures 1 to 3 The present application discloses a surge current suppression device, a first embodiment of which comprises:

[0034] An AC input port, the AC input port comprising a live wire input port and a neutral wire input port;

[0035] A load access port, wherein the load access port includes a first access port and a second access port;

[0036] A power supply circuit, connected to the live line input port and the neutral line input port respectively, and used for converting the input alternating current into a plurality of direct currents with different amplitudes;

[0037] A bidirectional thyristor DA, a current-limiting resistor RA and a first relay, wherein the bidirectional thyristor DA and the current-limiting resistor RA are connected in series between the live input port and the first access port, the second access port is connected to the neutral input port, and the first relay is used to control the on / off of the live input port and the first access port;

[0038] a thyristor drive circuit, connected to the live input port, the neutral input port and the control electrode of the bidirectional thyristor DA respectively, and the thyristor drive circuit is used to control the moment when the bidirectional thyristor DA is turned on according to the load type connected to the surge current suppression device;

[0039] A timing control circuit is connected to the control end of the first relay. The timing control circuit is configured to delay a first time period after the surge current suppression device is powered on and started, and short-circuit the live wire input port and the first access port through the first relay. The timing control circuit is connected to the power supply circuit.

[0040] Specifically, after power-on startup, this embodiment uses the thyristor drive circuit to control the conduction moment of the bidirectional thyristor DA, and uses the thyristor drive circuit to set the conduction moment of the bidirectional thyristor DA according to the load type connected in the actual application of this embodiment, thereby reducing the surge current generated when power is turned on; this embodiment performs a delay operation after power-on startup, and short-circuits the live wire input port and the first access port after a first delay period, so that the bidirectional thyristor DA and the current limiting resistor RA are short-circuited, thereby reducing energy loss.

[0041] Preferably, the current limiting resistor RA in this embodiment is an NTC thermistor.

[0042] As a further preferred embodiment, the timing control circuit in this embodiment is connected to the thyristor drive circuit, and the timing control circuit is specifically configured to delay the third time period after the power-on start of this embodiment, control the thyristor drive circuit to start, and then delay the first time period to short-circuit the live input port and the first access port through the first relay, and then delay the second time period to control the thyristor drive circuit to stop. In this embodiment, after the power-on start, the delay operation of delaying the third time period is performed, and its purpose is to prevent the load from causing the current limiting resistor RA to have an over-high temperature when the load is frequently turned on and off; after completing the delay of the third time period, the second time period needs to be continued to be delayed. After the delay operation is completed, the thyristor drive circuit is controlled to stop and the bidirectional thyristor DA is cut off. This design of this embodiment prevents high power loss caused by the first relay failing to short-circuit the live input port and the first access port due to an abnormal condition.

[0043] As a further preferred implementation, in this embodiment, the thyristor drive circuit includes a second relay, a resistor R1, a resistor R2, a bidirectional diode D1 and a capacitor C1, the timing control circuit is connected to the control end of the second relay, the resistor R1 and the capacitor C1 are connected in series between an output contact of the second relay and the live wire input port, the connection point between the resistor R1 and the capacitor C1 is connected to the control electrode of the bidirectional thyristor DA through the resistor R2 and the bidirectional diode D1, and the other output contact of the second relay is connected to the neutral line input end; in this embodiment, the resistance value of the resistor R1 and / or the capacitance value of the capacitor C1 are adjustable, and the resistance value of the resistor R1 and / or the capacitance value of the capacitor C1 are set according to the load type connected in the actual application of this embodiment, and the resistance value of the resistor R1 and the capacitance value of the capacitor C1 jointly determine the conduction moment of the bidirectional thyristor DA.

[0044] Preferably, in this embodiment, the second relay is an optocoupler relay.

[0045] Further as a preferred implementation, in this embodiment, in this embodiment, the timing control circuit includes a first-level delay module for implementing the first time period delay, a second-level delay module for implementing the second time period delay, a third-level delay module for implementing the third time period delay, and a first driving module for driving the first relay;

[0046] The power supply circuit is connected to the three-stage delay module, the three-stage delay module is connected to the two-stage delay module, the two-stage delay module is respectively connected to the thyristor drive circuit and the one-stage delay module, and the one-stage delay module is connected to the first relay through the first drive module;

[0047] After the surge current suppression device is powered on and started, the three-stage delay module starts the delay function. After delaying the third time period, the thyristor drive circuit is controlled to start, and the second-stage delay module and the first-stage delay module are controlled to start the delay function. After delaying the first time period, the live wire input port and the first access port are short-circuited through the first relay. After delaying the second time period, the thyristor drive circuit is controlled to stop.

[0048] Further as a preferred implementation, in this embodiment, in this embodiment, the timing control circuit also includes a switch module and a second drive module, the secondary delay module is connected to the thyristor drive circuit through the second drive module, and the secondary delay module is connected to the primary delay module through the switch module.

[0049] Specifically, in this embodiment, the three-stage delay module includes a capacitor C2, a capacitor C3, a resistor R3, a resistor R4, a resistor R5, a diode D2 and an NPN transistor Q1. The output end of the power supply circuit is grounded through the capacitor C2 and the resistor R3 in sequence. One end of the resistor R4 is connected to the connection point between the capacitor C2 and the resistor R3, and the other end of the resistor R4 is grounded through the capacitor C3. The positive electrode of the diode D2 is grounded, and the negative electrode of the diode D2 is connected to the connection point between the resistor R4 and the capacitor C3. The base of the transistor Q1 is connected to the negative electrode of the diode D2, the emitter of the transistor Q1 is grounded, the collector of the transistor Q1 is connected to the output end of the power supply circuit through the resistor R5, and the collector of the transistor Q1 is connected to the secondary delay module.

[0050] In this embodiment, the secondary delay module includes a capacitor C4, a capacitor C5, a resistor R6, a resistor R7, a resistor R8, a diode D3 and an NPN transistor Q2, one end of the capacitor C4 is connected to the collector of the transistor Q1, the other end of the capacitor C4 is grounded through the resistor R6, one end of the resistor R7 is connected to the connection point between the capacitor C4 and the resistor R6, the other end of the resistor R7 is grounded through the capacitor C5, the positive electrode of the diode D3 is grounded, the negative electrode of the diode D3 is connected to the connection point between the resistor R7 and the capacitor C5, the base of the transistor Q2 is connected to the negative electrode of the diode D3, the emitter of the transistor Q2 is grounded, the collector of the transistor Q2 is connected to the output end of the power supply circuit through the resistor R8, and the collector of the transistor Q2 is connected to the second driving module.

[0051] In this embodiment, the second driving module includes a resistor R17, a first inverter and an NPN transistor Q6, the collector of the transistor Q2 is connected to the base of the transistor Q6 through the first inverter, the emitter of the transistor Q6 is grounded, the collector of the transistor Q6 is connected to the output end of the power supply circuit through the resistor R17, and the collector of the transistor Q6 is connected to the thyristor driving circuit.

[0052] In this embodiment, the switch module includes a capacitor C6, a resistor R9, a resistor R10, a resistor R11, a resistor R12, an NPN transistor Q3 and a PNP transistor Q4. The output end of the inverter is grounded through the resistor R9 and the resistor R10 in sequence, the emitter of the transistor Q3 is grounded, the base of the transistor Q3 is connected to the connection point between the resistor R9 and the resistor R10, one end of the capacitor C6 is connected to the base of the transistor Q3, the other end of the capacitor C6 is grounded, the collector of the transistor Q3 is connected to the base of the transistor Q4 through the resistor R12, the emitter of the transistor Q4 is connected to the output end of the power supply circuit, one end of the resistor R11 is connected to the emitter of the transistor Q4, the other end of the resistor R11 is connected to the base of the transistor Q4, and the collector of the transistor Q4 is connected to the first-stage delay module.

[0053] In this embodiment, the first-stage delay module includes a capacitor C7, a resistor R13, a resistor R14, a resistor R15 and a PNP transistor Q5, the collector of the transistor Q4 is connected to the emitter of the transistor Q5 through the resistor R13, the base of the transistor Q5 is connected to the output end of the power supply circuit through the resistor R14, the collector of the transistor Q5 is grounded through the resistor R15, one end of the capacitor C7 is connected to the collector of the transistor Q5, the other end of the capacitor C7 is grounded, and the collector of the transistor Q5 is connected to the first driving module.

[0054] In this embodiment, the first driving module includes a diode R4, a second inverter and a transistor Q7, the collector of the transistor Q5 is connected to the base of the transistor Q7 through the second inverter, the emitter of the transistor Q7 is grounded, the collector of the transistor Q7 is connected to the anode of the diode D4, the cathode of the diode D4 is connected to the output end of the power supply circuit, and the collector of the transistor Q7 is connected to the first relay.

[0055] The preferred embodiments of the present invention are specifically described above, but the invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A surge current suppression device, characterized in that: include: An AC input port, the AC input port comprising a live wire input port and a neutral wire input port; A load access port, wherein the load access port includes a first access port and a second access port; A power supply circuit, connected to the live line input port and the neutral line input port respectively, and used for converting the input alternating current into a plurality of direct currents with different amplitudes; A bidirectional thyristor DA, a current-limiting resistor RA and a first relay, wherein the bidirectional thyristor DA and the current-limiting resistor RA are connected in series between the live input port and the first access port, the second access port is connected to the neutral input port, and the first relay is used to control the on / off of the live input port and the first access port; a thyristor drive circuit, connected to the live input port, the neutral input port and the control electrode of the bidirectional thyristor DA respectively, and the thyristor drive circuit is used to control the moment when the bidirectional thyristor DA is turned on according to the load type connected to the surge current suppression device; a timing control circuit connected to the control end of the first relay, wherein the timing control circuit is configured to delay a first time period after the inrush current suppression device is powered on and started, and short-circuit the live input port and the first access port through the first relay, and the timing control circuit is connected to the power supply circuit; The timing control circuit is connected to the thyristor drive circuit, and the timing control circuit is configured to control the thyristor drive circuit to start after the inrush current suppression device is powered on, delay the first time period, short-circuit the live wire input port and the first access port through the first relay, and then control the thyristor drive circuit to stop after delaying the second time period; The timing control circuit is further configured to delay a third time period after the inrush current suppression device is powered on and started, control the thyristor drive circuit to start, and after further delaying the first time period, short-circuit the live input port and the first access port through the first relay, and after further delaying the second time period, control the thyristor drive circuit to stop; The thyristor drive circuit includes a second relay, a resistor R1 and a capacitor C1, the timing control circuit is connected to the control end of the second relay, the resistor R1 and the capacitor C1 are connected in series between an output contact of the second relay and the live line input port, the other output contact of the second relay is connected to the neutral line input end, and the control electrode of the bidirectional thyristor DA is connected to the connection point between the resistor R1 and the capacitor C1; The resistance value of the resistor R1 and / or the capacitance value of the capacitor C1 are adjustable, and the resistance value of the resistor R1 and / or the capacitance value of the capacitor C1 are set according to the type of load connected to the surge current suppression device; The current limiting resistor RA is an NTC thermistor.

2. A surge current suppression device according to claim 1, characterized in that: The second relay is a photocoupler relay.

3. The surge current suppression device according to claim 1, characterized in that: The timing control circuit includes a first-level delay module for implementing the first time period delay, a second-level delay module for implementing the second time period delay, a third-level delay module for implementing the third time period delay, and a first driving module for driving the first relay; The power supply circuit is connected to the three-stage delay module, the three-stage delay module is connected to the two-stage delay module, the two-stage delay module is respectively connected to the thyristor drive circuit and the one-stage delay module, and the one-stage delay module is connected to the first relay through the first drive module; After the surge current suppression device is powered on and started, the three-stage delay module starts the delay function. After delaying the third time period, the thyristor drive circuit is controlled to start, and the second-stage delay module and the first-stage delay module are controlled to start the delay function. After delaying the first time period, the live wire input port and the first access port are short-circuited through the first relay. After delaying the second time period, the thyristor drive circuit is controlled to stop.

4. A surge current suppression device according to claim 3, characterized in that: The timing control circuit also includes a switch module, and the secondary delay module is connected to the primary delay module through the switch module.

5. A surge current suppression device according to claim 4, characterized in that: The timing control circuit also includes a second driving module, and the secondary delay module is connected to the thyristor driving circuit through the second driving module.

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