Deep neural network weight storage device and preparation method thereof, and electronic device

Abstract

The present invention discloses a deep neural network weight storage device and a preparation method and an electronic device thereof. The deep neural network weight storage device comprises: a plurality of first input lines arranged along a first direction, a plurality of second input lines arranged along the first direction, and a plurality of output lines arranged along the second direction, and a plurality of weight units located at the nodes where the first input line, the second input line and the output line intersect, each of the weight units comprises: a first transistor, a second transistor and a storage element; the first source of the first transistor is connected to the first input line, the second source of the second transistor is connected to the second input line, the first drain of the first transistor and the second drain of the second transistor are connected to the first end of the storage element, and the second end of the storage element is connected to the output line. The accuracy of the neural network weight storage device is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic storage, and in particular to a deep neural network weight storage device and a preparation method and an electronic device thereof. Background Art

[0002] Neural networks have been very successfully applied. However, the large-scale parameters of neural networks have become a huge challenge for neural network applications. On the one hand, large-scale weights place high demands on storage capacity. On the other hand, large-scale weights will lead to huge memory access energy consumption and require huge computing power.

[0003] A neural network layer connects N neurons to M neurons and maps them to a cross matrix of N×M weights, such as Figure 1 In order to reduce the chip size, power consumption and signal propagation delay problems, the existing analog neural network chip uses the w=G+-G- infrastructure to construct the weight matrix, that is, a pair of storage devices are set in each M neuron in the neural network weight storage device, and the difference between the conductance G+ and G- of a pair of storage devices is usually used to calculate the weight w, as shown in Figure 2 As shown. The neural network layer relies on the symmetry of a pair of memory devices, and in the specific manufacturing process of the memory devices, each specific step (such as photolithography, doping, etc.) will cause performance differences between the devices, making it difficult to ensure the symmetry of the pair of memory devices. The nonlinearity and asymmetry of the conductivity response of the neural network weight memory device limit the accuracy of both "training" and "testing" to 82-83%, and the accuracy is limited.

[0004] Therefore, it is considered to improve the deep neural network weight storage device to eliminate the above-mentioned problems that currently exist. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In order to overcome the existing problems, the present invention provides a deep neural network weight storage device, comprising: a plurality of first input lines arranged along a first direction, a plurality of second input lines arranged along the first direction, and a plurality of output lines arranged along the second direction, and a plurality of weight units located at nodes where the first input lines, the second input lines, and the output lines intersect, each of the weight units comprising: a first transistor, a second transistor, and a storage element;

[0007] The first source of the first transistor is connected to the first input line, the second source of the second transistor is connected to the second input line, the first drain of the first transistor and the second drain of the second transistor are connected to the first end of the storage element, and the second end of the storage element is connected to the output line.

[0008] Optionally, the deep neural network weight storage device further includes a first word line and a second word line extending in the second direction, the gate of the first transistor is electrically connected to the first word line, and the gate of the second transistor is electrically connected to the second word line.

[0009] Optionally, the first transistor includes a first gate, a first channel and a first gate dielectric layer;

[0010] The first gate dielectric layer is disposed between the first channel and the first gate, and the first gate dielectric layer comprises a ferroelectric insulating material layer; and / or

[0011] The second transistor includes a second gate, a second channel, and a second gate dielectric layer;

[0012] The second gate dielectric layer is disposed between the second channel and the second gate, and the second gate dielectric layer comprises a ferroelectric insulating material layer.

[0013] Optionally, the ferroelectric insulating material layer includes CuInP2S6 or HfO2.

[0014] Optionally, the first gate dielectric layer further comprises a first amorphous silicon layer disposed between the first channel and the ferroelectric insulating material layer; and / or

[0015] The second gate dielectric layer also includes a second amorphous silicon layer disposed between the second channel and the ferroelectric insulating material layer.

[0016] Optionally, the first channel and / or the second channel is in a columnar structure.

[0017] Optionally, the material of the first channel and / or the second channel includes MOS2 or amorphous silicon.

[0018] Optionally, the first transistor device further includes:

[0019] A first ladder-type interconnect structure electrically connects the first gate, the first source and the first drain respectively; and / or

[0020] The second transistor device further comprises:

[0021] The second ladder-type interconnection structure electrically connects the second gate, the second source and the second drain respectively.

[0022] Optionally, the storage element includes at least one of a phase change storage element, a resistive storage element, a magneto-variable storage element and a ferroelectric storage element.

[0023] Optionally, the storage element is a ferroelectric storage element, and the ferroelectric storage element includes HfO2.

[0024] Optionally, the ferroelectric memory element further includes a first electrode and a second electrode located on both sides of the HfO2.

[0025] The present application also provides a method for preparing the deep neural network weight storage device mentioned above, the preparation method comprising:

[0026] providing a substrate;

[0027] forming a plurality of first nanowires on the substrate, wherein the extending direction of the nanowires is perpendicular to the substrate;

[0028] Doping the bottom of the first nanowire to form a first source;

[0029] forming a first bottom isolation layer, a first gate dielectric layer and a first gate material layer on the substrate in sequence to below the top surface of the first nanowire;

[0030] Patterning the first gate material layer to form a first gate surrounding the first nanowire;

[0031] forming a first top isolation layer around the first gate and covering the first gate, wherein the first top isolation layer exposes a portion of the first nanowire;

[0032] Doping the exposed top of the first nanowire to form a first drain;

[0033] forming a first interlayer dielectric layer on the first top isolation layer and the first gate to the top surface of the first nanowire and exposing the top surface of the first drain;

[0034] forming a second interlayer dielectric layer and a storage element located in the second interlayer dielectric layer on the first interlayer dielectric layer, wherein the storage element is connected to the first drain;

[0035] forming a second nanowire on the memory element;

[0036] Doping the bottom of the second nanowire to form a second drain;

[0037] forming a second bottom isolation layer, a second gate dielectric layer, and a second gate material layer in sequence on the second interlayer dielectric layer to below the top surface of the second nanowire;

[0038] patterning the second gate material layer to form a second gate surrounding the second nanowire;

[0039] forming a second top isolation layer around the second gate and covering the second gate, wherein the second top isolation layer exposes a portion of the second nanowire;

[0040] The exposed top of the second nanowire is doped to form a second source.

[0041] Optionally, the first gate dielectric layer and / or the second gate dielectric layer comprises a ferroelectric insulating material layer.

[0042] Optionally, the ferroelectric insulating material layer includes CuInP2S6 or HfO2.

[0043] Optionally, the first nanowire and / or the second nanowire comprises MOS2 or amorphous silicon.

[0044] Optionally, the method further comprises: forming a first ladder-type interconnect structure to electrically connect the first gate, the first source and the first drain respectively; and / or

[0045] A second stair-type interconnect structure is formed to electrically connect the second gate, the second source, and the second drain, respectively.

[0046] Optionally, the storage element includes at least one of a phase change storage element, a resistive storage element, a magneto-variable storage element and a ferroelectric storage element.

[0047] Optionally, the storage element is a ferroelectric storage element, and the ferroelectric storage element includes HfO2.

[0048] Optionally, the ferroelectric memory element further includes a first electrode and a second electrode located on both sides of the HfO2.

[0049] Optionally, the preparation method is repeatedly performed on the prepared deep neural network weight storage device to form a deep neural network weight storage device with multiple layers stacked.

[0050] The present invention also provides an electronic device, which includes the deep neural network weight storage device described above.

[0051] In order to solve the above problems, the present application provides a deep neural network weight storage device and a preparation method thereof, wherein the deep neural network weight storage device comprises a plurality of first input lines arranged along a first direction, a plurality of second input lines arranged along a first direction, and a plurality of output lines arranged along a second direction, and a plurality of weight units located at the nodes where the first input line, the second input line and the output line intersect, each of the weight units comprises: a first transistor, a second transistor and a storage element; the first source of the first transistor is connected to the first input line, the second source of the second transistor is connected to the second input line, the first drain of the first transistor and the second drain of the second transistor are connected to the first end of the storage element, and the second end of the storage element is connected to the output line. In the present application, by assigning polarity and size to each weight storage unit in the deep neural network weight storage device, the product of input and weight can be functionally and structurally performed for calculation, and the improvement eliminates the dependence on the symmetry of the storage device, eliminates the restriction on |G+|=|G-|, and reduces the amount of calculation, reduces the power consumption of the device and improves the operation speed of the device. The nonlinearity and asymmetry of the conductance response of the neural network weight storage device greatly improves the accuracy of "training" and "testing". BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0053] In the attached figure:

[0054] Figure 1 It is a schematic diagram of a neural network layer of a deep neural network weight storage device in the prior art;

[0055] Figure 2 is a schematic diagram of a pair of transistor devices in a deep neural network weight storage device in the prior art;

[0056] Figure 3 is a schematic diagram of a neural network layer of a deep neural network weight storage device according to an embodiment of the present invention;

[0057] Figure 4 is a cross-sectional schematic diagram of a deep neural network weight storage device according to an embodiment of the present invention;

[0058] Figure 5 It is a schematic structural diagram of a mobile phone handset according to an embodiment of the present invention. DETAILED DESCRIPTION

[0059] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0060] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0061] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0062] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0063] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0064] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0065] In order to fully understand the present invention, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0066] In order to solve the existing problems, the first aspect of the present application provides a deep neural network weight storage device, such as Figure 3 and Figure 4 As shown, it includes: a plurality of first input lines 101 arranged along a first direction, a plurality of second input lines 102 arranged along the first direction, and a plurality of output lines 103 arranged along the second direction, and a plurality of weight units located at nodes where the first input lines 101, the second input lines 102 and the output lines 103 intersect, each of the weight units includes: a first transistor, a second transistor and a storage element 108;

[0067] The first source 104 of the first transistor is connected to the first input line 101, the second source 112 of the second transistor is connected to the second input line 102, the first drain 107 of the first transistor and the second drain 109 of the second transistor are connected to the first end of the storage element 108, and the second end of the storage element 108 is connected to the output line 103.

[0068] The first direction and the second direction may be the same or different, which is not limited here. For example, in one embodiment of the present application, the first direction and the second direction are different, and the first direction and the second direction are perpendicular to each other.

[0069] The deep neural network weight storage device also includes a first word line 105 and a second word line 110 extending along the second direction, the gate of the first transistor is electrically connected to the first word line 105, and the gate of the second transistor is electrically connected to the second word line 110.

[0070] Specifically, Figure 3 As shown, in one embodiment of the present application, the deep neural network weight storage device includes N first input lines 101 and N second input lines 102 arranged horizontally, and M output lines 103 arranged vertically, wherein the horizontal and vertical directions are perpendicular to each other, and the weight unit is formed at the node where the horizontal and vertical directions intersect. Each of the weight units includes: a first transistor, a second transistor and a storage element 108.

[0071] The structures of the first transistor and the second transistor are described in detail below. In the first transistor device, the substrate may be at least one of the following materials: silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), etc.

[0072] In one embodiment of the present application, the substrate is silicon.

[0073] A first nanowire is formed on the substrate, and the first source 104 is formed in the first nanowire. For example, the first source 104 can be formed by performing ion implantation.

[0074] The energy, dosage and depth of the ion implantation can be selected according to actual needs and are not limited to a certain numerical range.

[0075] Optionally, the implanted ion energy is 1kev-10kev, and the implanted ion dose is 5×10 14-5×10 16 Atom / cm 2 .

[0076] A first bottom isolation layer is formed on the substrate, wherein the first bottom isolation layer is made of an insulating material, for example, the first bottom isolation layer may be made of SiO2, fluorocarbon (CF), carbon-doped silicon oxide (SiOC), or silicon carbonitride (SiCN), a high-density plasma (HDP) oxide deposition layer, etc. The thickness of the first bottom isolation layer may be selected according to actual needs and is not limited to a certain value range.

[0077] In one embodiment of the present application, the first bottom isolation layer is a high density plasma (HDP) oxide deposition layer.

[0078] The first transistor includes a first gate 106 , a first channel, and a first gate dielectric layer; the first gate dielectric layer is disposed between the first channel and the first gate 106 , and the first gate dielectric layer includes a ferroelectric insulating material layer.

[0079] In the present application, the first gate dielectric layer includes a ferroelectric insulating material layer; the ferroelectric insulating material layer includes CuInP2S6 or HfO2, wherein the ferroelectric insulating material layer is not limited to the listed examples.

[0080] Among them, ferroelectric materials can exhibit spontaneous polarization in the absence of an external electric field. The polarization can be redirected by ion displacement in the crystal, and polarization switching can be triggered by an external electric field, so that the ferroelectric material can have two electrically controlled non-volatile states. In the present application, the ferroelectric insulating material layer is used as a gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET). Channel conductance is used to detect the polarization state in the ferroelectric gate insulator, so that data reading operations can be performed losslessly in the transistor. In transistors, the fast switching speed (nanoseconds or less) of ferroelectric materials, lossless readout, non-volatile storage states, and simple structures for high-density integration further improve the storage efficiency of the memory.

[0081] Furthermore, the first gate dielectric layer further includes an amorphous silicon layer. For example, in the present application, the first gate dielectric layer includes an amorphous silicon layer and a ferroelectric insulating material layer formed sequentially.

[0082] The first gate 106 includes, but is not limited to, silicon, polysilicon, doped polysilicon, and polysilicon-germanium alloy material (i.e., having a dielectric constant of about 1×10 18 to about 1×10 22doping concentration of doping atoms) and polysilicon metal silicide (polycide) material (doped polysilicon / metal silicide stack material).

[0083] In one embodiment of the present application, the first gate 106 is made of polysilicon.

[0084] The first gate 106 is disposed around the first channel, and the first channel is a portion of the first nanowire.

[0085] The first channel includes one of MOS2 or amorphous silicon, but is not limited to the examples.

[0086] A first drain 107 is formed on the top of the first nanowire, that is, a drain is formed above the first channel.

[0087] Specifically, the first nanowire is doped by performing an ion implantation method, thereby forming a drain on the top of the first nanowire.

[0088] The first transistor device further includes a ladder-type interconnect structure to electrically connect the first source 104 , the first gate 106 and the first drain 107 , respectively.

[0089] The storage element 108 is disposed above the first drain 107 and is electrically connected to the first drain 107 .

[0090] The storage element 108 includes at least one of a phase change storage element 108 (PCM), a resistive random access storage element 108 (RRAM), a magnetic random access storage element 108 (MRAM) and a ferroelectric storage element 108 .

[0091] The phase change memory element 108 includes a phase change material and a first electrode or a second electrode located on two opposite surfaces of the phase change material.

[0092] For example, the phase change memory element 108 is a circular structure, the phase change material is a circular ring structure, the first electrode and the second electrode are respectively arranged on the inner and outer sides of the circular ring structure, and one end of the second electrode is electrically connected to the first drain 107 .

[0093] The phase change material is usually Ge, Sb or Te, but is not limited to this example.

[0094] Among them, the shapes of the resistive memory element 108 (RRAM), the magneto-variable memory element 108 (MRAM) and the ferroelectric memory element 108 are similar to the phase change memory element 108, and the specific structure can be a conventional device structure, which will not be repeated here.

[0095] It should be noted that, when the memory element 108 is a ferroelectric memory element 108 , the ferroelectric material may be HfO 2 , which has all the advantages of the ferroelectric material described above.

[0096] Furthermore, the present application further includes a second transistor, the second transistor includes a second gate 111, a second channel and a second gate dielectric layer; the second gate dielectric layer is arranged between the second channel and the second gate 111, and the second gate dielectric layer includes a ferroelectric insulating material layer. The second gate dielectric layer also includes a second amorphous silicon layer arranged between the second channel and the ferroelectric insulating material layer. The second transistor device also includes: a second ladder-type interconnection structure, which electrically connects the second gate 111, the second source 112 and the second drain 109 respectively.

[0097] The second transistor is exactly the same as the first transistor and is disposed on the upper and lower sides of the storage element 108 in a mirror relationship. The composition and selected materials of the second transistor can refer to the relevant explanations and descriptions about the first transistor in the previous text and will not be repeated here.

[0098] Furthermore, the deep neural network weight storage device further includes a plurality of layers of repetitive units, each of which includes the structure described above, including: a plurality of first input lines 101 arranged along a first direction, a plurality of second input lines 102 arranged along the first direction, and a plurality of output lines 103 arranged along the second direction, and a plurality of weight units located at nodes where the first input lines 101, the second input lines 102, and the output lines 103 intersect, each of which includes: a first transistor, a second transistor, and a storage element 108;

[0099] The first source 104 of the first transistor is connected to the first input line 101, the second source 112 of the second transistor is connected to the second input line 102, the first drain 107 of the first transistor and the second drain 109 of the second transistor are connected to the first end of the storage element 108, and the second end of the storage element 108 is connected to the output line 103.

[0100] The present application provides a deep neural network weight storage device, which includes a plurality of first input lines 101 arranged along a first direction, a plurality of second input lines 102 arranged along the first direction, and a plurality of output lines 103 arranged along the second direction, and a plurality of weight units located at nodes where the first input line 101, the second input line 102 and the output line 103 intersect, each of the weight units including: a first transistor, a second transistor and a storage element 108; a first source 104 of the first transistor is connected to the first input line 101, a second source 112 of the second transistor is connected to the second input line 102, a first drain 107 of the first transistor and a second drain 109 of the second transistor are connected to a first end of the storage element 108, and a second end of the storage element 108 is connected to the output line 103.

[0101] In the present application, the gate of the first transistor is electrically connected to the first word line 105, and the gate of the second transistor is electrically connected to the second word line 110. When the first word line 105 controls the first transistor to be turned off, the second word line controls the second transistor to be turned on. At this time, the second transistor is connected to the storage element 108 for weight calculation. When the second word line 110 controls the second transistor to be turned off, the first word line controls the first transistor to be turned on. At this time, the first transistor is connected to the storage element 108 for weight calculation. The weight is calculated by the method. In the present application, by assigning polarity and size to each weight storage unit in the deep neural network weight storage device, the product of input and weight can be functionally and structurally performed for calculation. Since the storage element 108 calculated each time is the same, the improvement eliminates the dependence on the symmetry of the storage device, eliminates the restriction on |G+|=|G-|, and reduces the amount of calculation, reduces the power consumption of the device and improves the operation speed of the device. The nonlinearity and asymmetry of the conductance response of the neural network weight storage device greatly improve the accuracy of "training" and "testing".

[0102] A second aspect of the present application provides a method for preparing a deep neural network weight storage device, the preparation method comprising:

[0103] Step S1: providing a substrate;

[0104] Step S2: forming a plurality of first nanowires on the substrate, wherein the extending direction of the nanowires is perpendicular to the substrate;

[0105] Step S3: doping the bottom of the first nanowire to form a first source electrode;

[0106] Step S4: forming a first bottom isolation layer, a first gate dielectric layer and a first gate material layer on the substrate in sequence to below the top surface of the first nanowire;

[0107] Step S5: patterning the first gate material layer to form a first gate surrounding the first nanowire;

[0108] Step S6: forming a first top isolation layer covering the first gate around the first gate, wherein the first top isolation layer exposes a portion of the first nanowire;

[0109] Step S7: doping the exposed top of the first nanowire to form a first drain;

[0110] Step S8: forming a first interlayer dielectric layer on the first top isolation layer and the first gate to the top surface of the first nanowire and exposing the top surface of the first drain;

[0111] Step S9: forming a second interlayer dielectric layer and a storage element located in the second interlayer dielectric layer on the first interlayer dielectric layer, wherein the storage element is connected to the first drain;

[0112] Step S10: forming a second nanowire on the storage element;

[0113] Step S11: doping the bottom of the second nanowire to form a second drain;

[0114] Step S12: forming a second bottom isolation layer, a second gate dielectric layer and a second gate material layer in sequence on the second interlayer dielectric layer to below the top surface of the second nanowire;

[0115] Step S13: patterning the second gate material layer to form a second gate surrounding the second nanowire;

[0116] Step S14: forming a second top isolation layer covering the second gate around the second gate, wherein the second top isolation layer exposes a portion of the second nanowire;

[0117] Step S15: doping the exposed top of the second nanowire to form a second source.

[0118] The preparation method of the deep neural network weight storage device is described in detail below.

[0119] The deep neural network weight storage device described in this application, such as Figure 3 and Figure 4As shown, it includes: a plurality of first input lines 101 arranged along a first direction, a plurality of second input lines 102 arranged along the first direction, and a plurality of output lines 103 arranged along the second direction, and a plurality of weight units located at nodes where the first input lines 101, the second input lines 102 and the output lines 103 intersect, each of the weight units includes: a first transistor, a second transistor and a storage element 108;

[0120] The first source 104 of the first transistor is connected to the first input line 101, the second source 112 of the second transistor is connected to the second input line 102, the first drain 107 of the first transistor and the second drain 109 of the second transistor are connected to the first end of the storage element 108, and the second end of the storage element 108 is connected to the output line 103.

[0121] The first direction and the second direction may be the same or different, which is not limited here. For example, in one embodiment of the present application, the first direction and the second direction are different, and the first direction and the second direction are perpendicular to each other.

[0122] The deep neural network weight storage device also includes a first word line 105 and a second word line 110 extending along the second direction, the gate of the first transistor is electrically connected to the first word line 105, and the gate of the second transistor is electrically connected to the second word line 110.

[0123] Specifically, Figure 3 As shown, in one embodiment of the present application, the deep neural network weight storage device includes N first input lines 101 and N second input lines 102 arranged horizontally, and M output lines 103 arranged vertically, wherein the horizontal and vertical directions are perpendicular to each other, and the weight unit is formed at the node where the horizontal and vertical directions intersect. Each of the weight units includes: a first transistor, a second transistor and a storage element 108.

[0124] The specific preparation method of the first transistor device is described in detail below. In the step S1, the substrate can be at least one of the following materials: silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), etc.

[0125] In one embodiment of the present application, the substrate is silicon.

[0126] In the step S2, a first nanowire is grown on the substrate, wherein the first nanowire is a columnar structure that is perpendicular to a horizontal surface of the substrate.

[0127] The first nanowire includes one of MOS2 or amorphous silicon, but is not limited to the examples.

[0128] In the step S3 , the bottom region of the first nanowire is doped to form a first source 104 .

[0129] Specifically, in this step, ion implantation is performed to form the first source 104 .

[0130] The energy, dosage and depth of the ion implantation can be selected according to actual needs and are not limited to a certain numerical range.

[0131] In one embodiment of the present application, a patterned mask layer is formed on the first nanowire to expose a region where the first source electrode 104 needs to be formed;

[0132] Then, ion implantation is performed using the mask layer as a mask to form the first source 104 .

[0133] Optionally, in this step, the ion energy of the implantation is 1kev-10kev, and the ion dose of the implantation is 5×10 14 -5×10 16 Atom / cm 2 .

[0134] In the step S4, a first bottom isolation layer, a first gate dielectric layer and a first gate material layer are sequentially formed on the substrate to below the top surface of the first nanowire.

[0135] Specifically, after the first source 104 is formed, a high density plasma (HDP) oxide deposition layer, for example, 250 nm thick, is formed as the first bottom isolation layer, and wet etching is performed using DHF (1:25). Due to non-conformal deposition, HDP deposition results in a greater thickness at the bottom of the first nanowire and a smaller thickness on the sidewall of the first nanowire. After the wet etching of about 150 nm, a thicker oxide is retained to cover the root of the vertically upright first nanowire. The first gate 106 is separated from the extended pad of the first source 104 by the method, thereby reducing the edge capacitance from the gate to the source.

[0136] Then, a first gate dielectric layer is formed on the first bottom isolation layer. For example, a gate oxide layer may be thermally grown on the exposed surface of the first nanowire as the first gate dielectric layer, wherein the thickness of the first gate dielectric layer may be about 5 nm.

[0137] In one embodiment of the present application, the gate dielectric layer includes a ferroelectric insulating material layer; the ferroelectric insulating material layer includes CuInP2S6 or HfO2, wherein the ferroelectric insulating material layer is not limited to the listed examples.

[0138] Among them, ferroelectric materials can exhibit spontaneous polarization in the absence of an external electric field. The polarization can be redirected by ion displacement in the crystal, and polarization switching can be triggered by an external electric field, so that the ferroelectric material can have two electrically controlled non-volatile states. In the present application, the ferroelectric insulating material layer is used as a gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET). Channel conductance is used to detect the polarization state in the ferroelectric gate insulator, so that data reading operations can be performed losslessly in the transistor. In transistors, the fast switching speed (nanoseconds or less) of ferroelectric materials, lossless readout, non-volatile storage states, and simple structures for high-density integration further improve the storage efficiency of the memory.

[0139] Furthermore, the gate dielectric layer further includes an amorphous silicon layer. For example, in the present application, the gate dielectric layer includes an amorphous silicon layer and a ferroelectric insulating material layer formed sequentially.

[0140] Among them, the first gate material layer includes but is not limited to silicon, polysilicon, doped polysilicon and polysilicon-germanium alloy materials (i.e., having a doping concentration from approximately 1×1018 to approximately 1×1022 doping atoms per cubic centimeter) and polycrystalline silicon metal silicide (polycide) materials (doped polysilicon / metal silicide stack materials).

[0141] In one embodiment of the present application, the first gate material layer is polysilicon. The method for forming the polysilicon gate material can be selected from a low pressure chemical vapor deposition (LPCVD) process. The process conditions for forming the polysilicon layer include: the reaction gas is silane (SiH4), and the flow rate of the silane can range from 100 to 200 cubic centimeters per minute (sccm), such as 150 sccm; the temperature range in the reaction chamber can be 700 to 750 degrees Celsius; the pressure in the reaction chamber can be 250 to 350 mTorr, such as 300 mTorr; the reaction gas can also include a buffer gas, and the buffer gas can be helium (He) or nitrogen, and the flow rate of the helium and nitrogen can range from 5 to 20 liters per minute (slm), such as 8 slm, 10 slm or 15 slm.

[0142] In step S5, the method further patterns the first gate material layer to form a first gate 106 surrounding the first nanowire; and the method also includes forming a first gate pad for leading out the first gate 106 to achieve electrical connection.

[0143] In this step, a mask is formed to cover the first nanowire, and then the first gate pad is patterned to form an extension of polysilicon to provide contact for the first gate 106 .

[0144] In step S6, a first top isolation layer covering the first gate is formed around the first gate, and the first top isolation layer exposes a portion of the first nanowire. The first top isolation layer includes a high density plasma (HDP) oxide deposition layer, and its thickness can be selected as needed, but at least the top region of the first nanowire is exposed to form the first drain 107.

[0145] In the step S7 , ion implantation is performed to dope the exposed first nanowire, thereby forming a first drain 107 in the top of the first nanowire.

[0146] For example, in one embodiment of the present application, As ions are injected, the ion energy is 10 keV, and the injected ion dose is 1×10 15 Atom / cm 2 Four implantations may be performed in four directions of the first nanowire at intervals of 90 degrees, and the tilt angle of the ion implantation is 45 degrees or greater.

[0147] After forming the first drain 107, an annealing step is further included. In an embodiment of the present application, the annealing temperature is 200-500° C., and the thermal annealing time is 1-200 seconds, but is not limited to the numerical range.

[0148] In step S8 and step S9, a first interlayer dielectric layer is formed on the first top isolation layer and the first gate 106 to the top surface of the first nanowire and exposes the top surface of the first drain 107; then a second interlayer dielectric layer and a storage element 108 located in the second interlayer dielectric layer are formed on the first interlayer dielectric layer, and the storage element 108 is connected to the first drain 107.

[0149] The storage element 108 is disposed above the first drain 107 and is electrically connected to the first drain 107 .

[0150] The storage element 108 includes at least one of a phase change storage element 108 (PCM), a resistive random access storage element 108 (RRAM), a magnetic random access storage element 108 (MRAM) and a ferroelectric storage element 108 .

[0151] The phase change memory element 108 includes a phase change material and a first electrode or a second electrode located on two opposite surfaces of the phase change material.

[0152] Alternatively, the phase-change memory element 108 is a circular structure, the phase-change material is a circular ring structure, the first electrode and the second electrode are formed on the inner and outer sides of the circular ring structure respectively, and one end of the second electrode is electrically connected to the first drain 107 .

[0153] The phase change material is usually Ge, Sb or Te, but is not limited to this example.

[0154] Among them, the shapes of the resistive memory element 108 (RRAM), the magneto-variable memory element 108 (MRAM) and the ferroelectric memory element 108 are similar to the phase change memory element 108, and the specific structure can be a conventional device structure, which will not be repeated here.

[0155] Then, steps S10 to S15 are performed to form a second transistor, wherein the second transistor includes a second gate 111, a second channel, and a second gate dielectric layer; the second gate dielectric layer is disposed between the second channel and the second gate 111, and the second gate dielectric layer includes a ferroelectric insulating material layer. The second gate dielectric layer also includes a second amorphous silicon layer disposed between the second channel and the ferroelectric insulating material layer. The second transistor device also includes: a second ladder-type interconnect structure, electrically connecting the second gate 111, the second source 112, and the second drain 109, respectively.

[0156] The second transistor is identical to the first transistor and is disposed in a mirror-image relationship at the upper and lower sides of the storage element 108. The manufacturing method can refer to the manufacturing process of the first transistor, which will not be described in detail here.

[0157] Furthermore, after forming the drain, the method further includes: forming a ladder-type interconnection structure to electrically connect the first source 104 , the first gate 106 , the first drain 107 , the second source 112 , the second gate 111 , and the second drain 109 , respectively.

[0158] Specifically, in one embodiment of the present application, the method for forming the stepped interconnection structure includes: patterning the functional material layer above the first source 104, the first gate 106, the first drain 107, the second source 112, the second gate 111, the second drain 109 or their corresponding connecting pads to form an opening and expose the first source 104, the first gate 106, the first drain 107, the second source 112, the second gate 111, the second drain 109 or their corresponding connecting pads, and then filling the opening with a conductive material to form a stepped interconnection structure.

[0159] Furthermore, the deep neural network weight storage device further includes a plurality of layers of repetitive units, each of which includes the structure described above, including: a plurality of first input lines 101 arranged along a first direction, a plurality of second input lines 102 arranged along the first direction, and a plurality of output lines 103 arranged along the second direction, and a plurality of weight units located at nodes where the first input lines 101, the second input lines 102, and the output lines 103 intersect, each of which includes: a first transistor, a second transistor, and a storage element 108;

[0160] The first source 104 of the first transistor is connected to the first input line 101, the second source 112 of the second transistor is connected to the second input line 102, the first drain 107 of the first transistor and the second drain 109 of the second transistor are connected to the first end of the storage element 108, and the second end of the storage element 108 is connected to the output line 103.

[0161] Furthermore, the method also includes repeatedly executing the preparation method on the prepared deep neural network weight storage device to form a deep neural network weight storage device with multiple layers stacked.

[0162] So far, the introduction of the relevant steps for preparing the deep neural network weight storage device of the embodiment of the present invention has been completed. After the above steps, other related steps may also be included, which will not be repeated here. In addition, in addition to the above steps, the preparation method of this embodiment may also include other steps in the above steps or between different steps, and these steps can be implemented by various processes in the prior art, which will not be repeated here.

[0163] In summary, the present application provides a deep neural network weight storage device and a method for preparing the same. The weight storage unit of the deep neural network weight storage device prepared in the method no longer calculates the weight by the difference between the conductances of a pair of transistors. By assigning polarity and size to each weight storage unit in the deep neural network weight storage device, the multiplication of input and weight can be functionally and structurally performed for calculation. The improvement eliminates the dependence on the symmetry of the storage device and the restriction on |G+|=|G-|. The nonlinearity and asymmetry of the conductance response of the neural network weight storage device greatly improve the accuracy of "training" and "testing".

[0164] The third aspect of the present invention also provides an electronic device, which includes a layer neural network weight storage device, which is the layer neural network weight storage device in the aforementioned embodiment one, or a layer neural network weight storage device prepared by the preparation method of the layer neural network weight storage device described in embodiment two.

[0165] The electronic device may be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigator, camera, camcorder, voice recorder, MP3, MP4, PSP, etc., or an intermediate product having the above-mentioned semiconductor, such as a mobile phone motherboard having the integrated circuit.

[0166] in, Figure 5 An example of a mobile phone handset is shown. The mobile phone handset 300 is provided with a display portion 302 included in a housing 301, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like.

[0167] The mobile phone comprises the aforementioned layer neural network weight storage device, the layer neural network weight storage device comprises: a plurality of first input lines arranged along a first direction, a plurality of second input lines arranged along the first direction, and a plurality of output lines arranged along the second direction, and a plurality of weight units located at nodes where the first input lines, the second input lines and the output lines intersect, each of the weight units comprises: a first transistor, a second transistor and a storage element;

[0168] The first source of the first transistor is connected to the first input line, the second source of the second transistor is connected to the second input line, the first drain of the first transistor and the second drain of the second transistor are connected to the first end of the storage element, and the second end of the storage element is connected to the output line.

[0169] The electronic device described in the present application has all the advantages of a deep neural network weight storage device because it adopts the deep neural network weight storage device described above.

[0170] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for preparing a deep neural network weight storage device, characterized in that: The preparation method comprises: providing a substrate; forming a plurality of first nanowires on the substrate, wherein the extending direction of the first nanowires is perpendicular to the substrate; Doping the bottom of the first nanowire to form a first source; forming a first bottom isolation layer, a first gate dielectric layer and a first gate material layer on the substrate in sequence to below the top surface of the first nanowire; Patterning the first gate material layer to form a first gate surrounding the first nanowire; forming a first top isolation layer around the first gate and covering the first gate, wherein the first top isolation layer exposes a portion of the first nanowire; Doping the exposed top of the first nanowire to form a first drain; forming a first interlayer dielectric layer on the first top isolation layer and the first gate to the top surface of the first nanowire and exposing the top surface of the first drain; forming a second interlayer dielectric layer and a storage element located in the second interlayer dielectric layer on the first interlayer dielectric layer, wherein the storage element is connected to the first drain; forming a second nanowire on the memory element; Doping the bottom of the second nanowire to form a second drain; forming a second bottom isolation layer, a second gate dielectric layer, and a second gate material layer in sequence on the second interlayer dielectric layer to below the top surface of the second nanowire; patterning the second gate material layer to form a second gate surrounding the second nanowire; forming a second top isolation layer around the second gate and covering the second gate, wherein the second top isolation layer exposes a portion of the second nanowire; The exposed top of the second nanowire is doped to form a second source.

2. The preparation method according to claim 1, characterized in that: The first gate dielectric layer and / or the second gate dielectric layer include a ferroelectric insulating material layer.

3. The preparation method according to claim 2, characterized in that: The ferroelectric insulating material layer includes CuInP2S6 or HfO2.

4. The preparation method according to claim 1, characterized in that: The first nanowire and / or the second nanowire include MOS2 or amorphous silicon.

5. The preparation method according to claim 1, characterized in that: The method further includes: forming a first ladder-type interconnect structure to electrically connect the first gate, the first source and the first drain respectively; and / or A second stair-type interconnect structure is formed to electrically connect the second gate, the second source, and the second drain, respectively.

6. The preparation method according to claim 1, characterized in that: The storage element includes at least one of a phase change storage element, a resistive change storage element, a magneto-variable storage element and a ferroelectric storage element.

7. The preparation method according to claim 6, characterized in that: The memory element is a ferroelectric memory element, and the ferroelectric memory element includes HfO2.

8. The preparation method according to claim 7, characterized in that: The ferroelectric memory element further includes a first electrode and a second electrode located on both sides of the HfO 2 .

9. The preparation method according to any one of claims 1 to 8, characterized in that: The preparation method is repeatedly performed on the prepared deep neural network weight storage device to form a deep neural network weight storage device with multiple layers stacked.

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