A memory fault location method and device

Abstract

The present specification provides a memory fault location method and device, which relates to the field of communication technology. A memory fault location method, applied to BMC, includes: when a fault is determined according to the register in the logic chip on the mainboard, obtaining the fault information of the internal register from the processor of the mainboard; determining the system address of the faulty memory according to the fault information; performing address conversion on the system address according to the mapping relationship between the stored system address and the physical address, and obtaining the physical address of the faulty memory; recording the physical address in the system event log. The above method can improve the maintainability of the server.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a method and device for locating a memory fault. Background Art

[0002] With the rapid development of information technology at home and abroad, servers have been widely used in various industries, and people are paying more and more attention to the reliable operation of servers. Among the failures that occur in servers, hard disks and memory account for the top two. Among them, memory failures will directly affect system operation and cause customer business interruptions. Therefore, quickly locating memory failures has become an important research direction. Memory failures are mainly divided into correctable errors and uncorrectable errors. Correctable errors do not affect system operation, and uncorrectable errors will cause the system to hang and completely stop working. Therefore, uncorrectable errors need more attention.

[0003] There are two situations when the system hangs. One is MCERR (Machine Check Error) caused by the system software, and the other is IERR (Internal Error) caused by the system hardware. In the case of MCERR, the server's BIOS (Basic Input Output System) can still work and perform error detection and reporting. However, in the case of IERR, the BIOS will also stop running and cannot locate and report errors. Therefore, how to locate and report memory failures in the event of IERR is an urgent problem that technicians need to solve. Summary of the invention

[0004] In order to overcome the problems existing in the related art, this specification provides a memory fault location method and device.

[0005] According to a first aspect of an implementation manner of this specification, a memory fault location method is provided, which is applied to a BMC, and includes:

[0006] When a fault is determined to occur according to a register in a logic chip on the mainboard, fault information of an internal register is obtained from a processor of the mainboard;

[0007] Determine the system address of the fault memory according to the fault information;

[0008] According to the mapping relationship between the stored system address and the physical address, the system address is converted to obtain the physical address of the faulty memory;

[0009] Record the physical address in the system event log.

[0010] Optionally, before determining that a fault occurs according to a register in a logic chip on the mainboard, the method further includes:

[0011] Receive and store the mapping relationship between the system address and the physical address of the memory.

[0012] Further, determining the system address of the fault memory according to the fault information also includes:

[0013] determining a fault type according to first fault information obtained in the first register;

[0014] If the fault type is a fault of the processor, determining the fault module according to the second fault information obtained in the second register;

[0015] The system address corresponding to the faulty module is obtained from the third register corresponding to the faulty module.

[0016] Further, after determining the fault type according to the first fault information obtained in the first register, the method further includes:

[0017] If it is determined based on the fault type that the memory fault is not a fault of the processor, locating the memory fault is stopped.

[0018] Further, the faulty modules include IMC, IIO, MLC and DCU;

[0019] Obtaining the system address corresponding to the faulty module from the third register corresponding to the faulty module includes:

[0020] If the faulty module is the IIO and the system address cannot be parsed, the system address corresponding to the IMC is obtained from the third register corresponding to the IMC.

[0021] According to a second aspect of the embodiments of this specification, a memory fault location device is provided, which is applied to a BMC, including:

[0022] an acquisition unit, for acquiring fault information of an internal register from a processor of the mainboard when a fault is determined according to a register in a logic chip on the mainboard;

[0023] An address unit, used to determine a system address of a fault memory according to the fault information;

[0024] A conversion unit, used to convert the system address according to the stored mapping relationship between the system address and the physical address, and obtain the physical address of the faulty memory;

[0025] A logging unit for recording physical addresses in a system event log.

[0026] Optionally, the device further includes:

[0027] The storage unit is used to receive and store the mapping relationship between the system address and the physical address of the memory.

[0028] Furthermore, the address unit includes:

[0029] A type determination subunit, configured to determine a fault type according to the first fault information obtained in the first register;

[0030] a module determination subunit, configured to determine a faulty module according to second fault information obtained from a second register if the fault type is a fault of the processor;

[0031] The address determination subunit is used to obtain the system address corresponding to the faulty module from the third register corresponding to the faulty module.

[0032] Optionally, the device further includes:

[0033] The termination unit is used to stop locating the memory fault if it is determined according to the fault type that the fault is not caused by the processor.

[0034] Further, the faulty modules include IMC, IIO, MLC and DCU;

[0035] The address unit is further used to obtain the system address corresponding to the IMC from the third register corresponding to the IMC if the faulty module is the IIO and the system address cannot be parsed.

[0036] The technical solutions provided by the embodiments of this specification may have the following beneficial effects:

[0037] In the implementation mode of the present specification, after the fault is determined on the mainboard, the fault information of the internal register in the processor is obtained, and the system address of the faulty memory is determined based on the fault information and the address is converted to obtain the physical address, which is then recorded in the system event log, thereby avoiding the problem of system hangs caused by internal errors and the inability to locate the memory fault, thereby improving the maintainability of the server.

[0038] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0040] Figure 1 It is a flow chart of a memory fault location method involved in this application;

[0041] Figure 2 It is a structural schematic diagram of a mainboard to which a memory fault location method involved in the present application is applied;

[0042] Figure 3 It is a structural diagram of the relationship between the processor and memory involved in this application;

[0043] Figure 4 It is a structural schematic diagram of a memory fault locating device involved in the present application. DETAILED DESCRIPTION

[0044] Here, exemplary embodiments are described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification.

[0045] This application provides a memory fault location method, which is applied to BMC, such as Figure 1 As shown, including:

[0046] S100: When it is determined that a memory fault occurs according to a register in a logic chip on the mainboard, fault information of an internal register is obtained from a processor of the mainboard.

[0047] A mainboard for management is provided in the server, such as Figure 2 As shown in FIG. 1 , a processor, a logic chip, and a BMC (Baseboard Management Controller) are arranged on the motherboard. The BMC can monitor the devices and modules in the server and record them in the SEL (System Event Log). The processor can be a CPU or other computing device. Multiple CPUs can be arranged on the motherboard, such as Figure 2 The figure shows two CPUs. The logic chip can be a CPLD (Complex Programmable Logic Device). Figure 2 The BMC can be connected to the CPU through PECI (Platform Environment Control Interface), connected to the CPLD through CATERR / MSMI pins, and the CPU is connected to the CPLD through CATERR / MSMI pins.

[0048] When the CPU learns of a fault through a hardware interrupt, it sends a fault notification to the CPLD through the CATERR / MSMI pin, and the CPLD records the fault notification in its internal register. Figure 2In the scenario shown, it can be seen that CPU1 is connected to the CPLD through the CATERR1 / MSMI1 pin, and CPU2 is connected to the CPLD through the CATERR2 / MSMI2 pin.

[0049] During normal operation of the server, the BMC can periodically (for example, in a cycle of 1 second) read the value of the internal register from the CPLD through the CATERR3 / MSMI3 pin to determine whether the CPU has reported a fault. If the value of the internal register indicates that there is no fault, the timing will continue until the next cycle is read again. If the value of the internal register indicates that there is a fault, the BMC is triggered to access the CPU internal register through PECI to obtain the fault information recorded in the CPU internal register. When there are two CPUs on the motherboard, the BMC will obtain the fault information in the internal registers of the two CPUs respectively and record them separately.

[0050] S101. Determine a system address of a faulty memory according to fault information.

[0051] The CPU contains multiple internal registers for storing fault-related fault information. The BMC needs to determine the system address of the memory where the fault occurs based on the values ​​of the multiple internal registers. The following describes the internal memory to which the fault applies.

[0052] The first register (e.g., MCA_ERR_SRC_LOG): This register stores the fault type, including the fault of the CPU and the external fault (i.e., the fault occurs on other CPUs), and whether the fault is IERR or MCERR. When a memory fault occurs, although it can be identified as IERR, it will also be recorded in the MCERR-related registers, and more information about memory-related faults will be recorded in the MCERR-related registers.

[0053] According to the first fault information stored in the first register (for example, bits [28:27] and bits [19:18] in the first register), it can be determined whether the fault type is a fault of the CPU. If it is not a fault of the CPU, there is no need to continue analyzing other internal registers of the CPU, and the memory fault location for the CPU is stopped. If it is a fault of the CPU, the other internal registers of the CPU are continued to be analyzed.

[0054] Second register (eg MCerr_Logging_Reg): In this internal register, the module identifier of the module where the fault occurs (ie the second fault information) is stored. The module is generally a module associated with the memory. Figure 3As shown, an IMC is provided in the processor, each IMC is provided with multiple channels, and each channel can correspond to multiple memories. Then, the module can include the IMC, and the second fault information can be used to distinguish whether the fault occurs specifically in the IMC itself or in multiple channels associated with the IMC. Memory can be plugged into each channel. Figure 3 It can be seen that there are two IMCs in a processor, three channels are associated with one IMC, and two memories can be plugged into one channel.

[0055] For example, bits [7:0] in MCerr_Logging_Reg can be used to determine whether the fault originates from the IMC itself or the channel associated with the IMC. When bits [7:0] are used to determine whether the fault originates from the channel, bits [13:10] need to be further checked to determine which channel the fault is located.

[0056] Specifically, bit [7:0] = 01100000 represents IMC0, bit [7:0] = 01100100 represents IMC1, and after determining IMC, the channel is determined according to bit [13:10], bit [13:10] = 0101 represents channel 0, bit [13:10] = 0111 represents channel 1, and bit [13:10] = 1001 represents channel 2. For other channels, the specific bit values ​​in the register are not listed one by one.

[0057] The fault is determined to be from the IMC itself according to bit 2, and the IMC in which the fault is located can also be determined according to bits [7:0]. Bits [7:0] = 01100010 represent IMC0, and bits [7:0] = 01100110 represent IMC1.

[0058] Through the above process, the specific fault module can be determined from the second fault information obtained from the second register.

[0059] In the CPU, a corresponding register is set for the module to store the status of the module. This memory can be called a module-specific register. In this module. For example, for IMC0 itself and IMC1 itself, MC7_BANK and MC8_BANK can be set to store the status information and system address of the module. For the six channels associated with IMC0 and IMC1, the six registers from MC13_BANK to MC18_BANK can be set to store the status information and system address of the module.

[0060] In MC7_BANK, MC8_BANK, and MC13_BANK to MC18_BANK, there are multiple sub-registers, including the status register (MC_STATUS), address register (MC_ADDR), miscellaneous register (MC_MISC), and control register (MC_CTL). Among them, the validity flag is set in the status register and the address register. In the process of obtaining the system address, the BMC will first check whether the validity flag in the status register is valid. If it is valid, it will check the address register. When checking the address register, it will also confirm whether the validity flag in the address register is valid. If it is valid, the address stored in the address register will be obtained as the system address.

[0061] In addition, due to the impact of memory diffusion, memory failures may be recorded in other modules, such as IIO, MLC, and DCU. Among them, a corresponding register (MC3_BANK) is set for MLC, a corresponding register (MC1_BANK) is set for DCU, and a corresponding register (MC6_BANK) is set for IIO.

[0062] When the faulty module is IIO, the sub-register (MC6_MISC) in MC6_BANK can be used to determine whether there is a PCIE (Peripheral Component Interconnect Express) fault, that is, whether the system address of the PCIE associated with IIO can be parsed. If the system address of the PCIE cannot be parsed, it can be considered to be caused by a memory fault. At this time, the system address of the faulty memory can be obtained by targeting the register corresponding to the IMC.

[0063] S102: According to the stored mapping relationship between the system address and the physical address, perform address conversion on the system address to obtain the physical address of the faulty memory.

[0064] The mapping relationship between the system address and the physical address can be stored in the BMC. After the BMC obtains the system address based on the faulty memory, it can convert the system address into the actual physical address based on the mapping relationship. The physical address indicates where the memory is plugged in and can be used to locate the memory in the server.

[0065] The mapping relationship may be stored in the BMC in a fixed relationship, or may be sent to the BMC in the form of a file through a data channel between the BIOS and the BMC before step S100, i.e., during the BIOS power-on process, so that the BMC stores the file in a non-volatile memory for use when a memory failure is detected.

[0066] The specific method of converting the system address and the physical address is similar to the current method and will not be described in detail here.

[0067] S103. Record the physical address in the system event log.

[0068] After the BMC determines the physical address of the faulty memory, it can be recorded in the SEL (System Event Log) of the BMC and can be displayed through a display device such as a monitor.

[0069] After the physical address of the faulty memory is displayed, the staff can locate the position of the memory in the server according to the physical address and replace the faulty memory.

[0070] In the implementation mode of this specification, after the fault is determined on the mainboard, the fault information of the internal register in the processor is obtained, and the system address of the faulty memory is determined based on the fault information and the address is converted to obtain the physical address, which is then recorded in the system event log, thereby avoiding the problem of system hangs caused by internal errors and the inability to locate memory faults, thereby improving the maintainability of the server.

[0071] In a large server, a large number of memories may be provided therein. Through the above method, a failed memory can be located from the large number of memories.

[0072] Correspondingly, the present application also provides a memory fault location device, such as Figure 4 As shown, it is applied to BMC, including:

[0073] an acquisition unit, for acquiring fault information of an internal register from a processor of the mainboard when a fault is determined according to a register in a logic chip on the mainboard;

[0074] An address unit, used to determine a system address of a fault memory according to the fault information;

[0075] A conversion unit, used to convert the system address according to the stored mapping relationship between the system address and the physical address, and obtain the physical address of the faulty memory;

[0076] A logging unit for recording physical addresses in a system event log.

[0077] Optionally, the device further includes:

[0078] The storage unit is used to receive and store the mapping relationship between the system address and the physical address of the memory.

[0079] Furthermore, the address unit includes:

[0080] A type determination subunit, configured to determine a fault type according to the first fault information obtained in the first register;

[0081] a module determination subunit, configured to determine a faulty module according to second fault information obtained from a second register if the fault type is a fault of the processor;

[0082] The address determination subunit is used to obtain the system address corresponding to the faulty module from the third register corresponding to the faulty module.

[0083] Optionally, the device further includes:

[0084] The termination unit is used to stop locating the memory fault if it is determined according to the fault type that the fault is not caused by the processor.

[0085] Further, the faulty modules include IMC, IIO, MLC and DCU;

[0086] The address unit is further used to obtain the system address corresponding to the IMC from the third register corresponding to the IMC if the faulty module is the IIO and the system address cannot be parsed.

[0087] The technical solutions provided by the embodiments of this specification may have the following beneficial effects:

[0088] In the implementation mode of this specification, after the fault is determined on the mainboard, the fault information of the internal register in the processor is obtained, and the system address of the faulty memory is determined based on the fault information and the address is converted to obtain the physical address, which is then recorded in the system event log, thereby avoiding the problem of system hangs caused by internal errors and the inability to locate memory faults, thereby improving the maintainability of the server.

[0089] It should be understood that the present description is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

[0090] The above description is only a preferred implementation of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A memory fault location method, characterized in that: Applied to baseboard management controller BMC, including: When a fault is determined according to a register in a logic chip on the mainboard, obtaining fault information of the internal register from a processor of the mainboard; Determine the system address of the fault memory according to the fault information; According to the stored mapping relationship between the system address and the physical address, the system address is converted to obtain the physical address of the faulty memory; Recording the physical address in a system event log; The determining the system address of the fault memory according to the fault information further includes: determining a fault type according to first fault information obtained in the first register; If the fault type is a fault of the processor, determining a fault module according to the second fault information obtained in the second register; Acquire a system address corresponding to the fault module from a third register corresponding to the fault module; The first register is used to store the fault type, which includes a CPU fault and an external fault; the second register is used to store the identifier of the faulty module; and the third register is used to store the status information and system address of the faulty module.

2. The method according to claim 1, characterized in that Before determining the failure according to the register in the logic chip on the mainboard, the method further includes: Receive and store the mapping relationship between the system address and the physical address of the memory.

3. The method according to claim 1, characterized in that After determining the fault type of the memory fault according to the first fault information obtained in the first register, the method further includes: If it is determined according to the fault type that the fault is not caused by the processor, locating the memory fault is stopped.

4. The method according to claim 1, characterized in that The fault module includes an integrated management controller IMC, an integrated input and output module IIO, a middle cache MLC and a data cache DCU; The acquiring the system address corresponding to the fault module from the third register corresponding to the fault module includes: If the faulty module is IIO and the system address cannot be parsed, the system address corresponding to the IMC is obtained from the third register corresponding to the IMC.

5. A memory fault location device, characterized in that: Applied to BMC, including: an acquisition unit, configured to acquire fault information of an internal register from a processor of the mainboard when a fault is determined according to a register in a logic chip on the mainboard; An address unit, used to determine a system address of a fault memory according to the fault information; A conversion unit, configured to perform address conversion on the system address according to a stored mapping relationship between the system address and the physical address, and obtain the physical address of the faulty memory; A recording unit, configured to record the physical address in a system event log; The address unit comprises: A type determination subunit, configured to determine a fault type according to the first fault information obtained in the first register; a module determination subunit, configured to determine a faulty module according to second fault information obtained from a second register if the fault type is a fault of the processor; An address determination subunit, configured to obtain a system address corresponding to the fault module from a third register corresponding to the fault module; The first register is used to store the fault type, which includes a CPU fault and an external fault; the second register is used to store the identifier of the faulty module; and the third register is used to store the status information and system address of the faulty module.

6. The device according to claim 5, characterized in that Also includes: The storage unit is used to receive and store the mapping relationship between the system address and the physical address of the memory.

7. The device according to claim 6, characterized in that Also includes: The termination unit is used to stop locating the memory fault if it is determined according to the fault type that the fault is not caused by the processor.

8. The device according to claim 6, characterized in that The fault modules include IMC, IIO, MLC and DCU; The address unit is further used to obtain the system address corresponding to the IMC from the third register corresponding to the IMC if the faulty module is the IIO and the system address cannot be parsed.

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