A power semiconductor device and a method for manufacturing the same

Abstract

The present invention relates to the field of semiconductor technology, and in particular to a power semiconductor device and a method for manufacturing the same, wherein the power semiconductor device comprises an N substrate and an intermediate P+ layer, wherein both ends of the top of the N substrate are provided with an active region N+ layer and a P region wrapping the active region N+ layer, wherein the P region comprises a channel P-layer, wherein the channel P-layer is arranged on the inner side of the active region N+ layer, wherein the gate oxide layer is arranged on the middle of the surface of the N substrate and covers the active region N+ layer, and wherein the intermediate P+ layer is arranged between the two P regions and connected to the two P regions. The power semiconductor device provided by the present invention can reduce the electric field strength borne by the gate oxide layer when the drain is pressurized, reduce the probability of the gate oxide layer being broken down, improve the reliability of the device, and ensure the channel density of the device at the same time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power semiconductor device and a manufacturing method thereof. Background Art

[0002] Since SiC material has 10 times the critical breakdown electric field compared to Si material, when designing MOSFET devices of the same voltage level, the thickness of the device drift region can be greatly reduced, the doping concentration can also be increased, and the drift region resistance of the device can be reduced by 1000 times. Therefore, SiC becomes a very attractive semiconductor material when developing high-voltage power MOSFET devices.

[0003] However, in MOSFET devices using SiC as the semiconductor material, the maximum electric field bearing capacity of the gate oxide is low, and it is easy to be damaged after a high reverse voltage is applied to the drain and source. In addition, due to the existence of JFET resistance in planar SiC power MOSFET devices, the width of the gate is generally designed to be larger in the prior art, resulting in the middle part of the gate being subjected to a higher electric field strength after reverse pressure is applied to the drain, which is easy to be damaged. Summary of the invention

[0004] The present invention aims to solve the technical problem in the prior art that the gate width of the MOSFET device is large, which causes the gate oxide to be easily damaged after the drain is reversely pressurized. A power semiconductor device is proposed, which can reduce the electric field strength borne by the gate oxide when the drain is pressurized, reduce the probability of the gate oxide being broken down, and improve the reliability of the device.

[0005] The technical solution of the present invention:

[0006] A power semiconductor device, comprising:

[0007] An N substrate, wherein both ends of the top of the N substrate are provided with an active region N+ layer and a P region wrapping the active region N+ layer;

[0008] A P region, the P region including a channel P-layer, the channel P-layer being arranged inside the active region N+ layer;

[0009] A gate oxide layer, wherein the gate oxide layer is disposed in the middle of the surface of the N substrate and covers the active area N+ layer;

[0010] The middle P+ layer is arranged between the two P regions and connected to the two P regions.

[0011] Furthermore, there are a plurality of intermediate P+ layers, which are arranged at intervals along a direction perpendicular to a cross section of a cell structure of the power semiconductor device.

[0012] Optionally, the intermediate P+ layer includes a first intermediate P+ layer and a second intermediate P+ layer, the first intermediate P+ layer is arranged between the two channel P- layers, and the second intermediate P+ layer is formed by highly doping the channel P- layer.

[0013] Optionally, the P region further includes a P+1 layer configured outside the active region N+ layer and a P+2 layer configured at the bottom of the active region N+ layer, and the middle P+ layer is configured between the two P+2 layers and connected to the two P+2 layers.

[0014] Preferably, the N matrix comprises an N+ substrate and an N-drift region epitaxially formed on the N+ substrate, and an intermediate N+ layer is further provided at the middle position of the top of the N-drift region.

[0015] Preferably, the material of the N matrix is ​​SiC.

[0016] Another aspect of the present invention provides a method for manufacturing the above-mentioned power semiconductor device, wherein the intermediate P+ layer is formed by the following steps: using photolithography and ion implantation processes, photolithography defines the intermediate P+ layer region, and implants aluminum ions to form the intermediate P+ layer. In this way, the intermediate P+ layer of the present invention is located in the upper region of the device, so that the implantation process of the intermediate P+ layer is simple and easy to implement, especially in SiC material devices, the deeper the depth, the greater the difficulty of ion implantation, and the present invention solves this problem well.

[0017] Optionally, the method further comprises the following steps:

[0018] Using the epitaxial process, an N-epitaxial layer and a P-epitaxial layer of required thickness are epitaxially grown on the surface of the N+ substrate to form an N matrix;

[0019] The photolithography and ion implantation process is used to define the middle N+ layer area by photolithography, and the area corresponding to the middle N+ layer in the P-epitaxial layer is compensated with N-type doping to form the middle N+ layer by implanting nitrogen ions or phosphorus ions with different energies. In this way, the P-epitaxial layer is firstly grown by the epitaxial process, and then the corresponding N-type semiconductor impurities are implanted on the P-epitaxial layer to form the middle N+ layer.

[0020] Optionally, the method further comprises the following steps:

[0021] Using epitaxial process, an N- epitaxial layer of required thickness is grown on the surface of N+ substrate to form N matrix;

[0022] Using photolithography and ion implantation processes, the channel P-layer region is defined by photolithography, and aluminum ions are implanted to form the channel P-layer;

[0023] Photolithography and ion implantation processes are used to define the middle N+ layer area by photolithography, and nitrogen ions or phosphorus ions with different energies are implanted to form the middle N+ layer. In this way, ions are implanted on the N-epitaxial layer to form the channel P-layer and the middle N+ layer.

[0024] Furthermore, the method further comprises the following steps:

[0025] Photolithography and ion implantation processes are used to define the P+1 layer to be implanted. Aluminum ions with different energies are implanted into the corresponding areas at different depths of the active layer to form the P+1 layer.

[0026] Photolithography and ion implantation processes are used to define the P+2 layer to be implanted, and aluminum ions of different energies are implanted into the corresponding areas at different depths of the active layer to form the P+2 layer.

[0027] Photolithography and ion implantation processes are used. The photolithography defines the area to be implanted, and the corresponding area is implanted with nitrogen ions or phosphorus ions of different energies to form the active area N+ layer.

[0028] A thermal oxidation process is used to grow an oxide layer on the surface of the N substrate to form a gate oxide layer;

[0029] A deposition process is used to deposit a layer of polysilicon on the gate oxide layer to form a polysilicon gate;

[0030] Using photolithography and etching processes, different polysilicon gate regions are defined by photolithography, and unnecessary polysilicon is etched away;

[0031] Using a deposition process, an insulating dielectric layer is deposited on the surface of the polysilicon gate to serve as electrical isolation between the polysilicon gate and the metal;

[0032] Using photolithography and etching processes, the active layer hole layer and the hole layer on different polysilicon gates are defined by photolithography, and the unnecessary insulating dielectric layer is etched away;

[0033] A layer of metal is deposited on the insulating dielectric layer by using a deposition process;

[0034] Photolithography and etching processes are used to define the active layer metal area and the gate metal area, and etching is performed to form the active area electrode and the gate electrode of the device.

[0035] After adopting the above technical solution, the present invention has the following beneficial effects compared with the prior art: the power semiconductor device of the present invention is provided with an intermediate P+ layer at intervals below the gate oxide layer, and the intermediate P+ layer is connected to the active area. After the drain-source reverse voltage is applied, the electric field strength of the gate oxide layer can be reduced, the probability of the gate oxide layer being broken down can be reduced, and the reliability of the device can be improved. It is particularly suitable for power devices made of third-generation semiconductor materials such as SiC. At the same time, the intermediate P+ layer can also be designed as a buried layer solution, so that the channel density of the device is not reduced while reducing the electric field strength of the gate oxide layer when the device is reversely applied with a voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram of the cross-sectional structure of a planar MOSFET in the prior art;

[0037] Figure 2 for Figure 1 A top view of the mid-plane MOSFET structure (excluding the polysilicon gate and insulating dielectric layer);

[0038] Figure 3 A top view of a planar MOSFET structure (excluding a polysilicon gate and an insulating dielectric layer) in Example 1;

[0039] Figure 4a for Figure 3 A schematic diagram of the cross-sectional structure along line A1-A1';

[0040] Figure 4b for Figure 3 A schematic diagram of the cross-sectional structure of A2-A2';

[0041] Figure 5a for Figure 3 Schematic diagram of the cross-sectional structure of B1-B1';

[0042] Figure 5b for Figure 3 Schematic diagram of the cross-sectional structure of B2-B2';

[0043] Figure 5c for Figure 3 Schematic diagram of the cross-sectional structure of B3-B3';

[0044] Figure 6 It is a top view of the planar MOSFET structure (excluding the polysilicon gate and the insulating dielectric layer) in the fourth embodiment;

[0045] Figure 7a for Figure 6 A schematic diagram of the cross-sectional structure along line A1-A1';

[0046] Figure 7b for Figure 6A2-A2' cross-sectional structure diagram;

[0047] Figure 8a for Figure 6 Schematic diagram of the cross-sectional structure of B1-B1';

[0048] Figure 8b for Figure 6 Schematic diagram of the cross-sectional structure of B2-B2';

[0049] Figure 8c for Figure 6 Schematic diagram of the cross-sectional structure of B3-B3'.

[0050] in,

[0051] N base 1, N+ substrate 11, N- drift region 12, middle N+ layer 13, active area N+ layer 2, P region 3, channel P- layer 31, P+1 layer 32, P+2 layer 33, middle P+ layer 4, gate oxide layer 5, polysilicon gate 6, insulating dielectric layer 7. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0054] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0055] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0056] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0057] The purpose of the present invention is to provide a planar MOSFET device structure, wherein an intermediate P+ layer is arranged below the gate oxide in an N matrix, and the spacing between the intermediate P+ layers can be adjusted according to the degree of protecting the gate oxide. The intermediate P+ layer is connected to the active area, and after the drain-source reverse voltage is applied, the electric field strength of the gate oxide layer can be reduced, the probability of the gate oxide being broken down can be reduced, and the reliability of the device can be improved. It is particularly suitable for power devices made of third-generation semiconductor materials such as SiC. At the same time, the intermediate P+ layer can also be designed as a buried layer scheme, so that the electric field strength of the gate oxide when the device is reversely applied with a voltage is reduced, and the channel density of the device is not reduced. The structure of the power semiconductor device and its manufacturing method are specifically described below through specific embodiments.

[0058] Embodiment 1:

[0059] like Figure 1-2As shown, the planar MOSFET structure in the prior art includes an N substrate 1, an active region N+ layer 2, a P region 3 and a gate oxide layer 5. The top two ends of the N substrate 1 are provided with an active region N+ layer 2 and a P region 3 wrapping the active region N+ layer 2. A gate oxide layer 5 is provided in the middle of the surface of the N substrate 1. The gate oxide layer 5 covers the active region N+ layer 2. A polysilicon gate 6 and an insulating dielectric layer 7 are provided above the gate oxide layer 5. The active region N+ layer 2 is electrically connected to the source, and the bottom of the N substrate 1 is electrically connected to the drain. Further, the two P regions 3 each include a channel P-layer 31, which is arranged on the inner side of the active region N+ layer 2. When the gate is applied with a turn-on voltage, the channel P-layer 31 is inverted to form a conductive channel, and the conduction current flows in the N substrate 1 in a vertical direction. Due to the presence of JFET resistance in this MOSFET structure, the area below the gate oxide layer 5 is generally designed to be larger, that is, the space between the two channel P-layers 31 is larger. This makes the electric field strength below the gate oxide layer 5 higher when the device is subjected to a higher drain voltage, and the gate oxide layer 5 is easily broken down and damaged.

[0060] Furthermore, if Figure 1 As shown, the N matrix 1 also includes an N+ substrate 11 and an N-drift region 12 epitaxially formed on the N+ substrate 11. The N-drift region 12 is used to improve the voltage resistance. An intermediate N+ layer 13 is also provided at the top middle position of the N-drift region 12 to increase the conduction capability of the device. Figure 1 The middle dotted line is the approximate boundary between the middle N+ layer 13 and the N− drift layer 12 .

[0061] This embodiment makes improvements to the prior art, such as Figure 3-5c As shown, the power semiconductor device of this embodiment further includes an intermediate P+ layer 4, which is disposed between the two P regions 3 and connected to the two P regions 3. In this way, a PN junction is formed between the gate oxide layer 5 and the drain. When the power semiconductor device is subjected to a higher drain voltage, it is equivalent to applying reverse pressure to the PN junction. As the voltage increases, the depletion layer of the PN junction becomes wider and wider, and eventually the gate oxide layer 5 and the drain are pinched off, so that the electric field strength under the gate oxide layer 5 is greatly reduced, thereby reducing the probability of the gate oxide layer 5 being broken down and improving the reliability of the device.

[0062] Furthermore, in this embodiment, there are multiple intermediate P+ layers 4, which are arranged evenly or unevenly along a direction perpendicular to the cross section of the cell structure of the power semiconductor device. Specifically, Figure 4a and Figure 4b The structures shown are all cross-sections of the cell structure of the power semiconductor device. Figure 3As shown, in this embodiment, a plurality of intermediate P+ layers 4 are evenly spaced in a direction perpendicular to the above-mentioned cell cross section, and an intermediate N+ layer 13 is still between every two intermediate P+ layers 4, so that after the gate applies a turn-on voltage, these intermediate N+ layers 13 located between the P+ layers can still form a wider current path, so that the required conduction capability of the device can be maintained. Among them, the number and interval of the intermediate P+ layers 4 can be adjusted according to the reverse voltage and the degree of protection of the gate oxide, so that the conduction capability of the device can be improved as much as possible while meeting the reverse withstand voltage capability of the device.

[0063] Furthermore, the P region 3 of the present embodiment further includes a P+1 layer 32 disposed outside the active region N+ layer 2 and a P+2 layer 33 disposed at the bottom of the active region N+ layer 2 .

[0064] Furthermore, if Figure 4b As shown, the intermediate P+ layer 4 of this embodiment includes a first intermediate P+ layer and a second intermediate P+ layer. The first intermediate P+ layer is arranged between the two original channel P- layers 31, and the second intermediate P+ layer is formed by highly doping the channel P- layer 31. Figure 3 In the A2 - A2 ′ cross-sectional structure, the middle P+ layer 4 is located between the two active region N+ layers 2 and is connected to the two P regions 3 .

[0065] Preferably, the material of the N substrate 1 of the present embodiment is SiC. Since the critical breakdown electric field of SiC is much higher than that of ordinary Si material, when SiC is used as the substrate material, the thickness of the device drift region can be greatly reduced. However, the reduced thickness of the device drift region makes the gate oxide layer 5 easier to break down, and devices made of SiC material are generally used in high-voltage applications. Therefore, the risk of the gate oxide layer 5 being broken down is higher. The device structure of the present embodiment is particularly suitable for power devices made of SiC material. While reducing the thickness of the device drift region, the reverse voltage withstand capability of the device can be guaranteed to prevent the gate oxide layer 5 from being broken down, and at the same time, it has a certain conduction capability.

[0066] From the above content, it can be seen that the power semiconductor device provided by this embodiment can reduce the electric field strength borne by the gate oxide layer 5 when reverse pressure is applied, reduce the probability of the gate oxide layer 5 being broken down, improve the reliability of the device, and at the same time ensure a certain current conduction capability.

[0067] Embodiment 2:

[0068] This embodiment provides a method for manufacturing a power semiconductor device according to Embodiment 1, comprising the following steps:

[0069] S1: using an epitaxial process, an N-epitaxial layer 12 and a P-epitaxial layer of a desired thickness are epitaxially grown on the surface of an N+ substrate 11 to form an N matrix 1;

[0070] S2: using photolithography and ion implantation processes, photolithography defines the middle N+ layer 13 region, and by implanting nitrogen ions or phosphorus ions with different energies, the region corresponding to the middle N+ layer 13 in the corresponding P-epitaxial layer is compensated with N-type doping to form the middle N+ layer 13; in this way, firstly, a P-epitaxial layer is epitaxially grown by the epitaxial process, and then the corresponding N-type semiconductor impurities are implanted on the P-epitaxial layer to form the middle N+ layer 13, and a part of the P-epitaxial layer is reserved as the channel P-layer 31;

[0071] S3: using photolithography and ion implantation processes, photolithography defines the P+1 layer 32 to be implanted, and uses aluminum ions of different energies to implant into corresponding areas at different depths of the active layer to form the P+1 layer 32;

[0072] S4: using photolithography and ion implantation processes, photolithography defines the P+2 layer 33 to be implanted, and uses aluminum ions of different energies to be implanted into corresponding regions at different depths of the active layer to form the P+2 layer 33. The P+1 layer 32, the P+2 layer 33 and the P-layer constitute the P region 3 in the first embodiment;

[0073] S5: using photolithography and ion implantation processes, photolithography defines the middle P+ layer 4 region, and implants aluminum ions to form the middle P+ layer 4; in this way, the middle P+ layer 4 of the present invention is located in the upper region of the device, so that the implantation process of the middle P+ layer 4 is simple and easy to implement, especially in SiC material devices, the deeper the depth, the greater the difficulty of ion implantation, and the structure of the present invention can well avoid this problem;

[0074] S6: using photolithography and ion implantation processes, photolithography defines the area to be implanted, and implants nitrogen ions or phosphorus ions of different energies into the corresponding area to form an active area N+ layer 2;

[0075] S7: using a thermal oxidation process to grow an oxide layer on the surface of the N substrate 1 by thermal oxidation to form a gate oxide layer 5;

[0076] S8: using a deposition process to deposit a layer of polysilicon on the gate oxide layer 5 to form a polysilicon gate 6;

[0077] S9: using photolithography and etching processes, photolithography defines different polysilicon gate 6 regions, and etches away unnecessary polysilicon;

[0078] S10: using a deposition process, depositing an insulating dielectric layer 7 on the surface of the polysilicon gate 6 to serve as electrical isolation between the polysilicon gate 6 and the metal;

[0079] S11: using photolithography and etching processes, photolithography defines the active layer hole layer and the hole layers on different polysilicon gates 6, and etches away unnecessary insulating dielectric layers 7;

[0080] S12: using a deposition process to deposit a layer of metal on the insulating dielectric layer 7;

[0081] S13: Using photolithography and etching processes, photolithography is used to define the active layer metal area and the gate metal area, and etching is performed to form the active area electrode and the gate electrode of the device.

[0082] Furthermore, the order of the above steps S2-S6 can be readjusted as needed, that is, the order of forming the P region 3, the active region N+ layer 2, the middle N+ layer 13, and the middle P+ layer 4 can be adjusted as needed.

[0083] Embodiment three:

[0084] The manufacturing method of the power semiconductor device of this embodiment is different from that of the second embodiment in that steps S1-S2 in the second embodiment can be replaced by the following steps:

[0085] An N-epitaxial layer 12 of a desired thickness is epitaxially grown on the surface of the N+ substrate 11 by using an epitaxial process to form an N matrix 1;

[0086] Using photolithography and ion implantation processes, the channel P-layer 31 region is photolithographically defined, and aluminum ions are implanted to form the channel P-layer 31;

[0087] The photolithography and ion implantation processes are used to define the middle N+ layer 13 region by photolithography, and the middle N+ layer 13 is formed by implanting nitrogen ions or phosphorus ions with different energies; thus, the channel P-layer 31 and the middle N+ layer 13 are formed respectively by implanting different ions on the N-epitaxial layer 12.

[0088] Embodiment 4:

[0089] like Figure 6-8c As shown, the difference between the power semiconductor device of this embodiment and the embodiment 1 is that the intermediate P+ layer 4 of this embodiment is arranged between the two P+2 layers 33 and connected to the two P+2 layers 33, and the intermediate P+ layer 4 is a buried layer structure, and the intermediate N+ layer 13 is still retained above the intermediate P+ layer 4, so that after the gate is turned on, the channel P- layer 31 is still inverted to form a conduction loop, and the channel density of the device is not reduced.

[0090] The power semiconductor device of this embodiment can also adopt the manufacturing method of the second embodiment and the third embodiment, the difference lies in the implantation depth of the middle P+ layer 4. For other specific implementation methods, refer to the second embodiment and the third embodiment.

[0091] It can be seen from the above content that the power semiconductor device of this embodiment can reduce the electric field strength of the gate oxide layer when a high voltage is applied to the device in reverse, protect the gate oxide layer, and does not reduce the channel density of the device.

[0092] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A power semiconductor device, characterized in that: include: An N substrate (1), wherein both ends of the top of the N substrate (1) are provided with an active region N+ layer (2) and a P region (3) wrapping the active region N+ layer (2); A P region (3), the P region (3) comprising a channel P-layer (31), the channel P-layer (31) being arranged inside the active region N+ layer (2); A gate oxide layer (5), the gate oxide layer (5) being arranged in the middle of the surface of the N substrate (1) and covering the active area N+ layer (2); An intermediate P+ layer (4), the intermediate P+ layer (4) being arranged between the two P regions (3) and connected to the two P regions (3); The intermediate P+ layers (4) are multiple and are arranged in parallel at intervals along a direction perpendicular to the cross section of the cell structure of the power semiconductor device; The intermediate P+ layer (4) includes a first intermediate P+ layer and a second intermediate P+ layer, wherein the first intermediate P+ layer is arranged between the two channel P- layers (31), and the second intermediate P+ layer is formed by highly doping the channel P- layers (31); The method for preparing the power semiconductor device comprises: S1, using an epitaxial process, epitaxially growing an N-epitaxial layer (12) and a P-epitaxial layer of a desired thickness on the surface of an N+ substrate (11), to form an N matrix (1); S2, using photolithography and ion implantation processes, photolithography defines the middle N+ layer (13) region, and uses the implantation of nitrogen ions or phosphorus ions with different energies to compensate the region corresponding to the middle N+ layer (13) in the corresponding P-epitaxial layer for N-type doping to form the middle N+ layer (13); in this way, firstly, a P-epitaxial layer is epitaxially grown through the epitaxial process, and then corresponding N-type semiconductor impurities are implanted on the P-epitaxial layer to form the middle N+ layer (13), and a portion of the P-epitaxial layer is reserved as the channel P-layer (31); S3, using photolithography and ion implantation processes, photolithography defines the P+1 layer (32) to be implanted, and uses aluminum ions of different energies to implant into corresponding areas at different depths of the active layer to form the P+1 layer (32); S4, using photolithography and ion implantation processes, photolithography defines the P+2 layer (33) to be implanted, and uses aluminum ions of different energies to implant into corresponding areas at different depths of the active layer to form the P+2 layer (33), and the P+1 layer (32), the P+2 layer (33) and the P-layer constitute the P region (3); S5, using photolithography and ion implantation processes, photolithography defines the middle P+ layer (4) region, and implants aluminum ions to form the middle P+ layer (4); S6, using photolithography and ion implantation processes, photolithography defines the area to be implanted, and implants nitrogen ions or phosphorus ions of different energies into the corresponding area to form an active area N+ layer (2); S7, using a thermal oxidation process to grow an oxide layer on the surface of the N substrate (1) by thermal oxidation to form a gate oxide layer (5); S8, using a deposition process to deposit a layer of polysilicon on the gate oxide layer (5) to form a polysilicon gate (6); S9, using photolithography and etching processes to photolithographically define different polysilicon gate (6) regions, and etching away unnecessary polysilicon; S10, using a deposition process to deposit an insulating dielectric layer (7) on the surface of the polysilicon gate (6) to serve as electrical isolation between the polysilicon gate (6) and the metal; S11, using photolithography and etching processes, photolithography defines the active layer hole layer and the hole layers on different polysilicon gates (6), and etches away unnecessary insulating dielectric layers (7); S12, using a deposition process to deposit a layer of metal on the insulating dielectric layer (7); S13, using photolithography and etching processes, photolithography defines the active layer metal region and the gate metal region, and performs etching to form the active region electrode and the gate electrode of the device; The S1-S2 can also be replaced by: An N-epitaxial layer (12) of a desired thickness is epitaxially grown on the surface of an N+ substrate (11) by using an epitaxial process to form an N matrix (1); Using photolithography and ion implantation processes, photolithography defines a channel P-layer (31) region, and implants aluminum ions to form the channel P-layer (31); Photolithography and ion implantation processes are used to photolithographically define the middle N+ layer (13) region, and nitrogen ions or phosphorus ions with different energies are implanted to form the middle N+ layer (13); thus, a channel P-layer (31) and a middle N+ layer (13) are formed respectively by implanting different ions on the N-epitaxial layer (12).

2. The power semiconductor device according to claim 1, characterized in that: The P region (3) further comprises a P+1 layer (32) arranged outside the active region N+ layer (2) and a P+2 layer (33) arranged at the bottom of the active region N+ layer (2); the intermediate P+ layer (4) is arranged between the two P+2 layers (33) and connected to the two P+2 layers (33).

3. The power semiconductor device according to claim 1, characterized in that: The N matrix (1) comprises an N+ substrate (11) and an N-drift region (12) epitaxially formed on the N+ substrate (11), and an intermediate N+ layer (13) is also provided at the middle position of the top of the N-drift region (12).

4. The power semiconductor device according to claim 1, characterized in that: The material of the N matrix (1) is SiC.

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