A Phase-Locked Loop Based on Empirical Mode Decomposition

Abstract

The present application relates to the field of signal processing technology, and in particular to a phase-locked loop based on empirical mode decomposition, including: a voltage-controlled oscillator, which is used to determine a target output signal that matches an input signal based on a correlation relationship between the input signal and the output signal; a signal decomposition module, wherein the input end of the signal decomposition module is connected to the output end of the voltage-controlled oscillator, and the output end of the signal decomposition module is connected to the input end of a target filter, and the signal decomposition module is used to decompose the target output signal into multiple output components, and the output components include local characteristic signals of the target output signal; a target filter, which is used to filter the noise in the output components and output the local characteristic signal. The present application uses a signal decomposition module constructed by an empirical mode decomposition algorithm and a Savitzky‑Golay filter as a target filter to decompose and filter the signal at the output of a direct digital frequency synthesizer, thereby reducing the noise of the voltage-controlled oscillator both within and outside the bandwidth of the phase-locked loop.

Description

Technical Field

[0001] The present application relates to the technical field of signal processing, and in particular to a phase-locked loop based on empirical mode decomposition. Background Art

[0002] The phase-locked loop is a real-time feedback loop. It is mainly composed of a mixer, a loop filter, and a voltage-controlled oscillator. The mixer generally uses a multiplier, and the loop filter plays the role of a low-pass filter. The voltage-controlled oscillator is used as a reference signal source. The feedback loop is used to control the frequency of the voltage-controlled oscillator output signal to be consistent with the signal to be measured. Therefore, the phase-locked loop has the ability to track the relationship between the output of the fixed phase stage and the phase of the reference signal. This has made the phase-locked loop receive widespread attention since its birth. With the rapid development of electronic information technology, the phase-locked loop has been applied in many fields, such as power grid connection, clock synchronization, laser signal demodulation, radio communication, smart home and other fields. At present, the development direction of the phase-locked loop is low noise, high frequency, zero delay, etc., and the processing of phase-locked loop noise is a key and difficult problem.

[0003] As the reference signal source in the phase-locked loop, the voltage-controlled oscillator is an important noise source in the phase-locked loop. The phase-locked loop is a "high-pass" filter for the voltage-controlled oscillator noise. The phase noise in the low-frequency range within the loop bandwidth can be reduced by the phase-locked effect, while it remains unchanged outside this range. Reducing the noise of the voltage-controlled oscillator can significantly reduce the noise of the phase-locked loop.

[0004] At present, in the related art, a method for adaptively adjusting the loop bandwidth is designed to increase the bandwidth to achieve fast locking when the phase difference is large, and reduce the bandwidth to reduce phase jitter when the phase difference is small, thereby reducing the overall noise level of the phase-locked loop. Another loop bandwidth dynamic adjustment loop is also designed to suppress noise. There are also schemes that study voltage-controlled oscillator schemes with lower noise. For example, the reference clock alignment technology is used to reduce the phase noise within the bandwidth of the voltage-controlled oscillator. By adding an integrator and a clock generator to the traditional voltage-controlled oscillator, a new closed-loop voltage-controlled oscillator is designed to reduce the low-frequency 1 / f noise of the voltage-controlled oscillator, thereby reducing the noise within the bandwidth of the phase-locked loop. However, the above schemes can only reduce the noise within the loop bandwidth of the phase-locked loop.

[0005] Currently, no effective solution has been proposed to solve the problem that noise outside the loop bandwidth of the phase-locked loop cannot be suppressed. Summary of the invention

[0006] The present application provides a phase-locked loop based on empirical mode decomposition to solve the technical problem that noise outside the loop bandwidth range of the phase-locked loop cannot be suppressed.

[0007] According to one aspect of an embodiment of the present application, the present application provides a phase-locked loop based on empirical mode decomposition, including:

[0008] A voltage-controlled oscillator, used to determine a target output signal matching the input signal according to a correlation relationship between the input signal and the output signal;

[0009] A signal decomposition module, wherein the input end of the signal decomposition module is connected to the output end of the voltage-controlled oscillator, the output end of the signal decomposition module is connected to the input end of the target filter, and the signal decomposition module is used to decompose the target output signal into multiple output components, and the output components include local characteristic signals of the target output signal;

[0010] The target filter is used to filter the noise in the output component and output the local characteristic signal.

[0011] Optionally, the voltage-controlled oscillator includes a direct digital frequency synthesizer, which is used to output a first sinusoidal signal with adjustable frequency according to a voltage amplitude of an input signal, and the target output signal includes the first sinusoidal signal.

[0012] Optionally, the output component includes an eigenmode function signal of the first sinusoidal signal, and the plurality of eigenmode function signals have at least one frequency and at least one bandwidth.

[0013] Optionally, the target filter comprises a Savitzky-Golay filter, and the Savitzky-Golay filter is used to keep the waveform and bandwidth of the local characteristic signal unchanged when filtering the noise in the output component.

[0014] Optionally, the phase-locked loop also includes an adder, whose input end is connected to the output end of the Savitzky-Golay filter, and the adder is used to add multiple local characteristic signals obtained by filtering with the Savitzky-Golay filter to obtain a second sinusoidal signal, and the second sinusoidal signal is output through the first output end of the adder.

[0015] Optionally, the frequency of the second sinusoidal signal is the same as the frequency of the first sinusoidal signal.

[0016] Optionally, the phase-locked loop also includes a multiplier, the output end of the multiplier is connected to the input end of the direct digital frequency synthesizer, the first input end of the multiplier is used to input the signal to be tested, the second input end of the multiplier is connected to the second output end of the adder, and is used to receive the second sinusoidal signal output by the adder, the multiplier is used to mix the signal to be tested and the second sinusoidal signal and multiply them to output a mixed signal, and the input signal of the direct digital frequency synthesizer is a mixed signal.

[0017] Optionally, the frequency of the signal to be measured is the same as the frequency of the second sinusoidal signal and the frequency of the first sinusoidal signal.

[0018] Optionally, a low-pass filter is provided between the multiplier and the direct digital frequency synthesizer, the input end of the low-pass filter is connected to the output end of the multiplier, the output end of the low-pass filter is connected to the input end of the direct digital frequency synthesizer, the low-pass filter is used to filter the signal whose frequency is greater than the cut-off frequency in the mixed signal, and the input signal of the direct digital frequency synthesizer is the mixed signal filtered by the low-pass filter.

[0019] Optionally, a cutoff frequency of the low-pass filter is less than a product of a frequency of the target output signal and a target coefficient.

[0020] According to another aspect of an embodiment of the present application, the present application provides an electronic device, including a memory, a processor, a communication interface and a communication bus, wherein the memory stores a computer program that can be run on the processor, the memory and the processor communicate through the communication bus and the communication interface, and when the processor executes the computer program, it implements the above-mentioned phase-locked loop based on empirical mode decomposition.

[0021] According to another aspect of an embodiment of the present application, the present application further provides a computer-readable medium having a non-volatile program code executable by a processor, wherein the program code enables the processor to execute the above-mentioned phase-locked loop based on empirical mode decomposition.

[0022] The above technical solution provided by the embodiment of the present application has the following advantages compared with the related art:

[0023] The present application adopts an empirical mode decomposition algorithm and a Savitzky-Golay filter to decompose and filter the signal at the output of a direct digital frequency synthesizer, thereby reducing the noise of the voltage-controlled oscillator both within and outside the bandwidth of the phase-locked loop. The present application adopts a direct digital frequency synthesizer as a voltage-controlled oscillator, which can solve the phase drift problem of traditional analog phase-locked loops and digital phase-locked loops without performing phase compensation, ensure the normal operation of the phase-locked loop, and greatly reduce the complexity of the system and its ability to resist environmental interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0026] Figure 1A schematic diagram of an optional phase-locked loop provided according to an embodiment of the present application;

[0027] Figure 2 A schematic diagram of an optional electronic device structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0029] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application and have no specific meaning. Therefore, "module" and "component" can be used interchangeably.

[0030] In the related art, a method for adaptively adjusting the loop bandwidth is designed to increase the bandwidth to achieve fast locking when the phase difference is large, and reduce the bandwidth to reduce phase jitter when the phase difference is small, thereby reducing the overall noise level of the phase-locked loop. Another loop bandwidth dynamic adjustment loop is also designed to suppress noise. There are also schemes that study voltage-controlled oscillator schemes with lower noise. For example, the reference clock alignment technology is used to reduce the phase noise within the bandwidth of the voltage-controlled oscillator. By adding an integrator and a clock generator to the traditional voltage-controlled oscillator, a new closed-loop voltage-controlled oscillator is designed to reduce the low-frequency 1 / f noise of the voltage-controlled oscillator, thereby reducing the noise within the bandwidth of the phase-locked loop. However, the above schemes can only reduce the noise within the loop bandwidth of the phase-locked loop.

[0031] In order to solve the problem mentioned in the background technology, according to one aspect of the embodiment of the present application, an embodiment of a phase-locked loop based on empirical mode decomposition is provided, such as Figure 1 As shown, the phase-locked loop comprises:

[0032] A voltage controlled oscillator 101, used to determine a target output signal matching the input signal according to a correlation relationship between the input signal and the output signal;

[0033] A signal decomposition module 102, wherein the input end of the signal decomposition module is connected to the output end of the voltage-controlled oscillator, the output end of the signal decomposition module is connected to the input end of the target filter, and the signal decomposition module is used to decompose the target output signal into multiple output components, wherein the output components include local characteristic signals of the target output signal;

[0034] The target filter 103 is used to filter the noise in the output component and output the local characteristic signal.

[0035] In an embodiment of the present application, a voltage-controlled oscillator is used as a reference signal source, and a feedback loop is used to control the frequency of the output signal of the voltage-controlled oscillator to be consistent with the signal to be measured, so that the phase-locked loop has the ability to track the relationship between the output of the fixed phase stage and the phase of the reference signal. Preferably, the present application adopts a direct digital frequency synthesizer as a voltage-controlled oscillator, and the direct digital frequency synthesizer is used to output a first sinusoidal signal with adjustable frequency according to the voltage amplitude of the input signal, and the target output signal includes the first sinusoidal signal.

[0036] Traditional phase-locked loops are generally implemented using analog circuits or digital circuits. Hardware filters will cause phase shifts in the input signal while filtering, and this phase shift is nonlinear and will cause the phase-locked loop to fail. Using a direct digital frequency synthesizer as a voltage-controlled oscillator can solve the phase drift problem of traditional analog phase-locked loops and digital phase-locked loops without phase compensation, ensuring the normal operation of the phase-locked loop and greatly reducing the system's complexity and ability to resist environmental interference.

[0037] The signal decomposition module is an application module of the empirical mode decomposition algorithm. The empirical mode decomposition algorithm adaptively decomposes the first sinusoidal signal output by the direct digital frequency synthesizer, and a limited number of output components can be obtained after decomposition. In the embodiment of the present application, the output component is an intrinsic mode function signal. The decomposed intrinsic mode function signals contain local characteristic signals of different time scales of the original signal, and multiple intrinsic mode function signals have at least one frequency and at least one bandwidth.

[0038] Each eigenmode function signal obtained after empirical mode decomposition is subjected to noise filtering through a target filter. Preferably, in an embodiment of the present application, the target filter adopts a Savitzky-Golay filter, which is used to keep the waveform and bandwidth of the local characteristic signal unchanged when filtering the noise in the output component.

[0039] Optionally, the phase-locked loop also includes an adder 104, the input end of the adder is connected to the output end of the Savitzky-Golay filter, the adder is used to add multiple local characteristic signals obtained by filtering with the Savitzky-Golay filter to obtain a second sinusoidal signal, and the second sinusoidal signal is output through the first output end of the adder.

[0040] In the embodiment of the present application, the eigenmode function signal output by the Savitzky-Golay filter is added in the adder to obtain a reconstructed sinusoidal signal, i.e., a second sinusoidal signal. The second sinusoidal signal is obtained by re-adding the eigenfunction component of the first sinusoidal signal after noise filtering, so the frequency of the second sinusoidal signal is the same as the frequency of the first sinusoidal signal.

[0041] In the embodiment of the present application, the phase-locked loop is a real-time feedback loop, which also includes a mixer and a loop filter. Preferably, the present application uses a multiplier as the mixer and a low-pass filter as the loop filter.

[0042] Optionally, the phase-locked loop also includes a multiplier 105, the output end of the multiplier is connected to the input end of the direct digital frequency synthesizer, the first input end of the multiplier is used to input the signal to be tested, the second input end of the multiplier is connected to the second output end of the adder, and is used to receive the second sinusoidal signal output by the adder, the multiplier is used to mix the signal to be tested and the second sinusoidal signal and multiply them to output a mixed signal, and the input signal of the direct digital frequency synthesizer is a mixed signal.

[0043] Optionally, the frequency of the signal to be measured is the same as the frequency of the second sinusoidal signal and the frequency of the first sinusoidal signal.

[0044] In the embodiment of the present application, the signal obtained by mixing can be used as an input signal of a direct digital frequency synthesizer, and the signal obtained by mixing can also be filtered using a low-pass filter and then used as an input signal of the direct digital frequency synthesizer.

[0045] Optionally, a low-pass filter 106 is provided between the multiplier and the direct digital frequency synthesizer, the input end of the low-pass filter is connected to the output end of the multiplier, the output end of the low-pass filter is connected to the input end of the direct digital frequency synthesizer, the low-pass filter is used to filter the signal whose frequency is greater than the cut-off frequency in the mixed signal, and the input signal of the direct digital frequency synthesizer is the mixed signal filtered by the low-pass filter.

[0046] Optionally, a cutoff frequency of the low-pass filter is less than a product of a frequency of the target output signal and a target coefficient.

[0047] The following is a description of the working process of a phase-locked loop provided in an embodiment of the present application.

[0048] First, the signal to be measured enters the multiplier and is mixed and multiplied with the signal output by the adder. The signal output by the multiplier enters the low-pass filter, and the low-pass filter filters out signals higher than the cut-off frequency. The direct digital frequency synthesizer adjusts the frequency of the output sinusoidal signal according to the voltage amplitude of the output signal of the low-pass filter. The sinusoidal signal output by the digital frequency synthesizer is adaptively decomposed by the empirical mode decomposition algorithm, and a limited number of intrinsic mode functions can be obtained after decomposition. Each intrinsic mode function component decomposed contains local characteristic signals of different time scales of the original signal. The decomposed intrinsic mode function is subjected to noise suppression by a Savitzky-Golay filter. The intrinsic mode functions output by the Savitzky-Golay filter are added in the adder to obtain a reconstructed sinusoidal signal, and the frequency of the sinusoidal signal is the same as the frequency of the sinusoidal signal output by the direct digital frequency synthesizer. The frequency of the sinusoidal signal output by the adder is the same as the frequency of the signal to be measured input to the multiplier, and the sinusoidal signal output by the adder is the demodulated signal.

[0049] The sinusoidal signal output by the direct digital frequency synthesizer can be expressed as x(t). After the empirical mode decomposition algorithm, multiple intrinsic mode functions ci(t) and residuals r(t) are obtained, which can be expressed as:

[0050]

[0051] After the above empirical mode classification of the signal sequence, a series of eigenmode functions with different bandwidths from high frequency to low frequency can be obtained. The frequency components and bandwidths of these eigenmode functions change with the changes of the signal. Then these eigenmode functions are processed by Savitzky-Golay filter for noise reduction.

[0052] The Savitzky-Golay filter is a smoothing filter. This smoothing filter uses the least squares method to fit a polynomial in the time domain, which can effectively smooth the signal while ensuring that the shape and width of the signal remain unchanged. The Savitzky-Golay filter can be expressed as follows:

[0053]

[0054] Where n is the number of data points, m is the window width of the SG filter, and j is the running index in the original data table in the coordinate data. The Savitzky-Golay filter is used to filter multiple intrinsic mode functions ci(t), and the obtained intrinsic mode functions are added in the adder. The reconstructed signal can be expressed as:

[0055]

[0056] Compared with the sinusoidal signal x(t) output by the direct digital frequency synthesizer, the noise of x'(t) obtained after being processed by the Savitzky-Golay filter is suppressed, and the frequency of the x'(t) signal is the same as that of the signal to be measured.

[0057] In the embodiment of the present application, the empirical mode decomposition and Savitzky-Golay filter play a key role in the entire phase-locked loop system, and are responsible for decomposing and reducing the noise of the sinusoidal signal output by the direct digital frequency synthesizer, thereby reducing the system noise. The speed of the empirical mode decomposition will affect the response speed of the entire phase-locked loop.

[0058] Traditional phase-locked loops are generally implemented using analog or digital circuits. Hardware filters will cause phase shifts in the input signal while filtering, and this phase shift is nonlinear, which will cause the phase-locked loop to fail. Zero-phase filters can only be implemented through software filters. The phase-locked loop is a "high-pass" filter for the noise of the voltage-controlled oscillator. The phase noise in the low-frequency range within the loop bandwidth can be reduced by phase locking, while it remains unchanged outside this range. Traditional noise suppression methods can only reduce low-frequency noise within the bandwidth of the phase-locked loop, and high-frequency noise outside the bandwidth range is difficult to suppress.

[0059] The phase-locked loop proposed in the present application uses a direct digital frequency synthesizer as a voltage-controlled oscillator to solve the phase offset problem in the hardware system, ensure the normal operation of the phase-locked loop, and greatly reduce the complexity of the system and the ability to resist environmental interference; the empirical mode decomposition and Savitzky-Golay filter are used to suppress the noise of the voltage-controlled oscillator, and the high-frequency noise outside the bandwidth range can be effectively suppressed. Compared with the traditional phase-locked loop solution, the problem that the voltage-controlled oscillator noise outside the bandwidth range of the phase-locked loop is difficult to suppress can be solved.

[0060] According to another aspect of the embodiments of the present application, the present application provides an electronic device, such as Figure 2 As shown, it includes a memory 201, a processor 203, a communication interface 205 and a communication bus 207. The memory 201 stores a computer program that can be run on the processor 203. The memory 201 and the processor 203 communicate through the communication interface 205 and the communication bus 207. When the processor 203 executes the computer program, the above-mentioned phase-locked loop based on empirical mode decomposition is implemented.

[0061] The memory and processor in the above electronic device communicate via a communication bus and a communication interface. The communication bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc.

[0062] The memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0063] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0064] According to another aspect of the embodiments of the present application, a computer-readable medium having a non-volatile program code executable by a processor is provided.

[0065] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, and this embodiment will not be described in detail here.

[0066] When the embodiments of the present application are specifically implemented, reference may be made to the above-mentioned embodiments, which have corresponding technical effects.

[0067] It is understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit may be implemented in one or more application specific integrated circuits (ASIC), digital signal processors (DSP), digital signal processing devices (DSPD), programmable logic devices (PLD), field programmable gate arrays (FPGA), general purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described in the present application, or a combination thereof.

[0068] For software implementation, the technology described herein can be implemented by a unit that performs the functions described herein. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or outside the processor.

[0069] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0070] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0071] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0072] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0073] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0074] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk or an optical disk. It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements inherent to such a process, method, article or device. Without more constraints, an element defined by the phrase "comprising a..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.

[0075] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

Claims

1. A phase-locked loop based on empirical mode decomposition, characterized in that: include: A voltage-controlled oscillator, used to determine a target output signal matching the input signal according to a correlation relationship between the input signal and the output signal; A signal decomposition module, wherein the input end of the signal decomposition module is connected to the output end of the voltage-controlled oscillator, the output end of the signal decomposition module is connected to the input end of the target filter, and the signal decomposition module is used to decompose the target output signal into multiple output components, wherein the output components include local characteristic signals of the target output signal; The target filter is used to filter the noise in the output component and output the local characteristic signal; The voltage-controlled oscillator comprises a direct digital frequency synthesizer, and the direct digital frequency synthesizer is used to output a first sinusoidal signal with adjustable frequency according to the voltage amplitude of the input signal, and the target output signal comprises the first sinusoidal signal; The target filter comprises a Savitzky-Golay filter, and the Savitzky-Golay filter is used to keep the waveform and bandwidth of the local characteristic signal unchanged when filtering the noise in the output component; The phase-locked loop also includes an adder, the input end of the adder is connected to the output end of the Savitzky-Golay filter, the adder is used to add the multiple local characteristic signals obtained by filtering by the Savitzky-Golay filter to obtain a second sinusoidal signal, and the second sinusoidal signal is output through the first output end of the adder; The phase-locked loop also includes a multiplier, the output end of the multiplier is connected to the input end of the direct digital frequency synthesizer, the first input end of the multiplier is used to input the signal to be tested, the second input end of the multiplier is connected to the second output end of the adder, and is used to receive the second sinusoidal signal output by the adder, and the multiplier is used to mix the signal to be tested and the second sinusoidal signal and multiply them to output a mixed signal, wherein the input signal of the direct digital frequency synthesizer is the mixed signal.

2. The phase-locked loop according to claim 1, characterized in that: The output components include eigenmode function signals of the first sinusoidal signal, wherein a plurality of the eigenmode function signals have at least one frequency and at least one bandwidth.

3. The phase-locked loop according to claim 1, characterized in that: The frequency of the second sinusoidal signal is the same as the frequency of the first sinusoidal signal.

4. The phase-locked loop according to claim 1, characterized in that: The frequency of the signal to be measured is the same as the frequency of the second sinusoidal signal and the frequency of the first sinusoidal signal.

5. The phase-locked loop according to claim 1, characterized in that: A low-pass filter is arranged between the multiplier and the direct digital frequency synthesizer, the input end of the low-pass filter is connected to the output end of the multiplier, the output end of the low-pass filter is connected to the input end of the direct digital frequency synthesizer, the low-pass filter is used to filter the signal whose frequency is greater than the cut-off frequency in the mixed signal, and the input signal of the direct digital frequency synthesizer is the mixed signal filtered by the low-pass filter.

6. The phase-locked loop according to claim 5, characterized in that: The cutoff frequency of the low-pass filter is less than the product of the frequency of the target output signal and the target coefficient.

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