Method for aligning light emitting element and method for manufacturing display device using the same

Abstract

A method for aligning a light emitting element and a method for manufacturing a display device using the method for aligning a light emitting element are provided. The method for aligning a light emitting element includes: applying a ground voltage to a first electrode and applying a first AC voltage to a second electrode spaced apart from the first electrode; and applying the ground voltage to the first electrode and applying a second AC voltage to the second electrode, wherein the first AC voltage has an asymmetric waveform.

Description

Technical Field

[0001] The present invention relates to a method for aligning a light emitting element and a method for manufacturing a display device using the same. Background Art

[0002] As multimedia develops, the importance of display devices increases. Therefore, various types of display devices, such as organic light emitting displays (OLEDs) and liquid crystal displays (LCDs), have been used.

[0003] The display device is a device for displaying an image, and includes a display panel such as a light-emitting display panel or a liquid crystal panel. Among them, the light-emitting display panel can display an image by emitting light using a light-emitting element. In this case, when a light-emitting diode (LED) is used as a light-emitting element, an organic light-emitting diode (OLED) using an organic material as a fluorescent material or an inorganic light-emitting diode using an inorganic material as a fluorescent material can be used as a light-emitting element.

[0004] In the case of an organic light emitting diode (OLED), its advantage is that its manufacturing process is simple because it uses organic materials as fluorescent materials to emit light. However, organic materials as fluorescent materials may be susceptible to high temperature driving environments and may have lower blue light efficiency than light with another color.

[0005] On the other hand, in the case of an inorganic light emitting diode, it has advantages in that it has durability even in a high temperature environment and has higher blue light efficiency than an organic light emitting diode because it uses an inorganic semiconductor as a fluorescent material. Therefore, research on an inorganic light emitting diode having higher durability and efficiency than an organic light emitting diode is continuing. Summary of the invention

[0006] Technical issues

[0007] An object to be achieved by the present invention is to provide a method for aligning a light emitting element, by which the alignment accuracy of the light emitting element can be improved.

[0008] Another object to be achieved by the present invention is to provide a method for manufacturing a display device, by which the alignment accuracy of a light emitting element can be improved.

[0009] Other advantages, subjects, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon review of the following or may be learned from practice of the present invention.

[0010] Technical Solution

[0011] According to an embodiment of the present disclosure, a method for aligning a light-emitting element is provided, comprising: applying a ground voltage to a first electrode and applying a first AC voltage to a second electrode spaced apart from the first electrode; and applying a ground voltage to the first electrode and applying a second AC voltage to the second electrode, wherein the first AC voltage has an asymmetric waveform.

[0012] A voltage waveform in a positive polarity region of the first AC voltage and a voltage waveform in a negative polarity region of the first AC voltage may be left-right asymmetric.

[0013] The first AC voltage may have a sawtooth waveform or a lamp waveform.

[0014] The second AC voltage may have a symmetrical waveform.

[0015] A voltage waveform in a positive polarity region of the second AC voltage and a voltage waveform in a negative polarity region of the second AC voltage may be bilaterally symmetrical.

[0016] The second AC voltage may have a sinusoidal waveform, a square waveform, or a triangular waveform.

[0017] A driving frequency of the first AC voltage may be lower than a driving frequency of the second AC voltage.

[0018] The first AC voltage may have a driving frequency of 1 Hz to 1 kHz.

[0019] The second AC voltage may have a driving frequency of 1 kHz to 100 kHz.

[0020] When a ground voltage is applied to the first electrode and a first AC voltage is applied to a second electrode spaced apart from the first electrode, an electric field formed by the first electrode and the second electrode may be an asymmetric electric field in which any one of positive polarity and negative polarity dominates.

[0021] When the ground voltage is applied to the first electrode and the second AC voltage is applied to the second electrode, the electric field formed by the first electrode and the second electrode may be a symmetrical electric field.

[0022] According to an embodiment of the present disclosure, a method for manufacturing a display device is provided, which includes: forming a partition wall, a first electrode, and a second electrode on a substrate; applying a coating liquid containing a light-emitting element to a sub-pixel; forming an electric field between the first electrode and the second electrode to align the light-emitting element; volatilizing and removing the coating liquid; forming a first connecting electrode connecting the first electrode to one end of the light-emitting element; and forming a second connecting electrode connecting the second electrode to the other end of the light-emitting element, wherein forming an electric field between the first electrode and the second electrode to align the light-emitting element includes: applying a ground voltage to the first electrode, and applying a first AC voltage with an asymmetric waveform to the second electrode.

[0023] When a ground voltage is applied to the first electrode and a first AC voltage is applied to the second electrode, the light emitting element may be deflected toward the first electrode.

[0024] Each of the light emitting elements may include a first conductive semiconductor disposed at the other end of each of the light emitting elements and a second conductive semiconductor disposed at one end of each of the light emitting elements, wherein the first conductive semiconductor is disposed close to the second electrode and the second conductive semiconductor is disposed close to the first electrode.

[0025] The first conductive semiconductor may be an n-type semiconductor layer, and the second conductive semiconductor may be a p-type semiconductor layer.

[0026] Forming an electric field between the first electrode and the second electrode to align the light emitting element may further include applying a ground voltage to the first electrode, and applying a second AC voltage to the second electrode.

[0027] When a ground voltage is applied to the first electrode and a second AC voltage is applied to the second electrode, the light emitting element may be aligned toward a center between the first electrode and the second electrode.

[0028] The second AC voltage may have a symmetrical waveform.

[0029] A driving frequency of the first AC voltage may be lower than a driving frequency of the second AC voltage.

[0030] The method may further include disconnecting the first electrode after forming the second connection electrode so that the disconnected first electrodes correspond to each sub-pixel and are spaced apart from each other.

[0031] Beneficial Effects

[0032] Based on the method of aligning a light-emitting element according to the embodiment and the method of manufacturing a display device using the method, an asymmetric magnetic field can be formed by applying a first AC voltage having an asymmetric waveform to the second electrode, and thus the light-emitting element can be deflected toward the first electrode, so that the first conductive semiconductor of the light-emitting element is arranged toward the first electrode. Then, a symmetric magnetic field can be formed by applying a second AC voltage having a symmetric waveform to the second electrode, and thus the light-emitting element deflected to the first electrode can be aligned toward the center between the first electrode and the second electrode. Therefore, the alignment accuracy of the light-emitting element can be improved.

[0033] The effects of the present invention are not limited to the above-mentioned effects, and other unmentioned effects will be clearly understood by those skilled in the art from the description of the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0035] Figure 1 is a perspective view showing a display device according to an embodiment;

[0036] Figure 2 is a block diagram schematically showing a display device according to an embodiment;

[0037] Figure 3 Yes Description Figure 1 and Figure 2 A circuit diagram of an example of a pixel;

[0038] Figure 4 It specifically shows Figure 1 A plan view of a display panel;

[0039] Figure 5 It specifically shows Figure 4 A plan view of pixels of a display area;

[0040] Figure 6 is along Figure 5 sectional views taken along line II-I', line II-II' and line III-III';

[0041] Figure 7 It specifically shows Figure 6 A three-dimensional diagram of a light-emitting element;

[0042] Figure 8 is a flowchart showing a method of manufacturing a display device according to an embodiment;

[0043] Figure 9a to Figure 9g is a plan view of a pixel of a display area for explaining a method of manufacturing a display device according to an embodiment;

[0044] Figure 10a to Figure 10g is a cross-sectional view taken along line II-II′ for explaining a method of manufacturing a display device according to an embodiment;

[0045] Fig.11 is a plan view showing a pixel including a light emitting element, a first electrode branch portion, and a second branch portion aligned when an AC voltage having a high frequency sinusoidal waveform is applied to the second electrode;

[0046] Fig.12 yes Fig.11 Equivalent circuit diagram of

[0047] Fig.13 is a flow chart showing a method of aligning a light emitting element according to an embodiment;

[0048] Fig.14 is a plan view showing alignment of a light emitting element when a first AC voltage having an asymmetric waveform is applied to a second electrode;

[0049] Fig.15 is a diagram illustrating an example of a light emitting element for explaining a dipole moment;

[0050] Fig.16 It is as Fig.10c An equivalent circuit diagram of the first electrode, the second electrode, and the coating liquid when an electric field is formed between the first electrode and the second electrode as shown in FIG.

[0051] Fig.17a and Fig.17b is a graph showing waveforms of a first AC voltage and an electric field formed according to a waveform;

[0052] Fig.18 is a plan view showing alignment of the light emitting element when a second AC voltage having a symmetrical waveform is applied to the second electrode;

[0053] Figures 19a to 19n is a waveform diagram illustrating an example of a first AC voltage having an asymmetrical waveform; and

[0054] Figures 20a to 20c is a waveform diagram illustrating an example of a second AC voltage having a symmetrical waveform. DETAILED DESCRIPTION

[0055] The advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and these embodiments are only used to make the disclosure of the present invention complete. It is used to fully convey the scope of the present invention to those who obtain the present invention, and the present invention is limited only by the scope of the claims.

[0056] When an element or layer is referred to as being "on" another element or layer, it includes all cases where the element or layer is directly placed on the other element or layer or another element or layer is placed between the element or layer and the other element or layer. Throughout the specification, the same reference numerals represent the same components. The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings for describing the embodiments are exemplary, and the present invention is not limited to what is shown.

[0057] Although first, second, etc. are used to describe various elements, it goes without saying that these elements are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, it goes without saying that within the technical concept of the present invention, the first component mentioned below can be the second component.

[0058] Each of the features of the various embodiments of the present invention may be partially or completely combined or combined with each other, various interlocks and drives are technically possible, and each of the embodiments may be implemented independently of each other, or may be implemented together in a related relationship.

[0059] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, the display device 1 according to the embodiment will be described assuming that the display device 1 according to the embodiment is an inorganic light emitting display device using an inorganic light emitting diode including an inorganic semiconductor as a light emitting element.

[0060] Figure 1 is a perspective view showing a display device according to an embodiment. Figure 2 is a block diagram schematically showing a display device according to an embodiment. Figure 3 Yes Description Figure 1 and Figure 2 A circuit diagram of an example of a pixel.

[0061] Reference Figures 1 to 3 The display device 1 according to the embodiment may include a display panel 10, an integrated driving circuit 20, a scan driver 30, a circuit board 40, and a power supply circuit 50. The integrated driving circuit 20 may include a data driver 21 and a timing controller 22.

[0062] In this specification, "upper", "above", "top", "upper side" or "upper surface" refers to the Z-axis direction, and "lower", "lower", "bottom", "lower side" or "lower surface" refers to the direction opposite to the Z-axis direction. In addition, "left", "right", "upper" and "lower" refer to directions when the display panel 10 is viewed from a plane. For example, "left" refers to the direction opposite to the X-axis direction, "right" refers to the X-axis direction, "upper" refers to the Y-axis direction, and "lower" refers to the direction opposite to the Y-axis direction.

[0063] In a plan view, the display panel 10 may have a rectangular shape. Figure 1 As shown in , the display panel 10 may have a rectangular planar shape having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). A corner where the short side in the first direction (X-axis direction) meets the long side in the second direction (Y-axis direction) may be formed to have a right angle shape or a circular shape with a predetermined curvature. The planar shape of the display panel 10 is not limited to a rectangular shape, and may be formed to have another polygonal shape, a circular shape, or an elliptical shape. In addition, although in Figure 1 2 and 3. The display panel 10 is shown to be formed to be flat, but the present invention is not limited thereto. At least one side of the display panel 10 may be formed to be curved with a predetermined curvature.

[0064] The display panel 10 may be divided into a display area DA and a non-display area NDA disposed around the display area DA. The display area DA is an area where pixels PX are formed to display an image. The display panel 10 may include data lines D1 to Dm (m is an integer of 2 or more), scan lines S1 to Sn (n is an integer of 2 or more) intersecting the data lines D1 to Dm, a high potential voltage line VDDL to which a high potential voltage VDD is supplied, a low potential voltage line VSSL to which a low potential voltage VSS is supplied, and pixels PX connected to the data lines D1 to Dm and the scan lines S1 to Sn.

[0065] Each of the pixels PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1 may emit light of a first color, the second sub-pixel PX2 may emit light of a second color, and the third sub-pixel PX3 may emit light of a third color. The first color may be red, the second color may be green, and the third color may be blue, but the present invention is not limited thereto. In addition, although in Figure 2 , each of the pixels PX includes three sub-pixels, but the present invention is not limited thereto. That is, each of the pixels PX may include four or more sub-pixels.

[0066] Each of the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 may be connected to at least one of the data lines D1 to Dm, at least one of the scan lines S1 to Sn, and the high potential voltage line VDDL. Figure 3 As shown in FIG. 1 , the first subpixel PX1 may include a light emitting element LD, and a plurality of transistors and at least one capacitor for supplying current to the light emitting element LD.

[0067] Each of the light emitting elements LD may be an inorganic light emitting diode including a first electrode, an inorganic semiconductor, and a second electrode. Here, the first electrode may be an anode electrode, and the second electrode may be a cathode electrode.

[0068] like Figure 3 As shown in , the plurality of transistors may include a driving transistor DT for supplying current to the light emitting element LD and a scanning transistor ST for supplying a data voltage to the gate electrode of the driving transistor DT. The driving transistor DT may include a gate electrode connected to a source electrode of the scanning transistor ST, a source electrode connected to a high potential voltage line VDDL to which a high potential voltage VDD is applied, and a drain electrode connected to a first electrode of the light emitting element LD. The scanning transistor ST may include a gate electrode connected to a scanning line Sk (k satisfies 1≤k≤n), a source electrode connected to the gate electrode of the driving transistor DT, and a drain electrode connected to a data line Dj (j satisfies 1≤j≤m).

[0069] The capacitor is a storage capacitor Cst and is formed between the gate electrode and the source electrode of the driving transistor DT. The storage capacitor Cst stores a voltage difference between the gate electrode and the source electrode of the driving transistor DT.

[0070] Each of the driving transistor DT and the scanning transistor ST may be formed of a thin film transistor. Figure 3 1 and 2 show that each of the driving transistor DT and the scanning transistor ST can be formed by a P-type metal oxide semiconductor field effect transistor (MOSFET), but the present invention is not limited thereto. Each of the driving transistor DT and the scanning transistor ST can also be formed by an N-type MOSFET. In this case, the position of the source electrode and the drain electrode of each of the driving transistor DT and the scanning transistor ST can be changed.

[0071] In addition, despite the Figure 3 1 and 2 show that each of the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 may be a 2T1C (2 transistors-1 capacitor) having one driving transistor DT, one scanning transistor ST, and one storage capacitor Cst, but the present invention is not limited thereto. Each of the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 may include a plurality of scanning transistors ST and a plurality of storage capacitors Cst.

[0072] Since the second and third subpixels PX2 and PX3 may be represented by substantially the same circuit diagram as the first subpixel PX1 , a detailed description thereof will be omitted.

[0073] The integrated driving circuit 20 outputs signals and voltages for driving the display panel 10. To this end, the integrated driving circuit 20 may include a data driver 21 and a timing controller 22.

[0074] The data driver 21 receives the digital video data DATA and the source control signal DCS from the timing controller 22. The data driver 21 converts the digital video data DATA into analog data voltages in response to the source control signal DCS and supplies the analog data voltages to the data lines D1 to Dm.

[0075] The timing controller 22 receives digital video data DATA and timing signals from the host system. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock. The host system may be an application processor of a smart phone or a tablet PC or a system-on-chip of a monitor or a TV.

[0076] The timing controller 22 generates control signals for controlling operation timings of the data driver 21 and the scan driver 30. The control signals may include a source control signal DCS for controlling operation timings of the data driver 21 and a scan control signal SCS for controlling operation timings of the scan driver 30.

[0077] The integrated driving circuit 20 may be disposed in a non-display area NDA disposed at one side of the display panel 10. The integrated driving circuit 20 may be formed as an integrated circuit (IC) and mounted on the display panel 10 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic welding method. However, the present invention is not limited thereto. For example, the integrated driving circuit 20 may be mounted on the circuit board 40 instead of on the display panel 10.

[0078] In addition, despite the Figure 2 2 shows that the integrated driving circuit 20 includes a data driver 21 and a timing controller 22, but the present invention is not limited thereto. The data driver 21 and the timing controller 22 may not be integrated into one integrated circuit, but may be formed as separate integrated circuits. In this case, the data driver 21 may be mounted on the display panel 10 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic welding method, and the timing controller 22 may be mounted on the circuit board 40.

[0079] The scan driver 30 receives a scan control signal SCS from the timing controller 22. The scan driver 30 generates a scan signal in response to the scan control signal SCS and supplies the scan signal to the scan lines S1 to Sn of the display panel 10. The scan driver 30 may include a plurality of transistors and may be formed in the non-display area NDA of the display panel 10. Alternatively, the scan driver 30 may be formed as an integrated circuit and, in this case, may be mounted on a gate flexible film attached to the other side of the display panel 10.

[0080] The circuit board 40 may be attached to a pad provided on one side edge of the display panel 10 using an anisotropic conductive film. Thus, the leads of the circuit board 40 may be electrically connected to the pad. The circuit board 40 may be a flexible printed circuit board, a printed circuit board, or a flexible film, such as a chip on a film. The circuit board 40 may be bent downward from the display panel 10. Thus, one side of the circuit board 40 may be attached to one side edge of the display panel 10, and the other side thereof may be provided below the display panel 10 to be connected to a system board on which a host system is mounted.

[0081] The power circuit 50 can generate a voltage required to drive the display panel 10 from the main power source provided by the system board, and provide the generated voltage to the display panel 10. For example, the power circuit 50 generates a high potential voltage VDD and a low potential voltage VSS for driving the light emitting element LD of the display panel 10 from the main power source, and provides the generated high potential voltage VDD and low potential voltage VSS to a high potential voltage line VDDL and a low potential voltage line VSSL. In addition, the power circuit 50 can generate and provide a driving voltage for driving the integrated driving circuit 20 and the scan driver 30 from the main power source.

[0082] Despite Figure 1 4. The power supply circuit 50 is shown as an integrated circuit and mounted on the circuit board 40, but the embodiments of the present invention are not limited thereto. For example, the power supply circuit 50 may be integrally formed with the integrated driving circuit 20.

[0083] Figure 4 It specifically shows Figure 1 For ease of explanation, Figure 4 Data pads DP1 to DPp (p is an integer of 2 or more), floating pads FP1 and FP2, power pads PP1 and PP2, floating lines FL1 and FL2, a low potential voltage line VSSL, data lines D1 to Dm, a first electrode 210, and a second electrode 220 are shown.

[0084] Reference Figure 4 , the data lines D1 to Dm, the first electrode 210 , the second electrode 220 , and the pixels PX may be arranged in the display area DA of the display panel 10 .

[0085] The data lines D1 to Dm may extend in the second direction (Y-axis direction). One side of each of the data lines D1 to Dm may be connected to the integrated driving circuit 20. Therefore, the data voltage of the integrated driving circuit 20 may be applied to the data lines D1 to Dm.

[0086] The first electrodes 210 may be spaced apart from each other by a predetermined distance in the first direction (X-axis direction). Therefore, the first electrodes 210 may not overlap with the data lines D1 to Dm. Among the first electrodes 210, the first electrode 210 disposed at the right edge of the display area DA may be connected to the first floating line FL1 in the non-display area NDA. Among the first electrodes 210, the first electrode 210 disposed at the left edge of the display area DA may be connected to the second floating line FL2 in the non-display area NDA.

[0087] The second electrode 220 may extend in the first direction (X-axis direction). Therefore, the second electrode 220 may overlap the data lines D1 to Dm. In addition, the second electrode 220 may be connected to the low potential voltage line VSSL in the non-display area NDA. Therefore, the low potential voltage VSS of the low potential voltage line VSSL may be applied to the second electrode 220.

[0088] Each of the pixels PX may include a first sub-pixel PX1 , a second sub-pixel PX2 , and a third sub-pixel PX3 .

[0089] The first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 of each of the pixels PX may be arranged in a region defined in a matrix form by the first electrode 210, the second electrode 220, and the data lines D1 to Dm. Figure 4 , each of the pixels PX includes three sub-pixels, but the present invention is not limited thereto. That is, each of the pixels PX may include four or more sub-pixels.

[0090] The first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 of each of the pixels PX may be arranged in the first direction (X-axis direction), but the present invention is not limited thereto. That is, the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 of each of the pixels PX may be arranged in the second direction (Y-axis direction), or may be arranged in a zigzag form or in various other forms.

[0091] The first subpixel PX1 may emit light of a first color, the second subpixel PX2 may emit light of a second color, and the third subpixel PX3 may emit light of a third color. The first color may be red, the second color may be green, and the third color may be blue, but the present invention is not limited thereto.

[0092] A pad unit PA, an integrated driving circuit 20, a first floating line FL1, a second floating line FL2 and a low potential voltage line VSSL may be arranged in a non-display area NDA of the display panel 10, wherein the pad unit PA includes data pads DP1 to DPp, floating pads FP1 and FP2 and power pads PP1 and PP2.

[0093] A pad unit PA including data pads DP1 to DPp, floating pads FP1 and FP2, and power pads PP1 and PP2 may be disposed at one side edge of the display panel 10, for example, at a lower side edge of the display panel 10. The data pads DP1 to DPp, the floating pads FP1 and FP2, and the power pads PP1 and PP2 may be disposed in parallel in a first direction (X-axis direction) in the pad unit PA.

[0094] The circuit board 40 may be disposed on the data pads DP1 to DPp, the floating pads FP1 and FP2, and the power pads PP1 and PP2 using an anisotropic conductive film. Therefore, the circuit board 40 may be electrically connected to the data pads DP1 to DPp, the floating pads FP1 and FP2, and the power pads PP1 and PP2.

[0095] The integrated driving circuit 20 may be connected to the data pads DP1 to DPp through connection lines. The integrated driving circuit 20 may receive the digital video data DATA and the timing signal through the data pads DP1 to DPp. The integrated driving circuit 20 may convert the digital video data DATA into an analog data voltage and provide the analog data voltage to the data lines D1 to Dm of the display panel 10.

[0096] The low potential voltage line VSSL may be connected to the first power pad PP1 and the second power pad PP2 of the pad unit PA. The low potential voltage line VSSL may extend in the second direction (Y-axis direction) in the non-display area NDA located at the left outer side and the right outer side of the display area DA. The low potential voltage line VSSL may be connected to the second electrode 220. Therefore, the low potential voltage VSS of the power circuit 50 may be applied to the second electrode 220 through the circuit board 40, the first power pad PP1, the second power pad PP2, and the low potential voltage line VSSL.

[0097] The first floating line FL1 may be connected to the first floating pad FP1 of the pad unit PA. The first floating line FL1 may extend in the second direction (Y-axis direction) in the non-display area NDA located at the right outer side of the display area DA. The first floating pad FP1 and the first floating line FL1 may be a dummy pad and a dummy line, respectively, to which no voltage is applied.

[0098] The second floating line FL2 may be connected to the second floating pad FP2 of the pad unit PA. The second floating line FL2 may extend in the second direction (Y-axis direction) in the non-display area NDA located at the left outer side of the display area DA. The second floating pad FP2 and the second floating line FL2 may be a dummy pad and a dummy line to which no voltage is applied, respectively.

[0099] On the other hand, in order to align the light emitting element 300 during the manufacturing process (see Figure 5 ), an electric field may be applied to the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 of each of the pixels PX. Specifically, the light emitting element 300 may be aligned by applying an electrophoretic force to the light emitting element 300 using dielectrophoresis during the manufacturing process. In order to align the light emitting element 300 using dielectrophoresis during the manufacturing process, a ground voltage is applied to the first electrode 210, and an AC voltage is applied to the second electrode 220.

[0100] However, by driving the thin film transistor during the manufacturing process, it is difficult to apply the ground voltage to the first electrode 210. Therefore, in the completed display device 1, the first electrodes 210 are arranged at predetermined intervals in the first direction (X-axis direction), but, during the manufacturing process, the first electrodes 210 may extend in the first direction (X-axis direction) without being disconnected. Therefore, during the manufacturing process, the first electrode 210 may be connected to the first floating line FL1 and the second floating line FL2. Therefore, the first electrode 210 may receive the ground voltage through the first floating line FL1 and the second floating line FL2. Therefore, by aligning the light emitting element 300 using dielectrophoresis and then disconnecting the first electrode 210 during the manufacturing process, the first electrodes 210 may be arranged to be spaced apart from each other at predetermined intervals in the first direction (X-axis direction). Reference will be made later Figure 8 Describe its details.

[0101] On the other hand, the first floating line FL1 and the second floating line FL2 are lines for applying a ground voltage during a manufacturing process, and a voltage may not be applied thereto in the completed display device 1. Alternatively, in order to prevent static electricity in the completed display device 1, a ground voltage may be applied to the first floating line FL1 and the second floating line FL2.

[0102] Figure 5 It specifically shows Figure 4 A plan view of pixels of a display area.

[0103] Reference Figure 5 , each of the pixels PX may include a first subpixel PX1, a second subpixel PX2, and a third subpixel PX3. The first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 of each of the pixels PX may be arranged in a matrix form in a region defined by a cross structure of a scan line Sk and data lines Dj, Dj+1, Dj+2, and Dj+3. The scan line Sk may extend in a first direction (X-axis direction), and the data lines Dj, Dj+1, Dj+2, and Dj+3 may extend in a second direction (Y-axis direction) intersecting the first direction (X-axis direction).

[0104] Each of the first, second, and third subpixels PX1, PX2, and PX3 may include a first electrode 210, a second electrode 220, and a plurality of light emitting elements 300. The first and second electrodes 210 and 220 may be electrically connected to the light emitting elements 300 and may receive a voltage to allow the light emitting elements 300 to emit light.

[0105] The first electrode 210 of any one sub-pixel may be spaced apart from the first electrode 210 of the sub-pixel adjacent thereto. For example, the first electrode 210 of the first sub-pixel PX1 may be spaced apart from the first electrode 210 of the second sub-pixel PX2 adjacent thereto. In addition, the first electrode 210 of the second sub-pixel PX2 may be spaced apart from the first electrode 210 of the third sub-pixel PX3 adjacent thereto. In addition, the first electrode 210 of the third sub-pixel PX3 may be spaced apart from the first electrode 210 of the first sub-pixel PX1 adjacent thereto.

[0106] On the contrary, the second electrode 220 of any one sub-pixel may be connected to the second electrode 220 of the sub-pixel adjacent thereto. For example, the second electrode 220 of the first sub-pixel PX1 may be connected to the second electrode 220 of the second sub-pixel PX2 adjacent thereto. In addition, the second electrode 220 of the second sub-pixel PX2 may be connected to the second electrode 220 of the third sub-pixel PX3 adjacent thereto. In addition, the second electrode 220 of the third sub-pixel PX3 may be connected to the second electrode 220 of the first sub-pixel PX1 adjacent thereto.

[0107] On the other hand, in order to align the light emitting element 300 during the manufacturing process, the first electrode 210 and the second electrode 220 may be used to apply an electric field to each of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3. Specifically, the light emitting element 300 may be aligned by applying an electrophoretic force to the light emitting element 300 using dielectrophoresis during the manufacturing process. In order to align the light emitting element 300 using dielectrophoresis during the manufacturing process, a ground voltage is applied to the first electrode 210, and an AC voltage is applied to the second electrode 220. In this case, a capacitance is formed by the electric field, thereby applying an electrophoretic force to the light emitting element 300.

[0108] The first electrode 210 may be an anode electrode connected to the second conductive semiconductor of the light emitting element 300, and the second electrode 220 may be a cathode electrode connected to the first conductive semiconductor of the light emitting element 300. The first conductive semiconductor of the light emitting element 300 may be an n-type semiconductor layer, and the second conductive semiconductor thereof may be a p-type semiconductor layer. However, the present invention is not limited thereto, and the first electrode 210 may be a cathode electrode, and the second electrode 220 may be an anode electrode.

[0109] The first electrode 210 may include a first electrode rod portion 210S extending in a first direction (X-axis direction) and at least one first electrode branch portion 210B branching from the first electrode rod portion 210S in a second direction (Y-axis direction). The second electrode 220 may include a second electrode rod portion 220S extending in a first direction (X-axis direction) and at least one second electrode branch portion 220B branching from the second electrode rod portion 220S in a second direction (Y-axis direction).

[0110] The first electrode rod portion 210S may be electrically connected to the thin film transistor 120 through the first electrode contact hole CNTD (see Figure 6 ). Therefore, the first electrode rod portion 210S may receive a predetermined driving voltage through the thin film transistor 120. The thin film transistor 120 connected to the first electrode rod portion 210S may be Figure 3 The driving transistor DT shown in FIG.

[0111] The second electrode rod portion 220S may be electrically connected to the low potential auxiliary wiring 161 (see FIG. Figure 6 ). Therefore, the second electrode rod portion 220S can receive the low potential voltage of the low potential auxiliary wiring 161. Figure 5 2 shows that the second electrode rod portion 220S can be electrically connected to the low potential auxiliary wiring 161 through the second electrode contact hole CNTS in each of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 of the pixel PX, but the present invention is not limited thereto. For example, the second electrode rod portion 220S can be electrically connected to the low potential auxiliary wiring 161 through the second electrode contact hole CNTS in any one of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 of the pixel PX. Alternatively, as Figure 4 As shown in FIG. 1 , since the second electrode rod portion 220S is connected to the low potential voltage line VSSL of the non-display area NDA, the second electrode rod portion 220S may not be connected to the low potential auxiliary wiring 161 through the second electrode contact hole CNTS. That is, the second electrode contact hole CNTS may be omitted.

[0112] The first electrode rod portion 210S of any one sub-pixel may be arranged in parallel with the first electrode rod portion 210S of the sub-pixel adjacent thereto in the first direction (X-axis direction). For example, the first electrode rod portion 210S of the first sub-pixel PX1 may be arranged in parallel with the first electrode rod portion 210S of the second sub-pixel PX2 in the first direction (X-axis direction), the first electrode rod portion 210S of the second sub-pixel PX2 may be arranged in parallel with the first electrode rod portion 210S of the third sub-pixel PX3 in the first direction (X-axis direction), and the first electrode rod portion 210S of the third sub-pixel PX3 may be arranged in parallel with the first electrode rod portion 210S of the first sub-pixel PX1 in the first direction (X-axis direction). This is because the first electrode rod portions 210S are connected as one and then disconnected by a laser process after aligning the light emitting element 300 during the manufacturing process.

[0113] The second electrode branch portion 220B may be disposed between the first electrode branch portions 210B. The first electrode branch portion 210B may be symmetrically disposed with respect to the second electrode branch portion 220B. Figure 5 2 shows that each of the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 of the pixel PX includes two first electrode branch portions 210B, but the present invention is not limited thereto. For example, each of the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 of the pixel PX may include three or more first electrode branch portions 210B.

[0114] In addition, despite the Figure 5 , each of the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 of the pixel PX includes one second electrode branch portion 220B, but the present invention is not limited thereto. For example, each of the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 of the pixel PX includes a plurality of second electrode branch portions 220B, and the first electrode branch portion 210B may be disposed between the second electrode branch portions 220B. That is, in each of the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 of the pixel PX, the first electrode branch portion 210B, the second electrode branch portion 220B, the first electrode branch portion 210B, and the second electrode branch portion 220B may be arranged in this order in the first direction (X-axis direction).

[0115] A plurality of light emitting elements 300 may be arranged between the first electrode branch portion 210B and the second electrode branch portion 220B. One end of at least one of the plurality of light emitting elements 300 may be arranged to overlap with the first electrode branch portion 210B, and the other end thereof may be arranged to overlap with the second electrode branch portion 220B. A second conductive semiconductor as a p-type semiconductor layer may be provided at one end of at least one of the plurality of light emitting elements 300, and a first conductive semiconductor as an n-type semiconductor layer may be provided at the other end thereof. However, the present invention is not limited thereto. For example, a first conductive semiconductor as an n-type semiconductor layer may be provided at one end of at least one of the plurality of light emitting elements 300, and a second conductive semiconductor as a p-type semiconductor layer may be provided at the other end thereof.

[0116] A plurality of light emitting elements 300 may be arranged substantially in parallel in a first direction (X-axis direction). A plurality of light emitting elements 300 may be spaced apart in a second direction (Y-axis direction). In this case, the intervals between the plurality of light emitting elements 300 may be different from each other. For example, some of the plurality of light emitting elements 300 may be adjacent to each other to form a group, while other light emitting elements 300 in the plurality of light emitting elements 300 may be adjacent to each other to form another group. All of the plurality of light emitting elements 300 may have a non-uniform density.

[0117] The connection electrodes 260 may be disposed on the first electrode branch portion 210B and the second electrode branch portion 220B, respectively. The connection electrodes 260 may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). The connection electrode 260 may be connected to one end of at least one of the light emitting elements 300. The connection electrode 260 may be connected to the first electrode 210 or the second electrode 220.

[0118] The connection electrode 260 may include a first connection electrode 261 disposed on the first electrode branch portion 210B and connected to one end of at least one of the light emitting elements 300, and a second connection electrode 262 disposed on the second electrode branch portion 220B and connected to the other end of at least one of the light emitting elements 300. Therefore, the first connection electrode 261 may electrically connect the plurality of light emitting elements 300 to the first electrode 210, and the second connection electrode 262 may electrically connect the plurality of light emitting elements 300 to the second electrode 220.

[0119] The width of the first connection electrode 261 in the first direction (X-axis direction) may be wider than the width of the first electrode branch portion 210B in the first direction (X-axis direction). In addition, the width of the second connection electrode 262 in the first direction (X-axis direction) may be wider than the width of the second electrode branch portion 220B in the first direction (X-axis direction).

[0120] Figure 6 is along Figure 5 Cross-sectional views taken along line II', line II-II' and line III-III'.

[0121] The display panel 10 may include a substrate 110, at least one thin film transistor disposed on the substrate 110, electrodes 210 and 220 disposed on the thin film transistor, and a light emitting element 300 disposed on the thin film transistor. The at least one thin film transistor may include a first thin film transistor 120 and a second thin film transistor 140. The first thin film transistor 120 may be Figure 3 The driving transistor DT shown in FIG. 1 and the second thin film transistor 140 may be Figure 3The scanning transistor ST shown in .

[0122] Each of the first thin film transistor 120 and the second thin film transistor 140 may include an active layer, a gate electrode, a source electrode, and a drain electrode. The first electrode 210 may be electrically connected to the drain electrode of the first thin film transistor 120. Although the first electrode 210 is shown to be directly connected to the first thin film transistor 120 in the drawings, the present invention is not limited thereto. The first electrode 210 and the first thin film transistor 120 may be electrically connected to each other through any conductive layer.

[0123] More specifically, the substrate 110 may be an insulating substrate. The substrate 110 may be made of an insulating material such as glass, quartz, or a polymer resin. Examples of polymer resins may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), and combinations thereof. The substrate 110 may be a rigid substrate, or may be a flexible substrate that can be bent, folded, curled, and the like.

[0124] The buffer layer 115 may be disposed on the substrate 110. The buffer layer 115 may prevent diffusion of impurity ions, may prevent penetration of moisture or external air, and may perform a surface planarization function. The buffer layer 115 may include silicon nitride, silicon oxide, or silicon oxynitride.

[0125] The semiconductor layer is disposed on the buffer layer 115. The semiconductor layer may include a first active layer 126 of the first thin film transistor 120, a second active layer 146 of the second thin film transistor 140, and an auxiliary layer 163. The semiconductor layer may include polycrystalline silicon, single crystal silicon, oxide semiconductor, or the like.

[0126] The first gate insulating layer 170 is disposed on the semiconductor layer. The first gate insulating layer 170 covers the semiconductor layer. The first gate insulating layer 170 may be used as a gate electrode insulating film of a thin film transistor. The first gate insulating layer 170 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These compounds may be used alone or in combination with each other.

[0127] The first conductive layer is disposed on the first gate insulating layer 170. The first conductive layer may include a first gate electrode 121 disposed on the first active layer 126 of the first thin film transistor 120, a second gate electrode 141 disposed on the second active layer 146 of the second thin film transistor 140, and a low potential auxiliary wiring 161 disposed on the auxiliary layer 163, and the first gate insulating layer 170 is located between the first active layer 126 and the first gate electrode 121, the second active layer 146 and the second gate electrode 141, and the auxiliary layer 163 and the low potential auxiliary wiring 161. The first conductive layer may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer may be a single-layer film or a multi-layer film.

[0128] The second gate insulating layer 180 is disposed on the first conductive layer. The second gate insulating layer 180 may be an interlayer insulating film. The second gate insulating layer 180 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide.

[0129] The second conductive layer is disposed on the second gate insulating layer 180. The second conductive layer includes a capacitor electrode 128 disposed on the first gate electrode 121, and the second gate insulating layer 180 is located between the first gate electrode 121 and the capacitor electrode 128. The capacitor electrode 128 may constitute a storage capacitor Cst together with the first gate electrode 121.

[0130] Like the first conductive layer, the second conductive layer may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu).

[0131] The interlayer insulating layer 190 is disposed on the second conductive layer. The interlayer insulating layer 190 may be an interlayer insulating film. In addition, the interlayer insulating layer 190 may perform a surface planarization function. The interlayer insulating layer 190 may include an organic insulating material, such as a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or a benzocyclobutene (BCB).

[0132] The third conductive layer is disposed on the interlayer insulating layer 190. The third conductive layer includes the first drain electrode 123 and the first source electrode 124 of the first thin film transistor 120, the second drain electrode 143 and the second source electrode 144 of the second thin film transistor 140, and the power supply electrode 162 disposed on the low potential auxiliary wiring 161.

[0133] Each of the first source electrode 124 and the first drain electrode 123 may be electrically connected to the first active layer 126 through a first contact hole 129 passing through the interlayer insulating layer 190 and the second gate insulating layer 180. Each of the second source electrode 144 and the second drain electrode 143 may be electrically connected to the second active layer 146 through a second contact hole 149 penetrating the interlayer insulating layer 190 and the second gate insulating layer 180. The power electrode 162 may be electrically connected to the low potential auxiliary wiring 161 through a third contact hole 169 passing through the interlayer insulating layer 190 and the second gate insulating layer 180.

[0134] The third conductive layer may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu). The third conductive layer may be a single layer film or a multilayer film. For example, the third conductive layer may be formed by a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo or Ti / Cu.

[0135] The insulating substrate layer 200 is disposed on the third conductive layer. The insulating substrate layer 200 may include an organic insulating material, such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin or benzocyclobutene (BCB). The surface of the insulating substrate layer 200 may be flat.

[0136] A plurality of partition walls 410 and 420 may be disposed on the insulating substrate layer 200. The plurality of partition walls 410 and 420 are disposed to be spaced apart from each other and face each other in each of the pixels PX, and the first electrode 210 and the second electrode 220 may be disposed on the partition walls 410 and 420 spaced apart from each other, for example, the first partition wall 410 and the second partition wall 420. Figure 6 A case where two first partition walls 410 and one second partition wall 420 are provided in one sub-pixel and the first electrode 210 and the second electrode 220 are provided to cover these partition walls 410 and 420 is shown. Figure 6 Only a cross-sectional view of a first partition wall 410 and a second partition wall 420 is shown, and the arrangement structure thereof can also be similarly applied to Figure 6Another first partition wall 410 not shown.

[0137] However, the number of partition walls 410 and 420 is not limited thereto. For example, a greater number of partition walls 410 and 420 may be provided in one pixel PX, and thus a greater number of first electrodes 210 and second electrodes 220 may be provided. The partition walls 410 and 420 may include at least one first partition wall 410 on which the first electrode 210 is provided and at least one second partition wall 420 on which the second electrode 220 is provided. In this case, the first partition wall 410 and the second partition wall 420 may be arranged to be spaced apart from each other and face each other, and a plurality of partition walls 410 and 420 may be alternately arranged in one direction. In some embodiments, two first partition walls 410 may be provided to be spaced apart from each other, and one second partition wall 420 may be provided between the spaced first partition walls 410.

[0138] Despite Figure 6 Although not shown in the figure, as described above, the first electrode 210 and the second electrode 220 may include electrode rod portions 210S and 220S and electrode branch portions 210B and 220B, respectively. That is, it can be understood that the first electrode branch portion 210B and the second electrode branch portion 220B are respectively arranged Figure 6 On the first partition wall 410 and the second partition wall 420.

[0139] The plurality of partition walls 410 and 420 may be made of substantially the same material and thus may be formed in one process. In this case, the partition walls 410 and 420 may form a grid pattern. The partition walls 410 and 420 may include polyimide (PI).

[0140] On the other hand, although not shown in the drawings, at least some of the plurality of partition walls 410 and 420 may be disposed at the boundaries between the pixels PX to distinguish them from each other. In this case, the electrodes 210 and 220 may not be disposed on the partition walls 410 and 420 disposed at the boundaries between the pixels PX. These partition walls may be arranged in a substantially grid pattern together with the first partition walls 410 and the second partition walls 420 described above. At least some of the plurality of partition walls 410 and 420 disposed at the boundaries between the pixels PX may be disposed to cover the electrode lines of the display panel 10. However, the present invention is not limited thereto, and partition walls other than the first partition walls 410 and the second partition walls 420 on which the electrodes 210 and 220 are disposed, respectively, may be disposed by performing an additional process after forming the electrodes 210 and 220.

[0141] At least some of the plurality of partition walls 410 and 420 may have a structure protruding from the insulating substrate layer 200. The partition walls 410 and 420 may protrude upward from the plane on which the light emitting element 300 is arranged, and at least some of the protruding portions may have an inclination. The partition walls 410 and 420 having a protruding structure with an inclination may reflect light incident on the reflective layers 211 and 221 disposed on the partition walls 410 and 420. Light directed from the light emitting element 300 to the reflective layers 211 and 221 may be reflected and then transmitted to the outside of the display panel 10, for example, above the partition walls 410 and 420. The shape of each of the partition walls 410 and 420 having a protruding structure is not particularly limited. Although Figure 6 It is shown that the partition walls 410 and 420 each have a shape in which a side surface is inclined, an upper surface is flat, and thus an edge is angled, but the present invention is not limited thereto. Each of the partition walls 410 and 420 may have a curved convex structure.

[0142] Reflective layers 211 and 221 may be disposed on the plurality of partition walls 410 and 420 .

[0143] The first reflective layer 211 covers the first partition wall 410, and a portion of the first reflective layer 211 is electrically connected to the first drain electrode 123 of the first thin film transistor 120 through the fourth contact hole 319_1 penetrating the insulating substrate layer 200. The second reflective layer 221 covers the second partition wall 420, and a portion of the second reflective layer 221 is electrically connected to the power electrode 162 through the fifth contact hole 319_2 penetrating the insulating substrate layer 200.

[0144] The first reflective layer 211 may be electrically connected to the first drain electrode 123 of the first thin film transistor 120 through the fourth contact hole 319_1 in the pixel PX. Therefore, the first thin film transistor 120 may be disposed in a region overlapping with the pixel PX. Figure 5 2 shows that the first reflective layer 211 is electrically connected to the first thin film transistor 120 through the first electrode contact hole CNTD disposed on the first electrode rod portion 210S. That is, the first electrode contact hole CNTD may be the fourth contact hole 319_1.

[0145] The second reflective layer 221 may also be electrically connected to the power electrode 162 through the fifth contact hole 319_2 in the pixel PX. Figure 6 FIG. 2 shows that the second reflective layer 221 is electrically connected to the power electrode 162 through the fifth contact hole 319_2 in one pixel PX. Figure 5 2 shows that the second electrode 220 of each pixel PX is electrically connected to the low potential auxiliary wiring 161 through a plurality of second electrode contact holes CNTS on the second electrode rod portion 220S. That is, the second electrode contact hole CNTS may be a fifth contact hole 319_2.

[0146] As mentioned above, in Figure 5 In the embodiment, the first electrode contact hole CNTD and the second electrode contact hole CNTS are respectively disposed on the first electrode rod portion 210S and the second electrode rod portion 220S. Figure 6 In the cross-sectional view of the display panel 10, the first electrode 210 and the second electrode 220 are electrically connected to the first thin film transistor 120 and the low potential auxiliary wiring 161 through the fourth contact hole 319_1 and the fifth contact hole 319_2, respectively, in the area separated from the partition walls 410 and 420 where the first electrode branch portion 210B and the second electrode branch portion 220B are set.

[0147] However, the present invention is not limited thereto. Figure 5 In the embodiment, the second electrode contact hole CNTS may even be disposed at different positions on the second electrode rod portion 220S, and in some cases, the second electrode contact hole CNTS may be disposed on the second electrode branch portion 220B. In addition, in some embodiments, the second reflective layer 221 may be connected to one second electrode contact hole CNTS or one fifth contact hole 319_2 in an area other than the pixel PX. As described above, the second electrode 220 of each pixel PX may be electrically connected to each other through the second electrode rod portion 220S, and thus may receive the same electrical signal.

[0148] In some embodiments, in the second electrode 220, the second electrode rod portion 220S may be electrically connected to the power electrode 162 through a second electrode contact hole CNTS located in the non-display area NDA outside the display panel 10. Figure 5 Unlike the display panel 10 of the present invention, even when the second electrode rod portion 220S is connected to the power electrode 162 through one contact hole, the second electrode rod portion 220S extends to adjacent pixels PX and is electrically connected, so that the same electrical signal can be applied to the second electrode branch portion 220B of each pixel PX. In the case of the second electrode 220 of the display panel 10, the position of the contact hole for receiving the electrical signal from the power electrode 162 may vary according to the structure of the display panel 10.

[0149] On the other hand, refer again Figure 5 and Figure 6 Each of the reflective layers 211 and 221 may include a high reflectivity material to reflect light emitted from the light emitting element 300. For example, each of the reflective layers 211 and 221 may include a material such as silver (Ag) or copper (Cu), but the present invention is not limited thereto.

[0150] The first electrode layer 212 and the second electrode layer 222 may be disposed on the first reflective layer 211 and the second reflective layer 221 , respectively.

[0151] The first electrode layer 212 is directly disposed on the first reflective layer 211. The first electrode layer 212 may have substantially the same pattern as the first reflective layer 211. The second electrode layer 222 is directly disposed on the second reflective layer 221 and is spaced apart from the first electrode layer 212. The second electrode layer 222 may have substantially the same pattern as the second reflective layer 221.

[0152] In an embodiment, the electrode layers 212 and 222 may respectively cover the underlying reflective layers 211 and 221. That is, the electrode layers 212 and 222 may be formed larger than the reflective layers 211 and 221 to cover the side surfaces of the electrode layers 212 and 222. However, the present invention is not limited thereto.

[0153] The first electrode layer 212 and the second electrode layer 222 can transmit the electrical signal transmitted to the first reflective layer 211 and the second reflective layer 221 connected to the first thin film transistor 120 or the power electrode 162 to the connecting electrodes 261 and 262, which will be described later. The electrode layers 212 and 222 may include a transparent conductive material. For example, the electrode layers 212 and 222 may include materials such as indium tin oxide (ITO), indium zinc oxide (IZO) or indium tin zinc oxide (ITZO), but the present invention is not limited to this. In some embodiments, the reflective layers 211 and 221 and the electrode layers 212 and 222 may have a structure in which a transparent conductive layer (such as ITO, IZO or ITZO) and a metal layer (such as silver or copper) are laminated into one or more layers. For example, the reflective layers 211 and 221 and the electrode layers 212 and 222 may have a laminated structure of ITO / silver (Ag) / ITO.

[0154] The first reflective layer 211 and the first electrode layer 212 disposed on the first partition wall 410 constitute the first electrode 210. The first electrode 210 may protrude to a region extending from both ends of the first partition wall 410, and thus the first electrode 210 may contact the insulating substrate layer 200 in the protruding region. The second reflective layer 221 and the second electrode layer 222 disposed on the second partition wall 420 constitute the second electrode 220. The second electrode 220 may protrude to a region extending from both ends of the second partition wall 420, and thus the second electrode 220 may contact the insulating substrate layer 200 in the protruding region.

[0155] The first electrode 210 and the second electrode 220 may be provided to cover the entire area of ​​the first partition wall 410 and the entire area of ​​the second partition wall 420, respectively. However, as described above, the first electrode 210 and the second electrode 220 are spaced apart from each other and face each other. As will be described later, the first insulating layer 510 may be provided between the first electrode 210 and the second electrode 220 spaced apart from each other, and the light emitting element 300 may be provided on the first insulating layer 510.

[0156] The first reflective layer 211 may receive a driving voltage from the first thin film transistor 120 , and the second reflective layer 221 may receive a power supply voltage from the low potential auxiliary wiring 161 , so that the first electrode 210 and the second electrode 220 receive the driving voltage and the power supply voltage, respectively.

[0157] Specifically, the first electrode 210 may be electrically connected to the first thin film transistor 120, and the second electrode 220 may be electrically connected to the low potential auxiliary wiring 161. Therefore, the first connection electrode 261 and the second connection electrode 262 provided on the first electrode 210 and the second electrode 220 may receive a driving voltage and a power supply voltage. The driving voltage and the power supply voltage are transmitted to the light emitting element 300, and a predetermined current flows through the light emitting element 300 to emit light.

[0158] The first insulating layer 510 is disposed on the first electrode 210 and the second electrode 220 to partially cover the first electrode 210 and the second electrode 220. The first insulating layer 510 may cover most of the upper surfaces of the first electrode 210 and the second electrode 220, and may partially expose the first electrode 210 and the second electrode 220. In addition, the first insulating layer 510 may also be disposed in a space between the first electrode 210 and the second electrode 220 spaced apart from each other. Figure 5 To explain, in a plan view, the first insulating layer 510 may be disposed to have an island shape or a linear shape along a space between the first electrode branch portion 210B and the second electrode branch portion 220B.

[0159] exist Figure 6 , the first insulating layer 510 is shown to be arranged in the space between one first electrode 210 (e.g., the first electrode branch portion 210B) and one second electrode 220 (e.g., the second electrode branch portion 220B). However, as described above, since the number of first electrodes 210 and the number of second electrodes 220 can be plural, the first insulating layer 510 can also be arranged between one first electrode 210 and another second electrode 220, or between one second electrode 220 and another first electrode 210.

[0160] The first insulating layer 510 may overlap a portion of the region on each of the electrodes 210 and 220 (e.g., a portion of the region protruding in the direction in which the first electrode 210 and the second electrode 220 face each other). The first insulating layer 510 may even be disposed in a region where the inclined side surfaces and the flat upper surfaces of the partition walls 410 and 420 overlap with the electrodes 210 and 220. In addition, the first insulating layer 510 may be disposed to partially cover the opposite sides of the first electrode 210 and the second electrode 220 facing each other. That is, the first insulating layer 510 may be disposed to expose only the central portions of the first electrode 210 and the second electrode 220.

[0161] The first insulating layer 510 may be disposed between the light emitting element 300 and the insulating substrate layer 200. The lower surface of the first insulating layer 510 may be in contact with the insulating substrate layer 200, and the light emitting element 300 may be disposed on the upper surface of the first insulating layer 510. In addition, the first insulating layer 510 may be in contact with the electrodes 210 and 220 at both sides thereof to electrically insulate them from each other.

[0162] For example, the first insulating layer 510 may cover each end of the first electrode 210 and the second electrode 220 that protrudes in the direction in which the first electrode 210 and the second electrode 220 face each other. A portion of the lower surface of the first insulating layer 510 may contact the insulating substrate layer 200, and a portion of the lower surface of the first insulating layer 510 and a side surface of the first insulating layer 510 may contact each of the electrodes 210 and 220. Therefore, the first insulating layer 510 may protect the region overlapping with the electrodes 210 and 220 and electrically insulate them from each other. In addition, the first insulating layer 510 may prevent the first conductive semiconductor 310 (see Figure 7 ) and a second conductive semiconductor 320 (see Figure 7 ) is in direct contact with other substrates to prevent damage to the light emitting element 300.

[0163] However, the present invention is not limited thereto. In some embodiments, the first insulating layer 510 may be provided only in a region overlapping the inclined side surfaces of the partition walls 410 and 420 among the regions on the first electrode 210 and the second electrode 220. In this case, the lower surface of the first insulating layer 510 terminates at the inclined side surfaces of the partition walls 410 and 420, and each of the electrodes 210 and 220 provided on some of the inclined side surfaces of the partition walls 410 and 420 may be exposed to contact the connection electrode 260.

[0164] The first insulating layer 510 may be provided to expose both ends of the light emitting element 300. Therefore, the connection electrode 260 may contact the exposed upper surface of each of the electrodes 210 and 220 and both ends of the light emitting element 300, and the connection electrode 260 may transmit an electrical signal applied to the first electrode 210 and the second electrode 220 to the light emitting element 300.

[0165] The lower surface of the first insulating layer 510 may be in contact with the electrodes 210 and 220 to protect and insulate the electrodes 210 and 220 from direct contact with each other. In addition, the upper surface of the first insulating layer 510 may be partially in contact with the light emitting element 300, and the light emitting element 300 may be prevented from directly contacting the electrodes 210 and 220.

[0166] Figure 7 It specifically shows Figure 6 A three-dimensional diagram of a light-emitting element.

[0167] Reference Figure 7 , the light emitting element 300 may include a plurality of conductive semiconductors 310 and 320, an element active layer 330, an electrode material layer 370, and an insulating material film 380. The electrical signal received from the first electrode 210 and the second electrode 220 may be transmitted to the element active layer 330 through the plurality of conductive semiconductors 310 and 320 to emit light.

[0168] Specifically, the light emitting element 300 may include a rod-shaped semiconductor core including a first conductive semiconductor 310, a second conductive semiconductor 320, an element active layer 330 disposed between the first conductive semiconductor 310 and the second conductive semiconductor 320, and an electrode material layer 370 disposed on the second conductive semiconductor 320, and an insulating material film 380 disposed around the outer peripheral surface of the semiconductor core. Figure 7 3 shows that the light emitting element 300 has a structure in which a first conductive semiconductor 310, an element active layer 330, a second conductive semiconductor 320, and an electrode material layer 370 of a semiconductor core are sequentially stacked in the length direction, but the present invention is not limited thereto. The electrode material layer 370 may be omitted, and in some embodiments, the electrode material layer 370 may be disposed on at least one of the two side surfaces of the first conductive semiconductor 310 and the second conductive semiconductor 320. Hereinafter, the structure of the light emitting element 300 will be described as an example. Figure 7 The light emitting element 300 is shown in FIG. 1 , and it is apparent that the description of the light emitting element 300 to be described later can be equally applied to the case where the light emitting element 300 also has another structure.

[0169] The first conductive semiconductor 310 may be an n-type semiconductor layer. For example, when the light emitting element 300 emits light in a blue wavelength band, the first conductive semiconductor 310 may be a semiconductor layer having the formula In xAl y Ga 1-x-y The first conductive semiconductor 310 may be a semiconductor material of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the semiconductor material may be at least one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type semiconductor. The first conductive semiconductor 310 may be doped with a first conductive dopant, and for example, the first conductive dopant may be Si, Ge, Sn, etc. The length of the first conductive semiconductor 310 may be in the range of 1.5 μm to 5 μm, but is not limited thereto.

[0170] The second conductive semiconductor 320 may be a p-type semiconductor layer. For example, when the light emitting element 300 emits light in a blue wavelength band, the second conductive semiconductor 320 may be a semiconductor layer having a formula In x Al y Ga 1-x-y The second conductive semiconductor 320 may be a semiconductor material of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the semiconductor material may be at least one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type semiconductor. The second conductive semiconductor 320 may be doped with a second conductive dopant, and for example, the second conductive dopant may be Mg, Zn, Ca, Se, Ba, etc. The length of the second conductive semiconductor 320 may be in the range of 0.08 μm to 0.25 μm, but is not limited thereto.

[0171] The element active layer 330 may be disposed between the first conductive semiconductor 310 and the second conductive semiconductor 320, and may include a material having a single quantum well structure or a multi-quantum well structure. When the element active layer 330 includes a material having a multi-quantum well structure, the multi-quantum well structure may be a structure in which a plurality of quantum layers and a plurality of well layers are alternately stacked. The element active layer 330 may emit light by coupling electron-hole pairs according to an electrical signal applied through the first conductive semiconductor 310 and the second conductive semiconductor 320. For example, when the element active layer 330 emits light in a blue wavelength band, it may include a material such as AlGaN or AlInGaN. In particular, when the element active layer 330 has a multi-quantum well structure in which a plurality of quantum layers and a plurality of well layers are alternately stacked, the quantum layer may include a material such as AlGaN or AlInGaN, and the well layer may include a material such as GaN or AlGaN. However, the present invention is not limited thereto. The element active layer 330 may have a structure in which a semiconductor material having a high band gap energy and a semiconductor material having a low band gap energy are alternately stacked, and may include other III-V semiconductor materials according to the wavelength band of the emitted light. Therefore, the light emitted from the element active layer 330 is not limited to the light of the blue wavelength band, and in some cases, the element active layer 330 may emit light of the red wavelength band or the green wavelength band. The length of the element active layer 330 may be in the range of 0.05 μm to 0.25 μm, but is not limited thereto.

[0172] Light emitted from the element active layer 330 may be emitted not only to the outer surface of the light emitting element 300 in the length direction but also to the outer peripheral surface of the light emitting element 300. That is, the direction of light emitted from the element active layer 330 is not limited to one direction.

[0173] The electrode material layer 370 may be an ohmic connection electrode. However, the present invention is not limited thereto, and the electrode material layer 370 may be a Schottky connection electrode. The electrode material layer 370 may include a conductive metal. For example, the electrode material layer 370 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), and silver (Ag). The electrode material layer 370 may include the same material, and may also include different materials. However, the present invention is not limited thereto.

[0174] The insulating material film 380 is provided to surround the outer peripheral surface of the semiconductor core. Specifically, the insulating material film 380 may be formed outside the first conductive semiconductor 310, the second conductive semiconductor 320, the element active layer 330, and the electrode material layer 370, and may perform the function of protecting these components. For example, the insulating material film 380 is formed to surround the side surface of the component, and thus may not be formed at both ends of the light emitting element 300 in the length direction, for example, may not be formed at both ends where the first conductive semiconductor 310 and the electrode material layer 370 are provided. However, the present invention is not limited thereto.

[0175] Despite Figure 7 As shown in FIG. 3 , the insulating material film 380 may extend in the length direction to cover the first conductive semiconductor 310 and the electrode material layer 370, for example, Figure 7 The insulating material film 380 may cover only the first conductive semiconductor 310, the element active layer 330 and the second conductive semiconductor 320, or may cover only a portion of the electrode material layer 370 to expose a portion of the outer surface of the electrode material layer 370.

[0176] The length of the insulating material film 380 may be in the range of 0.5 μm to 1.5 μm, but is not limited thereto.

[0177] The insulating material film 380 may play a role in protecting the first conductive semiconductor 310, the second conductive semiconductor 320, the element active layer 330 and the electrode material layer 370. The insulating material film 380 may include a material having insulating properties, such as silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN) or aluminum oxide (Al 2 O 3 ). Therefore, an electrical short circuit that may occur when the element active layer 330 directly contacts the first electrode 210 or the second electrode 220 can be prevented. In addition, since the insulating material film 380 includes the element active layer 330 and protects the outer peripheral surface of the light emitting element 300, a decrease in light emitting efficiency can be prevented.

[0178] Figure 8 is a flowchart illustrating a method of manufacturing a display device according to an embodiment. Figure 9a to Figure 9g is a plan view of a pixel of a display area for explaining a method of manufacturing a display device according to an embodiment. Figure 10a to Figure 10g is a cross-sectional view taken along line II-II′ for explaining a method of manufacturing a display device according to an embodiment.

[0179] In the following, reference will be made to Figure 8, Figure 9a to Figure 9g ,as well as Figure 10a to Figure 10g A method of manufacturing a display device according to an embodiment is described in detail.

[0180] exist Figure 10a to Figure 10g In the figure, for the convenience of explanation, only the upper portion of the insulating substrate layer 200 is shown. Figure 10a to Figure 10g In the figure, the thin film transistors 120 and 140, the low potential auxiliary wiring 161, and the auxiliary layer 163 will not be shown.

[0181] First, refer to Figure 9a and Fig.10a , forming a first partition wall 410 and a second partition wall 420 on the insulating substrate layer 200, forming a first electrode 210 and a second electrode 220 on the first partition wall 410 and the second partition wall 420, and forming a first insulating material layer 510' on the first electrode 210 and the second electrode 220 Figure 8 S101).

[0182] Specifically, the first partition wall 410 and the second partition wall 420 are formed on the insulating substrate layer 200. The first partition wall 410 and the second partition wall 420 may be spaced apart from each other. The first partition wall 410 and the second partition wall 420 may be formed of an organic material such as polyimide (PI). The first partition wall 410 and the second partition wall 420 may be formed by patterning the organic material through a mask process.

[0183] Then, the first electrode 210 is formed on the first partition wall 410, and the second electrode 220 is formed on the second partition wall 420. Each of the first electrodes 210 may include a first reflective layer 211 and a first electrode layer 212. Each of the second electrodes 220 may include a second reflective layer 221 and a second electrode layer 222. Each of the first reflective layer 211 and the second reflective layer 221 may include a material such as silver (Ag) or copper (Cu). Each of the first electrode layer 212 and the second electrode layer 222 may be a transparent conductive layer including ITO, IZO or ITZO. The first reflective layer 211, the second reflective layer 221, the first electrode layer 212 and the second electrode layer 222 may be formed by patterning a metal layer through a mask process.

[0184] In this case, the first electrode 210 may extend in the first direction (X-axis direction) without being disconnected. Therefore, the first electrode 210 of the first subpixel PX1 may be connected to the first electrode 210 of the second subpixel PX2 adjacent thereto, the first electrode 210 of the second subpixel PX2 may be connected to the first electrode 210 of the third subpixel PX3 adjacent thereto, and the first electrode 210 of the third subpixel PX3 may be connected to the first electrode 210 of the first subpixel PX1 adjacent thereto. Therefore, as Figure 4 As shown in FIG. 1 , the first electrode 210 may be connected to the first floating line FL1 and the second floating line FL2 of the non-display area NDA. Therefore, in a process of aligning the light emitting element 300 (to be described later), the first electrode 210 may receive a ground voltage through the first floating line FL1 and the second floating line FL2 of the non-display area NDA.

[0185] Then, a first insulating material layer 510' is formed to cover the first electrode 210 and the second electrode 220. The first insulating material layer 510' may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first insulating material layer 510' may be formed as the first insulating layer 510 by aligning the light emitting element 300 and then patterning the first insulating material layer 510' in a process to be described later.

[0186] Second, refer to Figure 9b and Fig.10b , a coating solution S containing the light emitting element 300 is applied to the first insulating material layer 510' in the first sub-pixel PX1, the second sub-pixel PX2 and the third sub-pixel PX3 of each of the pixels PX ( Figure 8 S102).

[0187] like Figure 9b and Fig.10b As shown in , the light emitting elements 300 may be arranged in the coating liquid S irregularly and randomly.

[0188] The step of applying the coating liquid S may be performed using various methods such as inkjet printing, inkjet injection, slit dye coating, and slit dye printing. However, the present invention is not limited thereto.

[0189] Third, reference Fig.9c and Fig.10c , an electric field E is formed between the first electrode 210 and the second electrode 220 adjacent to each other to align the light emitting element 300 ( Figure 8 S103).

[0190] Specifically, since the first electrode 210 is connected to the first floating line FL1 and the second floating line FL2 without being disconnected, the first electrode 210 may receive the ground voltage through the first floating line FL1 and the second floating line FL2. Figure 4 As shown in FIG. 2 , the second electrode 220 is connected to the low potential voltage line VSSL, so the second electrode 220 can receive the AC voltage through the low potential voltage line VSSL. When the ground voltage is applied to the first electrode 210 and the AC voltage is applied to the second electrode 220, an electric field E is formed between the first electrode 210 and the second electrode 220. In this case, as Fig.10cAs shown in FIG. 1 , the light emitting element 300 may receive an electrophoretic force through the electric field E, so that the light emitting element 300 may be aligned in a first direction (X-axis direction) between the first electrode 210 and the second electrode 220. Fig.13 Details of a method of aligning the light emitting element 300 are described.

[0191] On the other hand, an electric field E is formed between the first electrode 210 and the second electrode 220 adjacent to each other to align the light emitting element 300, and then the coating liquid S containing the light emitting element 300 may be dried. When the coating liquid S is dried, when the solution molecules of the coating liquid S are first volatilized in an arbitrary region without being uniformly volatilized over the entire region, a hydraulic force may be generated in the coating liquid S. In this case, the position of the light emitting element 300 may be moved by the hydraulic force. Therefore, it is preferable to perform the process of drying the coating liquid S while maintaining the alignment of the light emitting element 300.

[0192] Fourth, refer to Figure 9d and Fig.10d , aligning the light emitting element 300 between the first electrode 210 and the second electrode 220, and then volatilizing and removing the coating liquid S ( Figure 8 S104).

[0193] Then, a second insulating layer 530 may be formed on the light emitting element 300. The second insulating layer 530 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0194] Fifth, refer to Fig.9e and Fig.10e , forming a first connection electrode 261 ( Figure 8 S105).

[0195] Specifically, the first insulating material layer 510' is partially etched to form the first insulating layer 510. The first insulating layer 510 may be formed to expose the first electrode layer 212 of the first electrode 210 and the second electrode layer 222 of the second electrode 220.

[0196] Then, the first connection electrodes 261 overlapping the first partition wall 410 are formed on the first insulating layer 510. Each of the first connection electrodes 261 may be connected to the first electrode layer 212 of the first electrode 210 that is exposed without being covered by the first insulating layer 510. In addition, each of the first connection electrodes 261 may be connected to one end of the light emitting element 300. Therefore, each of the first connection electrodes 261 may be connected to the first conductive semiconductor at one end of the light emitting element 300.

[0197] Then, a third insulating layer 540 may be formed (see Fig.10f) to cover the first connection electrode 261 and the second insulating layer 530. The third insulating layer 540 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0198] Sixth, reference Figure 9f and Fig.10f , forming a second connection electrode 262 ( Figure 8 S106).

[0199] Specifically, the second connection electrodes 262 overlapping the second partition wall 420 are formed on the first insulating layer 510. Each of the second connection electrodes 262 may be connected to the second electrode layer 222 of the second electrode 220 that is exposed without being covered by the first insulating layer 510. In addition, each of the second connection electrodes 262 may be connected to the other end of the light emitting element 300. Therefore, each of the second connection electrodes 262 may be connected to the second conductive semiconductor at the other end of the light emitting element 300.

[0200] Then, a fourth insulating layer 550 may be formed (see Figure 10g ) to cover the second connection electrode 262 and the third insulating layer 540. The fourth insulating layer 550 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0201] Seventh, reference Figure 9g and Figure 10g , disconnect the first electrodes 210 connected to each other ( Figure 8 S107).

[0202] Specifically, in Figures 9a to 9f and Figures 10a to 10f During the manufacturing process of the first electrode 210, the light emitting element 300 is aligned by forming an electric field E between the first electrode 210 and the second electrode 220 using a dielectrophoresis method. For this purpose, the first electrode 210 should be connected to the first floating line FL1 and the second floating line FL2 formed in the non-display area NDA to receive a ground voltage. Therefore, the first electrode 210 can extend in the first direction (X-axis direction) without being disconnected.

[0203] However, the first electrode 210 of each of the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 of each of the pixels PX is connected to the thin film transistor 120 through the first electrode contact hole CNTD to receive a predetermined driving voltage through the thin film transistor 120. Therefore, in order to drive the first subpixel PX1, the second subpixel PX2, and the third subpixel PX3 of each of the pixels PX, the first electrodes 210 should not be connected to each other. Figures 9a to 9f and Figures 10a to 10fAfter the manufacturing process is completed, the first electrodes 210 may be disconnected so as to be spaced apart from each other by a predetermined distance in the first direction (X-axis direction).

[0204] The first electrode 210 of the first subpixel PX1 of each of the pixels PX may be disconnected from the first electrode 210 of the second subpixel PX2 adjacent thereto, the first electrode 210 of the second subpixel PX2 may be disconnected from the first electrode 210 of the third subpixel PX3 adjacent thereto, and the first electrode 210 of the third subpixel PX3 may be disconnected from the first electrode 210 of the first subpixel PX1 adjacent thereto. In addition, the first electrode 210 may be disconnected so as not to overlap with the data lines Dj, Dj+1, Dj+2, and Dj+3. The first electrode 210 may be disconnected by a laser process.

[0205] according to Figure 8 According to the embodiment shown in FIG. 1 , during the manufacturing process of the display panel 10 , a magnetic field may be formed between the first electrode 210 and the second electrode 220 , thereby aligning the light emitting element 300 between the first electrode 210 and the second electrode 220 in the first direction (X-axis direction).

[0206] On the other hand, in the case where the first electrode 210 is an anode electrode and the second electrode 220 is a cathode electrode, current may flow through the light emitting element 300 only when the first conductive semiconductor (p) of the light emitting element 300 is electrically connected to the first electrode 210 and the second conductive semiconductor (n) is electrically connected to the second electrode 220. That is, in the case of a forward alignment in which the first conductive semiconductor (p) is disposed adjacent to the first electrode 210 and the second conductive semiconductor (n) is disposed adjacent to the second electrode 220, the light emitting element 300 may emit light. In the case of a reverse alignment in which the first conductive semiconductor (p) is disposed adjacent to the second electrode 220 and the second conductive semiconductor (n) is disposed adjacent to the first electrode 210, the light emitting element 300 may not emit light.

[0207] However, when Fig.11 When an AC voltage having a high frequency sine wave is applied to the second electrode 220 as shown in FIG, some of the light emitting elements 300, such as the first light emitting element LD1, the third light emitting element LD3, the fifth light emitting element LD5, the sixth light emitting element LD6, and the eighth light emitting element LD8, are aligned in the forward direction, while others of the light emitting elements 300, such as the second light emitting element LD2, the fourth light emitting element LD4, the seventh light emitting element LD7, the ninth light emitting element LD9, and the tenth light emitting element LD10, are aligned in the reverse direction. In this case, as shown in FIG. Fig.12As shown in FIG. 3 , only the first light emitting element LD1, the third light emitting element LD3, the fifth light emitting element LD5, the sixth light emitting element LD6 and the eighth light emitting element LD8 emit light, while the second light emitting element LD2, the fourth light emitting element LD4, the seventh light emitting element LD7, the ninth light emitting element LD9 and the tenth light emitting element LD10 do not emit light. Therefore, the brightness of the sub-pixel may be reduced. Therefore, a method for improving the alignment accuracy of the light emitting element 300 is required.

[0208] In the following, reference will be made to Fig.13 A method of aligning the light emitting element 300 that can improve alignment accuracy is described in detail.

[0209] Fig.13 is a flow chart illustrating a method of aligning a light emitting element according to an embodiment. Fig.13 Shown in Figure 8 A method for improving the alignment accuracy of the light emitting element 300 in step S103.

[0210] Reference Fig.13 First, a first AC voltage having an asymmetric waveform is applied to the second electrode 220, and a ground voltage is applied to the first electrode 210 ( Fig.13 S201).

[0211] like Fig.17a and Figures 19a to 19n As shown in FIG. 1 , when the first AC voltage having an asymmetric waveform is applied to the second electrode 220 and the ground voltage is applied to the first electrode 210, as shown in FIG. Fig.14 As shown in , the light emitting element 300 may be arranged to be inclined toward the first electrode 210. Fig.17a and Figures 19a to 19n Details of the first AC voltage having an asymmetrical waveform are described.

[0212] like Fig.14 As shown in , when the light emitting element 300 is deflected toward the first electrode 210, the first conductive semiconductor (p) of the light emitting element 300 may overlap with the first electrode branch portion 210B, while the second conductive semiconductor (n) thereof may not overlap with the second electrode branch portion 220B. The first conductive semiconductor (p) of the light emitting element 300 may be arranged toward the first electrode 210. Hereinafter, the case where the first conductive semiconductor (p) of the light emitting element 300 is arranged toward the first electrode 210 will be described in detail.

[0213] Specifically, when the light emitting element 300 includes a first conductive semiconductor (p) made of GaN doped with a p-type dopant and a second conductive semiconductor (n) made of GaN doped with an n-type dopant, as shown in FIG. Fig.15As shown in , holes of GaN doped with p-type dopant (hole-rich) migrate to GaN doped with n-type dopant, and electrons of GaN doped with n-type dopant (electron-rich) migrate to GaN doped with p-type dopant. Therefore, a permanent dipole moment can be generated in the direction from GaN doped with p-type dopant to GaN doped with n-type dopant. That is, light emitting element 300 can be defined as a particle having polarity in the length direction.

[0214] On the other hand, when Fig.10c When an electric field is formed between the first electrode 210 and the second electrode 220 as shown in FIG. 1 , an equivalent circuit diagram of the first electrode 210, the second electrode 220 and the coating liquid S can be Fig.16 In this case, the AC voltage V(t) applied to the second electrode 220 may be represented by Formula 1.

[0215] [Formula 1]

[0216]

[0217] In Formula 1, V(t) represents the AC voltage applied to the second electrode 220, R represents the resistance of the coating liquid S, i(t) represents the current flowing through the coating liquid S, and q(t) represents the charge induced in the first insulating material layer 510'. C of Formula 1 1 It is composed of formula 2.

[0218] [Formula 2]

[0219] C I =ε d ε o / d1

[0220] In formula 2, ε d represents the relative dielectric constant of the first insulating material layer 510′, ε o denotes a dielectric constant in a vacuum, and d1 denotes a thickness of the first insulating material layer 510 ′.

[0221] When i(t)=dq(t) / dt is substituted into Formula 1 and then Formula 1 is rearranged, Formula 3 can be derived.

[0222] [Formula 3]

[0223]

[0224] When the electric field is calculated from Formula 3, Formula 4 can be derived.

[0225] [Formula 4]

[0226]

[0227] By Fig.17a The electric field obtained by substituting the asymmetric waveform (ie, sawtooth waveform) shown in FIG. 4 into Formula 4 has a different electric field from that of the sawtooth waveform. Fig.17b In this case, if Fig.17b As shown in , the electric field can be an asymmetric electric field, in which the sum of the area of ​​the positive polarity and the area of ​​the negative polarity is not 0. That is, Fig.17b As shown in , the electric field generated by the first AC voltage may be an asymmetric electric field in which the negative polarity is dominant. Fig.17b 2 shows that the electric field generated by the first AC voltage is an asymmetric electric field in which the negative polarity is dominant, but the present invention is not limited thereto. That is, the electric field generated by the first AC voltage may be an asymmetric electric field in which the positive polarity is dominant.

[0228] The asymmetric electric field can be used to Fig.15 The permanent dipole moment of the light emitting element 300 described above has an influence. Therefore, the first conductive semiconductor (p) of the light emitting element 300 may be arranged toward the first electrode 210.

[0229] On the other hand, the frequency of the first AC voltage may be 1 Hz to 1 kHz, and preferably 10 Hz to 500 Hz. When the frequency of the first AC voltage exceeds 1 kHz, the period of the first AC voltage is shortened, so that even if Fig.17a As shown in FIG. , it is difficult to form a first AC voltage having an asymmetric waveform. Fig.17b The asymmetric electric field shown in .

[0230] Second, a second AC voltage having a symmetrical waveform is applied to the second electrode 220, and a ground voltage is applied to the first electrode 210 ( Fig.13 S202).

[0231] When the first AC voltage having an asymmetric waveform is applied to the second electrode 220, the first conductive semiconductor (p) of the light emitting element 300 may be arranged toward the first electrode 210, but the light emitting element 300 may be deflected toward the first electrode 210. However, in this case, the second conductive semiconductor (n) of the light emitting element 300 may be spaced apart from the second electrode branch portion 220B, and thus may not be connected to the second connection electrode 262 during a process of forming the second connection electrode 262 to be described later. Therefore, in order to stably connect the second conductive semiconductor (n) of the light emitting element 300 to the second electrode branch portion 220B, it is necessary to align the light emitting element 300 toward the center between the first electrode branch portion 201B and the second electrode branch portion 220B.

[0232] When the second AC voltage having a symmetrical waveform is applied to the second electrode 220, the electric field formed between the first electrode 210 and the second electrode 220 may be a symmetrical electric field in which the sum of the area of ​​the positive polarity and the area of ​​the negative polarity is 0. In this case, Fig.18 As shown, the light emitting element 300 is no longer tilted toward the first electrode 210 and can be aligned toward the center between the first electrode branch portion 210B and the second electrode branch portion 220B. Therefore, the second conductive semiconductor (n) of the light emitting element 300 can be electrically connected to the second electrode branch portion 220B.

[0233] On the other hand, preferably, the frequency of the second AC voltage is higher than the frequency of the first AC voltage. For example, the frequency of the second AC voltage may be 1 kHz to 100 kHz, and preferably 10 kHz to 100 kHz. As the frequency of the second AC voltage increases, the electric field formed between the first electrode 210 and the second electrode 220 also increases, and thus the light emitting element 300 can be stably aligned toward the center between the first electrode branch portion 210B and the second electrode branch portion 220B.

[0234] according to Fig.13 In the embodiment shown in , since an asymmetric magnetic field can be formed by applying a first AC voltage having an asymmetric waveform to the second electrode 220, the light emitting element 300 can be deflected toward the first electrode 210, so that the first conductive semiconductor (p) of the light emitting element 300 is arranged toward the first electrode 210. Then, since a symmetric magnetic field can be formed by applying a second AC voltage having a symmetric waveform to the second electrode 220, the light emitting element 300 deflected toward the first electrode 210 can be aligned toward the center between the first electrode branch portion 210B and the second electrode branch portion 220B. Therefore, the alignment accuracy of the light emitting element can be improved.

[0235] On the other hand, Fig.13 In the embodiment shown in , the process of applying the second AC voltage having a symmetrical waveform to the second electrode 220 (S202) may be omitted. In this case, as shown in FIG. Fig.14 As shown in , the light emitting element 300 may be tilted toward the first electrode 210 , but when the second connection electrode 262 is formed to move toward the first electrode branch portion 210B at the tilting degree of the first electrode 210 , the second conductive semiconductor (n) of the light emitting element 300 may be connected to the second connection electrode 262 .

[0236] Figures 19a to 19n is a waveform diagram showing an example of a first AC voltage having an asymmetrical waveform.

[0237] exist Figures 19a to 19n In , the X-axis represents time and the Y-axis represents voltage level. Figures 19a to 19n 2 shows that the first AC voltage has a highest level voltage HV and a lowest level voltage LV. In this case, the highest level voltage HV is 20V, and the lowest level voltage LV is -20V, but the present invention is not limited thereto.

[0238] like Figures 19a to 19n As shown in , the first AC voltage having an asymmetric waveform is an AC voltage in which the voltage waveform of the positive polarity region of the first AC voltage and the voltage waveform of the negative polarity region of the first AC voltage are asymmetric left-right. Figures 19a to 19n , the positive polarity region of the first AC voltage indicates a region where the first AC voltage is 0V or more, and the negative polarity region of the first AC voltage indicates a region where the first AC voltage is less than 0V.

[0239] like Fig.19a As shown in , the first AC voltage may have a waveform in which the first AC voltage directly rises from the lowest level voltage LV to the highest level voltage HV during one period T11 and then drops from the highest level voltage HV to the lowest level voltage LV with a first straight line slope. Fig.19a The waveform of the first AC voltage shown in can be called a sawtooth waveform.

[0240] like Fig.19b As shown in , the first AC voltage may have a waveform in which the first AC voltage rises from the lowest level voltage LV to the highest level voltage HV with a second straight line slope during one period T12 and then directly drops from the highest level voltage HV to the lowest level voltage LV. Fig.19b The waveform of the first AC voltage shown in can be referred to as a lamp waveform.

[0241] like Fig.19c As shown in , the first AC voltage can have a waveform in which the first AC voltage directly rises from the lowest level voltage LV to the highest level voltage HV during a first period T131 of a period T13 and then drops from the highest level voltage HV to the lowest level voltage LV at a third straight line slope, and maintains the lowest level voltage LV during a second period T132 of a period T13.

[0242] like Fig.19dAs shown in , the first AC voltage may have a waveform in which the first AC voltage rises directly from the lowest level voltage LV to the highest level voltage HV during a first period T141 of a period T14 and then drops from the highest level voltage HV to the lowest level voltage LV at a fourth straight line slope, and then rises directly from the lowest level voltage LV to the highest level voltage HV during a second period T142 of a period T14 and then drops from the highest level voltage HV to the lowest level voltage LV at a fifth straight line slope, wherein the absolute magnitude of the fifth straight line slope is smaller than the absolute magnitude of the fourth straight line slope. In this case, the first period T141 may be shorter than the second period T142.

[0243] like Fig.19e As shown in , the first AC voltage may have a waveform in which the first AC voltage rises directly from the lowest level voltage LV to the highest level voltage HV during one period T15 and then drops from the highest level voltage HV to the lowest level voltage LV at a first curved slope. The absolute magnitude of the first curved slope may decrease from the highest level voltage HV to the lowest level voltage LV.

[0244] like Fig.19f As shown in , the first AC voltage may have a waveform in which the first AC voltage rises from the lowest level voltage LV to the highest level voltage HV with a second curved slope during one period T16 and then directly drops from the highest level voltage HV to the lowest level voltage LV. The absolute magnitude of the second curved slope may increase from the lowest level voltage LV to the highest level voltage HV.

[0245] like Figure 19g As shown in FIG. 1 , the first AC voltage may have a waveform in which the first AC voltage rises directly from the lowest level voltage LV to the highest level voltage HV during a first period T171 of one period T17 and then drops from the highest level voltage HV to the lowest level voltage LV at a third curved slope, and then maintains the lowest level voltage LV during a second period T172 of one period T17. The absolute magnitude of the third curved slope may decrease from the highest level voltage HV toward the lowest level voltage LV.

[0246] like Figure 19h As shown in FIG. 1 , the first AC voltage may have a waveform in which the first AC voltage rises directly from the lowest level voltage LV to the highest level voltage HV during one period T18, and then drops from the highest level voltage HV to the lowest level voltage LV at a fourth curved slope. The absolute magnitude of the fourth curved slope may increase from the highest level voltage HV to the lowest level voltage LV.

[0247] like Fig.19iAs shown in , the first AC voltage may have a waveform in which the first AC voltage rises from the lowest level voltage LV to the highest level voltage HV at a fifth curved slope during one period T19 and then directly drops from the highest level voltage HV to the lowest level voltage LV. The absolute magnitude of the fifth curved slope may decrease from the lowest level voltage LV to the highest level voltage HV.

[0248] like Fig.19j As shown in FIG. 1 , the first AC voltage may have a waveform in which the first AC voltage rises directly from the lowest level voltage LV to the highest level voltage HV during a first period T311 of one period T31 and then drops from the highest level voltage HV to the lowest level voltage LV at a sixth curved slope, and then maintains the lowest level voltage LV during a second period T322 of one period T32. The absolute magnitude of the sixth curved slope may increase from the highest level voltage HV toward the lowest level voltage LV.

[0249] like Figure 19k As shown in , the first AC voltage may have a waveform in which the first AC voltage rises directly from the lowest level voltage LV to the highest level voltage HV during a first period T321 of one period T32 and then drops from the highest level voltage HV to the lowest level voltage LV at a sixth straight line slope, and then rises directly from the lowest level voltage LV to a predetermined point above 0V during a second period T322 of one period T32 and then drops from the predetermined point to the lowest level voltage LV at a seventh straight line slope, wherein the absolute magnitude of the seventh straight line slope is smaller than the absolute magnitude of the sixth straight line slope. In this case, the first period T321 may be shorter than the second period T322.

[0250] like Figure 19l As shown in , the first AC voltage can have a waveform in which the first AC voltage directly rises from the lowest level voltage LV to the highest level voltage HV and then maintains the highest level voltage HV during a first period T331 of a period T33, and drops from the highest level voltage HV to the lowest level voltage LV at an eighth straight line slope during a second period T332 of a period T33.

[0251] like Fig.19m As shown, the first AC voltage may have a waveform in which the first AC voltage rises directly from the lowest level voltage LV to the highest level voltage HV during a first period T341 of one period T34 and then maintains the highest level voltage HV, and then drops from the highest level voltage HV to the lowest level voltage LV at a seventh curved slope during a second period T342 of one period T34. The absolute magnitude of the seventh curved slope may decrease from the highest level voltage HV toward the lowest level voltage LV.

[0252] like Figure 19n As shown in FIG. 3 , the first AC voltage may have a waveform in which the first AC voltage rises directly from the lowest level voltage LV to the highest level voltage HV during a first period T351 of one period T35 and then maintains the highest level voltage HV, and then drops from the highest level voltage HV to the lowest level voltage LV at an eighth curved slope during a second period T352 of one period T35. The absolute magnitude of the eighth curved slope may increase from the highest level voltage HV toward the lowest level voltage LV.

[0253] As described above, the first AC voltage having an asymmetric waveform may have a waveform in which the first AC voltage rises from the lowest level voltage LV to the highest level voltage HV and then drops from the highest level voltage HV to the lowest level voltage LV with a straight line or a curve slope. In addition, the first AC voltage having an asymmetric waveform may have a waveform in which the first AC voltage rises from the lowest level voltage LV to the highest level voltage HV and then drops from the highest level voltage HV to the lowest level voltage LV with a straight line or a curve slope. In this case, a period in which the first AC voltage rises from the lowest level voltage LV to the highest level voltage HV and then maintains the highest level voltage HV and a period in which the first AC voltage drops from the highest level voltage HV to the lowest level voltage LV and then maintains the lowest level voltage LV may be included.

[0254] The first AC voltage having an asymmetrical waveform according to the embodiment is not limited to Figures 19a to 19n The example shown in .

[0255] Figures 20a to 20c is a waveform diagram illustrating an example of the second AC voltage of high frequency.

[0256] exist Figures 20a to 20c In , the X-axis represents time and the Y-axis represents voltage level. Figures 20a to 20c 2 shows that the second AC voltage has a highest level voltage HV and a lowest level voltage LV. In this case, the highest level voltage HV is 20V, and the lowest level voltage LV is -20V, but the present invention is not limited thereto.

[0257] like Figures 20a to 20c As shown in , the second AC voltage having a symmetrical waveform is an AC voltage in which the voltage waveform of the positive polarity region of the second AC voltage and the voltage waveform of the negative polarity region of the second AC voltage are symmetrical to each other. Figures 20a to 20c , the positive polarity region of the second AC voltage indicates a region where the second AC voltage is 0V or more, and the negative polarity region of the second AC voltage indicates a region where the second AC voltage is less than 0V.

[0258] The second AC voltage may have a value such as Fig.20aThe sine wave shown in (see T21), Fig.20b The triangular form shown in (see T22) or as Fig.20c The square waveform shown in (see T23).

[0259] The second AC voltage having a symmetrical waveform according to the embodiment is not limited to Figures 20a to 20c The example shown in .

[0260] Although the preferred embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims

1. A method for aligning a light emitting element, comprising: applying a ground voltage to a first electrode and applying a first AC voltage to a second electrode spaced apart from the first electrode; as well as applying the ground voltage to the first electrode and applying a second AC voltage to the second electrode, wherein the first AC voltage has an asymmetric waveform, wherein the second AC voltage has a symmetrical waveform, and Wherein, a driving frequency of the first AC voltage is lower than a driving frequency of the second AC voltage.

2. The method according to claim 1, in, A voltage waveform in a positive polarity region of the first AC voltage is left-right asymmetric to a voltage waveform in a negative polarity region of the first AC voltage.

3. The method according to claim 1, in, The first AC voltage has a sawtooth waveform or a lamp waveform.

4. The method according to claim 1, in, A voltage waveform in a positive polarity region of the second AC voltage is bilaterally symmetrical to a voltage waveform in a negative polarity region of the second AC voltage.

5. The method according to claim 1, in, The second AC voltage has a sine waveform, a square waveform, or a triangle waveform.

6. The method according to claim 1, in, The first AC voltage has a driving frequency of 1 Hz to 1 kHz.

7. The method according to claim 1, in, The second AC voltage has a driving frequency of 1 kHz to 100 kHz.

8. The method according to claim 1, in, When the ground voltage is applied to the first electrode and the first AC voltage is applied to the second electrode spaced apart from the first electrode, an electric field formed by the first electrode and the second electrode is an asymmetric electric field in which any one of positive polarity and negative polarity dominates.

9. The method according to claim 1, in, When the ground voltage is applied to the first electrode and the second AC voltage is applied to the second electrode, the electric field formed by the first electrode and the second electrode is a symmetrical electric field.

10. A method for manufacturing a display device, comprising: forming a partition wall, a first electrode and a second electrode on a substrate; applying a coating liquid containing a light-emitting element to the sub-pixel; forming an electric field between the first electrode and the second electrode to align the light emitting element; volatilize the coating liquid and remove the coating liquid; forming a first connection electrode connecting the first electrode to one end of the light emitting element; as well as forming a second connection electrode connecting the second electrode to the other end of the light emitting element, wherein forming the electric field between the first electrode and the second electrode to align the light emitting element comprises: applying a ground voltage to the first electrode and applying a first AC voltage having an asymmetric waveform to the second electrode, and applying the ground voltage to the first electrode and applying a second AC voltage having a symmetric waveform to the second electrode, and Wherein, a driving frequency of the first AC voltage is lower than a driving frequency of the second AC voltage.

11. The method according to claim 10, in, When the ground voltage is applied to the first electrode and the first AC voltage is applied to the second electrode, the light emitting element is deflected toward the first electrode.

12. The method according to claim 10, in, Each of the light emitting elements comprises: a first conductive semiconductor provided at the other end of each of the light emitting elements; and a second conductive semiconductor provided at the one end of each of the light emitting elements, The first conductive semiconductor is disposed close to the second electrode, and the second conductive semiconductor is disposed close to the first electrode.

13. The method according to claim 12, in, The first conductive semiconductor is an n-type semiconductor layer, and the second conductive semiconductor is a p-type semiconductor layer.

14. The method according to claim 10, in, When the ground voltage is applied to the first electrode and the second AC voltage is applied to the second electrode, the light emitting element is aligned toward a center between the first electrode and the second electrode.

15. The method of claim 10, further comprising: After forming the second connection electrode, the first electrodes are disconnected so that the disconnected first electrodes correspond to each sub-pixel and are spaced apart from each other.

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