Semiconductor structure and method for forming the same

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure comprises the following steps: providing a substrate, wherein the surface of the substrate has a dielectric layer; forming a plurality of contact holes penetrating the dielectric layer, forming a first isolation layer covering the sidewalls of the contact holes, and forming a node contact layer filling the contact holes and covering the surface of the dielectric layer; patterning the node contact layer and the first isolation layer to form an etching groove connected to the contact hole, wherein the bottom surface of the etching groove is located below the top surface of the etching hole; forming a second isolation layer covering the sidewalls of the etching groove and exposing the dielectric layer; removing the dielectric layer along the etching groove to form a gap connected to the etching groove; and forming a third isolation layer to close the top opening of the etching groove. The present invention reduces the parasitic resistance inside the semiconductor structure and improves the yield of chip manufacturing.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor structure commonly used in computers, which is composed of multiple storage units, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.

[0003] The transistor and capacitor in each of the memory cells in the DRAM are electrically connected via a capacitor contact window. As the size of DRAM becomes smaller and smaller, the capacitor contact windows formed by the etching process are prone to problems such as short circuits between adjacent capacitor contact windows and open circuits inside the capacitor contact windows due to pattern transfer deviation, thereby reducing the device yield. For example, when the capacitor contact windows are formed using a pitch double pattern process, the following problems often occur:

[0004] First, the thickness of the spacer formed on the sidewall surface of the etched groove in the mask layer determines the characteristic size of the capacitor contact window. However, in the process of downward transfer, the size of the spacer becomes smaller and smaller, resulting in the size of the insulating layer between adjacent capacitor contact windows being smaller than the size of the spacer.

[0005] Second, in the process of increasing the size of the spacer, the adjacent spacers often stick together, resulting in the final capacitor contact window not being able to open normally;

[0006] Third, the edge of the startup area circuit is often abnormal due to the peeling of mask layer materials such as SION;

[0007] Fourth, since the capacitor is connected to the contact area of ​​the start-up area transistor through the capacitor contact window to achieve electrical connection between the start-up area transistor and the capacitor, however, with the continuous increase in DRAM storage capacity, the size and spacing of DRAM circuits are constantly shrinking, and the capacitor contact window and the start-up area are prone to short circuit at the edge of the capacitor contact window;

[0008] Fifth, as the size of DRAM becomes smaller and smaller, the capacitance generated between adjacent metal wires increases, which will cause reading delays and weakening of the internal DRAM signals. More seriously, it will lead to low or even zero yield of the chip.

[0009] Therefore, how to improve the formation process of the capacitor contact window to increase the yield of DRAM is a technical problem that needs to be solved urgently. Summary of the invention

[0010] The present invention provides a semiconductor structure and a method for forming the same, which are used to solve the problem of poor performance of the existing semiconductor structure, so as to improve the yield of the semiconductor structure and enhance the performance of the semiconductor structure.

[0011] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising the following steps:

[0012] Providing a substrate, wherein a dielectric layer is provided on the surface of the substrate;

[0013] forming a plurality of contact holes penetrating the dielectric layer, forming a first isolation layer covering the sidewalls of the contact holes, and forming a node contact layer filling the contact holes and covering the surface of the dielectric layer;

[0014] Patterning the node contact layer and the first isolation layer to form an etched groove connected to the contact hole, wherein the bottom surface of the etched groove is located below the top surface of the contact hole;

[0015] forming a second isolation layer covering the sidewalls of the etching groove and exposing the dielectric layer;

[0016] removing the dielectric layer along the etching groove to form a gap communicating with the etching groove;

[0017] A third isolation layer is formed to close the top opening of the etched groove.

[0018] Optionally, the dielectric layer includes a first dielectric layer located on the surface of the substrate and a second dielectric layer covering the surface of the first dielectric layer; and the specific steps of forming a plurality of contact holes penetrating the dielectric layer include:

[0019] forming a first mask layer on the surface of the dielectric layer;

[0020] forming a second mask layer on the surface of the first mask layer, wherein the second mask layer has a plurality of grooves exposing a portion of the surface of the first mask layer;

[0021] forming an insulating layer covering at least the inner wall of the groove;

[0022] Backfilling the trench to form a filling layer exposing the insulating layer;

[0023] The second dielectric layer is etched using the filling layer as a mask pattern to form a contact hole penetrating the second dielectric layer.

[0024] Optionally, after forming the contact hole penetrating the second dielectric layer, the following steps are further included:

[0025] forming a first isolation layer covering the inner wall of the contact hole and the top surface of the second dielectric layer;

[0026] The first isolation layer located on the top surface of the second dielectric layer and the bottom wall of the contact hole is removed, and the first dielectric layer is penetrated to extend the contact hole to the substrate surface.

[0027] Optionally, after forming the contact hole penetrating the second dielectric layer, the following steps are further included:

[0028] forming a first isolation layer covering the inner wall of the contact hole and the top surface of the second dielectric layer;

[0029] forming a protection layer covering the first isolation layer in the contact hole;

[0030] removing a portion of the protective layer located at the bottom of the contact hole and a portion of the first isolation layer located at the bottom of the contact hole, and extending the contact hole into the first isolation layer;

[0031] The protection layer and the first isolation layer at the bottom of the contact hole are removed, and the first dielectric layer is penetrated to extend the contact hole to the surface of the substrate.

[0032] Optionally, the node contact layer includes a first sub-node contact layer and a second sub-node contact layer located on the first sub-node contact layer; after extending the contact hole to the substrate surface, the method further includes the following steps:

[0033] forming a first subnode contact layer filling the contact hole;

[0034] Etching back the first subnode contact layer to expose a portion of the contact hole;

[0035] A second subnode contact layer is formed to fill the contact hole and cover the surface of the second dielectric layer.

[0036] Optionally, the specific steps of graphing the node contact layer and the first isolation layer include:

[0037] A portion of the node contact layer and a portion of the first isolation layer are etched to form an etching groove extending into the contact hole and exposing the dielectric layer.

[0038] Optionally, the specific steps of forming the second isolation layer covering the sidewalls of the etching groove and exposing the dielectric layer include:

[0039] forming a second isolation layer covering the inner wall of the etching groove and the top surface of the dielectric layer;

[0040] The second isolation layer located on the top surface of the dielectric layer and the bottom surface of the etching groove, and a portion of the first isolation layer are removed.

[0041] In order to solve the above problem, the present invention further provides a semiconductor structure, comprising:

[0042] A substrate, wherein a dielectric layer is provided on the surface of the substrate;

[0043] A plurality of contact holes, wherein the contact holes penetrate the dielectric layer, a portion of the sidewalls of the contact holes are covered with a first isolation layer, and a node contact layer is filled in the contact holes and extends out of the contact holes;

[0044] an air spacer layer, comprising interconnected etched grooves and gaps, wherein the etched grooves extend from the top surface of the node contact layer to the contact holes, the gaps are located between adjacent contact holes, and the sidewalls of the etched grooves are covered with a second isolation layer;

[0045] The third isolation layer closes the top opening of the etching groove.

[0046] Optionally, the dielectric layer includes a first dielectric layer located on the surface of the substrate and a second dielectric layer covering the surface of the first dielectric layer;

[0047] The contact hole penetrates the first dielectric layer and the second dielectric layer, and the width of the bottom of the contact hole is the same as that of the top.

[0048] Optionally, the dielectric layer includes a first dielectric layer located on the surface of the substrate and a second dielectric layer covering the surface of the first dielectric layer;

[0049] The contact hole penetrates the first dielectric layer and the second dielectric layer, and a portion of the contact hole that penetrates the first dielectric layer is in a step shape.

[0050] Optionally, the node contact layer includes:

[0051] A first subnode contact layer is filled in the contact hole and is in contact with the substrate;

[0052] The second subnode contact layer is filled in the contact hole and extends out of the contact hole, and the second subnode contact layer is located on the first subnode contact layer.

[0053] Optionally, the air spacer layer further comprises:

[0054] A connecting cavity is located between the bottom surface of the second isolation layer and the top surface of the first isolation layer, and is used to connect the etching groove and the gap.

[0055] Optionally, in a direction perpendicular to the substrate, the length of the connecting cavity is 10 nm to 30 nm.

[0056] Optionally, the thickness of the first isolation layer is 3 nm to 10 nm.

[0057] Optionally, the first isolation layer, the second isolation layer and the third isolation layer are made of the same material.

[0058] The semiconductor structure and the method for forming the same provided by the present invention reduce the parasitic resistance inside the semiconductor structure by forming an air spacing layer between adjacent node contact layers, avoid problems such as reading delay and strength reduction of signals inside semiconductor structures such as DRAM, and improve the yield rate of chip manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Attached Figure 1 is a flow chart of a method for forming a semiconductor structure in a first specific embodiment of the present invention;

[0060] Attached Figures 2A-2S is a schematic cross-sectional view of the main processes in the process of forming a semiconductor structure in the first specific embodiment of the present invention;

[0061] Attached Figures 3A-3G It is a schematic cross-sectional view of the main processes in the process of forming a semiconductor structure according to the second specific embodiment of the present invention. DETAILED DESCRIPTION

[0062] The specific implementation manner of the semiconductor structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0063] First specific embodiment

[0064] This specific embodiment provides a method for forming a semiconductor structure. Figure 1 is a flow chart of a method for forming a semiconductor structure in a first specific embodiment of the present invention, Figures 2A-2S FIG. 1 is a schematic cross-sectional view of the main processes in forming a semiconductor structure in the first specific embodiment of the present invention. Figure 1 , Figure 2A-2S As shown, the method for forming a semiconductor structure provided in this specific embodiment includes the following steps:

[0065] Step S11, providing a substrate 10, wherein the surface of the substrate 10 has a dielectric layer 11, such as Figure 2A shown.

[0066] In this specific implementation, the substrate 10 may be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator) or GOI (Germanium On Insulator), etc. In this specific implementation, the substrate 10 is described as a Si substrate as an example.

[0067] Step S12 , forming a plurality of contact holes 21 penetrating the dielectric layer 11 , forming a first isolation layer 22 covering the sidewalls of the contact holes 21 , and forming a node contact layer filling the contact holes 21 and covering the surface of the dielectric layer 11 .

[0068] Optionally, the dielectric layer 11 includes a first dielectric layer 111 located on the surface of the substrate 10 and a second dielectric layer 112 covering the surface of the first dielectric layer 111; the specific steps of forming a plurality of contact holes 21 penetrating the dielectric layer 11 include:

[0069] A first mask layer 14 is formed on the surface of the dielectric layer 11, such as Figure 2A As shown;

[0070] A second mask layer 15 is formed on the surface of the first mask layer 14. The second mask layer 15 has a plurality of grooves 151 exposing the first mask layer 14. Figure 2B As shown;

[0071] An insulating layer 18 is formed to at least cover the inner wall of the groove 151. Figure 2C As shown;

[0072] The trench 151 is backfilled to form a filling layer 19 exposing the insulating layer 18. Figure 2E As shown;

[0073] The second dielectric layer 112 is etched using the filling layer 19 as a mask pattern to form a contact hole 21 penetrating the second dielectric layer 112. Fig.2I shown.

[0074] This specific embodiment adopts a pitch multiplication process to form the contact hole 21. Specifically, along the first direction, first, the first dielectric layer 111 and the second dielectric layer 112 are sequentially deposited on the surface of the substrate 10, and a plurality of mask layers are deposited on the surface of the second dielectric layer 112, such as a third mask layer 13, a first mask layer 14, a second mask layer 15 and a fourth mask layer 16 stacked in sequence, and a photoresist layer 17 is formed on the surface of the topmost mask layer (such as the fourth mask layer 16), and the photoresist layer 17 has a plurality of first etching windows 171, such as Figure 2AThen, the fourth mask layer 16 and the second mask layer 15 are etched along the first etching window 171 to form a plurality of the grooves 151 in the second mask layer 15, as shown in FIG. Figure 2B As shown; then, an atomic layer deposition process is used to deposit an insulating material as shown Figure 2B The insulating layer 18 is formed on the surface of the structure shown in FIG. 1 , and the insulating layer 18 does not fill the groove 151. Figure 2C Then, the trench 151 is backfilled to form a filling layer 19 that fills the trench 151 and covers the surface of the fourth mask layer 16, as shown in FIG. Figure 2D As shown; then, chemical mechanical polishing or dry etching is used to expose the insulating layer 18 (in this step, the insulating layer 18 covering the surface of the fourth mask layer 16 may be removed or not), as shown Figure 2E Then, using the etching selectivity of the insulating layer 18 and the filling layer 19, the insulating layer 18 and the first mask layer 14 are etched by a dry etching process to open the first mask layer 14 to form a second etching window 20, as shown in FIG. Figure 2F As shown, in this step, since the insulating layer 18 is etched away and the first mask layer 14 is opened, the insulating layer 18 and the first mask layer 14 are not left in the peripheral area, and the first mask layer 14 and / or the insulating layer 18 are prevented from being peeled off into the contact hole 21 formed subsequently, thereby improving the problem of abnormal circuit at the edge of the start-up area; then, the filling layer 19 and the second mask layer 15 are peeled off by a dry etching process, and the following is obtained. Figure 2G Then, the insulating layer 18 is washed away by a wet etching process to obtain the structure shown in FIG. Figure 2H The structure shown in Figure 2H After the structure shown in the figure, in a second direction intersecting with the first direction, on the first mask layer 14, a method similar to the above is adopted. Figure 2A-2H A similar step is performed to form a third etching window, the extension direction of which intersects with the second etching window 20. Then, the projected overlapping area of ​​the third etching window and the second etching window 20 is used as an etching pattern to perform downward etching to form the contact hole 21 penetrating the second dielectric layer 112, as shown in FIG. Fig.2I The "intersection" described in this specific implementation manner can be a vertical intersection or an oblique intersection.

[0075] The material of the first dielectric layer 111 may be silicon oxynitride material, the material of the second dielectric layer 112 may be SOD (Spin On Dielectrics) material; the material of the third mask layer 13 may be TEOS (Tetraethyl orthosilicate); the material of the first mask layer 14 may be silicon oxynitride material; the materials of the second mask layer 15 and the filling layer 19 may both be SOC (Spin On Carbon) materials; the material of the fourth mask layer 16 may be SHB (Si-O-Based Hard Mask) material; and the material of the insulating layer 18 may be an oxide material.

[0076] In this specific embodiment, the thickness of the insulating layer 18 covering the sidewall of the groove 151 determines the size of the contact hole 21 formed subsequently. Therefore, the inner diameter of the contact hole 21 can be indirectly adjusted by adjusting the thickness of the insulating layer 18.

[0077] Optionally, after forming the contact hole 21 penetrating the second dielectric layer 112, the following steps are further included:

[0078] A first isolation layer 22 is formed covering the inner wall of the contact hole 21 and the top surface of the second dielectric layer 112. Figure 2K As shown;

[0079] The first isolation layer 22 located on the top surface of the second dielectric layer 112 and the bottom wall of the contact hole 21 is removed, and the first dielectric layer 111 is penetrated to extend the contact hole 21 to the surface of the substrate 10 .

[0080] Specifically, first, the first isolation layer 22 is formed on the inner wall of the contact hole 21 and the top surface of the second dielectric layer 112 by using an atomic layer deposition process. Figure 2J As shown, the thickness of the first isolation layer 22 deposited in this step is preferably 3nm to 10nm. Next, a dry etching process is used to remove the first isolation layer 22 on the top surface of the second dielectric layer 112 and the bottom wall of the contact hole 21, and the first dielectric layer 111 is opened, so that the contact hole 21 extends to the surface of the substrate 10, as shown in FIG. Figure 2K shown.

[0081] Optionally, the node contact layer includes a first sub-node contact layer 23 and a second sub-node contact layer 24 located on the first sub-node contact layer 23; after extending the contact hole 21 to the surface of the substrate 10, the following steps are further included:

[0082] A first subnode contact layer 23 is formed to fill the contact hole 21. Figure 2L As shown;

[0083] The first subnode contact layer 23 is etched back to expose a portion of the contact hole 21. Figure 2M As shown;

[0084] A second subnode contact layer 24 is formed to fill the contact hole 21 and cover the surface of the second dielectric layer 112. Figure 2N shown.

[0085] The material of the first subnode contact layer 23 may be polysilicon material, and the material of the second subnode contact layer 24 may be metal material. The above is only an exemplary description, and those skilled in the art may also select specific materials of the first subnode contact layer 23 and the second subnode contact layer 24 according to actual needs.

[0086] Step S13, patterning the node contact layer and the first isolation layer 22 to form an etching groove 25 connected to the contact hole 21, wherein the bottom surface of the etching groove 25 is located below the top surface of the contact hole 21. Fig.2O shown.

[0087] Optionally, the specific steps of patterning the node contact layer and the first isolation layer 22 include:

[0088] A portion of the node contact layer and a portion of the first isolation layer 22 are etched to form an etched groove 25 extending into the contact hole 21 and exposing the dielectric layer 11 .

[0089] Specifically, the second subnode contact layer 24 is etched from the top surface of the second subnode contact layer 24, and a portion of the first isolation layer 22 on the side wall of the contact hole 21 is etched downward to form the etched groove 25 exposing the second dielectric layer 112. The bottom surface of the etched groove 25 is located below the top surface of the contact hole 21 (i.e., below the top surface of the second dielectric layer 112), which means that the etched groove 25 extends into the contact hole 21. Fig.2O In the structure shown, the etching groove 25 can also be formed by etching downwards two overlapping patterns with intersecting projection areas.

[0090] Step S14, forming a second isolation layer 26 covering the sidewalls of the etching groove 25 and exposing the dielectric layer 11, such as Figure 2Q shown.

[0091] Optionally, the specific steps of forming the second isolation layer 26 covering the sidewalls of the etching groove 25 and exposing the dielectric layer 11 include:

[0092] A second isolation layer 26 is formed to cover the inner wall of the etching groove 25 and the top surface of the dielectric layer 11. Figure 2P As shown;

[0093] The second isolation layer 26 located on the top surface of the dielectric layer 26 and the bottom surface of the etching groove 25, and a part of the first isolation layer 22 are removed. Figure 2Q shown.

[0094] Specifically, first, the second isolation layer 26 covering the inner wall of the etching groove 25 and the top surface of the second dielectric layer 112 is formed by an atomic layer deposition process; then, the second isolation layer 26 on the top surface of the second dielectric layer 112 and the bottom surface of the etching groove 25 is removed, and the etching is continued downward to remove part of the first isolation layer 22, so as to form a connecting cavity 27 between the second dielectric layer 112 and the second sub-node contact layer 24. The length of the first isolation layer 22 overetched downward in this step (i.e., the length of the connecting cavity 27 in the direction perpendicular to the substrate 10) can be 10nm to 30nm.

[0095] Step S15, removing the dielectric layer 11 along the etching groove 25 to form a gap 28 connected to the etching groove 25, such as Figure 2R shown.

[0096] Step S16, forming a third isolation layer 29 to close the top opening of the etching groove, such as Figure 2S shown.

[0097] Specifically, a wet etching process is used to wash away the second dielectric layer 112 between adjacent node contact layers along the etching groove 25 to form the gap 28 connected to the etching groove 25. In this way, an air spacer layer including the etching groove 25 and the gap 28 is formed between adjacent node contact layers, thereby greatly reducing the parasitic resistance inside the semiconductor structure. Among them, the specific method of sealing the top opening of the etching groove 25 is etching by an atomic layer deposition process combined with a plasma enhanced chemical vapor deposition process. The materials of the first isolation layer 22, the second isolation layer 26 and the third isolation layer 29 can be the same, for example, all of them are silicon nitride materials.

[0098] In addition, this specific embodiment also provides a semiconductor structure. The schematic diagram of the semiconductor structure provided by this specific embodiment can be seen in Figure 2S The semiconductor structure may be as follows: Figure 1 , Figure 2A-2S The method shown is formed. Figure 2A-2S As shown, the semiconductor structure provided in this specific embodiment includes:

[0099] A substrate 10, wherein a dielectric layer 11 is provided on the surface of the substrate 10;

[0100] A plurality of contact holes 21, wherein the contact holes 21 penetrate the dielectric layer 11, a portion of the sidewalls of the contact holes 21 are covered with a first isolation layer 22, and a node contact layer is filled in the contact holes 21 and extends out of the contact holes 21;

[0101] An air spacer layer, comprising interconnected etched grooves 25 and gaps 28, wherein the etched grooves 25 extend from the top surface of the node contact layer to the contact holes 21, the gaps 28 are located between adjacent contact holes 21, and the sidewalls of the etched grooves 25 are covered with a second isolation layer 26;

[0102] The third isolation layer 29 closes the top opening of the etched groove 25 .

[0103] Optionally, the dielectric layer 11 includes a first dielectric layer 111 located on the surface of the substrate 10 and a second dielectric layer 112 covering the surface of the first dielectric layer 111;

[0104] The contact hole 21 penetrates the first dielectric layer 111 and the second dielectric layer 112 , and the width of the bottom of the contact hole 21 is the same as that of the top.

[0105] Optionally, the node contact layer includes:

[0106] A first subnode contact layer 23 is filled in the contact hole 21 and is in contact with the substrate 10;

[0107] The second subnode contact layer 24 fills the contact hole 21 and extends out of the contact hole 21 . The second subnode contact layer 24 is located on the first subnode contact layer 23 .

[0108] Optionally, the air spacer layer further comprises:

[0109] The connecting cavity 27 is located between the bottom surface of the second isolation layer 26 and the top surface of the first isolation layer 22 , and is used to connect the etching groove 25 and the gap 28 .

[0110] Optionally, in a direction perpendicular to the substrate, the length of the connecting cavity 27 is 10 nm to 30 nm.

[0111] Optionally, the thickness of the first isolation layer 22 is 3 nm to 10 nm.

[0112] Optionally, the first isolation layer 22 , the second isolation layer 26 and the third isolation layer 29 are made of the same material.

[0113] The semiconductor structure and its formation method provided in this specific embodiment reduce the parasitic resistance inside the semiconductor structure by forming an air spacing layer between adjacent node contact layers, avoid problems such as reading delay and intensity reduction of signals inside semiconductor structures such as DRAM, and improve the yield of chip manufacturing.

[0114] Second specific embodiment

[0115] This specific embodiment provides a method for forming a semiconductor structure. Figures 3A-3G This is a schematic cross-sectional view of the main processes in the process of forming a semiconductor structure in the second embodiment of the present invention. The same points as the first embodiment will not be described in detail in this embodiment, and the differences from the first embodiment will be mainly described below.

[0116] Specifically, after forming the contact hole 33 penetrating the second dielectric layer 312, the following steps are further included:

[0117] A first isolation layer 34 is formed to cover the inner wall of the contact hole 33 and the top surface of the second dielectric layer 312. Figure 3B As shown;

[0118] A protection layer 35 covering the first isolation layer 34 is formed in the contact hole 33. Figure 3C As shown;

[0119] The protective layer 35 at the bottom of the contact hole 33 and the first isolation layer 34 at the bottom of the contact hole 33 are removed, and the contact hole 33 is extended into the first isolation layer 34. Figure 3D As shown;

[0120] The protective layer 35 and the first isolation layer 34 at the bottom of the contact hole 33 are removed, and the first dielectric layer 311 is penetrated to extend the contact hole 33 to the surface of the substrate 30. Figure 3F shown.

[0121] Specifically, after forming the contact hole by the same method as the first specific embodiment, the first isolation layer 34 and the protective layer 35 covering the surface of the first isolation layer 34 are sequentially deposited on the inner wall of the contact hole 33 by an atomic layer deposition process, as shown in FIG. Figure 3C As shown. The material of the first isolation layer 34 can be a nitride material, such as silicon nitride; the material of the protective layer 35 can be an oxide material, such as silicon oxide. The thickness of the first isolation layer 34 and the protective layer 35 can both be 3nm to 10nm. Afterwards, the protective layer 35 on the bottom surface of the contact hole 33 is removed, and a portion of the first isolation layer 34 at the bottom of the contact hole 33 is etched away, but the first isolation layer 34 is not completely opened, as shown in FIG. Figure 3D In this step, the thickness of the first isolation layer 34 remaining at the bottom of the contact hole 33 is preferably 3nm to 6nm. Next, the remaining protection layer 35 is removed by a wet etching process to form Figure 3E Then, the first isolation layer 34 and the first dielectric layer 311 at the bottom of the contact hole 33 are opened by dry etching process to expose the substrate 30, as shown in FIG. Figure 3F shown.

[0122] In this specific embodiment, by forming the protective layer 35 and partially but not completely opening the first isolation layer 34 when removing the protective layer 35 at the bottom of the contact hole 33, the bottom of the contact hole 33 finally formed is stepped. On the one hand, the problem of short circuit between the capacitor contact window and the start-up area at the edge of the capacitor contact window is reduced or even avoided; on the other hand, since the protective layer 35 is fully removed, the resistance inside the semiconductor structure is further reduced.

[0123] This specific embodiment also provides a semiconductor structure. The schematic diagram of the semiconductor structure provided in this specific embodiment can be found in Figure 3G The semiconductor structure may be as follows: Figures 3A-3G The same aspects as the first embodiment are not described in detail in this embodiment, and the differences from the first embodiment are mainly described below.

[0124] Optionally, the dielectric layer includes a first dielectric layer 311 located on the surface of the substrate 10 and a second dielectric layer 312 covering the surface of the first dielectric layer 311;

[0125] The contact hole 33 penetrates the first dielectric layer 311 and the second dielectric layer 312 , and a portion of the contact hole 33 that penetrates the first dielectric layer 311 is in a step shape.

[0126] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: The steps include: Providing a substrate, wherein a dielectric layer is provided on the surface of the substrate; forming a plurality of contact holes penetrating the dielectric layer, forming a first isolation layer covering the sidewalls of the contact holes, and forming a node contact layer filling the contact holes and covering the surface of the dielectric layer; Patterning the node contact layer and the first isolation layer to form an etched groove connected to the contact hole, wherein the bottom surface of the etched groove is located below the top surface of the contact hole; forming a second isolation layer covering the sidewalls of the etching groove and exposing the dielectric layer; removing the dielectric layer along the etching groove to form a gap communicating with the etching groove; A third isolation layer is formed to close the top opening of the etched groove.

2. The method for forming a semiconductor structure according to claim 1, wherein: The dielectric layer comprises a first dielectric layer located on the surface of the substrate and a second dielectric layer covering the surface of the first dielectric layer; The specific steps of forming a plurality of contact holes penetrating the dielectric layer include: forming a first mask layer on the surface of the dielectric layer; forming a second mask layer on the surface of the first mask layer, wherein the second mask layer has a plurality of grooves exposing a portion of the surface of the first mask layer; forming an insulating layer covering at least the inner wall of the groove; Backfilling the trench to form a filling layer exposing the insulating layer; The second dielectric layer is etched using the filling layer as a mask pattern to form a contact hole penetrating the second dielectric layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: After forming the contact hole penetrating the second dielectric layer, the method further comprises the following steps: forming a first isolation layer covering the inner wall of the contact hole and the top surface of the second dielectric layer; The first isolation layer located on the top surface of the second dielectric layer and the bottom wall of the contact hole is removed, and the first dielectric layer is penetrated to extend the contact hole to the substrate surface.

4. The method for forming a semiconductor structure according to claim 2, wherein: After forming the contact hole penetrating the second dielectric layer, the method further comprises the following steps: forming a first isolation layer covering the inner wall of the contact hole and the top surface of the second dielectric layer; forming a protection layer covering the first isolation layer in the contact hole; removing a portion of the protective layer located at the bottom of the contact hole and a portion of the first isolation layer located at the bottom of the contact hole, and extending the contact hole into the first isolation layer; The protection layer and the first isolation layer at the bottom of the contact hole are removed, and the first dielectric layer is penetrated to extend the contact hole to the surface of the substrate.

5. The method for forming a semiconductor structure according to claim 3 or 4, characterized in that: The node contact layer includes a first sub-node contact layer and a second sub-node contact layer located on the first sub-node contact layer; after extending the contact hole to the surface of the substrate, the following steps are also included: forming a first subnode contact layer filling the contact hole; Etching back the first subnode contact layer to expose a portion of the contact hole; A second subnode contact layer is formed to fill the contact hole and cover the surface of the second dielectric layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of patterning the node contact layer and the first isolation layer include: A portion of the node contact layer and a portion of the first isolation layer are etched to form an etching groove extending into the contact hole and exposing the dielectric layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The specific steps of forming the second isolation layer covering the sidewalls of the etching groove and exposing the dielectric layer include: forming a second isolation layer covering the inner wall of the etching groove and the top surface of the dielectric layer; The second isolation layer located on the top surface of the dielectric layer and the bottom surface of the etching groove, and a portion of the first isolation layer are removed.

8. A semiconductor structure, characterized in that: include: A substrate, wherein a dielectric layer is provided on the surface of the substrate; A plurality of contact holes, wherein the contact holes penetrate the dielectric layer, a portion of the sidewalls of the contact holes are covered with a first isolation layer, and a node contact layer is filled in the contact holes and extends out of the contact holes; an air spacer layer, comprising interconnected etched grooves and gaps, wherein the etched grooves extend from the top surface of the node contact layer to the contact holes, the gaps are located between adjacent contact holes, and the sidewalls of the etched grooves are covered with a second isolation layer; The third isolation layer closes the top opening of the etching groove.

9. The semiconductor structure according to claim 8, characterized in that: The dielectric layer comprises a first dielectric layer located on the surface of the substrate and a second dielectric layer covering the surface of the first dielectric layer; The contact hole penetrates the first dielectric layer and the second dielectric layer, and the width of the bottom of the contact hole is the same as that of the top.

10. The semiconductor structure according to claim 8, characterized in that The dielectric layer comprises a first dielectric layer located on the surface of the substrate and a second dielectric layer covering the surface of the first dielectric layer; The contact hole penetrates the first dielectric layer and the second dielectric layer, and a portion of the contact hole that penetrates the first dielectric layer is in a step shape.

11. The semiconductor structure according to claim 8, characterized in that: The node contact layer comprises: A first subnode contact layer is filled in the contact hole and is in contact with the substrate; The second subnode contact layer is filled in the contact hole and extends out of the contact hole, and the second subnode contact layer is located on the first subnode contact layer.

12. The semiconductor structure according to claim 11, characterized in that: The air spacer layer also includes: A connecting cavity is located between the bottom surface of the second isolation layer and the top surface of the first isolation layer, and is used to connect the etching groove and the gap.

13. The semiconductor structure according to claim 12, characterized in that: In a direction perpendicular to the substrate, the length of the connecting cavity is 10 nm to 30 nm.

14. The semiconductor structure according to claim 8, characterized in that The thickness of the first isolation layer is 3nm~10nm.

15. The semiconductor structure according to claim 8, characterized in that The first isolation layer, the second isolation layer and the third isolation layer are made of the same material.

Images