CPU module packaging method, CPU module, mainboard, server and computing device

Abstract

This application provides a CPU module packaging method, as well as a CPU module, motherboard, server, and computing device. The CPU module packaging method includes: classifying the functions of the CPU die and fabricating corresponding die sub-units according to the function types; assembling multiple die sub-units to form a 3D structure with openings on the bottom, sides, and top; electrically connecting the die sub-units on the sides to the die sub-units on the bottom. Signal pins are reserved on the sides and bottom of the 3D structure. Memory chips adapted to the CPU die are connected to the signal pins on the sides of the 3D structure. A substrate electrically connected to the signal pins on the bottom of the 3D structure is disposed. The 3D structure and memory chips are packaged to form a CPU module, with the substrate serving as the external signal pins of the CPU module. The technical solution of this application effectively reduces signal transmission interference between the processor and memory and reduces the difficulty of motherboard design.

Description

Technical Field

[0001] The present application relates to the technical field of packaging and construction of computing device components, and in particular to a CPU module packaging method and a CPU module, a motherboard, a server, and a computing device. Background Art

[0002] The central processing unit (CPU) is the computing and control core of the computer system and the final execution unit for information processing and program execution. Memory is also called internal memory and main memory. It is used to temporarily store the computing data in the CPU and the data exchanged with external memory such as the hard disk.

[0003] A server is a type of computing device. The architecture of an existing server motherboard includes a CPU, a memory stick, and peripheral bridge chips, expansion interface chips, etc. The existing CPU and memory are independent devices, and the CPU is in a flat package. Therefore, when the CPU and memory are used on the motherboard, the signal transmission distance between them is relatively far, which makes the signal easily interfered, resulting in poor signal quality.

[0004] In addition, since the data path between the CPU and the memory has a very high rate, when designing the PCB (Printed Circuit Board), in order to ensure the integrity of the high-speed signal between the CPU and the memory, the impedance must be matched, and at the same time, signal reflection, attenuation and distortion must be avoided. Therefore, high requirements are placed on PCB design. Technical personnel in this field must have rich design experience when designing the PCB motherboard, and be able to use complete simulation tools for inspection, which increases the difficulty of motherboard design.

[0005] Therefore, how to design a CPU module that can effectively reduce the interference in signal transmission between the processor and memory and reduce the difficulty of motherboard design has become a hot topic in the industry. Summary of the invention

[0006] The purpose of the embodiments of the present application is to provide a CPU module packaging method, which can effectively reduce the signal transmission interference between the processor and the memory and reduce the difficulty of motherboard design.

[0007] The second purpose of the embodiment of the present application is to provide a CPU module.

[0008] The third purpose of the embodiment of the present application is also to provide a mainboard using the above-mentioned CPU module.

[0009] The fourth purpose of the embodiment of the present application is to provide a server using the above-mentioned motherboard.

[0010] The fifth purpose of the embodiment of the present application is also to provide a computing device using the above-mentioned motherboard.

[0011] In a first aspect, a CPU module packaging method is provided, comprising the following steps:

[0012] Classifying the functions of the CPU die and manufacturing corresponding die sub-units according to the types of functions, assembling multiple die sub-units to form a 3D structure with a bottom surface, side surfaces and a top opening, and electrically connecting the die sub-units on the side surfaces with the die sub-units on the bottom surface;

[0013] Signal pins are reserved on the side and bottom of the 3D structure;

[0014] A memory chip adapted to the CPU die is connected to the signal pins on the side of the 3D structure, and the memory chip is closely attached to the side of the 3D structure;

[0015] A substrate electrically connected to the signal pins on the bottom surface is arranged on the bottom surface of the 3D structure;

[0016] The packaged 3D structure and memory chip constitute the CPU module, and the substrate serves as the external signal pin of the CPU module.

[0017] In an implementable solution, the die sub-unit includes a base die sub-unit and a plurality of memory interface die sub-units. The base die sub-unit constitutes the bottom surface of the 3D structure, and the plurality of memory interface die sub-units constitute the side surfaces of the 3D structure.

[0018] In an implementable solution, the signal pins of the 3D structure are arranged on the side surface and the bottom surface of the outer surface of the 3D structure.

[0019] According to a second aspect of the present application, a CPU module is also provided, comprising a CPU bare chip, a memory particle chip, a packaging layer and a substrate.

[0020] The CPU die includes multiple die sub-units, which are assembled into a 3D structure with a bottom, side and top openings. The die sub-units on the side are electrically connected to the die sub-units on the bottom, and signal pins are reserved on the side and bottom of the 3D structure. The memory particle chip fits tightly to the side of the 3D structure and is connected to the signal pins on the side of the 3D structure. The encapsulation layer is used to encapsulate the CPU die and the memory particle chip. The substrate is set on the bottom of the 3D structure and is connected to the signal pins on the bottom of the 3D structure, serving as the external signal pins of the CPU module composed of the 3D structure and the memory particle chip.

[0021] In an implementable solution, the plurality of die sub-units include a base die sub-unit and a plurality of memory interface die sub-units. The base die sub-unit constitutes a bottom surface of a 3D structure, and the plurality of memory interface die sub-units constitute a side surface of the 3D structure.

[0022] In an implementable solution, the signal pins of the 3D structure are arranged on the side surface and the bottom surface of the outer surface of the 3D structure.

[0023] In an implementable solution, the basic die sub-unit is a polygon, and the number of the memory interface die sub-units is equal to the number of sides of the basic die sub-unit.

[0024] According to the third aspect of the present application, a mainboard is also provided, characterized in that it includes the CPU module in the above technical solution.

[0025] According to a fourth aspect of the present application, a server is also provided, comprising the mainboard in the above technical solution.

[0026] According to a fifth aspect of the present application, a computing device is also provided, comprising the mainboard in the above technical solution.

[0027] Compared with the prior art, the beneficial effects of this application are:

[0028] 1. The CPU module packaging method of the present application changes the original planar structure of the CPU bare chip, assembles multiple bare chip sub-units to form a 3D structure with bottom, side and top openings, and closely attaches the memory particle chip to the side of the 3D structure. The above structural setting greatly shortens the signal transmission distance between the CPU and the memory, reduces signal interference, improves the signal transmission quality between the CPU and the memory, and achieves a higher interconnection frequency between the CPU and the memory.

[0029] 2. This application packages the 3D structure of the CPU and the memory chip into one device, and uses the substrate electrically connected to the bottom surface of the 3D structure as the external signal pin of the CPU module. When designing the PCB, there is no need to design the communication circuit between the CPU and the memory to ensure the quality of the high-speed signal, which reduces the complexity of the circuit, thereby reducing the design difficulty of the PCB motherboard, improving the design success rate of the PCB motherboard, and shortening the design cycle of the PCB motherboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 A flowchart of a CPU module packaging method according to an embodiment of the present application;

[0032] Figure 2 It is a schematic diagram of the circuit structure of CPU and memory in practical application in the prior art;

[0033] Figure 3 Based on Figure 1 The circuit structure diagram of the CPU module obtained by the method in practical application;

[0034] Figure 4 A schematic diagram of the structure of a CPU module according to an embodiment of the present application;

[0035] Figure 5 for Figure 4 The exploded structural diagram of the CPU module shown;

[0036] Figure 6 It is a structural schematic diagram of a CPU bare chip according to an embodiment of the present application;

[0037] Figure 7 It is a structural schematic diagram of another CPU bare chip according to an embodiment of the present application;

[0038] Figure 8 for Figure 4 A schematic diagram of the internal support structure of the CPU module is shown;

[0039] Fig. 9 for Figure 4 Another schematic diagram of the internal support structure of the CPU module shown;

[0040] Fig.10 The figure is a schematic diagram of a heat conduction structure of a CPU module according to an embodiment of the present application.

[0041] In the figure: 10, 3D structure; 11, bare die subunit; 111, basic bare die subunit; 112, memory interface bare die subunit; 20, memory particle chip; 30, substrate; 40, supporting ribs; 50, thermal conductive layer; 60, thermal conductive structure. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0044] Figure 2 The schematic diagram of the circuit structure of the CPU and memory in the actual application in the prior art. Because the existing CPU and memory are independent devices, when used in the circuit, the signal transmission distance between the two is far, and the signal is easily interfered. In addition, in order to ensure the data signal transmission rate between the CPU and the memory, and to ensure the integrity and accuracy of the signal, the design requirements for the PCB motherboard are high, which increases the design difficulty of the PCB motherboard. Therefore, on the one hand, in order to effectively reduce the signal transmission interference between the processor CPU and the memory, the signal transmission distance between the CPU and the memory can be shortened; on the other hand, in order to reduce the difficulty of the motherboard design, it is necessary to simplify or even remove the circuit design between the CPU and the memory, thereby reducing the design difficulty of the PCB motherboard.

[0045] According to the first aspect of the present application, a CPU module packaging method is first provided. Figure 1 , the method comprises the following steps:

[0046] S101: Classify the functions of the CPU die and make corresponding die sub-units according to the types of functions, assemble multiple die sub-units to form a 3D structure with a bottom surface, side surfaces and a top opening, and electrically connect the die sub-units on the side surfaces with the die sub-units on the bottom surface.

[0047] S102: Reserve signal pins on the side and bottom of the 3D structure.

[0048] S103: Connecting a memory chip that is compatible with the CPU die to the signal pins on the side of the 3D structure, so that the memory chip fits tightly with the side of the 3D structure.

[0049] S104: Disposing a substrate 30 electrically connected to the signal pins on the bottom surface of the 3D structure.

[0050] S105: The 3D structure and memory chip are packaged to form a CPU module, and the substrate serves as an external signal pin of the CPU module.

[0051] It should be noted that in actual operation, some steps can be interchanged in order or performed simultaneously. For example, steps S103 and S104 can be interchanged in order, steps S103 and S104 can be performed simultaneously, and steps S102 and S101 can be performed simultaneously.

[0052] Figure 3 This is a schematic diagram of the circuit structure of a CPU module in actual application according to an embodiment of the present application. Figure 2 Compared with the existing technology represented, in the technical solution of the present application, the CPU and the memory become an integrated CPU module device, which shortens the signal transmission distance. In actual circuit applications, it is only necessary to design the connection circuit between the overall CPU module device and other circuits (power supply circuit, switch circuit, etc.), without designing the circuit between the CPU and the memory, thereby simplifying the PCB motherboard design and reducing the difficulty of PCB motherboard design.

[0053] Specifically, the CPU module packaging method of the present application classifies the functions of the CPU die and produces corresponding die sub-units according to the types of functions, assembles multiple die sub-units to form a 3D structure with a bottom surface, side surfaces and top openings, and then closely attaches the memory particle chip to the side surface of the 3D structure and electrically connects it to the side surface. The above structural setting changes the original planar structural form of the CPU die, greatly shortens the signal transmission distance between the CPU and the memory, reduces signal interference, improves the signal transmission quality between the CPU and the memory, and achieves a higher interconnection frequency between the CPU and the memory.

[0054] The CPU module packaging method of the present application further packages the 3D structure of the CPU and the memory particle chip into one device, and uses the substrate electrically connected to the bottom surface of the 3D structure as the external signal pin of the CPU module. The CPU and the memory are completely packaged into one device, rather than being separate devices. Therefore, when designing the PCB, there is no need to design the communication circuit between the CPU and the memory to ensure the quality of the high-speed signal, reduce the complexity of the circuit, thereby reducing the design difficulty of the PCB mainboard, improving the design success rate of the PCB mainboard, and shortening the design cycle of the PCB mainboard.

[0055] In one embodiment, the die sub-unit includes: a base die sub-unit and a plurality of memory interface die sub-units. The base die sub-unit constitutes the bottom surface of the 3D stereoscopic structure, and the plurality of memory interface die sub-units constitute the side surfaces of the 3D stereoscopic structure.

[0056] In one embodiment, the signal pins of the 3D structure are arranged on the side and bottom surfaces of the outer surface of the 3D structure, which can facilitate the connection between the substrate and the memory chip and the 3D structure.

[0057] In one embodiment, the bare chip subunit on the side and the bare chip subunit on the bottom are connected by gold wire bonding, and the memory particle chip is connected to the side of the 3D structure through the gold wire. The bonding gold wire is the main connecting material between the chip and the external circuit, has good corrosion resistance and conductivity, and can achieve extremely high bonding speed.

[0058] In one implementation, the signal pins related to the memory chip signals are led out from the side of the 3D structure, and other signal pins unrelated to the memory chip signals are led out from the bottom of the 3D structure, and other signal pins refer to power pins, ground signal pins, control signal pins, etc. The three-dimensional pins of the 3D structure are reasonably distributed to achieve reasonable regional allocation of signal pins, so that each bare chip sub-unit can perform its duties and exert its specific functions, reduce mutual interference between different signals, and also facilitate the subsequent modularization and standardized design of the bare chip sub-unit.

[0059] In one embodiment, the substrate is made into a structure with an upper surface and a lower surface, the upper surface of the substrate is electrically connected to and closely fits the outer surface of the bottom surface of the 3D structure, and the external signal pins of the CPU module are arranged on the lower surface of the substrate. The design of the substrate in this application enables the CPU and memory packaged into one device to be flexibly connected to the peripheral circuit. Among them, the substrate can adopt a high-frequency and low-dielectric-loss dielectric substrate, such as a polytetrafluoroethylene (PTFE) substrate, a thermosetting PPO (Polyphenyl Oxide), a cross-linked polybutadiene substrate, and an epoxy resin composite substrate (FR-4).

[0060] According to the second aspect of the present application, there is also provided a CPU module obtained by using the above CPU module packaging method, see Figure 4 and Figure 5 The CPU module includes a CPU bare chip, a memory particle chip 20, a packaging layer and a substrate 30.

[0061] Among them, the CPU die includes a plurality of die sub-units 11, and the plurality of die sub-units 11 are assembled into a 3D structure 10 with a bottom surface, a side surface and a top opening. The die sub-units 11 on the side surface are electrically connected to the die sub-units 11 on the bottom surface, and signal pins are reserved on the side and bottom surfaces of the 3D structure 10. The memory particle chip 20 is tightly fitted to the side surface of the 3D structure 10 and is connected to the signal pins on the side surface of the 3D structure 10. The encapsulation layer is used to encapsulate the CPU die and the memory particle chip 20. The substrate 30 is arranged on the bottom surface of the 3D structure 10 and is connected to the signal pins on the bottom surface of the 3D structure 10, serving as the external signal pins of the CPU module composed of the 3D structure 10 and the memory particle chip 20.

[0062] In the technical solution of the present application, the original planar structure of the CPU bare chip is changed, the signal transmission distance between the CPU and the memory is greatly shortened, the signal interference is reduced, the signal transmission quality between the CPU and the memory is improved, and a higher interconnection frequency between the CPU and the memory is achieved. In addition, the packaging layer is used to package the 3D structure 10 of the CPU and the memory particle chip 20 into one device, rather than separate devices. Therefore, when designing the PCB, there is no need to design the communication circuit between the CPU and the memory to ensure the quality of the high-speed signal, and the complexity of the circuit is reduced, thereby reducing the design difficulty of the PCB mainboard, improving the design success rate of the PCB mainboard, and shortening the design cycle of the PCB mainboard.

[0063] It should be noted that the top of the 3D structure 10 is open, which is convenient for the heat dissipation of the CPU module. In addition, the top of the 3D structure 10 is open, and the cavity inside can be used to place a reinforcing bracket and / or fill with thermal conductive materials to further improve the heat dissipation and cooling effect.

[0064] In one embodiment, the plurality of bare die sub-units 11 include a basic bare die sub-unit 111 and a plurality of memory interface bare die sub-units 112. The basic bare die sub-unit 111 constitutes the bottom surface of the 3D stereoscopic structure 10, and the plurality of memory interface bare die sub-units 112 constitute the side surface of the 3D stereoscopic structure 10. The plurality of bare die sub-units 11 include the basic bare die sub-unit 111, i.e., a bare die sub-unit 11 classified according to the functions of the CPU bare die and manufactured according to the functional types. The above setting separates the memory signal pins from other signal pins, the bare die sub-unit 11 on the side is only responsible for the signal communication with the memory, and the bare die sub-unit 11 at the bottom is responsible for the power connection with the mainboard circuit, the control signal communication, etc., so that each bare die sub-unit 11 can perform its duties, exert its specific functions, and reduce the mutual interference between different signals.

[0065] In one embodiment, the signal pins of the 3D structure 10 are arranged on the side and bottom surfaces of the outer surface of the 3D structure 10. Specifically, the memory interface die subunit 112 includes an inner surface and an outer surface, the inner surfaces of the multiple memory interface die subunits 112 constitute the inner wall of the internal cavity of the 3D structure 10, and the outer surfaces of the multiple memory interface die subunits 112 constitute the surrounding sides of the 3D structure 10. The base die subunit 111 includes a first surface and a second surface, the first surface of the base die subunit 111 is the bottom surface of the 3D structure 10 and is tightly attached to and electrically connected to the substrate 30, and the second surface of the base die subunit 111 is bonded to the memory interface die subunit 112 by gold wire.

[0066] It should be noted that the outer surface of the memory interface die subunit 112 is provided with signal pins related to the signals of the memory particle chip 20, and one or more of the memory particle chips 20 are closely attached to and electrically connected with the outer surface of the memory interface die subunit 112. According to actual application requirements, the memory particle chip 20 can also use memory particles or memory chips with different capacity specifications, and according to the specifications of the memory particle chip 20, the memory interface die subunit 112 of a predetermined size can also be customized, and one or more memory particle chips 20 are arranged on its outer surface to meet different requirements.

[0067] In one embodiment, the basic bare chip subunit 111 is a polygon, and the number of the memory interface bare chip subunits 112 is equal to the number of sides of the basic bare chip subunit 111. The polygon is a shape that is easier to process, and the basic bare chip subunit 111 can be customized into various forms such as triangles, quadrilaterals, pentagons, etc. The number of sides of the memory interface bare chip subunit 112 is equal to that of the basic bare chip subunit 111, so that a variety of packaging specifications can appear, thereby meeting the design requirements of different PCB motherboards.

[0068] See also Figure 4 , Figure 6 and Figure 7 , showing three different forms of CPU die structures, Figure 4 It is a cuboid with an open top and a square bottom. Figure 6 It is a triangular prism with an open top and a triangular bottom. Figure 7 It is a pentagonal prism with an open top and a regular pentagonal bottom. Figure 4 , Figure 6 and Figure 7 The bottom surface of the 3D structure 10 of the CPU die is a polygon with equal sides, which is conducive to the subsequent standardized production and the formation of standardized packaging sizes of various specifications. It should be noted that the bottom surface of the 3D structure 10 in this application is not limited to Figure 4 , Figure 6 and Figure 7 The type shown may also be other equilateral or unequal polygons. In addition, the side memory interface die subunit 112 may also be in a shape other than a rectangle or a square. Figure 6 It can be seen that the memory interface bare chip subunit 112 has a trapezoidal shape and is non-vertically connected to the base bare chip subunit 111 on the bottom surface, forming a certain angle installation. This angle structure can reduce the overall height of the 3D stereoscopic structure 10 and is suitable for scenarios where the motherboard installation height is low.

[0069] In one embodiment, see Figure 8 and Fig. 9The CPU module further includes a support rib 40, which connects the basic die subunit 111 and the memory interface die subunit 112. The support rib 40 forms a stable structural connection between the basic die subunit 111 and the memory interface die subunit 112 to prevent bending at the circuit connection between the basic die subunit 111 and the memory interface die subunit 112, which may cause problems in signal connection. The support rib 40 plays a role in reinforcing the 3D structure 10 and ensuring stable circuit connection. The support rib 40 may be made of the same material as the substrate 30, or the same material as the CPU die.

[0070] In one embodiment, see Figure 8 The number of the supporting ribs 40 is the same as the number of the memory interface die subunits 112, and each supporting rib 40 connects the basic die subunit 111 and a memory interface die subunit 112. The above structure enables each memory interface die subunit 112 to form an effective reinforcement structure with the basic die subunit 111.

[0071] In one embodiment, see Fig. 9 , multiple support ribs 40 are cross-distributed in the internal cavity of the 3D structure 10, so that each memory interface die sub-unit 112 can be connected to the basic die sub-unit 111 through the support ribs 40. The support ribs 40 of the above structure are an integral structure that crosses each other, and this integral structure reinforces and connects multiple memory interface die sub-units 112 and the basic die sub-unit 111 together. Because the cross-distributed support ribs 40 not only connect the memory interface die sub-unit 112 and the basic die sub-unit 111, but also connect the multiple memory interface die sub-units 112 to each other, it is better than the effect of using multiple support ribs 40 for reinforcement alone.

[0072] It should be noted that the structure of the support rib 40 is not limited to Figure 8 and Fig. 9 In the two types, any structure that can support the memory interface die sub-unit 112 falls within the protection scope of this application.

[0073] In one embodiment, see Fig.10 The CPU module further includes a heat-conducting layer 50, which is disposed in the internal cavity of the 3D structure 10. The heat-conducting layer 50 cooperates with the internal cavity of the 3D structure 10, and specifically, the heat-conducting layer 50 is coated on the inner surface of the memory interface bare chip subunit 112 and the basic bare chip subunit 111, so as to further expand the heat dissipation area and improve the heat dissipation effect. The heat-conducting layer 50 can be made of one of pure white thermal grease, ceramic thermal grease, silver-containing thermal grease, gold-containing thermal grease, diamond thermal grease, liquid metal, etc.

[0074] In one embodiment, see Fig.10The CPU module further includes a heat-conducting structure 60, one end of which is connected to the heat-conducting layer 50, and the other end is connected to the outside. The heat-conducting structure 60 can fully conduct the heat of the 3D structure 10 to the outside. The heat-conducting structure 60 can be closely attached to the heat-conducting layer and lead out from the top surface of the 3D structure 10. The heat-conducting structure 60 is conducive to faster and better heat dissipation. The heat-conducting structure 60 can be a metal heat-conducting structure such as a heat-conducting copper block and a heat-conducting copper pipe.

[0075] In one embodiment, the CPU module further includes a packaging shell, which encapsulates other structures except the external signal pins of the substrate 30. The packaging shell structure plays a good protective role for the entire CPU module and its internal circuit connections. The packaging shell can be made of metal, ceramic, plastic, etc., corresponding to metal packaging, ceramic packaging, plastic packaging, etc.

[0076] According to the third aspect of the present application, a mainboard is provided, comprising the CPU module in the above embodiment. The mainboard using the CPU module of the present application has greatly reduced design difficulty, improved design success rate of the mainboard, and shortened design cycle of the mainboard.

[0077] According to a fourth aspect of the present application, a server is also provided, comprising the mainboard in the above embodiment.

[0078] According to a fifth aspect of the present application, a computing device is also provided, comprising the mainboard in the above embodiment.

[0079] The motherboard made of the CPU module of the implementation scheme of the present application is adopted by computing devices such as servers, because when designing the motherboard, there is no need to design the communication circuit between the CPU and the memory, which reduces the complexity of the circuit, thereby reducing the design difficulty of the motherboard, improving the design success rate of the PCB motherboard, shortening the design cycle of the PCB motherboard, and then reducing the research and development cost of the motherboard, thereby also reducing the design and production cost of the motherboard of computing devices such as servers. In addition, the CPU module greatly shortens the signal transmission distance between the CPU and the memory, reduces signal interference, improves the signal transmission quality of the CPU and the memory, and achieves a higher interconnection frequency between the CPU and the memory, thereby improving the performance of computing devices such as servers.

[0080] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A CPU module packaging method, characterized in that: The following steps are involved: Classifying the functions of the CPU die and manufacturing corresponding die sub-units according to the types of functions, assembling a plurality of die sub-units to form a 3D structure having a bottom surface, side surfaces and a top opening, and electrically connecting the die sub-units on the side surfaces with the die sub-units on the bottom surface; Signal pins are reserved on the side and bottom of the 3D structure; A memory chip adapted to the CPU die is connected to the signal pins on the side of the 3D structure, and the memory chip is closely attached to the side of the 3D structure; Disposing a substrate electrically connected to the signal pins on the bottom surface of the 3D structure; The 3D structure and the memory chip are packaged to form a CPU module, and the substrate serves as an external signal pin of the CPU module.

2. The CPU module packaging method according to claim 1, characterized in that: The die subunit includes: a basic die subunit and a plurality of memory interface die subunits; The basic bare chip subunit constitutes the bottom surface of the 3D structure; The plurality of memory interface die sub-units constitute side surfaces of the 3D structure.

3. The CPU module packaging method according to claim 1 or 2, characterized in that: The signal pins of the 3D structure are arranged on the side surface and the bottom surface of the outer surface of the 3D structure.

4. A CPU module, characterized in that: include: A CPU bare chip, comprising a plurality of bare chip sub-units (11), wherein the plurality of bare chip sub-units (11) are assembled into a 3D stereoscopic structure (10) having a bottom surface, side surfaces and a top opening, the bare chip sub-units (11) on the side surfaces are electrically connected to the bare chip sub-units (11) on the bottom surface, and signal pins are reserved on the side surfaces and the bottom surface of the 3D stereoscopic structure (10); A memory particle chip (20) is tightly attached to the side surface of the 3D stereoscopic structure (10) and is connected to the signal pin on the side surface of the 3D stereoscopic structure (10); A packaging layer, used for packaging the CPU bare chip and the memory particle chip (20); A substrate (30) is arranged on the bottom surface of the 3D structure (10) and is connected to the signal pins on the bottom surface of the 3D structure (10), serving as an external signal pin of a CPU module formed by the 3D structure (10) and the memory chip (20); The plurality of bare die sub-units (11) include a basic bare die sub-unit (111) and a plurality of memory interface bare die sub-units (112); The basic bare chip subunit (111) constitutes the bottom surface of the 3D structure (10); The plurality of memory interface die sub-units (112) constitute the side surfaces of the 3D structure (10); The CPU module further comprises a supporting rib (40), wherein the supporting rib (40) connects the basic die subunit (111) and the memory interface die subunit (112).

5. The CPU module according to claim 4, characterized in that: The signal pins of the 3D stereoscopic structure (10) are arranged on the side surface and the bottom surface of the outer surface of the 3D stereoscopic structure (10).

6. The CPU module according to claim 4, characterized in that: The basic die subunit (111) is a polygon, and the number of the memory interface die subunits (112) is equal to the number of sides of the basic die subunit (111).

7. A motherboard, characterized in that: The method comprises the CPU module according to any one of claims 4 to 6.

8. A server, characterized in that: Comprising the mainboard as claimed in claim 7.

9. A computing device, characterized in that: Comprising the mainboard as claimed in claim 7.

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