A semiconductor structure and a method for manufacturing the same

Abstract

The present invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a device layer, an insulating layer, a corrosion barrier layer, a self-limiting corrosion cavity, a first corrosion cavity and a substrate, wherein the device layer is located on the first side of the substrate, the self-limiting corrosion cavity is located on the second side of the substrate, the insulating layer and the corrosion barrier layer are located on the side of the self-limiting corrosion cavity close to the device layer, and the self-limiting corrosion cavity is located in the space defined by the insulating layer and the corrosion barrier layer, the first corrosion cavity is located on the side of the self-limiting corrosion cavity away from the device layer, and the first corrosion cavity is connected to the self-limiting corrosion cavity. The semiconductor structure and the manufacturing method thereof provided by the present invention enable the self-limiting corrosion cavity on the second side of the substrate to be defined by the corrosion barrier layer formed on the first side of the substrate, so that the patterns on the first side and the second side of the substrate can be positioned and aligned on the first side of the substrate, and the self-limiting corrosion cavity is not affected by the error of double-sided lithography, thereby improving the alignment accuracy of the self-limiting corrosion cavity and the device layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In semiconductor technology, double-sided processing is sometimes required, such as the need to make patterns on both the front and back sides of the silicon wafer, especially for some MEMS devices, such as pressure sensors, thermopile temperature sensors, etc., where deep etching is required on the back side of MEMS devices, so that the final device is a thin film device. Among them, the double-sided processing requires the use of special equipment, double-sided photolithography, and deep etching can be done by dry etching or wet etching.

[0003] Double-sided photolithography machines use proximity or contact exposure, that is, the optical system projects the pattern onto the silicon wafer at a 1:1 ratio. Therefore, the mask used is the same size as the silicon wafer, and the size and position of the pattern on the mask must also be consistent with the actual situation. As a result, the traditional double-sided photolithography process basically uses manual methods to place and align the mask. However, manual placement of the mask generally results in inaccurate alignment, including center deviation, that is, the center of the exposure pattern will deviate from the center of the wafer, with the maximum deviation reaching more than ten millimeters; and also includes rotation deviation, that is, the exposure pattern will rotate relative to the flat edge of the wafer, with the maximum deviation reaching dozens of degrees. Although skilled engineers can overcome this problem to a large extent, the alignment accuracy is still affected by the proficiency of the operator.

[0004] When a certain deviation is formed in the patterns on the front and back sides of the silicon wafer, the patterns after deep etching will continue to maintain this deviation or even amplify this deviation, thus adversely affecting the performance of the device. Summary of the invention

[0005] The invention provides a semiconductor structure and a manufacturing method thereof, so as to improve the alignment accuracy of deep etching devices.

[0006] In a first aspect, an embodiment of the present invention provides a semiconductor structure, including a device layer, an isolation layer, an etching barrier layer, a self-limiting etching chamber, a first etching chamber and a substrate;

[0007] The device layer is located on a first side of the substrate, the self-limiting corrosion cavity is located on a second side of the substrate, the isolation layer and the corrosion barrier layer are located on a side of the self-limiting corrosion cavity close to the device layer, and the self-limiting corrosion cavity is located in a space defined by the isolation layer and the corrosion barrier layer;

[0008] The first etching chamber is located at a side of the self-limiting etching chamber away from the device layer, and the first etching chamber is communicated with the self-limiting etching chamber.

[0009] Optionally, the isolation layer is located on a side of the device layer close to the substrate, and the corrosion barrier layer is located on a side of the isolation layer away from the device layer.

[0010] Optionally, the substrate comprises a first substrate section and a second substrate section, wherein the second substrate section is located on a side of the first substrate section away from the device layer;

[0011] The insulating layer is located between the first substrate section and the second substrate section;

[0012] The corrosion barrier layer is located on a side of the device layer close to the first corrosion cavity, and the corrosion barrier layer penetrates the first substrate portion, the isolation layer and at least a portion of the second substrate portion.

[0013] Optionally, the vertical projection of the self-limiting corrosion chamber on the plane where the device layer is located is located within the vertical projection of the first corrosion chamber on the plane where the device layer is located, and the area of ​​the vertical projection of the first corrosion chamber on the plane where the device layer is located is larger than the area of ​​the vertical projection of the self-limiting corrosion chamber on the plane where the device layer is located.

[0014] Optionally, the material of the isolation layer includes silicon oxide or silicon nitride, and the material of the corrosion barrier layer includes silicon oxide.

[0015] In a second aspect, an embodiment of the present invention further provides a method for preparing a semiconductor structure, which is used to prepare any semiconductor structure described in the first aspect, and the method comprises:

[0016] providing a substrate;

[0017] forming an isolation layer and a corrosion barrier layer on the substrate;

[0018] preparing a device layer on a first side of the substrate;

[0019] preparing a first etching cavity on the second side of the substrate;

[0020] A self-limiting corrosion cavity is prepared on the second side of the substrate, wherein the isolation layer and the corrosion barrier layer are located on a side of the self-limiting corrosion cavity close to the device layer, the self-limiting corrosion cavity is located in a space defined by the isolation layer and the corrosion barrier layer, the first corrosion cavity is located on a side of the self-limiting corrosion cavity away from the device layer, and the first corrosion cavity is connected to the self-limiting corrosion cavity.

[0021] Optionally, the substrate is a single-layer silicon substrate;

[0022] Forming an isolation layer and a corrosion barrier layer on the substrate, comprising:

[0023] Etching a first cavity on a first side of the substrate, and filling the first cavity with silicon oxide or silicon nitride to form a corrosion barrier layer;

[0024] The isolation layer is formed on the first side of the substrate and on the side of the corrosion barrier layer away from the substrate.

[0025] Optionally, the substrate is an SOI silicon wafer, the SOI silicon wafer comprises a first substrate section, the isolation layer and a second substrate section, and the isolation layer is located between the first substrate section and the second substrate section;

[0026] Forming an isolation layer and a corrosion barrier layer on the substrate, comprising:

[0027] A second cavity is etched on the first side of the substrate, and silicon oxide or silicon nitride is filled in the second cavity to form a corrosion barrier layer, wherein the corrosion barrier layer penetrates the first substrate portion, the isolation layer and at least a portion of the second substrate portion.

[0028] Optionally, a first etching cavity is prepared on the second side of the substrate by an anisotropic wet etching process or a deep silicon dry etching process;

[0029] A self-limiting etching cavity is prepared on the second side of the substrate by an isotropic wet etching process or an anisotropic wet etching process.

[0030] Optionally, a self-limiting etching cavity is prepared on the second side of the substrate by an anisotropic wet etching process, and the etching surface of the substrate is a (100) crystal plane.

[0031] The semiconductor structure provided by the embodiment of the present invention is configured such that a device layer is located on the first side of a substrate, a self-limiting corrosion cavity is located on the second side of the substrate, an insulating layer and a corrosion barrier layer are located on the side of the self-limiting corrosion cavity close to the device layer, and the self-limiting corrosion cavity is located in a space defined by the insulating layer and the corrosion barrier layer, a first corrosion cavity is located on the side of the self-limiting corrosion cavity away from the device layer, and the first corrosion cavity is connected to the self-limiting corrosion cavity, so that the self-limiting corrosion cavity on the second side of the substrate is defined by the corrosion barrier layer formed on the first side of the substrate, so that the patterns on the first side and the second side of the substrate can be positioned and aligned on the first side of the substrate, and the process is simple and controllable, the self-limiting corrosion cavity formed by the corrosion barrier layer prepared on the first side of the substrate is not affected by the error of double-sided lithography, and is mainly affected by the error of single-sided lithography, and the error of single-sided lithography can be controlled very small in modern semiconductor processes, so that the problem of inaccurate alignment caused by the manual placement and alignment of the mask in the double-sided lithography process in the prior art is solved, and the alignment accuracy of the self-limiting corrosion cavity on the second side of the substrate and the device layer on the first side of the substrate in the deep etching device is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present invention;

[0033] Figure 2 A bottom-up structural schematic diagram of a semiconductor structure provided by an embodiment of the present invention;

[0034] Figure 3 A schematic cross-sectional view of another semiconductor structure provided by an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of a process for preparing a semiconductor structure provided by an embodiment of the present invention;

[0036] Figure 5 A schematic flow chart of another method for preparing a semiconductor structure provided by an embodiment of the present invention;

[0037] Figure 6 A schematic flow chart of another method for preparing a semiconductor structure provided by an embodiment of the present invention;

[0038] Figure 7 A schematic flow chart of another method for preparing a semiconductor structure provided by an embodiment of the present invention;

[0039] Figure 8 A schematic flow chart of another method for preparing a semiconductor structure provided by an embodiment of the present invention;

[0040] Fig. 9 A schematic flow chart of another method for preparing a semiconductor structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0042] Figure 1 A schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present invention. Figure 2 A bottom-up structural diagram of a semiconductor structure provided by an embodiment of the present invention is shown in FIG. Figure 1 and Figure 2As shown, the semiconductor structure provided by the embodiment of the present invention includes a device layer 10, an isolation layer 11, a corrosion barrier layer 12, a self-limiting corrosion cavity 13, a first corrosion cavity 14 and a substrate 15. The device layer 10 is located on a first side 151 of the substrate 15, the self-limiting corrosion cavity 13 is located on a second side 152 of the substrate 15, the isolation layer 11 and the corrosion barrier layer 12 are located on a side of the self-limiting corrosion cavity 13 close to the device layer 10, and the self-limiting corrosion cavity 13 is located in a space defined by the isolation layer 11 and the corrosion barrier layer 13, the first corrosion cavity 14 is located on a side of the self-limiting corrosion cavity 13 away from the device layer 10, and the first corrosion cavity 14 is connected to the self-limiting corrosion cavity 13.

[0043] Specifically, Figure 1 and Figure 2 As shown, the device layer 10 is located on the first side 151 of the substrate 15, wherein the device layer 10 may be part of the final functional layer of the MEMS device, the device layer 10 may be one layer or multiple layers, each layer of the device layer 10 may constitute a sub-functional layer, each sub-functional layer may contain a single type of device or a mixture of various types of devices, and those skilled in the art may set the device layer 10 according to the preset function.

[0044] Continue to refer Figure 1 and Figure 2 The insulating layer 11 and the corrosion barrier layer 12 are located on the side of the self-limiting corrosion cavity 13 close to the device layer 10. The insulating layer 11 and the corrosion barrier layer 12 can be prepared by the first side 151 of the substrate 15. The self-limiting corrosion cavity 13 and the first corrosion cavity 14 can be prepared by the second side 152 of the substrate 15, and the self-limiting corrosion cavity 13 is located in the space defined by the insulating layer 11 and the corrosion barrier layer 13, so that the pattern of the second side 152 of the substrate 15 is defined by designing the pattern of the insulating layer 11 and the corrosion barrier layer 12 on the first side 151 of the substrate 15.

[0045] Specifically, when preparing the semiconductor structure, the corrosion barrier layer 12 and the device layer 10 are prepared on the first side 151 of the substrate 15, and the corrosion barrier layer 12 is used to form a first corrosion cavity and a self-limiting corrosion cavity on the second side 152 of the substrate 15, so that the self-limiting corrosion cavity 13 on the second side 152 of the substrate 15 is limited by the corrosion barrier layer 13 formed on the first side 151 of the substrate 15, so that the patterns on the first side 151 and the second side 152 of the substrate 15 can be positioned and aligned on the first side 151 of the substrate 15. The process is simple and controllable. The self-limiting corrosion cavity 13 formed by the corrosion barrier layer 12 prepared on the first side 151 of the substrate 15 is not affected by the error of double-sided lithography, but is mainly affected by the error of single-sided lithography. The error of single-sided lithography can be controlled to be very small in modern semiconductor processes, which greatly improves the alignment accuracy of the self-limiting corrosion cavity 13 on the second side 152 of the substrate 15 and the device layer 10 on the first side 151 of the substrate 15 in the deep etching device.

[0046] The semiconductor structure provided by the embodiment of the present invention is configured such that the device layer 10 is located on the first side 151 of the substrate 15, the self-limiting corrosion cavity 13 is located on the second side 152 of the substrate 15, the insulating layer 11 and the corrosion barrier layer 12 are located on the side of the self-limiting corrosion cavity 13 close to the device layer 10, and the self-limiting corrosion cavity 13 is located in the space defined by the insulating layer 11 and the corrosion barrier layer 13, the first corrosion cavity 14 is located on the side of the self-limiting corrosion cavity 13 away from the device layer 10, and the first corrosion cavity 14 is connected to the self-limiting corrosion cavity 13, so that the self-limiting corrosion cavity 13 on the second side 152 of the substrate 15 is defined by the corrosion barrier layer 13 formed on the first side 151 of the substrate 15, thereby making the substrate 15 The patterns on the first side 151 and the second side 152 of the substrate 15 can be positioned and aligned on the first side 151 of the substrate 15, and the process is simple and controllable. The self-limiting etching cavity 13 formed by the etching barrier layer 12 prepared on the first side 151 of the substrate 15 is not affected by the error of double-sided lithography, but is mainly affected by the error of single-sided lithography. The error of single-sided lithography can be controlled very small in modern semiconductor processes, which solves the problem of inaccurate alignment caused by the manual placement and alignment of the mask in the double-sided lithography process in the prior art, and greatly improves the alignment accuracy of the self-limiting etching cavity 13 on the second side 152 of the substrate 15 and the device layer 10 on the first side 151 of the substrate 15 in the deep etching device.

[0047] Continue to refer Figure 1 and Figure 2 Optionally, the isolation layer 11 is located on a side of the device layer 10 close to the substrate 15 , and the corrosion barrier layer 12 is located on a side of the isolation layer 11 away from the device layer 10 .

[0048] Among them, Figure 1 and Figure 2 As shown, the substrate 15 can be a single-layer silicon substrate. The corrosion barrier layer 12 is first prepared on the first side 151 of the substrate 15, and then the isolation layer 11 is prepared on the first side 151 of the substrate 15 and on the side of the corrosion barrier layer 12 away from the substrate 15, so as to form a self-limiting corrosion cavity 13 on the first side 151 of the substrate 15 to limit the second side 152 of the substrate 15, so that the self-limiting corrosion cavity 13 is not affected by the error of double-sided lithography, which solves the problem of inaccurate alignment caused by the manual placement and alignment of the mask in the double-sided lithography process in the prior art, and improves the alignment accuracy of the self-limiting corrosion cavity 13 on the second side 152 of the substrate 15 and the device layer 10 on the first side 151 of the substrate 15 in the deep etching device.

[0049] Figure 3 A schematic cross-sectional view of another semiconductor structure provided by an embodiment of the present invention is shown in FIG. Figure 3As shown, optionally, the substrate 15 includes a first substrate section 21 and a second substrate section 22, and the second substrate section 22 is located on a side of the first substrate section 21 away from the device layer 10. The insulating layer 11 is located between the first substrate section 21 and the second substrate section 22, and the corrosion barrier layer 12 is located on a side of the device layer 10 close to the first corrosion cavity 14, and the corrosion barrier layer 12 runs through the first substrate section 21, the insulating layer 11 and at least a portion of the second substrate section 22.

[0050] Among them, Figure 3 As shown, the substrate 15 can be a SOI silicon wafer, which includes a first substrate portion 21, an insulating layer 11 and a second substrate portion 22, and the insulating layer 11 is located between the first substrate portion 21 and the second substrate portion 22. The corrosion barrier layer 12 is first prepared on the first side 151 of the substrate 15, and the corrosion barrier layer 12 penetrates the first substrate portion 21, the insulating layer 11 and at least a portion of the second substrate portion 22, so that a self-limiting corrosion cavity 13 is formed on the first side 151 of the substrate 15 to limit the second side 152 of the substrate 15, so that the self-limiting corrosion cavity 13 is not affected by the error of double-sided lithography, which solves the problem of inaccurate alignment caused by the manual placement and alignment of the mask in the double-sided lithography process in the prior art, and improves the alignment accuracy of the self-limiting corrosion cavity 13 on the second side 152 of the substrate 15 and the device layer 10 on the first side 151 of the substrate 15 in the deep etching device.

[0051] In addition, the use of SOI silicon wafers can omit the process step of preparing the isolation layer 11, thereby further simplifying the process.

[0052] Continue to refer Figure 1-3 Optionally, the vertical projection of the self-limiting corrosion chamber 13 on the plane where the device layer 10 is located is located within the vertical projection of the first corrosion chamber 14 on the plane where the device layer 10 is located, and the area of ​​the vertical projection of the first corrosion chamber 14 on the plane where the device layer 10 is located is larger than the area of ​​the vertical projection of the self-limiting corrosion chamber 13 on the plane where the device layer 10 is located.

[0053] Among them, Figure 1-3 As shown, a first etching cavity 14 is first prepared on the second side 152 of the substrate 15. By setting the area of ​​the first etching cavity 14 to be larger, the etching barrier layer 12 is exposed, so that the patterning process on the second side 152 of the substrate 15 can use the exposed etching barrier layer 12 for lithography alignment to form a self-limiting etching cavity 13, thereby making the self-limiting etching cavity 13 not affected by the error of double-sided lithography, solving the problem of inaccurate alignment caused by the manual placement and alignment of the mask in the double-sided lithography process in the prior art, and improving the alignment accuracy of the self-limiting etching cavity 13 on the second side 152 of the substrate 15 and the device layer 10 on the first side 151 of the substrate 15 in the deep etching device.

[0054] Optionally, the material of the isolation layer 11 includes silicon oxide or silicon nitride, and the material of the corrosion barrier layer 12 includes silicon oxide.

[0055] The isolation layer 11 is made of corrosion-resistant materials such as silicon oxide or silicon nitride, and the corrosion barrier layer 12 is made of corrosion-resistant materials such as silicon oxide, so as to limit the range of the self-limiting corrosion cavity 13.

[0056] In other embodiments, the insulating layer 11 and the corrosion barrier layer 12 may also be made of other corrosion-resistant materials, and those skilled in the art may configure them according to actual needs, which is not limited in the embodiments of the present invention.

[0057] Based on the same inventive concept, an embodiment of the present invention further provides a method for preparing a semiconductor structure, which is used to prepare any semiconductor structure provided by the above embodiments. The explanations of structures and terms that are the same as or corresponding to the above embodiments are not repeated here. Figure 4 A schematic diagram of a process for preparing a semiconductor structure provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, the method comprises the following steps:

[0058] Step 110: Provide a substrate.

[0059] The substrate may be made of silicon material or other materials, which is not limited in the embodiment of the present invention.

[0060] Step 120: forming an isolation layer and a corrosion barrier layer on the substrate.

[0061] The isolation layer and the corrosion barrier layer may be prepared from the first side of the substrate.

[0062] Step 130: Prepare a device layer on the first side of the substrate.

[0063] Among them, the device layer can be part of the final functional layer of the MEMS device. The device layer can be one layer or multiple layers. Each device layer can constitute a sub-functional layer. Each sub-functional layer can contain a single type of device or a mixture of various types of devices. Technical personnel in this field can set the device layer according to the preset functions.

[0064] Step 140: Prepare a first etching cavity on the second side of the substrate.

[0065] The first etching cavity may be prepared from the second side of the substrate.

[0066] Step 150, preparing a self-limiting corrosion cavity on the second side of the substrate, wherein the isolation layer and the corrosion barrier layer are located on a side of the self-limiting corrosion cavity close to the device layer, the self-limiting corrosion cavity is located in a space defined by the isolation layer and the corrosion barrier layer, the first corrosion cavity is located on a side of the self-limiting corrosion cavity away from the device layer, and the first corrosion cavity is connected to the self-limiting corrosion cavity.

[0067] Among them, the self-limiting corrosion cavity can be prepared by the second side of the substrate, and the self-limiting corrosion cavity is located in the space defined by the isolation layer and the corrosion barrier layer, so that the pattern of the second side of the substrate is defined by designing the pattern of the isolation layer and the corrosion barrier layer on the first side of the substrate, so that the patterns on the first side and the second side of the substrate can be positioned and aligned on the first side of the substrate. The process is simple and controllable. The self-limiting corrosion cavity formed by the corrosion barrier layer prepared on the first side of the substrate is not affected by the error of double-sided lithography, but is mainly affected by the error of single-sided lithography. The error of single-sided lithography can be controlled very small in modern semiconductor processes, which greatly improves the alignment accuracy of the self-limiting corrosion cavity on the second side of the substrate and the device layer on the first side of the substrate in the deep etching device.

[0068] Figure 5 A schematic diagram of a process for preparing another semiconductor structure provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, optionally, the substrate is a single-layer silicon substrate.

[0069] Forming an isolation layer and a corrosion barrier layer on the substrate, comprising:

[0070] A first cavity is etched on the first side of the substrate, and silicon oxide or silicon nitride is filled in the first cavity to form a corrosion barrier layer.

[0071] The isolation layer is formed on the first side of the substrate and on the side of the corrosion barrier layer away from the substrate.

[0072] Specifically, Figure 5As shown, the provided substrate 15 is a single-layer silicon substrate, a window of the corrosion barrier layer 12 is formed on the first side 151 of the substrate 15 by photolithography, and then the window is deep silicon etched to form a first cavity 23 corresponding to the corrosion barrier layer 12, and silicon oxide or silicon nitride is filled in the first cavity 23, thereby forming the corrosion barrier layer 12. An isolation layer 11 is prepared on the first side 151 of the substrate 15 and the side of the corrosion barrier layer 12 away from the substrate 15, and then a device layer 10 is made on the side of the isolation layer 11 away from the substrate 15, and an etching window of the first corrosion cavity 14 is formed on the second side 152 of the substrate 15 by double-sided photolithography, thereby forming the first corrosion cavity 14, and then etching is continued to form a self-limiting corrosion cavity 13. Among them, the self-limiting corrosion cavity 13 on the second side 152 of the substrate 15 is defined by designing the pattern of the isolation layer 11 and the corrosion barrier layer 12 on the first side 151 of the substrate 15, so that the device layer 10 on the first side 151 of the substrate 15 and the self-limiting corrosion cavity 13 on the second side 152 can be positioned and aligned on the first side 151 of the substrate 15. The process is simple and controllable. The self-limiting corrosion cavity 13 formed by the corrosion barrier layer 12 is not affected by the error of double-sided lithography, but is mainly affected by the error of single-sided lithography. The error of single-sided lithography can be controlled to be very small in modern semiconductor processes, which greatly improves the alignment accuracy of the self-limiting corrosion cavity 13 on the second side 152 of the substrate 15 and the device layer 10 on the first side 151 of the substrate 15 in the deep etching device.

[0073] Figure 6 A schematic diagram of a process for preparing another semiconductor structure provided by an embodiment of the present invention is shown in FIG. Figure 6 As shown, optionally, the substrate 15 is an SOI silicon wafer, and the SOI silicon wafer includes a first substrate portion 21 , an isolation layer 11 and a second substrate portion 22 , and the isolation layer 11 is located between the first substrate portion 21 and the second substrate portion 22 .

[0074] Forming an isolation layer and a corrosion barrier layer on the substrate, comprising:

[0075] A second cavity is etched on the first side of the substrate, and silicon oxide or silicon nitride is filled in the second cavity to form a corrosion barrier layer, wherein the corrosion barrier layer penetrates the first substrate portion, the isolation layer and at least a portion of the second substrate portion.

[0076] Specifically, Figure 6As shown, the provided substrate 15 is a SOI silicon wafer, and the SOI silicon wafer includes a first substrate sub-section 21, an isolation layer 11, and a second substrate sub-section 22. A window of the corrosion barrier layer 12 is formed by photolithography on the first side 151 of the substrate 15, and then the window is deep silicon etched to form a second cavity 24 corresponding to the corrosion barrier layer 12, and silicon oxide or silicon nitride is filled in the second cavity 24, thereby forming the corrosion barrier layer 12, wherein the corrosion barrier layer 12 penetrates the first substrate sub-section 21, the isolation layer 11, and at least a part of the second substrate sub-section 22. The device layer 10 is formed on the side of the first substrate sub-section 21 and the corrosion barrier layer 12 away from the substrate 15, and an etching window of the first etching cavity 14 is formed on the second side 152 of the substrate 15 by double-sided photolithography, thereby forming the first etching cavity 14, and then etching is continued to form the self-limiting etching cavity 13. Among them, the self-limiting corrosion cavity 13 on the second side 152 of the substrate 15 is defined by designing the pattern of the isolation layer 11 and the corrosion barrier layer 12 on the first side 151 of the substrate 15, so that the device layer 10 on the first side 151 of the substrate 15 and the self-limiting corrosion cavity 13 on the second side 152 can be positioned and aligned on the first side 151 of the substrate 15. The process is simple and controllable. The self-limiting corrosion cavity 13 formed by the corrosion barrier layer 12 is not affected by the error of double-sided lithography, but is mainly affected by the error of single-sided lithography. The error of single-sided lithography can be controlled to be very small in modern semiconductor processes, which greatly improves the alignment accuracy of the self-limiting corrosion cavity 13 on the second side 152 of the substrate 15 and the device layer 10 on the first side 151 of the substrate 15 in the deep etching device.

[0077] Continue to refer Figure 5 and Figure 6 Optionally, a first corrosion chamber 14 is prepared on the second side 152 of the substrate 15 by an anisotropic wet corrosion process or a deep silicon dry etching process, and a self-limiting corrosion chamber 13 is prepared on the second side 152 of the substrate 15 by an isotropic wet corrosion process or an anisotropic wet corrosion process.

[0078] For example, Figure 5 and Figure 6 As shown, taking the preparation of the first corrosion chamber 14 on the second side 152 of the substrate 15 by a deep silicon dry etching process and the preparation of the self-limiting corrosion chamber 13 on the second side 152 of the substrate 15 by an isotropic wet etching process as an example, wherein the corrosion solution used in the isotropic wet etching process is an acidic solution that can corrode silicon, such as a mixture of nitric acid and hydrofluoric acid, etc., and those skilled in the art can set it according to actual needs.

[0079] Figure 7 A schematic diagram of a process for preparing another semiconductor structure provided by an embodiment of the present invention is shown in FIG. Figure 7As shown, illustratively, taking the preparation of the first corrosion chamber 14 on the second side 152 of the substrate 15 by an anisotropic wet corrosion process and the preparation of the self-limiting corrosion chamber 13 on the second side 152 of the substrate 15 by an isotropic wet corrosion process as an example, the corrosion solution used in the anisotropic wet corrosion process is an alkaline solution that can corrode silicon, such as KOH solution, TMAH solution, etc.; the corrosion solution used in the isotropic wet corrosion process is an acidic solution that can corrode silicon, such as a mixture of nitric acid and hydrofluoric acid, etc., and those skilled in the art can make settings according to actual needs.

[0080] Figure 8 A schematic diagram of a process for preparing another semiconductor structure provided by an embodiment of the present invention is shown in FIG. Figure 8 As shown, illustratively, taking the preparation of the first corrosion chamber 14 on the second side 152 of the substrate 15 by a deep silicon dry etching process and the preparation of the self-limiting corrosion chamber 13 on the second side 152 of the substrate 15 by an anisotropic wet etching process as an example, the corrosion solution used in the anisotropic wet etching process is an alkaline solution that can corrode silicon, such as KOH solution, TMAH solution, etc., and those skilled in the art can set it according to actual needs.

[0081] Fig. 9 A schematic diagram of a process for preparing another semiconductor structure provided by an embodiment of the present invention is shown in FIG. Fig. 9 As shown, illustratively, taking the preparation of the first corrosion chamber 14 on the second side 152 of the substrate 15 by an anisotropic wet corrosion process and the preparation of the self-limiting corrosion chamber 13 on the second side 152 of the substrate 15 by an anisotropic wet corrosion process as an example, the corrosion solution used in the anisotropic wet corrosion process is an alkaline solution that can corrode silicon, such as KOH solution, TMAH solution, etc., and those skilled in the art can set it according to actual needs.

[0082] Continue to refer Figure 8 and Fig. 9 Optionally, a self-limiting etching cavity 13 is prepared on the second side 152 of the substrate 15 by an anisotropic wet etching process, and the etching surface of the substrate 15 is a (100) crystal plane.

[0083] The substrate 15 may be a single-layer silicon substrate or an SOI silicon wafer, such as Figure 8 and Fig. 9 As shown, taking the substrate 15 as a single-layer silicon substrate as an example, when a self-limiting corrosion cavity 13 is prepared on the second side 152 of the substrate 15 by an anisotropic wet etching process, the (100) crystal plane of the substrate 15 can be selected as the etching surface, thereby obtaining a self-limiting corrosion cavity 13 with a "V"-shaped cross-section.

[0084] In other embodiments, those skilled in the art may select different methods for preparing the self-limiting corrosion chamber 13 according to actual needs, and the embodiments of the present invention are not limited thereto.

[0085] The method for preparing a semiconductor structure provided by an embodiment of the present invention defines a self-limiting corrosion cavity on the second side of the substrate by designing patterns of an isolation layer and an etching barrier layer on the first side of the substrate, so that both the device layer on the first side of the substrate and the self-limiting corrosion cavity on the second side can be positioned and aligned on the first side of the substrate. The process is simple and controllable. The self-limiting corrosion cavity formed by the etching barrier layer is not affected by the error of double-sided lithography, but is mainly affected by the error of single-sided lithography. The error of single-sided lithography can be controlled to be very small in modern semiconductor processes, which greatly improves the alignment accuracy of the self-limiting corrosion cavity on the second side of the substrate and the device layer on the first side of the substrate in a deep etching device.

[0086] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor structure, characterized in that: It includes a device layer, an isolation layer, a corrosion barrier layer, a self-limiting corrosion chamber, a first corrosion chamber and a substrate; The device layer is located on the first side of the substrate, the first corrosion chamber and the self-limiting corrosion chamber are both formed on the second side of the substrate, the isolation layer and the corrosion barrier layer are located on the side of the first corrosion chamber close to the device layer, and the self-limiting corrosion chamber is located in the space defined by the isolation layer and the corrosion barrier layer; the first corrosion chamber is connected to the self-limiting corrosion chamber; The vertical projection of the self-limiting corrosion chamber on the plane where the device layer is located is located within the vertical projection of the first corrosion chamber on the plane where the device layer is located, and the area of ​​the vertical projection of the first corrosion chamber on the plane where the device layer is located is larger than the area of ​​the vertical projection of the self-limiting corrosion chamber on the plane where the device layer is located.

2. The semiconductor structure according to claim 1, characterized in that: The isolation layer is located on a side of the device layer close to the substrate, and the corrosion barrier layer is located on a side of the isolation layer away from the device layer.

3. The semiconductor structure according to claim 1, characterized in that: The substrate comprises a first substrate sub-portion and a second substrate sub-portion, wherein the second substrate sub-portion is located at a side of the first substrate sub-portion away from the device layer; The insulating layer is located between the first substrate section and the second substrate section; The corrosion barrier layer is located on a side of the device layer close to the first corrosion cavity, and the corrosion barrier layer penetrates the first substrate section, the isolation layer and at least a portion of the second substrate section.

4. The semiconductor structure according to claim 1, characterized in that: The material of the isolation layer includes silicon oxide or silicon nitride, and the material of the corrosion barrier layer includes silicon oxide.

5. A method for preparing a semiconductor structure, used for preparing the semiconductor structure according to any one of claims 1 to 4, characterized in that: include: providing a substrate; forming an isolation layer and a corrosion barrier layer on the substrate; preparing a device layer on a first side of the substrate; preparing a first etching cavity on the second side of the substrate; A self-limiting corrosion cavity is prepared on the second side of the substrate, wherein the isolation layer and the corrosion barrier layer are located on a side of the self-limiting corrosion cavity close to the device layer, the self-limiting corrosion cavity is located in a space defined by the isolation layer and the corrosion barrier layer, the first corrosion cavity is located on a side of the self-limiting corrosion cavity away from the device layer, and the first corrosion cavity is connected to the self-limiting corrosion cavity.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The substrate is a single-layer silicon substrate; Forming an isolation layer and a corrosion barrier layer on the substrate, comprising: Etching a first cavity on a first side of the substrate, and filling the first cavity with silicon oxide or silicon nitride to form a corrosion barrier layer; The isolation layer is formed on the first side of the substrate and on the side of the corrosion barrier layer away from the substrate.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that: The substrate is an SOI silicon wafer, and the SOI silicon wafer comprises a first substrate sub-part, the isolation layer and a second substrate sub-part, and the isolation layer is located between the first substrate sub-part and the second substrate sub-part; Forming an isolation layer and a corrosion barrier layer on the substrate, comprising: A second cavity is etched on the first side of the substrate, and silicon oxide or silicon nitride is filled in the second cavity to form a corrosion barrier layer, wherein the corrosion barrier layer penetrates the first substrate portion, the isolation layer and at least a portion of the second substrate portion.

8. The method for preparing a semiconductor structure according to claim 5, characterized in that: preparing a first etching cavity on the second side of the substrate by an anisotropic wet etching process or a deep silicon dry etching process; A self-limiting etching cavity is prepared on the second side of the substrate by an isotropic wet etching process or an anisotropic wet etching process.

9. The method for preparing a semiconductor structure according to claim 5, characterized in that: A self-limiting etching cavity is prepared on the second side of the substrate by an anisotropic wet etching process, and the etching surface of the substrate is a (100) crystal plane.

Images