Multi-layer structure

Abstract

The present invention discloses a multi-layer structure, including a substrate and a plurality of sub-stacks. The sub-stacks respectively extend along a first direction and are arranged on an upper surface of the substrate along a second direction. Each sub-stack includes a plurality of insulating layers and a plurality of patterned sacrificial layers alternately stacked on the upper surface along a third direction, a plurality of conductive layers alternately stacked with the insulating layers on the upper surface along the third direction, and a plurality of interlayer connectors extending along the third direction. Among them, the patterned sacrificial layer has a first side and a second side opposite to the first side, and the conductive layer includes a plurality of first-side conductive layers corresponding to the first side and a plurality of second-side conductive layers corresponding to the second side. Among them, the interlayer connectors are electrically connected and directly contact the corresponding conductive layers. The first direction, the second direction, and the third direction intersect each other.

Description

Technical Field

[0001] The present invention relates to a multi-layer structure and a manufacturing method thereof, and more particularly to a multi-layer structure for a semiconductor device and a manufacturing method thereof. Background Art

[0002] In a semiconductor device or between different semiconductor devices, electrical connections between components are usually required through interlayer connectors in a multi-layer structure. Generally, the multi-layer structure includes a plurality of conductive layers and a plurality of insulating layers alternately stacked on a substrate, and the interlayer connectors formed of a conductive material extend along a vertical direction and are electrically connected to specific conductive layers. However, as the number of layers of the multi-layer structure increases, the amount of conductive material required also increases, and the process becomes more complicated, which may greatly increase the manufacturing cost.

[0003] Therefore, it is necessary to propose an advanced multi-layer structure and a manufacturing method thereof to solve the problems faced by the known technology. Summary of the Invention

[0004] The present invention relates to a multi-layer structure and a manufacturing method thereof. Since a plurality of conductive layers and a plurality of interlayer connectors can be formed together by the same conductor process, the process method of the present case can reduce the complexity of the process and reduce the cost.

[0005] According to one aspect of the present invention, a multi-layer structure is provided. The multi-layer structure includes a substrate and a plurality of sub-stacks. The sub-stacks respectively extend along a first direction and are arranged on an upper surface of the substrate along a second direction. Each sub-stack includes a plurality of insulating layers and a plurality of patterned sacrificial layers alternately stacked on the upper surface along a third direction, a plurality of conductive layers alternately stacked with the insulating layers on the upper surface along the third direction, and a plurality of interlayer connectors extending along the third direction. Among them, the patterned sacrificial layer has a first side and a second side opposite to the first side, and the conductive layer includes a plurality of first-side conductive layers corresponding to the first side and a plurality of second-side conductive layers corresponding to the second side. Among them, the interlayer connector is electrically connected and directly contacts the corresponding conductive layer. The first direction, the second direction, and the third direction intersect each other.

[0006] According to one aspect of the present invention, a method for manufacturing a multi-layer structure is provided. The method includes the following steps. First, a substrate is provided, and the substrate has an upper surface. Then, a stacked body is formed on the upper surface of the substrate, wherein the stacked body includes a plurality of insulating layers and a plurality of sacrificial layers alternately stacked on the upper surface. Next, a plurality of vertical openings are formed, and the vertical openings penetrate through some of the insulating layers and sacrificial layers. A plurality of channels are formed, and the channels penetrate through the stacked body and expose the lowermost insulating layer in the insulating layers. Part of the sacrificial layers are removed, and a plurality of lateral openings are formed at the positions where the sacrificial layers are removed, wherein the remaining sacrificial layers form a plurality of patterned sacrificial layers. Thereafter, a conductive material is filled in the vertical openings and the lateral openings to form a plurality of interlayer connectors in the vertical openings and a plurality of conductive layers in the lateral openings, wherein the interlayer connectors, the conductive layers, the patterned sacrificial layers, and the insulating layers constitute a plurality of sub-stacked layers, wherein the sub-stacked layers respectively extend along a first direction and are arranged on the upper surface of the substrate along a second direction, and the interlayer connectors extend along a third direction, wherein the first direction, the second direction, and the third direction intersect with each other. Wherein, the patterned sacrificial layers have a plurality of first sides and a plurality of second sides opposite to the first sides, and the conductive layers include a plurality of first-side conductive layers corresponding to the first sides and a plurality of second-side conductive layers corresponding to the second sides. Wherein, the interlayer connectors are electrically connected and directly contact the corresponding conductive layers.

[0007] For a better understanding of the above and other aspects of the present invention, the following specific embodiments are given, and are described in detail in conjunction with the accompanying drawings as follows: Description of the Drawings

[0008] Figure 1A A top view showing a method for manufacturing a multi-layer structure according to an embodiment of the present invention.

[0009] Figure 1B Showing along Figure 1A A cross-sectional view taken along the line 1B-1B' of.

[0010] Figure 2A Showing subsequent to Figure 1A A top view of the method for manufacturing a multi-layer structure of.

[0011] Figure 2B Showing along Figure 2A A cross-sectional view taken along the line 2B-2B' of.

[0012] Figure 3 Showing subsequent to Figure 2B A cross-sectional view of the method for manufacturing a multi-layer structure of.

[0013] Figure 4 Showing subsequent to Figure 3 A cross-sectional view of the method for manufacturing a multi-layer structure of.

[0014] Figure 5 A cross-sectional view showing the manufacturing method of a multi-layer structure connected to Figure 4 .

[0015] Figure 6 A cross-sectional view showing the manufacturing method of a multi-layer structure connected to Figure 5 .

[0016] Figure 7 A cross-sectional view showing the manufacturing method of a multi-layer structure connected to Figure 6 .

[0017] Figure 8 A cross-sectional view showing the manufacturing method of a multi-layer structure connected to Figure 7 .

[0018] Figure 9 A cross-sectional view showing the manufacturing method of a multi-layer structure connected to Figure 8 .

[0019] Figure 10A A top view showing the manufacturing method of a multi-layer structure connected to Figure 9 .

[0020] Figure 10B A cross-sectional view showing the manufacturing method of a multi-layer structure connected to Figure 9 .

[0021] Figure 11 A cross-sectional view showing the manufacturing method of a multi-layer structure connected to Figure 10B .

[0022] Figure 12 A cross-sectional view showing the manufacturing method of a multi-layer structure connected to Figure 11 .

[0023] Figure 13 A cross-sectional view showing the manufacturing method of a multi-layer structure connected to Figure 12 .

[0024] Figure 14 A cross-sectional view showing the manufacturing method of a multi-layer structure connected to Figure 13 .

[0025] Figure 15 A cross-sectional view showing the manufacturing method of a multi-layer structure connected to Figure 14 .

[0026] Figure 16 A cross-sectional view showing the manufacturing method of a multi-layer structure connected to Figure 15 .

[0027] Figure 17A A top view showing the manufacturing method of a multi-layer structure connected to Figure 16 .

[0028] Figure 17B Shows a cross-sectional view of a method for manufacturing a multi-layer structure connected to Figure 16 .

[0029] Figure 18 Shows a cross-sectional view of a method for manufacturing a multi-layer structure connected to Figure 17B .

[0030] Figure 19 Shows a cross-sectional view of a method for manufacturing a multi-layer structure connected to Figure 18 .

[0031] Figure 20 Shows a cross-sectional view of a method for manufacturing a multi-layer structure connected to Figure 19 .

[0032] Figure 21 Shows a cross-sectional view of a method for manufacturing a multi-layer structure connected to Figure 20 .

[0033] Figure 22A Shows a cross-sectional view of a method for manufacturing a multi-layer structure connected to Figure 21 Top view of the method for manufacturing the multi-layer structure.

[0034] Figure 22B Shows a cross-sectional view of a method for manufacturing a multi-layer structure connected to Figure 21 .

[0035] Figure 23A Shows a cross-sectional view of a method for manufacturing a multi-layer structure connected to Figure 22A Top view of the method for manufacturing the multi-layer structure.

[0036] Figure 23B Shows a cross-sectional view of a method for manufacturing a multi-layer structure connected to Figure 22B .

[0037] Figure 24 Shows a cross-sectional view of a method for manufacturing a multi-layer structure connected to Figure 23B .

[0038] Figure 25A Shows a cross-sectional view of a method for manufacturing a multi-layer structure connected to Figure 24 Top view of the method for manufacturing the multi-layer structure.

[0039] Figure 25B Shows a cross-sectional view of a method for manufacturing a multi-layer structure connected to Figure 24 .

[0040] Figure 25C Shows a cross-sectional view of a method for manufacturing a multi-layer structure connected to Figure 24 .

[0041] Figure 26A Shows a top view of a multi-layer structure after forming upper vias according to another embodiment of the present invention.

[0042] Figure 26B Shows a cross-sectional view along the Figure 26A connection line 26B - 26B'.

[0043] Figure 27A Shows a top view of the manufacturing method of the multi-layer structure 200 following Figure 26A .

[0044] Figure 27B Shows a cross-sectional view along the Figure 27A connection line 27B - 27B'.

[0045] Figure 27C Shows Figure 27A a simplified perspective view of.

[0046] Figure 28 Shows a cross-sectional view of a multi-layer structure according to another embodiment of the present invention.

[0047]

Symbol Explanation

[0048] 100, 200, 300: Multi-layer structure

[0049] 101, 301: Substrate

[0050] 101a: Upper surface

[0051] 102, 202, 302, 1021, 1022, 1023, 1024, 1025, 1026, 1027, 1028, 1029: Insulating layer

[0052] 104, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048: Sacrificial layer

[0053] 104t, 204t, 1041t, 1042t, 1043t, 1044t, 1045t, 1046t, 1047t, 1048t: Patterned sacrificial layer

[0054] 112: First initial mask

[0055] 112p: First initial mask opening

[0056] 114: First initial through-hole

[0057] 116: Second initial mask

[0058] 116p: Second initial mask opening

[0059] 118: Second initial through-hole

[0060] 120: Third initial mask

[0061] 120p: Third initial mask opening

[0062] 122: Third initial via hole

[0063] 124: Etch-back opening

[0064] 126, 226, 326: Protective layer

[0065] 128a: First flat layer

[0066] 128b: Second flat layer

[0067] 130: Etching mask

[0068] 130p: Etching mask opening

[0069] 132: First etching via hole

[0070] 134: Second etching via hole

[0071] 136: Patterned mask

[0072] 136p: Patterned mask opening

[0073] 138: Channel

[0074] 140a: Vertical opening

[0075] 140b: Lateral opening

[0076] 142: Barrier layer

[0077] 144': Conductive material

[0078] 144a, 244a, 344a: Interlayer connector

[0079] 144b, 244b, 344b: Conductive layer

[0080] 144bB, 244bB: Second side conductive layer

[0081] 144bF, 244bF: First side conductive layer

[0082] 146: Trimming mask

[0083] 146p: Trimming mask opening

[0084] 150, 250: Oxide material

[0085] 250p: Upper opening

[0086] 252, 252A1, 252A2, 252C1, 252C2, 252H1, 252H2: Upper via hole

[0087] 254, 354, 2541, 2542, 2543, 2544, 2545, 2546, 2547, 2548, 2549: Conductors

[0088] 301V: Substrate via hole

[0089] 353: Insulating material layer

[0090] 370A, 370B, 370C: Chips

[0091] A, B, C, D, E, F, G, F, H, I, II, III, IV, V, VI, VII, VIII, IX, X, XI, XII, XIII, XIV, AIV, BIV, CIV, DIV: Positions

[0092] EN: Etching logarithm

[0093] IP: Signal input terminal

[0094] OP: Signal output terminal

[0095] L1: First length

[0096] L2: Second length

[0097] P1: First etching path

[0098] P2: Second etching path

[0099] R1, R2, R3: Contact areas

[0100] S1': Stacked body

[0101] SS1': Sub-stacked body

[0102] SS1, SS2, SS3, SS4, ST1, ST2, ST3, ST4, SU: Sub-stacks

[0103] MN: Coordinates

[0104] W1, W2, W3, W4: Coordinates Detailed implementation manners

[0105] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0106] Figures 1A to 25C The top view and cross-sectional view of the manufacturing method of the multi-layer structure 100 according to an embodiment of the present invention are shown.

[0107] Figure 1AA top view showing a method of manufacturing a multi-layer structure 100 according to an embodiment of the present invention. Figure 1B Showing along Figure 1A A cross-sectional view taken along the line 1B-1B'.

[0108] Please refer to Figure 1A and Figure 1B simultaneously. A substrate 101 is provided, and a stacked body S1' is formed on the upper surface 101a of the substrate 101. The stacked body S1' includes a plurality of insulating layers 102 and a plurality of sacrificial layers 104 alternately stacked on the upper surface 101a of the substrate 101 (for example, by a deposition process). In this embodiment, there are 9 insulating layers 102, which are insulating layers 1021 to 1029 from bottom to top, and 8 sacrificial layers 104, which are sacrificial layers 1041 to 1048 from bottom to top. However, the present invention is not limited thereto, and in other embodiments, the number of insulating layers 102 and sacrificial layers 104 can be adjusted according to requirements. In this embodiment, the bottommost insulating layer 1021 has a greater thickness than the other insulating layers 1022 to 1029. However, the present invention is not limited thereto.

[0109] In some embodiments, the substrate 101 can be a silicon substrate or other suitable substrate, and the substrate 101 can be electrically connected to a complementary metal oxide semiconductor (CMOS) (not shown) or other suitable components. The insulating layer 102 can be formed of an oxide, such as silicon dioxide (SiO 2 ). The sacrificial layer 104 can be formed of a nitride, such as silicon nitride (SiN).

[0110] In Figure 1A , the numbers 0 to 7 marked in the stacked body S1' represent the number of pairs of insulating layers 102 and sacrificial layers 104 that the third initial via 122 (shown in Figure 10B ) passes through in the subsequent process. Similarly, the number of pairs of insulating layers 102 and sacrificial layers 104 that the third initial via 122 (shown in Figure 10B ) passes through is represented by the etching logarithm EN of 0 to 7 in Figure 1B . The third initial via 122 (shown in Figure 10B ) extends, for example, along the normal direction of the upper surface 101a of the substrate 101. In this embodiment, the third initial via 122 (shown in Figure 10B ) is formed at a predetermined position in an array arranged in columns A to H and rows I to VIII. For example, the predetermined position of the third initial via 122 in the second row of column A (shown in Figure 10B ) is marked as 1, indicating that the third initial via 122 in the second row of column A (shown in Figure 10B(in the figure) passes through a pair of insulating layers 102 and sacrificial layer 104, that is, passes through the uppermost insulating layer 1029 and sacrificial layer 1048; the third initial via hole 122 in the 4th row of column A (shown in Figure 10B (in the figure), the predetermined position is marked as 3, indicating that the third initial via hole 122 in the 4th row of column A (shown in Figure 10B (in the figure) passes through 3 pairs of insulating layers 102 and sacrificial layer 104, that is, passes through insulating layers 1029, 1028, 1027 and sacrificial layers 1048, 1047, 1046. However, the present invention is not limited thereto. In other embodiments, the number of pairs of insulating layers 102 and sacrificial layer 104 that the initial via hole passes through may vary according to design requirements.

[0111] Figure 1B (in the figure), the coordinates MN represent the predetermined positions AI to AVIII of the third initial via hole 122 (shown in Figure 10B (in the figure). For example, when the coordinates MN are AIII, it represents the predetermined position corresponding to the third initial via hole 122 in the 3rd row of column A (shown in Figure 10B (in the figure), and the predetermined etching logarithm EN is 2, indicating that the third initial via hole 122 (shown in Figure 10B (in the figure) will pass through 2 pairs of insulating layers 102 and sacrificial layer 104, that is, pass through insulating layers 1029, 1028, 1027, 1026 and sacrificial layers 1048, 1047, 1046, 1045. For example, when the coordinates MN are AV, it represents the predetermined position corresponding to the third initial via hole 122 in the 5th row of column A (shown in Figure 10B (in the figure), and the predetermined etching logarithm EN is 2, indicating that the third initial via hole 122 (shown in Figure 10B (in the figure) will pass through 2 pairs of insulating layers 102 and sacrificial layer 104, that is, pass through insulating layers 1029, 1028 and sacrificial layers 1048, 1047.

[0112] Figure 2A (The figure) shows a top view of the manufacturing method of the multilayer structure 100 following Figure 1A (in the figure). Figure 2B (The figure) shows a cross-sectional view along the Figure 2A 2B - 2B' connection line in (the figure).

[0113] Please refer to Figure 2A and Figure 2B (in the figure) at the same time. A first initial mask 112 is formed on the stacked body S1', and a plurality of first initial mask openings 112p passing through the first initial mask 112 are formed. In Figure 2B (in the figure), the first initial mask openings 112p correspond to the positions where the coordinates MN are AII, AIV, AVI and AVIII. The first initial mask 112 is formed of a photoresist material, for example.

[0114] Figure 3 A cross-sectional view showing a method of fabricating a multi-layer structure 100 that is connected to Figure 2B .

[0115] Please refer to Figure 3 , a pair (2 0 pairs) of the insulating layer 102 and the sacrificial layer 104 are removed through an etching process by the first initial mask opening 112p to form a plurality of first initial through-holes 114 exposing the insulating layer 1028. In some embodiments, each pair of the insulating layer 102 and the sacrificial layer 104 will have a consistent etching time for the performed etching process.

[0116] Figure 4 A cross-sectional view showing a method of fabricating a multi-layer structure 100 that is connected to Figure 3 .

[0117] Please refer to Figure 4 , the first initial mask 112 is removed.

[0118] Figure 5 A cross-sectional view showing a method of fabricating a multi-layer structure 100 that is connected to Figure 4 .

[0119] Please refer to Figure 5 , a second initial mask 116 is formed on the stacked body S1', and a plurality of second initial mask openings 116p passing through the second initial mask 116 are formed. In this embodiment, the second initial mask 116 covers a part of the first initial through-holes 114 (for example, the positions corresponding to the coordinates MN being AII and AVI), exposes other parts of the first initial through-holes 114 (for example, the positions corresponding to the coordinates MN being AIV and AVIII), and exposes a part of the insulating layer 1029 (for example, the positions corresponding to the coordinates MN being AIII and AVII).

[0120] Figure 6 A cross-sectional view showing a method of fabricating a multi-layer structure 100 that is connected to Figure 5 .

[0121] Please refer to Figure 6 , 2 pairs (2 1 pairs) of the insulating layer 102 and the sacrificial layer 104 are removed through an etching process by the second initial mask opening 116p to form a plurality of second initial through-holes 118 exposing the insulating layer 1026 or 1027. For example, the second initial through-holes 118 at the positions AIII and AVII expose the insulating layer 1026, and the second initial through-holes 118 at the positions AIV and AVIII expose the insulating layer 1027.

[0122] Figure 7 A cross-sectional view showing a method of fabricating a multi-layer structure 100 that is connected to Figure 6 .

[0123] Please refer to Figure 7 and remove the second initial mask 116 to further form a plurality of second initial vias 118 exposing the insulating layer 1028. For example, the second initial vias 118 at positions AII and AVI expose the insulating layer 1026.

[0124] Figure 8 Illustrates a cross-sectional view of a method of manufacturing the multilayer structure 100 following Figure 7 .

[0125] Please refer to Figure 8 and form a third initial mask 120 on the stacked body S1' and form a plurality of third initial mask openings 120p through the third initial mask 120. In this embodiment, the third initial mask 120 covers a part of the second initial vias 118 (for example, the positions corresponding to AII to AIV of the coordinate MN), exposes other parts of the second initial vias 118 (for example, the positions corresponding to AVI to AVIII of the coordinate MN), and exposes a part of the insulating layer 1029 (for example, the position corresponding to AV of the coordinate MN).

[0126] Figure 9 Illustrates a cross-sectional view of a method of manufacturing the multilayer structure 100 following Figure 8 .

[0127] Please refer to Figure 9 and remove 4 pairs (2 2 pairs) of the insulating layer 102 and the sacrificial layer 104 through the third initial mask openings 120p by an etching process to form a plurality of third initial vias 122 exposing the insulating layers 1022, 1023, 1024, or 1025. For example, the third initial via 122 at position AV exposes the insulating layer 1025, the third initial via 118 at position AVI exposes the insulating layer 1024, the third initial via 118 at position AVII exposes the insulating layer 1023, and the third initial via 118 at position AVIII exposes the insulating layer 1022.

[0128] Figure 10A Illustrates a top view of a method of manufacturing the multilayer structure 100 following Figure 9 . Figure 10B Illustrates a cross-sectional view of a method of manufacturing the multilayer structure 100 following Figure 9 , wherein Figure 10B illustrates a cross-sectional view along the Figure 10A 10B - 10B' connection line.

[0129] Please also refer to Figure 10A and Figure 10B, the third initial mask 120 is removed, and a plurality of third initial vias 122 are further formed to expose the insulating layers 1026-1028. For example, the third initial via 122 at position AII exposes the insulating layer 1028, the third initial via 122 at position AIII exposes the insulating layer 1027, and the third initial via 122 at position AIV exposes the insulating layer 1026. The plurality of third initial vias 122 are for forming the interlayer connectors 144a (shown in Figure 22B ), and initially define the relative height between the interlayer connectors 144a (shown in Figure 22B ).

[0130] Figure 11 Shown is a cross-sectional view of the manufacturing method of the multilayer structure 100 following Figure 10B .

[0131] Please refer to Figure 11 , and through an etching process, part of the sacrificial layer 104 is removed through the third initial vias 122 to form a plurality of etch openings 124. This etching process is carried out, for example, by hot phosphoric acid (H 3 PO 4 ).

[0132] Figure 12 Shown is a cross-sectional view of the manufacturing method of the multilayer structure 100 following Figure 11 .

[0133] Please refer to Figure 12 , and a protective layer 126 conformal to the etch openings 124 is formed through a deposition process. This deposition process is, for example, atomic layer deposition (ALD). The protective layer 126 is formed, for example, of a dielectric material, and the dielectric material is, for example, silicon dioxide (SiO 2 ).

[0134] Figure 13 Shown is a cross-sectional view of the manufacturing method of the multilayer structure 100 following Figure 12 .

[0135] Please refer to Figure 13 , and a first planar layer 128a is formed on the protective layer 126 through a deposition process. The first planar layer 128a is formed, for example, of an organic dielectric material. Then, an etch mask 130 is formed on the first planar layer 128a, and a plurality of etch mask openings 130p exposing the first planar layer 128a are formed. The first planar layer 128a can provide a flat deposition surface for the etch mask 130, and the etch mask 130 can be in direct contact with the first planar layer 128a. The etch mask openings 130p correspond to the formation positions of the interlayer connectors 144a (shown in Figure 22B ) in the subsequent process. At Figure 13In the figure, the etching mask opening 130p corresponds to positions AI to AVIII.

[0136] Figure 14 Shows a cross-sectional view of a method for manufacturing the multi-layer structure 100 that continues from Figure 13 the above.

[0137] Please refer to Figure 14 , through an etching process, part of the first flat layer 128a is removed through the etching mask opening 130p to form a plurality of first etching through-holes 132 that expose the protective layer 126.

[0138] Figure 15 Shows a cross-sectional view of a method for manufacturing the multi-layer structure 100 that continues from Figure 14 the above.

[0139] Please refer to Figure 15 , through an etching process, the protective layer 126 and an insulating layer 102 located below the first etching through-hole 132 are removed through the first etching through-hole 132 to form a plurality of second etching through-holes 134 that expose the sacrificial layer 104.

[0140] Figure 16 Shows a cross-sectional view of a method for manufacturing the multi-layer structure 100 that continues from Figure 15 the above.

[0141] Please refer to Figure 16 , the etching mask 130 is removed. The second etching through-holes 134 may have different depths and respectively pass through part of the stacked body S1' and the protective layer 126.

[0142] Figure 17A Shows a top view of a method for manufacturing the multi-layer structure 100 that continues from Figure 16 the above. Figure 17B Shows a cross-sectional view of a method for manufacturing the multi-layer structure 100 that continues from Figure 16 the above, where Figure 17B shows a cross-sectional view along the Figure 17A connection line 17B - 17B' above.

[0143] Please also refer to Figure 17A and Figure 17B , through a deposition process, a second flat layer 128b is formed on the protective layer 126 and in the second etching through-holes 134. The second flat layer 128b is formed of, for example, an organic dielectric material. Then, a patterned mask 136 is formed on the second flat layer 128b, and a plurality of patterned mask openings 136p that expose the second flat layer 128b are formed. The second flat layer 128b can provide a flat deposition surface for the patterned mask 136, and the patterned mask 136 can be in direct contact with the second flat layer 128b. In Figure 17BExemplarily shown are positions AIV, BIV, CIV, and DIV. In the normal direction of the upper surface 101a of the substrate 101, the patterned mask opening 136p does not overlap with the second etching through-hole 134.

[0144] Figure 18 Shown is a cross-sectional view of the manufacturing method of the multilayer structure 100 following Figure 17B .

[0145] Please refer to Figure 18 , and through an etching process, part of the second planarization layer 128b and the stacked body S1' are removed through the patterned mask opening 136p to form a plurality of channels 138 exposing the lowermost insulating layer 1021 in the insulating layer 102. The channels 138 extend along a first direction (e.g., the X direction) and pass through all the sacrificial layers 104 along a third direction (e.g., the Z direction), dividing the stacked body S1' into a plurality of sub-stacked bodies (e.g., SS1' and SS2') arranged along a second direction (e.g., the Y direction). Figure 18 Exemplarily shown are 2 of the sub-stacked bodies, but the present invention is not limited thereto. In some embodiments, the first direction, the second direction, and the third direction intersect each other, that is, there is a non-flat angle between the first direction, the second direction, and the third direction respectively. For example, the included angle between the first direction and the second direction can be 90°, the included angle between the second direction and the third direction can be 90°, and the included angle between the first direction and the third direction can be 90°.

[0146] Figure 19 Shown is a cross-sectional view of the manufacturing method of the multilayer structure 100 following Figure 18 .

[0147] Please refer to Figure 19 , remove the patterned mask 136 and the second planarization layer 128b to expose a plurality of vertical openings 140a. The vertical openings 140a pass through part of the insulating layer 102 and the sacrificial layer 104, and the bottom of the vertical openings 140a exposes the corresponding sacrificial layer 104.

[0148] Figure 20 Shown is a cross-sectional view of the manufacturing method of the multilayer structure 100 following Figure 19 .

[0149] Please refer to Figure 20, through an etching process, a portion of the sacrificial layer 104 is selectively removed through the vertical opening 140a and the channel 138. The sacrificial layer 104 located in the middle part of the sub-stack body (such as SS1' and SS2') is retained, forming a patterned sacrificial layer 104t (including patterned sacrificial layers 1041t to 1048t). The positions where the sacrificial layer 104 is removed thus form lateral openings 140b in the sub-stack body (such as SS1' and SS2'). This etching process is, for example, carried out by an etchant of hot phosphoric acid.

[0150] In some embodiments, the etching process can remove the portion of the sacrificial layer 104 that is not adjacent to the vertical opening 140a via a first etching path P1 from the side of the channel 138. For example, at Figure 20 the position BIV, the portions of the sacrificial layers 1041 to 1045 that are not adjacent to the vertical opening 140a are removed via the first etching path P1 from the side of the channel 138.

[0151] In some embodiments, since the etchant can flow in from above the vertical opening 140a, the etching process can remove the portion of the sacrificial layer 104 adjacent to the bottom of the vertical opening 140a not only via the first etching path P1 from the side of the channel 138 but also via a second vertical etching path P2 from the vertical opening 140a. The protective layer 126 on the sidewall of the vertical opening 140a can block the inflow of the etchant, so the portion of the sacrificial layer 104 adjacent to the protective layer 126 is not removed. For example, at Figure 20 the position BIV, the portion of the sacrificial layer 1046 adjacent to the vertical opening 140a is removed via the first etching path P1 from the side of the channel 138 and the second vertical etching path P2 from the vertical opening 140a. In addition, the portions of the sacrificial layers 1047 and 1048 adjacent to the protective layer 126 on the sidewalls of the vertical opening 140a at the positions BIV and AIV are not removed because they are protected by the protective layer 126.

[0152] Figure 21 Shows a cross-sectional view of the manufacturing method of the multi-layer structure 100 following Figure 20 of.

[0153] Please refer to Figure 21, a barrier layer 142 is deposited on the sidewalls of the vertical opening 140a and the lateral opening 140b. Then, a conductive material 144' is filled into the vertical opening 140a and the lateral opening 140b through a conductor process, and the conductive material 144' covers the sub-stack body (such as SS1' and SS2'). The conductor process can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), or electroplating. The barrier layer 142 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten titanium (WTi), or other suitable materials. The conductive material 144' is, for example, tungsten (W), copper (Cu), or other suitable materials.

[0154] Figure 22A Shows a top view of the manufacturing method of the multi-layer structure 100 following Figure 21 . Figure 22B Shows a cross-sectional view of the manufacturing method of the multi-layer structure 100 following Figure 21 , where Figure 22B Shows a cross-sectional view along the line 22B - 22B' of Figure 22A .

[0155] Please refer to Figure 22A and Figure 22B simultaneously. Remove the conductive material 144' outside the vertical opening 140a and the lateral opening 140b to form an interlayer connector 144a in the vertical opening 140a and a conductive layer 144b in the lateral opening 140b. Pattern the sacrificial layer 104t, the conductive layer 144b, and the insulating layer 102 to form a plurality of sub-stacks (such as SS1, SS2,... etc.) arranged along the second direction (such as the Y direction). Since the interlayer connector 144a and the conductive layer 144b are an integral structure formed simultaneously through the same conductor process, the interlayer connector 144a is in direct contact with the underlying conductive layer 144b, and there is no other layer (such as a barrier layer) in the contact area R1 between the interlayer connector 144a and the underlying conductive layer 144b.

[0156] For example, at the position BIV of Figure 22B , the interlayer connector 144a is in direct contact with the corresponding conductive layer 1046. The interlayer connector 144a and the conductive layer 1046 are a continuous integral structure, and there is no other layer (such as a barrier layer) in the contact area R1 between the interlayer connector 144a and the conductive layer 1046.

[0157] According to some embodiments of the present invention, the patterned sacrificial layer 104t is located in the middle part of each sub-stack (such as SS1, SS2, etc.). Each patterned sacrificial layer 104t has a first side FS and a second side BS opposite to the first side FS. The conductive layer 144b corresponding to the first side FS is called the first-side conductive layer 144bF, and the conductive layer 144b corresponding to the second side BS is called the second-side conductive layer 144bB. In the second direction (such as the Y direction), the patterned sacrificial layer 104t is located between the first-side conductive layer 144bF and the second-side conductive layer 144bB.

[0158] Figure 23A Shows a top view of the manufacturing method of the multi-layer structure 100 following Figure 22A . Figure 23B Shows a cross-sectional view of the manufacturing method of the multi-layer structure 100 following Figure 22B , where Figure 23B Shows a cross-sectional view along the line 23B - 23B' of Figure 23A .

[0159] Please refer to Figure 23A and Figure 23B simultaneously. A trimming mask 146 is formed on the protective layer 126, and a plurality of trimming mask openings 146p exposing the bottommost insulating layer 1021 are formed. In some embodiments, the trimming mask openings 146p are used to remove the redundant portions of the conductive layer 144b to avoid short circuits.

[0160] Figure 24 Shows a cross-sectional view of the manufacturing method of the multi-layer structure 100 following Figure 23B .

[0161] Please refer to Figure 24 . The redundant portions of the conductive layer 144b are removed through an etching process. The etching process is, for example, an isotropic etching process.

[0162] Figure 25A Shows a top view of the manufacturing method of the multi-layer structure 100 following Figure 24 . Figure 25B Shows a cross-sectional view of the manufacturing method of the multi-layer structure 100 following Figure 24 , where Figure 25B Shows a cross-sectional view along the line 25B - 25B' of Figure 25A . Figure 25C Shows a cross-sectional view of the manufacturing method of the multi-layer structure 100 following Figure 24 , where Figure 25C Shows a cross-sectional view along the line 25C - 25C' of Figure 25A .

[0163] Please refer to Figures 25A to 25C, the trimming mask 146 is removed, after which the oxide material 150 is deposited on the protective layer 126, on the bottommost insulating layer 1021, and in the positions where the redundant portions of the conductive layer 144b are removed, forming the multilayer structure 100. In other words, the oxide material 150 covers the sub-stacks SS1, SS2, SS3, and SS4 and fills the spaces between the sub-stacks SS1, SS2, SS3, and SS4. Figure 25A The maximum widths of the first-side conductive layer 244bF and the second conductive layer 244bB in the second direction (e.g., the Y direction) are respectively exemplarily illustrated in the top view. For the width relationships of the first-side conductive layer 244bF between different layers and the width relationships of the second conductive layer 244bB between different layers, please refer to Figure 25C for understanding.

[0164] According to an embodiment of the present invention, a multilayer structure 100 is provided. The multilayer structure 100 includes a substrate 101 and a plurality of sub-stacks SS1 to SS4 disposed on the upper surface 101a of the substrate 101. In this embodiment, 4 sub-stacks are exemplarily illustrated, but the present invention is not limited thereto. The sub-stacks SS1 to SS4 are separated by an oxide material 150. The sub-stacks SS1 to SS4 respectively extend along a first direction (e.g., the X direction) and are arranged on the upper surface 101a along a second direction (e.g., the Y direction). Each of the sub-stacks SS1 to SS4 includes a plurality of insulating layers 102, a plurality of patterned sacrificial layers 104t, a plurality of conductive layers 144b, a plurality of interlayer connectors 144a, a protective layer 126, and a plurality of barrier layers 142.

[0165] The insulating layer 102 and the patterned sacrificial layer 104t are alternately stacked on the upper surface 101a along a third direction (e.g., the Z direction). The conductive layer 144b and the insulating layer 102 are alternately stacked on the upper surface 101a along a third direction (e.g., the Z direction). Each conductive layer 144b is coplanar with the corresponding patterned sacrificial layer 104t. The bottommost insulating layers 102 of the sub-stacks SS1 to SS4 may be connected to each other. The interlayer connectors 144a pass through some of the sub-stacks SS1 to SS4, extend along the third direction (e.g., the Z direction), and the bottom of each interlayer connector 144a directly contacts the corresponding conductive layer 144b. Since the interlayer connectors 144a and the conductive layers 144b are simultaneously formed by the same conductor process, each interlayer connector 144a and the corresponding conductive layer 144b may be an integral structure, and there is no presence of other layers (e.g., barrier layers) in the contact region R1 between the interlayer connector 144a and the corresponding conductive layer 144b.

[0166] According to some embodiments of the present invention, the patterned sacrificial layer 104t is located in the middle part of each sub-stack (such as SS1, SS2, SS2, SS3). Each patterned sacrificial layer 104t has a first side FS and a second side BS opposite to the first side FS. The conductive layer 144b includes a plurality of first-side conductive layers 144bF and a plurality of second-side conductive layers 144bB, wherein the conductive layer 144b corresponding to the first side FS is the first-side conductive layer 144bF, and the conductive layer 144b corresponding to the second side BS is the second-side conductive layer 144bB. In the second direction (such as the Y direction), the patterned sacrificial layer 104t is located between the first-side conductive layer 144bF and the second-side conductive layer 144bB.

[0167] In some embodiments, the first-side conductive layer 144bF that overlaps with the interlayer connector 144a in the third direction (such as the Z direction) (i.e., the first-side conductive layer 144bF that is in direct contact with the interlayer connector 144a) has a first width W1 in the second direction (such as the Y direction), and the first-side conductive layer 144bF that does not overlap with the interlayer connector 144a in the third direction (such as the Z direction) (i.e., the first-side conductive layer 144bF that is not in contact with the interlayer connector 144a) has a second width W2 in the second direction (such as the Y direction), and the first width W1 is greater than the second width W2.

[0168] Similarly, the second-side conductive layer 144bB that overlaps with the interlayer connector 144a in the third direction (such as the Z direction) (i.e., the second-side conductive layer 144bB that is in direct contact with the interlayer connector 144a) has a third width W3 in the second direction (such as the Y direction), and the second-side conductive layer 144bB that does not overlap with the interlayer connector 144a in the third direction (such as the Z direction) (i.e., the second-side conductive layer 144bB that is not in contact with the interlayer connector 144a) has a fourth width W4 in the second direction (such as the Y direction), and the third width W3 is greater than the fourth width W4.

[0169] In some embodiments, the first width W1 may be equal to the third width W3, and the second width W2 may be equal to the fourth width W4.

[0170] In some embodiments, the first-side conductive layer 144bF has a first length L1 in the first direction (such as the X direction), and the second-side conductive layer 144bB has a second length L in the first direction (such as the X direction), and the first length L1 may be equal to the second length L.

[0171] In some embodiments, the cross-section of the interlayer connector 144a (such as the plane in the X direction and the Y direction) may be rectangular, circular, elliptical, or any shape.

[0172] In some embodiments, the protective layer 126 covers the uppermost insulating layer 1029 and surrounds the interlayer connector 144a. The protective layer 126 can be located between the uppermost insulating layer 1029 and the oxide material 150. The oxide material 150 can be the same material as the insulating layer 102, for example, silicon dioxide.

[0173] In some embodiments, except for the conductive layer 144b directly connected to the interlayer connector 144a, the other conductive layers 144b located on the same side of the patterned sacrificial layer 104t have the same width in the second direction (e.g., the Y direction).

[0174] In some embodiments, the barrier layer 142 surrounds the interlayer connector 144a and the conductive layer 144b. The barrier layer 142 can be located between the interlayer connector 144a and the protective layer 126, between the patterned sacrificial layer 104t and the conductive layer 144b, and between the insulating layer 102 and the interlayer connector 144a.

[0175] In some embodiments of the present invention, since multiple conductive layers 144b (e.g., 8-layer conductive layers 144b) and multiple interlayer connectors 144a can be formed together by the same conductor process, compared with the comparative example that requires multiple deposition processes to form the barrier layer, the conductive layer, and the interlayer connector, the process method of this case can reduce the complexity of the process, reduce the usage amount of conductive materials, and reduce costs.

[0176] Figures 26A to 27C The top view, cross-sectional view, and three-dimensional view showing the manufacturing method of the multilayer structure 200 according to another embodiment of the present invention are presented. The structure and manufacturing process of the multilayer structure 200 are similar to those of the multilayer structure 100, except for the design of the interlayer connector 244a and the formation of the wire 254 to transmit signals into the multilayer structure 200 after forming the oxide material 250. The elements in the multilayer structure 200 that are the same as or similar to those in the multilayer structure 100 are denoted by the same or similar element symbols. Some detailed descriptions will not be repeated.

[0177] Figure 26A The top view of the multilayer structure 200 according to another embodiment of the present invention after forming the upper vias 252 is shown, Figure 26B The cross-sectional view along the Figure 26A connection line 26B - 26B' is shown.

[0178] Please refer to Figures 26A to 26B simultaneously. After the step of forming the oxide material 250 (similar to the step shown in Figures 25A to 25C ), multiple upper openings 250p are formed through the oxide material 250 located above the protective layer 226. Thereafter, a conductive material is deposited in the upper openings 250p to form multiple upper vias 252.

[0179] In some embodiments, the upper vias 252 may correspond to part of the interlayer connectors 244a, but not to all of the interlayer connectors 244a, depending on the requirements. Therefore, part of the interlayer connectors 244a are electrically connected to the upper vias 252, and other parts of the interlayer connectors 244a are floating, not electrically connected to any of the upper vias 252, but covered by the oxide material 250. Therefore, the multiple interlayer connectors 244a of the present invention can provide a wide range of options for circuit design, and users can design circuits as needed.

[0180] Figure 26A The positions I to XIV marked along the first direction (eg, X direction) and the positions A to H marked along the second direction (eg, Y direction) can be used to indicate the coordinate position of the interlayer connector 244a. Figure 26A The interlayer connector 244a at position BXIII (column B, row XIII) is Figure 26B The interlayer connector 244 a is electrically connected to the upper via 252 .

[0181] The multilayer structure 200 includes a substrate 101 and a plurality of sub-layers ST1 to ST4 disposed on the upper surface 101a of the substrate 101. This embodiment exemplarily depicts four sub-layers, but the present invention is not limited thereto. The sub-layers ST1 to ST4 can be separated by oxide materials 250. The sub-layers ST1 to ST4 extend along a first direction (e.g., X direction) and are arranged along a second direction (e.g., Y direction). Each sub-layer ST1 to ST4 includes a plurality of insulating layers 202, a plurality of patterned sacrificial layers 204t (shown in FIG. 1 ), and a plurality of patterned sacrificial layers 204t (shown in FIG. 1 ). Figure 27C ), multiple conductive layers 244b, multiple interlayer connectors 244a, a protective layer 226 and multiple barrier layers 242.

[0182] In some embodiments, the bottom of the interlayer connector 244a directly contacts the corresponding conductive layer 244b. Since the interlayer connector 244a and the conductive layer 244b are formed simultaneously by the same conductor process, the interlayer connector 244a and the corresponding conductive layer 244b can be an integral structure, and no other layer (such as a barrier layer) exists in the contact area R2 between the interlayer connector 244a and the corresponding conductive layer 244b.

[0183] According to some embodiments of the present invention, the patterned sacrificial layer 204t (shown in FIG. Figure 27C ) is located in the middle of each sub-stack (e.g., SS1, SS2, SS2, SS3). Each patterned sacrificial layer 204t (shown in Figure 27Chas a first side and a second side opposite the first side. The conductive layer 244b includes a plurality of first-side conductive layers 244bF and a plurality of second-side conductive layers 244bB, where the conductive layer 244b corresponding to the first side is the first-side conductive layer 244bF, and the conductive layer 244b corresponding to the second side is the second-side conductive layer 244bB. In the second direction (e.g., the Y direction), the patterned sacrificial layer 204t (shown in Figure 27C is located between the first-side conductive layer 244bF and the second-side conductive layer 244bB.

[0184] Figure 26A The numbers 0 to 7 above the conductive layer 244b and Figure 26B The etching logarithm EN above indicate the number of insulating layers 202 and sacrificial layer pairs (similar to Figure 10B the third initial through hole 122 in

[0185] Figure 27A is shown following Figure 26A a top view of the manufacturing method of the multi-layer structure 200, Figure 27B is shown along Figure 27A a cross-sectional view taken along the line 27B-27B' of Figure 27C is shown Figure 27A a simplified three-dimensional view of

[0186] Please also refer to Figures 27A to 27C , a plurality of wires 254 (including wires 2541 to 2549) are formed on the oxide material 250, and the extending direction of the wires 254 can be parallel to the upper surface 101a of the substrate 101. That is, the wires 254 can extend along the first direction (e.g., the X direction) (e.g., wires 2543 and 2549) or along the second direction (e.g., the Y direction) (e.g., wires 2541 to 2542 and 2544 to 2548). The lengths or widths of the wires 254 can be the same or different from each other, depending on requirements. For example, in the first direction (e.g., the X direction), the width of the wire 2546 can be greater than the width of the wire 2542. Each wire 254 is electrically connected to the corresponding upper through hole 252, the interlayer connector 244a, and the conductive layer 244b. Some of the wires 254 can be used as signal input terminals (e.g., wires 2541 to 2542), and some of the wires 254 can be used as signal output terminals (e.g., wires 2543, 2549). Signals can enter the multi-layer structure 200 from the signal input terminals and then be transmitted to the target components from the signal output terminals.

[0187] For example, please also refer toFigure 27A and Figure 27C After the signal enters the multilayer structure 200 via the wire 2541 as the signal input terminal IP, the signal enters the second side conductive layer 244bB located at the 8th layer in the sub-stack ST1 through the upper through hole 252A1 and the interlayer connector 244a located at the position AXIV (the Ath column, the XIVth row), and then is transmitted upward to the interlayer connector 244a located at the position AI (the Ath column, the Ith row), the upper through hole 252A2 and the wire 2548, and then is transmitted to the upper through hole 252C1 and the interlayer connector 244a located at the position CI (the Cth column, the Ith row) through the wire 2548, and enters the second side conductive layer 244bB located at the 8th layer in the sub-stack ST2. The second side conductive layer 244bB of the 4th layer is then transmitted upward to the interlayer connector 244a, the upper through hole 252C2 and the wire 2545 at the position CXI (the Cth column and the XIth row), and then transmitted to the upper through hole 252H1 and the interlayer connector 244a at the position HXI (the Hth column and the XIth row) through the wire 2545, and then enters the first side conductive layer 244bF of the 7th layer in the secondary stack ST4, and then upward to the interlayer connector 244a, the upper through hole 252H2 and the wire 2549 as the signal output terminal OP at the position HI (the Hth column and the Ith row), and is transmitted to the target element. Figure 27C Only one signal transmission path is shown for exemplary purposes, but the present invention is not limited thereto.

[0188] Figure 28 A cross-sectional view of a multilayer structure 300 according to another embodiment of the present invention is shown. The structure and manufacturing process of the multilayer structure 300 are similar to the multilayer structure 100, except that the interlayer connector 344a is designed and the substrate through hole 301V is formed in the substrate 301. In addition, after the oxide material 350 is formed, a wire 354 is formed to electrically connect to the chip (e.g., chip 370A, 370B and 370C) disposed above the multilayer structure 300. The same or similar element numbers are used for the components in the multilayer structure 300 that are the same or similar to the multilayer structure 100. Some detailed descriptions will not be repeated.

[0189] Please refer to Figure 28, the multi-layer structure 300 includes a substrate 301 and multiple sub-stacks (in this figure, an exemplary illustration shows 1 sub-stack SU). The sub-stacks extend along a first direction (for example, the X direction) respectively, and are arranged on the upper surface 301a of the substrate 301 along a second direction (for example, the Y direction). Each sub-stack includes multiple insulating layers 302 and multiple patterned sacrificial layers (not shown) that are alternately stacked along a third direction (for example, the Z direction), includes multiple conductive layers 344b that are alternately stacked with the insulating layers 302 along a third direction (for example, the Z direction), and includes multiple interlayer connectors 344a. Among them, the patterned sacrificial layer has a first side and a second side (not shown) opposite to the first side. The conductive layer 344b includes multiple first-side conductive layers corresponding to the first side and multiple second-side conductive layers (not shown) corresponding to the second side. The multiple interlayer connectors 344a extend along the third direction respectively and are electrically connected to the corresponding conductive layers 344b. The protective layer 326 surrounds the interlayer connectors 344a. The oxide material 350 covers the sub-stack (for example, SU). The upper through-hole 352 passes through the oxide material 350 along the third direction (for example, the Z direction) and is electrically connected to the corresponding interlayer connector 344a. The insulating material layer 353 can cover the oxide material 350. The multiple wires 354 can pass through the insulating material layer 353 and be electrically connected to the corresponding upper through-holes 352. Chips A, B, and C can be formed on the multi-layer structure 300 and be electrically connected to the multi-layer structure 300 through the corresponding wires 354 and upper through-holes 352.

[0190] The multi-layer structure of the present invention can be applied to system-in-package (SIP), for example, it can be applied to 2.1D IC, 2.5D IC, and 3D IC. In this embodiment, the multi-layer structure 300 can be used as a silicon interposer circuit board (SI Interposer).

[0191] In some embodiments, the substrate 301 can be a silicon substrate or other suitable substrates. The substrate through-hole 301V can be a through-silicon via (TSV). The wire 354 can be a redistribution layer, and the redistribution layer has the function of bonding different chips in system-in-package. The substrate through-hole 301V can be a selective component and can be electrically connected to other chips and substrates.

[0192] In some embodiments, chips A, B, and C can be the same chips, for example, they are all logic devices (such as a central processing unit (CPU)).

[0193] In some embodiments, the multi-layer structure 300 may provide heterogeneous integration. Chips A, B, and C may be different chips. For example, chip A is a central processing unit, chip B is a non-volatile memory (NVM), and chip C is a dynamic random access memory (DRAM).

[0194] According to an embodiment of the present invention, a multi-layer structure and a manufacturing method thereof are provided. The multi-layer structure includes a substrate and a plurality of sub-layers. The sub-layers respectively extend along a first direction (e.g., the X direction) and are arranged on the upper surface of the substrate along a second direction (e.g., the Y direction). Each sub-layer includes a plurality of insulating layers and a plurality of patterned sacrificial layers alternately stacked on the upper surface of the substrate along a third direction (e.g., the Z direction), includes a plurality of conductive layers alternately stacked with the insulating layers on the upper surface of the substrate along the third direction (e.g., the Z direction), and includes a plurality of interlayer connectors 344a extending along the third direction (e.g., the Z direction). Among them, the patterned sacrificial layer has a first side and a second side opposite to the first side. The conductive layer includes a plurality of first-side conductive layers corresponding to the first side and a plurality of second-side conductive layers corresponding to the second side. The plurality of interlayer connectors are electrically connected and directly contact the corresponding conductive layer.

[0195] In the multi-layer structure of the present invention, the interlayer connector directly contacts the corresponding conductive layer, and there is no other layer (e.g., a barrier layer) in the contact area between the interlayer connector and the corresponding conductive layer. Since a plurality of conductive layers and a plurality of interlayer connectors can be formed by the same conductor process, compared with a comparative example that requires multiple deposition processes to form a barrier layer, a conductive layer, and an interlayer connector, the process method of this case can reduce the complexity of the process, reduce the amount of conductive material used, and reduce costs.

[0196] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A multi-layer structure, wherein, comprising: a substrate and a plurality of sub-stacks, wherein these sub-stacks respectively extend along a first direction and are arranged on an upper surface of the substrate along a second direction, and each of these sub-stacks comprises: a plurality of insulating layers and a plurality of patterned sacrificial layers alternately stacked on the upper surface along a third direction; a plurality of conductive layers alternately stacked on the upper surface with these insulating layers along the third direction; and a plurality of interlayer connectors extending along the third direction, wherein the first direction, the second direction and the third direction intersect each other; wherein, these patterned sacrificial layers have a plurality of first sides and a plurality of second sides opposite to these first sides, and these conductive layers comprise a plurality of first-side conductive layers corresponding to these first sides and a plurality of second-side conductive layers corresponding to these second sides; wherein, these patterned sacrificial layers are located between these first-side conductive layers and these second-side conductive layers; wherein, these interlayer connectors are electrically connected and in direct contact with the corresponding conductive layers.

2. The multi-layer structure according to claim 1, wherein, there is no barrier layer in the contact area between these interlayer connectors and the corresponding conductive layers.

3. The multi-layer structure according to claim 1, wherein, these first-side conductive layers in direct contact with these interlayer connectors have a first width in the second direction, these first-side conductive layers not in contact with these interlayer connectors have a second width in the second direction, and the first width is greater than the second width.

4. The multi-layer structure according to claim 3, wherein, these second-side conductive layers in direct contact with these interlayer connectors have a third width in the second direction, these second-side conductive layers not in contact with these interlayer connectors have a fourth width in the second direction, and the third width is greater than the fourth width.

5. The multi-layer structure according to claim 4, wherein, the first width is equal to the third width, and the second width is equal to the fourth width.

6. The multi-layer structure according to claim 1, wherein, these first-side conductive layers have a first length in the first direction, these second-side conductive layers have a second length in the first direction, and the first length is equal to the second length.

7. The multi-layer structure according to claim 1, wherein, some of these interlayer connectors are floating.

8. The multi-layer structure according to claim 1, wherein, further comprising an oxide material, the oxide material covering these sub-stacks, and a plurality of upper vias passing through the oxide material along the third direction and electrically connected to the corresponding interlayer connectors.

9. The multi-layer structure according to claim 1, wherein the multi-layer structure is for electrically connecting to at least one chip, and the at least one chip is disposed on the multi-layer structure.

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