Trench-type high-voltage isolation capacitor device based on Trench process and preparation method thereof

Abstract

The present invention relates to a trench-type high-voltage isolation capacitor device and a preparation method based on a Trench process, wherein at least four grooves are provided on a silicon substrate, and the silicon substrate on the side and bottom of the grooves and the upper surface of the silicon substrate are subjected to high-temperature oxidation to form a silicon dioxide dielectric layer, and polysilicon is filled in the grooves, and grounded polysilicon is formed in the grooves on the leftmost and right sides, and polysilicon of a high-voltage isolation capacitor device is formed in the middle groove, and an insulating silicon dioxide layer and an insulating silicon nitride layer are provided on the upper surface of the polysilicon, and a contact hole is provided on the insulating covering layer, and a grounded polysilicon lead-out electrode and a high-voltage isolation capacitor device polysilicon lead-out electrode are provided in the contact hole. The capacitor device of the present invention has a high withstand voltage and a simple structure, and the preparation method of the present invention solves the problem that the thickness of the silicon dioxide dielectric layer of the capacitor device is difficult to grow, and realizes a high isolation voltage of the capacitor device.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and specifically provides a trench-type high-voltage isolation capacitor device based on a Trench process and a preparation method thereof. Background Art

[0002] Galvanicisolation refers to a method of preventing current from flowing directly from one area to another in a circuit, that is, not establishing a direct current flow path between two areas. Although current cannot flow directly, energy or information can still be transmitted through other means, such as capacitance, inductance or electromagnetic waves, or by optical, acoustic or mechanical means.

[0003] The birth and development of isolators have always been accompanied by the development of the power industry. Isolators were born to filter out industrial site noise and high and low frequency pulse signal interference and isolate and protect control systems to ensure accurate, stable and reliable signal output. Later, signal transmission and load capacity enhancement designs were also added.

[0004] Isolation has three main functions: protecting operators and low-voltage circuits from high voltage, handling ground potential differences between communication subsystems, and improving noise immunity. For this reason, isolation is widely used in industry and automobiles to ensure the safety and reliability of signal transmission at different voltage levels.

[0005] Initially, most isolators used optocoupler isolators. However, with the continuous advancement of CMOS technology, digital isolation technology began to make great strides and was gradually recognized by the market. Its high reliability and high speed far exceeded the limits of traditional optocoupler technology.

[0006] Currently, the commonly used CMOS high-voltage capacitor isolation devices are manufactured using a surface dielectric stacking process. The isolation withstand voltage depends on the thickness of the dielectric stack, which is related to the number of metal wiring layers in the process. The more metal layers there are, the thicker the dielectric thickness is. However, this directly leads to an increase in the cost of the device. In addition, the number of metal wiring layers in the conventional CMOS process is limited, and the withstand voltage of the isolation capacitor is difficult to further increase.

[0007] Generally, high-voltage isolation capacitors are implemented in the back-end process of silicon-based semiconductors. The capacitor structure is implemented by surface stacking. First, a layer of metal is deposited on the surface of the silicon wafer as the lower plate of the capacitor. Then, a thick layer of silicon dioxide or silicon dioxide silicon nitride composite layer is grown on the metal lower plate as the dielectric layer of the high-voltage isolation capacitor. Finally, another layer of metal is deposited on the dielectric layer as the upper plate of the capacitor.

[0008] The withstand voltage of high-voltage isolation capacitors is related to the thickness of the dielectric layer. The breakdown electric field of silicon dioxide and silicon nitride is about 1E7V / cm. To achieve a withstand voltage greater than 5KV, the thickness of the dielectric layer of silicon dioxide and silicon nitride needs to be greater than 5um.

[0009] The thermal growth process of silicon dioxide shows an exponential decay characteristic. In the initial stage, the growth rate of silicon dioxide is relatively fast, but it is difficult to continue growing after reaching a certain thickness. The conventional solution is to stack multiple layers of silicon dioxide and metal layers, which will lead to an increase in process costs. At the same time, the parasitic capacitance from the bottom metal plate to the silicon substrate (usually grounded) is much larger than the high-voltage isolation capacitor, which affects the signal transmission of the high-voltage isolation capacitor. Summary of the invention

[0010] The purpose of the present invention is to overcome the deficiencies in the prior art and to provide a trench-type high-voltage isolation capacitor device based on a Trench process and a preparation method thereof, which has high withstand voltage, simple structure and simple and easy preparation method.

[0011] According to the technical solution provided by the present invention, the trench-type high-voltage isolation capacitor device based on the Trench process has at least four grooves opened on the silicon substrate, and the silicon substrate on the side and bottom of the grooves and the upper surface of the silicon substrate are subjected to high-temperature oxidation to form a silicon dioxide dielectric layer, each groove is filled with polycrystalline silicon, the polycrystalline silicon located in the leftmost and rightmost grooves forms grounded polycrystalline silicon, the polycrystalline silicon located in the middle groove forms high-voltage isolation capacitor device polycrystalline silicon, the silicon column between the grounded polycrystalline silicon and the high-voltage isolation capacitor device polycrystalline silicon has been completely oxidized into a silicon dioxide dielectric, an insulating covering silicon dioxide layer is provided on the upper surface of the polycrystalline silicon, an insulating covering silicon nitride layer is provided on the insulating covering silicon dioxide layer, contact holes are opened on the insulating covering silicon dioxide layer and the insulating covering silicon nitride layer, and a grounded polycrystalline silicon lead-out electrode connected to the grounded polycrystalline silicon and a high-voltage isolation capacitor device polycrystalline silicon lead-out electrode connected to the high-voltage isolation capacitor device polycrystalline silicon are provided in the contact hole.

[0012] Preferably, the silicon dioxide dielectric layer between adjacent grooves is thickened.

[0013] Preferably, the thickness of the silicon dioxide dielectric layer is 5-15 um.

[0014] Preferably, the width of the groove is 5-10 um, the depth of the groove is 10-30 um, and the spacing between adjacent grooves is 5-10 um.

[0015] Preferably, the trench-type high-voltage isolation capacitor device is an axisymmetric structure, and is disposed bilaterally symmetrically about a central axis of the device.

[0016] Preferably, the thickness of the insulating covering silicon dioxide layer is 5-15 um, and the thickness of the insulating covering silicon nitride layer is 2-5 um.

[0017] Preferably, the thickness ratio of the insulating silicon dioxide layer to the insulating silicon nitride layer is (3-4): 1. Further preferably, the thickness ratio of the insulating silicon dioxide layer to the insulating silicon nitride layer is 3:1.

[0018] A method for preparing a trench-type high-voltage isolation capacitor device based on a Trench process, the method comprising the following steps:

[0019] Step 1: providing a silicon substrate; by implementing this step, it can be compatible with conventional silicon process, reduce manufacturing difficulty and manufacturing cost;

[0020] Step 2: High temperature oxidation is performed on the upper surface of the silicon substrate to form a silicon dioxide layer; by implementing this step, the surface of the silicon substrate can be protected to avoid defects caused by subsequent processes;

[0021] Step 3: using the Trench process to sequentially form at least 4 grooves on the silicon substrate, and forming silicon pillars between adjacent grooves; by implementing this step, the silicon oxide contact surface can be increased, which is conducive to forming a thick silicon dioxide layer;

[0022] Step 4: forming a silicon dioxide dielectric layer on the side and bottom of the groove by high temperature oxidation; by implementing this step, the growth rate of the silicon dioxide layer can be increased;

[0023] Step 5: Fill the groove with polysilicon. During the high-temperature oxidation process, it is difficult for the silicon dioxide layer to continue to grow after it grows to a certain thickness. By implementing this step, silicon dioxide can be quickly grown on the polysilicon to increase the thickness of the silicon dioxide layer.

[0024] Step 6: reverse etching of polysilicon, leaving a layer of polysilicon in the groove; by implementing this step, the growth of silicon dioxide can be controlled at a local position;

[0025] Step 7: high-temperature oxidation again to increase the thickness of the silicon dioxide dielectric layer located on the side of the groove, and at the same time, the remaining layer of polysilicon in the groove is oxidized into silicon dioxide, so that the thickness of the silicon dioxide dielectric layer located at the bottom of the groove increases; by implementing this step, the thickness of the silicon dioxide layer can be increased, and the silicon column between two adjacent grooves has been completely oxidized into silicon dioxide dielectric;

[0026] Step 8: Fill the groove with polysilicon again; during the high-temperature oxidation process, it is difficult for the silicon dioxide layer to continue to grow after it grows to a certain thickness. By implementing this step, silicon dioxide can be quickly grown on the polysilicon to increase the thickness of the silicon dioxide layer;

[0027] Step 9: Repeat steps 6 to 8 as many times as required; the thickness of the silicon dioxide layer can be increased by implementing this step;

[0028] Step 10: reverse-etch the polysilicon again to form grounding polysilicon located in the leftmost and rightmost grooves and high-voltage isolation capacitor device polysilicon located in the middle groove; by implementing this step, the plate of the high-voltage isolation capacitor can be formed;

[0029] Step 11: first deposit an insulating covering silicon dioxide layer on the upper surface of the grounded polysilicon and the polysilicon of the high-voltage isolation capacitor device, and then deposit an insulating covering silicon nitride layer on the insulating covering silicon dioxide layer; by implementing this step, the surface electric field can be prevented from being broken down;

[0030] Step 12: Open contact holes layer by layer and make grounded polysilicon lead-out electrodes and high-voltage isolation capacitor device polysilicon lead-out electrodes; by implementing this step, it is possible to avoid parasitic capacitance suspension affecting signal communication.

[0031] The present invention has the following advantages:

[0032] The capacitor device of the present invention has high withstand voltage and simple structure. The preparation method of the present invention solves the problem that the thickness of the silicon dioxide dielectric layer of the capacitor device is difficult to grow, and realizes the high isolation voltage of the capacitor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 1 is a structural diagram of the device obtained through step 1 of Example 1.

[0034] Figure 2 It is a structural diagram of the device obtained through step 2 of Example 1.

[0035] Figure 3 It is a structural diagram of the device obtained through step three of Example 1.

[0036] Figure 4 It is a structural diagram of the device obtained through step 4 of Example 1.

[0037] Figure 5 This is a structural diagram of the device obtained through step five of Example 1.

[0038] Figure 6 It is a structural diagram of the device obtained through step six of Example 1.

[0039] Figure 7 This is a structural diagram of the device obtained through step seven of Example 1.

[0040] Figure 8 It is a structural diagram of the device obtained through step eight of Example 1.

[0041] Fig. 9This is a structural diagram of the device obtained through step nine of Example 1.

[0042] Fig.10 3 is a structural diagram of the device obtained through step ten of Example 1.

[0043] Fig.11 This is a structural diagram of the device obtained through step eleven of Example 1. DETAILED DESCRIPTION

[0044] The present invention will be further described below in conjunction with specific embodiments.

[0045] Example 1

[0046] A trench-type high-voltage isolation capacitor device based on a Trench process, wherein four grooves 2 are provided on a silicon substrate 1, and the silicon substrate 1 on the side and bottom of the grooves 2 and the upper surface of the silicon substrate 1 are subjected to high-temperature oxidation to form a silicon dioxide dielectric layer 3, each groove 2 is filled with polysilicon, the polysilicon in the leftmost and rightmost grooves 2 forms a grounding polysilicon 4, the polysilicon in the middle groove 2 forms a high-voltage isolation capacitor device polysilicon 5, the silicon column between the grounding polysilicon 4 and the high-voltage isolation capacitor device polysilicon 5 has been completely oxidized into a silicon dioxide dielectric, an insulating covering silicon dioxide layer 6 is provided on the upper surface of the polysilicon, an insulating covering silicon nitride layer 7 is provided on the insulating covering silicon dioxide layer 6, contact holes are provided on the insulating covering silicon dioxide layer 6 and the insulating covering silicon nitride layer 7, and a grounding polysilicon lead-out electrode 8 connected to the grounding polysilicon 4 and a high-voltage isolation capacitor device polysilicon lead-out electrode 9 connected to the high-voltage isolation capacitor device polysilicon 5 are provided in the contact hole.

[0047] The silicon dioxide dielectric layer 3 between the adjacent grooves 2 is arranged to be thicker.

[0048] The thickness of the silicon dioxide dielectric layer 3 is 5-15 um.

[0049] The width of the groove 2 is 5-10 um, the depth of the groove 2 is 10-30 um, and the distance between adjacent grooves 2 is 5-10 um.

[0050] The trench-type high-voltage isolation capacitor device is an axisymmetric structure and is disposed in a left-right symmetric manner about the central axis of the device.

[0051] The thickness of the insulating silicon dioxide layer 6 is 6 um, and the thickness of the insulating silicon nitride layer 7 is 2 um. At this time, the thickness ratio of the insulating silicon dioxide layer 6 to the insulating silicon nitride layer 7 is 3:1.

[0052] A method for preparing a trench-type high-voltage isolation capacitor device based on a Trench process, the method comprising the following steps:

[0053] Step 1: Provide a silicon substrate 1, such as Figure 1 As shown;

[0054] Step 2: The upper surface of the silicon substrate 1 is oxidized at high temperature to form a silicon dioxide layer, such as Figure 2 As shown;

[0055] Step 3: Use Trench process to sequentially form four grooves 2 on the silicon substrate 1, and form silicon columns between adjacent grooves, such as Figure 3 As shown;

[0056] Step 4: Form a silicon dioxide dielectric layer 3 on the side and bottom of the groove 2 by high temperature oxidation. Figure 4 As shown;

[0057] Step 5: Fill the groove 2 with polysilicon. Figure 5 As shown;

[0058] Step 6: reverse etching of polysilicon, leaving a layer of polysilicon in the groove 2, such as Figure 6 As shown;

[0059] Step 7: high temperature oxidation again, so that the thickness of the silicon dioxide dielectric layer 3 located on the side of the groove 2 increases, and at the same time, the remaining layer of polysilicon in the groove 2 is oxidized into silicon dioxide, so that the thickness of the silicon dioxide dielectric layer 3 located on the bottom of the groove 2 increases, and the silicon column between two adjacent grooves 2 has been completely oxidized into silicon dioxide dielectric, such as Figure 7 As shown;

[0060] Step 8: Fill the groove 2 with polysilicon again. Figure 8 As shown;

[0061] Step 9: Reverse-etch the polysilicon again to form grounding polysilicon 4 located in the leftmost and rightmost grooves 2 and high-voltage isolation capacitor polysilicon 5 located in the middle groove 2, such as Fig. 9 As shown;

[0062] Step 10: firstly deposit an insulating covering silicon dioxide layer 6 on the upper surface of the grounding polysilicon 4 and the high voltage isolation capacitor device polysilicon 5, and then deposit an insulating covering silicon nitride silicon nitride layer 7 on the insulating covering silicon dioxide layer 6. Fig.10 As shown;

[0063] Step 11: Open contact holes layer by layer and make grounding polysilicon lead-out electrodes 8 and high-voltage isolation capacitor device polysilicon lead-out electrodes 9, such as Fig.11 shown.

[0064] Example 2

[0065] A trench-type high-voltage isolation capacitor device based on a Trench process, wherein four grooves 2 are opened on a silicon substrate 1, the silicon substrate 1 on the side and bottom of the grooves 2 and the upper surface of the silicon substrate 1 are subjected to high-temperature oxidation to form a silicon dioxide dielectric layer 3, each groove 2 is filled with polysilicon, the polysilicon in the leftmost and rightmost grooves 2 forms a grounding polysilicon 4, the polysilicon in the middle groove 2 forms a high-voltage isolation capacitor device polysilicon 5, an insulating covering silicon dioxide layer 6 is provided on the upper surface of the polysilicon, an insulating covering silicon nitride layer 7 is provided on the insulating covering silicon dioxide layer 6, contact holes are opened on the insulating covering silicon dioxide layer 6 and the insulating covering silicon nitride layer 7, and a grounding polysilicon lead-out electrode 8 connected to the grounding polysilicon 4 and a high-voltage isolation capacitor device polysilicon lead-out electrode 9 connected to the high-voltage isolation capacitor device polysilicon 5 are provided in the contact hole.

[0066] The silicon dioxide dielectric layer 3 between the adjacent grooves 2 is arranged to be thicker.

[0067] The thickness of the silicon dioxide dielectric layer 3 is 5-15 um.

[0068] The width of the groove 2 is 5-10 um, the depth of the groove 2 is 10-30 um, and the distance between adjacent grooves 2 is 5-10 um.

[0069] The trench-type high-voltage isolation capacitor device is an axisymmetric structure and is disposed in a left-right symmetric manner about the central axis of the device.

[0070] The thickness of the insulating silicon dioxide layer 6 is 10 um, and the thickness of the insulating silicon nitride layer 7 is 2.5 um. At this time, the ratio of the thickness of the insulating silicon dioxide layer 6 to the insulating silicon nitride layer 7 is 4:1.

[0071] A method for preparing a trench-type high-voltage isolation capacitor device based on a Trench process, the method comprising the following steps:

[0072] Step 1: providing a silicon substrate 1;

[0073] Step 2: performing high temperature oxidation on the upper surface of the silicon substrate 1 to form a silicon dioxide layer;

[0074] Step 3: using a Trench process to sequentially form four grooves 2 on the silicon substrate 1, and forming silicon columns between adjacent grooves;

[0075] Step 4: forming a silicon dioxide dielectric layer 3 on the side and bottom of the groove 2 by high temperature oxidation;

[0076] Step 5: Filling the groove 2 with polysilicon;

[0077] Step 6: reverse etching of polysilicon, leaving a layer of polysilicon remaining in the groove 2;

[0078] Step 7: high-temperature oxidation again to increase the thickness of the silicon dioxide dielectric layer 3 located on the side of the groove 2, and at the same time, the remaining layer of polysilicon in the groove 2 is oxidized into silicon dioxide, so that the thickness of the silicon dioxide dielectric layer 3 located on the bottom of the groove 2 increases;

[0079] Step 8: Filling the groove 2 with polysilicon again;

[0080] Step nine, reverse etching the polysilicon, leaving a layer of polysilicon remaining in the groove;

[0081] Step 10: high-temperature oxidation again to increase the thickness of the silicon dioxide dielectric layer located on the side of the groove, and at the same time, a layer of polysilicon remaining in the groove is oxidized into silicon dioxide, so that the thickness of the silicon dioxide dielectric layer located on the bottom of the groove increases;

[0082] Step 11: Fill the groove with polysilicon again;

[0083] Step 12: reverse-etch the polysilicon again to form grounding polysilicon 4 located in the leftmost and rightmost grooves 2 and high-voltage isolation capacitor device polysilicon 5 located in the middle groove 2;

[0084] Step 13: firstly deposit an insulating covering silicon dioxide layer 6 on the upper surface of the grounding polysilicon 4 and the high voltage isolation capacitor device polysilicon 5, and then deposit a silicon nitride insulating covering silicon nitride layer 7 on the insulating covering silicon dioxide layer 6;

[0085] Step 14: Open contact holes layer by layer and make grounding polysilicon lead-out electrodes 8 and high-voltage isolation capacitor device polysilicon lead-out electrodes 9.

[0086] The principle of the present invention is as follows:

[0087] The present invention provides a trench-type high-voltage isolation capacitor device based on the Trench process, wherein the capacitor plates of the trench-type high-voltage isolation capacitor device are composed of grounded polysilicon 4 and high-voltage isolation capacitor device polysilicon 5, and the capacitor dielectric layer of the trench-type high-voltage isolation capacitor device is composed of a silicon dioxide dielectric layer 3. The withstand voltage of the high-voltage isolation capacitor depends on the thickness of the silicon dioxide dielectric layer 3. The plates on both sides of the trench-type high-voltage isolation capacitor device are grounded to form an isolated capacitor.

[0088] The silicon dioxide dielectric layer 3 of the trench-type high-voltage isolation capacitor device is generated by high-temperature oxidation of silicon, and the thickness of silicon dioxide is difficult to continue to grow after it grows to a certain thickness. Four grooves 2 are dug out on the silicon substrate 1 using the Trench process, and three silicon pillars are formed between the four grooves 2. During the high-temperature oxidation process, both the left and right sides of the silicon pillar can be oxidized. The thickness of the silicon dioxide dielectric layer 3 finally formed is equal to the superposition of the silicon dioxide thickness on both sides of the silicon pillar, which solves the problem that the silicon dioxide dielectric layer 3 is difficult to grow thick.

[0089] After the silicon at the bottom of the groove 2 is oxidized at high temperature once, the thickness of the silicon dioxide is difficult to increase. Therefore, a layer of polysilicon is deposited on the silicon dioxide at the bottom of the groove 2 and then oxidized at high temperature. Finally, the thickness of the silicon dioxide dielectric layer 3 at the bottom of the groove 2 is equal to the sum of the multiple silicon dioxide thicknesses.

[0090] The preparation method of the present invention solves the problem that the thickness of the silicon dioxide dielectric layer 3 of the capacitor device is difficult to grow, and achieves a high isolation voltage of the capacitor device. In addition, the preparation method of the present invention is compatible with the silicon-based CMOS process, and can easily integrate the high-voltage isolation capacitor into the conventional silicon-based CMOS process.

[0091] The high-voltage isolation capacitor in the present invention is implemented in the silicon-based semiconductor front-end process by vertical integration, and the process is relatively simple. A silicon column is formed by opening a groove 2, and both sides of the groove 2 can be oxidized at high temperature, which is easy to form a thicker silicon dioxide dielectric layer 3; multiple polycrystalline filling and polycrystalline reverse etching can be performed to increase the thickness of the silicon dioxide dielectric layer 3 at the bottom of the groove 2; the parasitic capacitance from the plates on the left and right sides of the high-voltage isolation capacitor to the ground is similar to the capacitance of the high-voltage isolation capacitor, which is much smaller than the parasitic capacitance from the high-voltage isolation capacitor to the ground using the surface stacking method in the background technology, which is conducive to signal transmission.

[0092] Taking the stress problem into consideration (SiO2≈-3E8Pa, SiN≈1E9Pa), it is best to use an insulating covering silicon dioxide layer 6 and an insulating covering silicon nitride layer 7 as a composite as the insulating covering layer, and use a thickness ratio of the insulating covering silicon dioxide layer 6 to the insulating covering silicon nitride layer 7 of (3~4):1 for compensation.

[0093] In this specification, the specific features, structures, materials or characteristics described are included in at least one embodiment or example of the present invention. The above schematic representations do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and purpose of the present invention, and the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A trench-type high-voltage isolation capacitor device based on a Trench process, characterized in that: At least four grooves (2) are formed on a silicon substrate (1). The silicon substrate (1) on the side and bottom of the grooves (2) and the upper surface of the silicon substrate (1) are subjected to high temperature oxidation to form a silicon dioxide dielectric layer (3). Polycrystalline silicon is filled in each groove (2). The polycrystalline silicon in the leftmost and rightmost grooves (2) forms grounding polycrystalline silicon (4). The polycrystalline silicon in the middle groove (2) forms high-voltage isolation capacitor device polycrystalline silicon (5). The grounding polycrystalline silicon (4) and the high-voltage isolation capacitor device polycrystalline silicon (5) are connected to each other. The silicon pillars between the polysilicon and the insulating silicon have been completely oxidized into silicon dioxide dielectrics, an insulating covering silicon dioxide layer (6) is provided on the upper surface of the polysilicon, an insulating covering silicon nitride layer (7) is provided on the insulating covering silicon dioxide layer (6), contact holes are provided on the insulating covering silicon dioxide layer (6) and the insulating covering silicon nitride layer (7), and a grounding polysilicon lead-out electrode (8) connected to the grounding polysilicon (4) and a high-voltage isolation capacitor device polysilicon lead-out electrode (9) connected to the high-voltage isolation capacitor device polysilicon (5) are provided in the contact hole.

2. The trench-type high-voltage isolation capacitor device based on the Trench process according to claim 1, characterized in that: The thickness of the silicon dioxide dielectric layer (3) is 5-15 um.

3. The trench-type high-voltage isolation capacitor device based on the Trench process according to claim 1, characterized in that: The width of the groove (2) is 5 to 10 um, the depth of the groove (2) is 10 to 30 um, and the spacing between adjacent grooves (2) is 5 to 10 um.

4. The trench-type high-voltage isolation capacitor device based on the Trench process according to claim 1, characterized in that: The trench-type high-voltage isolation capacitor device is an axisymmetric structure and is disposed in a left-right symmetric manner about the central axis of the device.

5. The trench type high voltage isolation capacitor device based on the Trench process according to claim 1, characterized in that: The thickness of the insulating covering silicon dioxide layer (6) is 5 to 15 um, and the thickness of the insulating covering silicon nitride layer (7) is 2 to 5 um.

6. The trench type high voltage isolation capacitor device based on the Trench process according to claim 5, characterized in that: The thickness ratio of the insulating covering silicon dioxide layer (6) to the insulating covering silicon nitride layer (7) is (3-4):

1.

7. The trench-type high-voltage isolation capacitor device based on the Trench process according to claim 6, characterized in that: The thickness ratio of the insulating covering silicon dioxide layer (6) to the insulating covering silicon nitride layer (7) is 3:

1.

8. A method for preparing a trench-type high-voltage isolation capacitor device based on a Trench process, characterized in that The preparation method comprises the following steps: Step 1: providing a silicon substrate (1); Step 2: performing high temperature oxidation on the upper surface of the silicon substrate (1) to form a silicon dioxide layer; Step 3: using a trench process to sequentially form at least four grooves (2) on the silicon substrate (1), and forming silicon columns between adjacent grooves (2); Step 4: Forming a silicon dioxide dielectric layer (3) on the side and bottom of the groove (2) by high temperature oxidation; Step 5: Filling the groove (2) with polysilicon; Step 6: reverse etching the polysilicon, so that a layer of polysilicon remains in the groove (2); Step 7: high-temperature oxidation again to increase the thickness of the silicon dioxide dielectric layer (3) located on the side of the groove (2). At the same time, the remaining layer of polysilicon in the groove (2) is oxidized into silicon dioxide, so that the thickness of the silicon dioxide dielectric layer (3) located on the bottom of the groove (2) is increased. The silicon pillar between two adjacent grooves (2) has been completely oxidized into silicon dioxide dielectric; Step 8: Fill the groove (2) with polysilicon again; Step 9: Repeat steps 6 to 8 as many times as required; Step 10: reverse-etch the polysilicon again to form grounding polysilicon (4) located in the leftmost and rightmost grooves (2) and high-voltage isolation capacitor device polysilicon (5) located in the middle groove (2); Step 11: firstly deposit an insulating covering silicon dioxide layer (6) on the upper surface of the grounding polysilicon (4) and the high voltage isolation capacitor device polysilicon (5), and then deposit an insulating covering silicon nitride layer (7) on the insulating covering silicon dioxide layer (6); Step 12: Open contact holes layer by layer and make grounding polysilicon lead-out electrodes (8) and high-voltage isolation capacitor device polysilicon lead-out electrodes (9).

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