Thin film transistor array substrate and digital X-ray detector device including the same

Abstract

A thin film transistor array substrate and a digital X-ray detector device for a digital X-ray detector device are provided, which can minimize the generation of leakage current and minimize the reduction in light transmittance of a PIN diode. According to the present disclosure, a p+ type semiconductor layer and a p-type semiconductor layer having different impurity concentrations are arranged above the intrinsic semiconductor layer of the PIN diode, and an n+ type semiconductor layer and an n-type semiconductor layer having different impurity concentrations are arranged below the intrinsic semiconductor layer of the PIN diode to minimize the injection of holes from the p-type semiconductor layer and minimize the injection of electrons from the n-type semiconductor layer, thereby minimizing the occurrence of leakage current of the PIN diode. In addition, according to the present disclosure, a p-type semiconductor layer having a low impurity concentration is arranged under a p+ type semiconductor layer having a high impurity concentration, and an n-type semiconductor layer having a low impurity concentration is arranged on the n+ type semiconductor layer to minimize the reduction in light transmittance of the PIN diode due to the high impurity concentration.

Description

Technical Field

[0001] The present disclosure relates to a thin film transistor array substrate capable of minimizing leakage current of a PIN diode for a digital X-ray detector device and a digital X-ray detector device including the thin film transistor array substrate. Background Art

[0002] Because X-rays have a short wavelength, they can easily pass through objects. The transmittance of X-rays depends on the internal density of the object. Therefore, the internal structure of the object can be observed by detecting the amount of X-rays transmitted through the object.

[0003] One of the X-ray-based inspection methods used in the medical field is a film printing scheme. However, in the film printing scheme, in order to inspect the result, an image is taken, and then a film is printed. Therefore, it takes a long time to inspect the result. In particular, in the film printing scheme, there are some difficulties in storing and preserving the printed film.

[0004] Digital X-ray detector (DXD) devices using thin film transistors have been developed and widely used in the medical field.

[0005] The DXD device detects the transmittance of X-rays transmitted through an object and displays the internal state of the object on a display based on the transmittance.

[0006] Therefore, the digital X-ray detector device can display the internal structure of an object without using additional film and printing paper. In addition, the DXD device can check the results in real time immediately after X-ray photography. Summary of the invention

[0007] The digital X-ray detector device detects current within the digital X-ray detection panel to implement an image based on the current, and includes a photo PIN (p-type semiconductor-intrinsic semiconductor-n-type semiconductor) diode.

[0008] The digital X-ray detector device can minimize the noise generated in the X-ray image to obtain the precise and clear image expected by the user.

[0009] Since noise may be generated based on a leakage current occurring after a reverse voltage is applied to the top of the PIN diode, the leakage current generated by the PIN diode may be minimized.

[0010] Therefore, the inventors of the present disclosure have invented a thin film transistor array substrate for a digital X-ray detector device and a digital X-ray detector device capable of minimizing leakage current generated by a PIN diode.

[0011] The present disclosure provides a thin film transistor array substrate for a digital X-ray detector device and a digital X-ray detector device capable of minimizing leakage current of a PIN diode.

[0012] The present disclosure also provides a thin film transistor array substrate for a digital X-ray detector device and a digital X-ray detector device capable of minimizing a decrease in transmittance of light incident on a PIN diode.

[0013] The purpose of the present disclosure is not limited to the above-mentioned purpose, and other purposes and advantages of the present disclosure that are not mentioned can be understood by the following description, and can be more clearly understood by the embodiments of the present disclosure. It is also easy to understand that the purposes and advantages of the present disclosure can be implemented by the features described in the attached claims and their combinations.

[0014] According to an embodiment of the present disclosure, a thin film transistor array substrate for a digital X-ray detector device and a digital X-ray detector device capable of minimizing generation of leakage current and minimizing reduction in light transmittance of a PIN diode are provided.

[0015] According to an embodiment of the present disclosure, a thin film transistor array substrate for a digital X-ray detector device and a digital X-ray detector device include a base substrate, a driving thin film transistor arranged on the base substrate, and a PIN diode connected to the driving thin film transistor and including a lower electrode, a PIN layer and an upper electrode, and the PIN layer includes a p+ type semiconductor layer, a p-type semiconductor layer, an I (intrinsic) semiconductor layer, an n-type semiconductor layer and an n+ type semiconductor layer.

[0016] In this case, the p+ type semiconductor layer and the p- type semiconductor layer each contain p-type impurities, the concentration of the p-type impurities in the p- type semiconductor layer is lower than the concentration of the p-type impurities in the p+ type semiconductor layer, and the p-type impurities may include at least one of the Group III elements.

[0017] In addition, the n+ type semiconductor layer and the n- type semiconductor layer each contain n type impurities, the concentration of the n- type semiconductor layer is lower than that of the n+ type semiconductor layer, and the n type impurities may include at least one of Group V elements.

[0018] Furthermore, according to another embodiment of the present disclosure, the p+ type semiconductor layer may have the same thickness as the n+ type semiconductor layer, and the p- type semiconductor layer may have the same thickness as the n- type semiconductor layer.

[0019] According to the present disclosure, a plurality of p-type semiconductor layers including a p+ type semiconductor layer and a p-type semiconductor layer having different impurity concentrations are disposed above an intrinsic semiconductor layer of a PIN diode, and a plurality of n-type semiconductor layers including an n+ type semiconductor layer and an n-type semiconductor layer having different impurity concentrations are disposed below the intrinsic semiconductor layer to minimize the ejection of holes from the p-type semiconductor layer and the ejection of electrons from the n-type semiconductor layer, thereby minimizing the occurrence of leakage current of the PIN diode.

[0020] In addition, according to the present disclosure, a p-type semiconductor layer with a low impurity concentration is disposed below a p+ type semiconductor layer with a high impurity concentration, and an n-type semiconductor layer with a low impurity concentration is disposed on the n+ type semiconductor layer with a high impurity concentration to minimize the reduction in light transmittance of the PIN diode due to the high impurity concentration.

[0021] In addition to the above-described effects, specific effects of the present disclosure will be described together with description of specific matters to implement the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic block diagram illustrating an exemplary digital X-ray detector apparatus.

[0023] Figure 2 is a plan view showing an exemplary area of ​​a digital X-ray detector device.

[0024] Figure 3 : is a cross-sectional view showing an exemplary region taken along line II' of the digital X-ray detector device.

[0025] Figure 4 is an enlarged cross-sectional view showing an exemplary PIN diode.

[0026] FIG. 5A to FIG. 5C The PIN leakage currents in Comparative Example 1, Comparative Example 2, and the embodiment are shown respectively. DETAILED DESCRIPTION

[0027] Some embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Therefore, a person skilled in the art to which the present disclosure belongs can easily implement the technical ideas of the present disclosure. In the description of the present disclosure, if it is determined that the detailed description of the known technology related to the present disclosure unnecessarily makes the main points of the present disclosure difficult to understand, the detailed description may be omitted. One or more embodiments of the present disclosure are described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals may be used to represent the same or similar components.

[0028] In this document, the terms "upper", "lower", "on", "under", etc. are used, so that when a first component is arranged at the "upper part" or "lower part" of a second component, the first component may be arranged in contact with the upper surface (or lower surface) of the second component, or another component may be provided between the first component and the second component. Similarly, when a first component is arranged on or under a second component, the first component may be directly arranged on or under the second component (in contact with the second component), or one or more other components may be provided between the first component and the second component.

[0029] In addition, the terms "connected", "coupled", etc. are used, so that when a first component is connected or coupled to a second component, the first component can be directly connected or connectable to the second component, or one or more additional components can be arranged between the first component and the second component, or the first component and the second component can be connected or coupled through one or more additional components.

[0030] Hereinafter, a thin film transistor array substrate for a digital X-ray detector device and a digital X-ray detector device including the thin film transistor array substrate according to some embodiments of the present disclosure are described.

[0031] Figure 1 is a schematic block diagram showing a digital X-ray detector device. The digital X-ray detector device may include a thin film transistor array 110 , a gate driver 120 , a bias power supply 130 , a readout circuit 140 , and a timing controller 150 .

[0032] The thin film transistor array 110 may include a plurality of cell regions defined by a plurality of gate lines GL arranged in a first direction and a plurality of data lines DL arranged in a second direction orthogonal to the first direction.

[0033] The unit regions are arranged in a matrix configuration. Each unit region may include a pixel region in which a photosensitive pixel Ps is disposed. The thin film transistor array 110 may detect X-rays emitted from an X-ray source, may convert the detected X-rays into electrical signals, and may output the electrical signals.

[0034] Each photosensitive pixel may include a PIN diode, which converts light in the visible light region converted from X-rays by a scintillator into an electrical signal and outputs the electrical signal, and a thin film transistor TFT, which transmits a detection signal output from the PIN diode to a readout circuit 140. A first end of the PIN diode may be connected to the thin film transistor, and a second end thereof may be connected to a bias line BL.

[0035] The gate electrode of the thin film transistor can be connected to the gate line GL carrying the scan signal. The source / drain electrodes of the thin film transistor can be respectively connected to the PIN diode and the data line DL, which carries the detection signal output from the PIN diode. Each bias line BL can extend to each data line DL in a parallel manner.

[0036] The gate driver 120 may sequentially apply gate signals to the thin film transistors of the light-sensitive pixels through the gate lines GL. The thin film transistors of the light-sensitive pixels may be turned on in response to the gate signals having a gate-on voltage level.

[0037] The bias power supply 130 may apply a driving voltage to the photosensitive pixel through the bias line BL. The bias power supply 130 may selectively apply a reverse bias or a forward bias to the PIN diode.

[0038] The readout circuit 140 may read out a detection signal received from a thin film transistor turned on in response to a gate signal of a gate driver. For example, a detection signal output from a PIN diode may be input to the readout circuit 140 through a thin film transistor and a data line DL.

[0039] The readout circuit 140 may have an offset readout period for reading out an offset image and an X-ray readout period for reading out a detection signal after X-ray exposure, and may read out the detection signal output from the photosensitive pixel during the X-ray readout period.

[0040] The readout circuit 140 may include a signal detector and a multiplexer. The signal detector includes a plurality of amplifying circuits corresponding to the data lines DL, respectively. Each amplifying circuit may include an amplifier, a capacitor, and a reset element.

[0041] The timing controller 150 may control the operation of the gate driver 120 by generating a start signal and a clock signal and providing each of the start signal and the clock signal to the gate driver 120. In addition, the timing controller 150 may control the operation of the readout circuit 140 by generating a readout control signal and a readout clock signal and providing each of the readout control signal and the readout clock signal to the readout circuit 140.

[0042] In the following, reference Figures 2 to 4 The digital X-ray detector device 200 according to one embodiment of the present disclosure is described in detail.

[0043] The digital X-ray detector device 200 according to one embodiment of the present disclosure includes a base substrate 210 .

[0044] The base substrate 210 may be embodied as a glass substrate made of glass, but is not limited thereto. In some cases where the base substrate 210 is used for a flexible digital X-ray detector device, a substrate made of a polyimide material and having flexible characteristics may be used as an example of the base substrate 210 .

[0045] On the base substrate 210, a plurality of unit regions are defined by a plurality of gate lines 223 and a plurality of data lines 225 that cross each other in an orthogonal manner. Each pixel may correspond to each unit region to define a plurality of pixel regions. The region corresponding to the gate line 223 and the data line 225 may be defined as a boundary region between pixel regions.

[0046] Each pixel includes a thin film transistor 220 and a PIN diode 230. A plurality of thin film transistors 220 and a plurality of PIN diodes 230 may be disposed on an array substrate having a plurality of pixel regions. The thin film transistor 220 and the PIN diode 230 of a pixel are described below, and unless otherwise specified, the configuration may also be applied to adjacent pixels.

[0047] A thin film transistor 220 including a first electrode 225 a , a second electrode 225 b , a gate electrode 223 a , and an active layer 221 is disposed over the base substrate 210 .

[0048] The buffer layer 211 may be disposed between the base substrate 210 and the thin film transistor 220. In this case, the buffer layer 211 may be made of, for example, silicon oxide (SiO x ) or silicon nitride (SiN x ) and can be provided as a multi-buffer layer consisting of multiple sub-layers.

[0049] The active layer 221 is disposed over the base substrate 210. The active layer 221 may be made of an oxide semiconductor material such as indium gallium zinc oxide (IGZO), but is not limited thereto, and may be made of low temperature polysilicon (LTPS) or amorphous silicon (a-Si).

[0050] The active layer 221 may include, for example, a channel region and a conductive region, wherein the channel region is disposed between the two conductive regions. In some examples, the conductive region may be divided into a first conductive region directly contacting the first electrode 225a and a second conductive region directly contacting the second electrode 225b.

[0051] The conductive region of the active layer 221 may be formed by making both ends of the active layer 221 conductive, and various types of methods such as dry etching, hydrogen plasma treatment, helium plasma treatment, etc. may be used as examples of a conductive treatment method.

[0052] The gate electrode 223 a is disposed over the active layer 221 , and the gate insulating layer 222 is disposed between the active layer 221 and the gate electrode 223 a to insulate the active layer 221 from the gate electrode 223 a .

[0053] For example, the gate electrode 223a may be disposed on the gate insulating layer 222 to correspond to a channel region of the active layer 221. The gate electrode 223a may be made of one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), copper (Cu), and alloys thereof, and may include a single layer or a multilayer.

[0054] The gate electrode 223a may extend from the gate line 223. The gate line 223 and the gate electrode 223a may be integrated with each other such that the gate electrode 223a is disposed in the gate line 223. Therefore, the gate line 223 and the gate electrode 223a may be disposed on the same layer.

[0055] The gate insulating layer 222 made of an inorganic material is disposed under the gate electrode 223 a , and for effective insulation, the gate insulating layer 222 may have an area that is the same as or larger than that of the gate electrode 223 a .

[0056] The gate electrode 223a and the gate insulating layer 222 may each be disposed in a central region of the active layer 221. In this example, a first region of the active layer 221 that is exposed due to not being covered by the gate electrode 223a (e.g., a first end of the active layer 221 excluding the channel region) may be a first conductive region, and a second region of the active layer 221 that is exposed due to not being covered by the gate electrode 223a (e.g., a second end of the active layer 221 excluding the channel region) may be a second conductive region.

[0057] In this case, the first conductive region may be a drain region, and the second conductive region may be a source region.

[0058] The source region of the active layer 221 may be disposed closer to the PIN diode 230 than the drain region, but is not limited thereto, and the positions of the source region and the drain region may be interchanged.

[0059] An interlayer insulating layer 224 made of an inorganic material may be disposed on the gate electrode 223a to cover the base substrate 210. A first electrode 225a and a second electrode 225b may each be disposed on the interlayer insulating layer 224.

[0060] The first electrode 225a may be disposed on a first side of the active layer 221, and the second electrode 225b may be disposed on a second side of the active layer 221. Thus, the gate electrode 223a may be disposed between the first electrode 225a and the second electrode 225b. The first contact hole 224a may be disposed in the interlayer insulating layer 224 at a region where the active layer 221 overlaps with the first electrode 225a, and the second contact hole 224b may be disposed in the interlayer insulating layer 224 at a region where the active layer 221 overlaps with the second electrode 225b.

[0061] In some examples, the first contact hole 224a may be disposed on the drain region of the active layer 221, and the second contact hole 224b may be disposed on the source region of the active layer 221. Therefore, the first electrode 225a is connected to the drain region of the active layer 221 through the first contact hole 224a, and the second electrode 225b is connected to the source region of the active layer 221 through the second contact hole 224b.

[0062] Therefore, the first electrode 225 a connected to the drain region may be a drain electrode, and the second electrode 225 b connected to the source region may be a source electrode.

[0063] The first electrode 225 a and the second electrode 225 b may each extend from the data line 225 , and may each be disposed on the same layer as the data line 225 .

[0064] The data line 225 may be made of one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), copper (Cu), and alloys thereof, but is not limited thereto.

[0065] The first passivation layer 226 may be disposed on or above the thin film transistor 220 to cover the entire surface of the base substrate. The first passivation layer 226 may be made of a material such as silicon oxide (SiO x ) or silicon nitride (SiN x ) is made of inorganic materials, but is not limited thereto. The first passivation layer 226 can protect the lower thin film transistor 220, for example, the active layer 221.

[0066] The PIN diode 230 is disposed on the first passivation layer 226 to be connected to the lower thin film transistor 220. The PIN diode 230 may be disposed in a pixel region.

[0067] The PIN diode 230 may include a lower electrode 231 connected to the thin film transistor 220 , a PIN layer 232 on the lower electrode 231 , and an upper electrode 233 on the PIN layer 232 .

[0068] The lower electrode 231 may be used as a pixel electrode in the PIN diode 230. According to the characteristics of the PIN diode 230, the lower electrode 231 may be made of an opaque metal (e.g., molybdenum Mo), or made of at least one of transparent oxides (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO)).

[0069] The lower electrode 231 may be connected to the second electrode 225 b of the thin film transistor 220 through a third contact hole 226 a which is a contact hole in the first passivation layer 226 , so that the thin film transistor 220 may be connected to the PIN diode 230 .

[0070] The PIN layer 232 may be disposed on the lower electrode 231 to convert the visible light converted from the X-ray into an electrical signal. At this point, the scintillator may convert the X-ray into the visible light.

[0071] The PIN layer 232 can be set by sequentially stacking an n+ type semiconductor layer containing n-type impurities with a high concentration, an n- type semiconductor layer containing n-type impurities with a low concentration, an I (intrinsic) type semiconductor layer 232i, a p- type semiconductor layer containing p-type impurities with a low concentration, and a p+ type semiconductor layer containing p-type impurities with a high concentration on the lower electrode 231.

[0072] The I-type semiconductor layer may be relatively thicker than each of the n+ type semiconductor layer and the n- type semiconductor layer, the p- type semiconductor layer and the p+ type semiconductor layer. The PIN layer 232 may be made of a material capable of converting visible light (converted from X-rays emitted from the X-ray source) into an electrical signal, such as a-Se, HgI 2 、CdTe、PbO、PbI 2 ,BiI 3 , GaAs and Ge.

[0073] The upper electrode 233 may be disposed on the PIN layer 232. The upper electrode 233 may be made of at least one of transparent oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO), and may improve a fill factor of the PIN diode 230.

[0074] The second passivation layer 235 may be disposed above the PIN diode 230. The second passivation layer 235 may be made of, for example, silicon oxide (SiO x ) or silicon nitride (SiN x ) is made of an inorganic material, but is not limited thereto. The second passivation layer 235 may cover up to the side surface of the PIN diode 230 to protect the side surface of the PIN diode 230 from moisture or other foreign substances.

[0075] The bias electrode 243 may be disposed on the second passivation layer 235 on the PIN diode 230. The bias electrode 243 may be connected to the upper electrode 233 of the PIN diode 230 through a fourth contact hole 235a which is a contact hole in the second passivation layer 235 and may apply a bias voltage to the PIN diode 230.

[0076] The bias electrode 243 may be branched from a bias line 241 arranged in parallel with the data line 225 .

[0077] In this case, the first planarization layer 237 may be disposed between the second passivation layer 235 and the bias electrode 243 to cover the entire surface of the base substrate 210 including the PIN diode 230 .

[0078] The first planarization layer 237 may be made of an organic material such as PAC (photo acrylic), but is not limited thereto.

[0079] In this case, the fifth contact hole 237a is provided in the first planarization layer 237 to expose the upper electrode 233 to a position of the second passivation layer 235 corresponding to the fourth contact hole 235a. The bias electrode 243 may be electrically connected to the upper electrode 233 through the fourth contact hole 235a and the fifth contact hole 237a.

[0080] The second planarization layer 245 may be disposed on the bias electrode 243 to cover the entire surface of the base substrate 210 .

[0081] The second planarization layer 245 may be made of an organic material such as photo acrylic (PAC), but is not limited thereto.

[0082] The scintillator layer 250 may be disposed on the second planarization layer 245 to cover the PIN diode 230 .

[0083] In some examples, the scintillator layer 250 is disposed over each of the thin film transistor 220 and the PIN diode 230 to cover each of the thin film transistor 220 and the PIN diode 230 .

[0084] Since the scintillator layer 250 may be directly deposited on the array substrate 201, planarization of the lower surface of the scintillator layer 250 may be required. Therefore, the second planarization layer 245 is provided to planarize the lower surface of the scintillator layer 250, thereby facilitating the formation of the scintillator layer 250 by deposition of the scintillator.

[0085] The scintillator layer 250 may grow in a vertical direction to have a plurality of columnar crystal phases so that a plurality of scintillator columnar crystals may be arranged in a side-by-side manner, but is not limited thereto. The scintillator may be made of a material such as cesium iodide (CsI), but is not limited thereto.

[0086] The digital X-ray detector device 200 according to the present disclosure operates as follows.

[0087] X-rays are irradiated to the digital X-ray detector device 200. The scintillator layer 250 converts the X-rays into visible light. The PIN layer 232 of the PIN diode 230 converts light in the visible region into an electrical signal.

[0088] For example, when light in the visible region is irradiated to the PIN layer 232, the I-type semiconductor layer is depleted by each of the n-type semiconductor layer and the p-type semiconductor layer, thereby generating an electric field therein. Then, holes and electrons generated by light drift based on the electric field and are collected in the p-type semiconductor layer and the n-type semiconductor layer, respectively.

[0089] The PIN diode 230 converts light in the visible region into an electric signal and transmits the electric signal to the thin film transistor 220. The electric signal thus transmitted is displayed as an image signal via a data line 225 connected to the thin film transistor 220.

[0090] Reference Figure 4 The PIN diode 230 according to an embodiment of the present disclosure is described in detail.

[0091] According to an embodiment of the present disclosure, a PIN diode includes a lower electrode, a PIN layer and an upper electrode, and the PIN layer includes a p+ type semiconductor layer, a p-type semiconductor layer, an intrinsic semiconductor layer, an n-type semiconductor layer and an n+ type semiconductor layer.

[0092] In some examples, the PIN layer is formed by sequentially stacking an n+ type semiconductor layer, an n- type semiconductor layer, an intrinsic semiconductor layer, a p- type semiconductor layer, and a p+ type semiconductor layer on the lower electrode.

[0093] The p+ type semiconductor layer and the p- type semiconductor layer each contain a p type impurity, and are doped with the p type impurity containing at least one of the Group III elements such as boron (B).

[0094] The p+ type semiconductor layer is doped with a high concentration of p type impurities, the p- type semiconductor layer is doped with a low concentration of p type impurities, and the p- type semiconductor layer is doped with a p type impurity concentration lower than that of the p+ type semiconductor layer.

[0095] In this case, the p-type semiconductor layer may contain p-type impurities corresponding to 1 / 20 to 1 / 10 of the p-type impurities of the p+ type semiconductor layer.

[0096] The n+ type semiconductor layer and the n- type semiconductor layer each contain an n type impurity, and may each be doped with an n type impurity including at least one of Group V elements such as phosphorus (P), arsenic (As), and antimony (Sb).

[0097] The n+ type semiconductor layer is doped with a high concentration of n type impurities, the n- type semiconductor layer is doped with a low concentration of n type impurities, and the n- type semiconductor layer is doped with a lower n type impurity concentration than that of the n+ type semiconductor layer.

[0098] In this case, the n-type semiconductor layer may include n-type impurities corresponding to 1 / 10 to 1 / 5 of the n-type impurities of the n+ type semiconductor layer.

[0099] For example, according to the present disclosure, in the PIN layer of the PIN diode, the p-type semiconductor layer and the p+ type semiconductor layer are each disposed above the intrinsic semiconductor layer, and the n-type semiconductor layer and the n+ type semiconductor layer are each disposed below the intrinsic semiconductor layer. That is, the multi-doped layer is disposed above and below the intrinsic semiconductor layer to minimize the leakage current of the PIN diode. This configuration is described in detail below.

[0100] In an off-state in which light is not applied to the PIN diode but a reverse bias is applied, electron and hole pairs are not provided in the PIN diode, and thus, current may not flow.

[0101] The intrinsic semiconductor layer of a PIN diode is the region where electron and hole pairs meet and act as a capacitor or a variable resistor depending on the applied voltage.

[0102] Since the digital X-ray detector device operates based on current generated in proportion to the applied light when light is applied to the PIN diode that absorbs light, maintaining a low current state in the off state is important for the characteristics of the digital X-ray detector device.

[0103] Since the PIN diode may be implemented with a thin film having a thickness of at least several tens of nanometers (nm), leakage current may be generated due to various reasons even if a reverse voltage is applied.

[0104] For example, leakage current may be generated along the side surface of the PIN diode directly contacting the passivation layer, and leakage current may also be generated by impurities in the intrinsic semiconductor layer.

[0105] In particular, the digital X-ray detector device is sensitive to leakage current because the digital X-ray detector device adjusts the value in units of femtoamperes (fA). Therefore, it is important for the digital X-ray detector device to minimize the leakage current.

[0106] Therefore, according to the present disclosure, a p-type semiconductor layer may not be disposed above the intrinsic semiconductor layer, but a multiple p-type semiconductor layer including a p+ type semiconductor layer and a p-type semiconductor layer having different impurity concentrations may be disposed above the intrinsic semiconductor layer, and an n-type semiconductor layer may not be disposed below the intrinsic semiconductor layer, but a multiple n-type semiconductor layer including an n+ type semiconductor layer and an n-type semiconductor layer having different impurity concentrations may be disposed below the intrinsic semiconductor layer to prevent the emission of holes and electrons, thereby minimizing the occurrence of leakage current.

[0107] Based on a reverse voltage applied to the PIN diode, holes are accumulated in a p-type semiconductor layer disposed above the intrinsic semiconductor layer and electrons are accumulated in an n-type semiconductor layer disposed below the intrinsic semiconductor layer, and the intrinsic semiconductor layer is in a depletion state.

[0108] In this case, holes in the p-type semiconductor layer and electrons in the n-type semiconductor layer are ejected, thereby generating leakage current.

[0109] According to the present disclosure, since a multi-p-type semiconductor layer including a p+ type semiconductor layer and a p-type semiconductor layer is provided, even if holes are ejected from the p+ type semiconductor layer, the holes cannot be ejected below the p+ type semiconductor layer due to the electric field generated in the p-type semiconductor layer, and the holes are trapped in the p-type semiconductor layer.

[0110] Similarly, since a multi-n-type semiconductor layer including an n+ type semiconductor layer and an n- type semiconductor layer is provided, even if electrons are ejected from the n+ type semiconductor layer, due to the electric field generated in the n- type semiconductor layer, the electrons are not ejected above the n+ type semiconductor layer and are trapped in the n- type semiconductor layer.

[0111] According to the present disclosure, multiple p-type semiconductor layers and multiple n-type semiconductor layers having different impurity concentrations are provided to minimize the reduction in light transmittance of a PIN diode and effectively minimize the emission of holes and electrons.

[0112] Even if the p-type semiconductor layer includes a p+ type semiconductor layer having a thick thickness to prevent the emission of some holes, the p+ type semiconductor layer including a high impurity concentration may block the transmission of light based on the light applied to the PIN diode. When the light transmittance of the PIN diode is reduced, the performance of the PIN diode in the on state may be deteriorated.

[0113] According to the present disclosure, a p-type semiconductor layer having a low impurity concentration is disposed below a p+ type semiconductor layer having a high impurity concentration to minimize a reduction in light transmittance due to the high impurity concentration and prevent the ejection of holes, thereby eliminating current leakage.

[0114] Similarly, the n-type semiconductor layer may be implemented as a multiple n-type semiconductor layer including an n+ type semiconductor layer and an n- type semiconductor layer having different concentrations to obtain the same effect.

[0115] When the p-type semiconductor layer has a thickness corresponding to 80% to 100% of the thickness of the p+ type semiconductor layer and the n-type semiconductor layer has a thickness corresponding to 40% to 50% of the thickness of the n+ type semiconductor layer, the effect can be effectively obtained.

[0116] When the p-type semiconductor layer has a thickness thicker than that of the p+ type semiconductor layer, leakage current characteristics of the PIN diode can be improved, but light transmittance is reduced, and based on the degraded light transmittance, light efficiency (ie, sensitivity) of the PIN diode may be degraded.

[0117] Furthermore, when the thickness of the n-type semiconductor layer is more than 50% thicker than that of the n+ type semiconductor layer, a depletion region decreases and the number of electron-hole pairs (EHP) decreases, thereby degrading light efficiency characteristics.

[0118] In the case where the thickness of the intrinsic semiconductor layer of the PIN diode is in the range of 1 to 2 μm and the p+ type semiconductor layer has The thickness of the p-type semiconductor layer is to The thickness of the n+ type semiconductor layer is The thickness of the n-type semiconductor layer is to In some cases where the thickness is , the light efficiency can be effectively improved and the emission of holes and electrons can be effectively prevented.

[0119] In addition, when the p+ type semiconductor layer also contains 10 to 20 times the p-type impurities corresponding to the p-type impurities of the p-type semiconductor layer, for example, the p-type semiconductor layer contains 1 / 20 to 1 / 10 of the p-type impurities corresponding to the p+ type semiconductor layer, the blocking of light transmittance can be minimized and the emission of holes can be minimized.

[0120] In addition, when the n+ type semiconductor layer also contains 5 to 10 times the n-type impurities corresponding to the n-type semiconductor layer, for example, the n-type semiconductor layer contains 1 / 10 to 1 / 15 of the n-type impurities corresponding to the n+ type semiconductor layer, the reduction in light transmittance can be minimized and the emission of electrons can be minimized.

[0121] In another embodiment of the present disclosure, the p+ type semiconductor layer has the same thickness as the n+ type semiconductor layer, and the p- type semiconductor layer has the same thickness as the n- type semiconductor layer to minimize the reduction in light transmittance and further minimize the occurrence of leakage current by preventing the emission of holes and electrons.

[0122] In some examples, the intrinsic semiconductor layer can be depleted to minimize leakage current of the PIN diode when a reverse voltage is applied by preventing the ejection of holes in the p-type semiconductor layer and electrons in the n-type semiconductor layer.

[0123] In this case, the p-type semiconductor layer and the n-type semiconductor layer each generate a uniform electric field to equalize the force pulling out holes in the p-type semiconductor layer and the force pulling out electrons in the n-type semiconductor layer, thereby minimizing holes and electrons ejected from the semiconductor layers.

[0124] Therefore, according to another embodiment of the present disclosure, the p+ type semiconductor layer may have the same thickness as the n+ type semiconductor layer, and the p- type semiconductor layer may have the same thickness as the n- type semiconductor layer to balance the force of pulling out holes in the p-type semiconductor layer and the force of pulling out electrons in the n-type semiconductor layer, thereby minimizing the reduction in light transmittance and minimizing the occurrence of leakage current.

[0125] Figure 5A and Figure 5B Leakage currents measured for the PIN diodes in Comparative Examples 1 and 2 having a stacked structure of PIN diodes are shown. Figure 5C An exemplary leakage current of a PIN diode in an embodiment having a stacked structure of PIN diodes is shown.

[0126] In some examples, Figure 5A Corresponding to Comparative Example 1, when a digital X-ray detector device including an amorphous silicon (a-Si) thin film transistor and a PIN diode including a p-type semiconductor layer, an intrinsic semiconductor layer and an n-type semiconductor layer is in a cut-off state, a leakage current of the PIN diode is measured.

[0127] In Comparative Example 1, Figure 5A As shown, the minimum leakage current in the off state is 5.5fA.

[0128] Figure 5B Corresponding to Comparative Example 2, when a digital X-ray detector device including an oxide thin film transistor and a PIN diode including a p-type semiconductor layer, an intrinsic semiconductor layer, and an n-type semiconductor layer is in an off state, a leakage current of the PIN diode is measured.

[0129] In Comparative Example 2, Figure 5B As shown, the minimum leakage current in the off state is 2.74fA.

[0130] Figure 5CCorresponding to an embodiment of the present disclosure, when a digital X-ray detector device including an oxide thin film transistor and a PIN diode having a p+ type semiconductor layer, a p- type semiconductor layer, an intrinsic semiconductor layer, an n- type semiconductor layer and an n+ type semiconductor layer is in a cut-off state, the leakage current of the PIN diode is measured.

[0131] In an embodiment, Figure 5C As shown, the minimum leakage current in the off state is 0.51fA.

[0132] The leakage current in the embodiment is significantly reduced compared to Comparative Example 1. The leakage current in the embodiment is significantly reduced compared to the leakage current in Comparative Example 2 for the same thin film transistor. For example, the leakage current is reduced from 2.74 fA in the embodiment to 0.51 fA in Comparative Example 2, and thus, according to the stacked structure of the PIN layer of the PIN diode, the leakage current can be minimized.

[0133] According to the present disclosure, a digital X-ray detector device includes a base substrate, a driving thin film transistor arranged above the base substrate, a PIN diode connected to the driving thin film transistor and including a lower electrode, a PIN layer and an upper electrode, and the PIN layer includes a p+ type semiconductor layer, a p-type semiconductor layer, an intrinsic semiconductor layer, an n-type semiconductor layer and an n+ type semiconductor layer.

[0134] In this case, the p+ type semiconductor layer and the p type semiconductor layer each contain p type impurities, the concentration of the p type impurities of the p- type semiconductor layer is lower than the concentration of the p type impurities of the p+ type semiconductor layer, and the p type impurities may include at least one of the Group III elements.

[0135] The p-type semiconductor layer may have a thickness corresponding to 80% to 100% of the thickness of the p+ type semiconductor layer, and the p-type semiconductor layer may contain p type impurities corresponding to 1 / 20 to 1 / 10 of the p type impurities of the p+ type semiconductor layer.

[0136] In addition, the n+ type semiconductor layer and the n- type semiconductor layer each contain n type impurities, the concentration of the n- type semiconductor layer is lower than the concentration of the n+ type semiconductor layer, and the n type semiconductor layer may include at least one of the Group V elements.

[0137] The n-type semiconductor layer may have a thickness corresponding to 40% to 50% of the thickness of the n+ type semiconductor layer, and the n-type semiconductor layer may contain n type impurities corresponding to 1 / 10 to 1 / 5 of the n type impurities of the n+ type semiconductor layer.

[0138] In addition, the p+ type semiconductor layer may have the same thickness as the n+ type semiconductor layer, and the p- type semiconductor layer may have the same thickness as the n- type semiconductor layer.

[0139] Although the present disclosure has been described with reference to the exemplary drawings, the present disclosure is not limited to the embodiments and drawings disclosed herein, and those skilled in the art may make various modifications within the scope of the technical concept of the present disclosure. In addition, even if the working effect obtained based on the configuration of the present disclosure is not explicitly described in the description of the embodiments of the present disclosure, it must be recognized that the effect that can be predicted based on the corresponding configuration is also recognized.

Claims

1. A thin film transistor array substrate for a digital X-ray detector device, comprising: base substrate; a driving thin film transistor disposed above the base substrate; as well as A PIN (p-type semiconductor-intrinsic semiconductor-n-type semiconductor) diode, the PIN diode is connected to the driving thin film transistor and includes a lower electrode, a PIN layer and an upper electrode; as well as The PIN layer includes a p+ type semiconductor layer, a p- type semiconductor layer, an intrinsic semiconductor layer, an n- type semiconductor layer and an n+ type semiconductor layer. wherein the p-type semiconductor layer has a thickness corresponding to 80% to 100% of the thickness of the p+ type semiconductor layer, and The n-type semiconductor layer has a thickness corresponding to 40% to 50% of the thickness of the n+ type semiconductor layer.

2. The thin film transistor array substrate for a digital X-ray detector device according to claim 1, in, The p+ type semiconductor layer and the p- type semiconductor layer each contain p type impurities, and The p-type impurity concentration of the p-type semiconductor layer is lower than the p-type impurity concentration of the p+ type semiconductor layer.

3. The thin film transistor array substrate for a digital X-ray detector device according to claim 2, wherein: The p-type impurity includes at least one of Group III elements.

4. The thin film transistor array substrate for a digital X-ray detector device according to claim 2, wherein: The p-type semiconductor layer contains p-type impurities corresponding to 1 / 20 to 1 / 10 of the p-type impurities of the p+ type semiconductor layer.

5. The thin film transistor array substrate for a digital X-ray detector device according to claim 1, in, The n+ type semiconductor layer and the n- type semiconductor layer each contain n-type impurities, and The n-type impurity concentration of the n-type semiconductor layer is lower than the n-type impurity concentration of the n+ type semiconductor layer.

6. The thin film transistor array substrate for a digital X-ray detector device according to claim 5, wherein: The n-type impurity includes at least one of Group V elements.

7. The thin film transistor array substrate for a digital X-ray detector device according to claim 5, wherein: The n-type semiconductor layer contains n-type impurities corresponding to 1 / 10 to 1 / 5 of the n-type impurities of the n+ type semiconductor layer.

8. The thin film transistor array substrate for a digital X-ray detector device according to claim 1, in, The p+ type semiconductor layer has the same thickness as the n+ type semiconductor layer, and The p-type semiconductor layer has the same thickness as that of the n-type semiconductor layer.

9. A thin film transistor array substrate for a digital X-ray detector device, comprising: base substrate; an active layer disposed above the base substrate; a gate insulating layer disposed above the active layer; a gate electrode disposed on the gate insulating layer; an interlayer insulating layer disposed on the gate electrode; a first electrode and a second electrode, the first electrode being disposed on the interlayer insulating layer and being configured to be connected to the active layer through a first contact hole in the interlayer insulating layer, and the second electrode being disposed on the interlayer insulating layer and being configured to be connected to the active layer through a second contact hole in the interlayer insulating layer; as well as a PIN diode comprising a lower electrode electrically connected to the second electrode, a PIN layer, and an upper electrode; The PIN layer includes a p+ type semiconductor layer, a p- type semiconductor layer, an intrinsic semiconductor layer, an n- type semiconductor layer and an n+ type semiconductor layer. wherein the p-type semiconductor layer has a thickness corresponding to 80% to 100% of the thickness of the p+ type semiconductor layer, and The n-type semiconductor layer has a thickness corresponding to 40% to 50% of the thickness of the n+ type semiconductor layer.

10. A digital X-ray detector device, comprising: The thin film transistor array substrate for a digital X-ray detector device according to claim 1; as well as A scintillator layer is disposed above the thin film transistor array substrate for the digital X-ray detector device.

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