Fully digital phase-locked loop system and frequency calibration method for full digital phase-locked loop

Abstract

The present invention discloses a fully digital phase-locked loop system and a frequency calibration method for the fully digital phase-locked loop, wherein the fully digital phase-locked loop system comprises a fully digital phase-locked loop, which is used to generate a first control code and a second control code when the corresponding loop is locked according to a carrier frequency signal and a crystal frequency signal respectively during a calibration phase, and to generate a target output frequency signal according to the crystal frequency signal and the second frequency magnification during a normal working phase; a calibration unit is used to calibrate the first frequency magnification according to the first control code and the second control code to generate a second frequency magnification. The fully digital phase-locked loop system and the frequency calibration method for the fully digital phase-locked loop can track the crystal frequency, output a frequency signal that meets the system requirements, and reduce the risk of a decrease in the frequency accuracy of the fully digital phase-locked loop output when the carrier is interfered or there is no carrier.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to a full digital phase locked loop system and a frequency calibration method of the full digital phase locked loop. Background Art

[0002] In the past decade, the wireless RF chip market has been booming, and with the continuous advancement of CMOS manufacturing technology, digital technology has played an increasingly important role in RF chips. That is, more and more circuits will be implemented by digital circuits. This is because it can reduce the chip area, reduce costs, and enhance the configurability and process portability of RF chips. In the entire RF chip, the first digital circuit to replace the original analog circuit was the phase-locked loop in the transceiver. Usually, in RF applications, the accuracy and frequency range of the phase-locked loop output frequency are relatively high, which is a great challenge for the phase-locked loop implemented by digital circuits.

[0003] With the continuous expansion of personal wireless communication methods, new mobile electronic terminals, especially mobile phones, are becoming more and more powerful and feature-rich. Among them, the market prospect of Near-field-communication (NFC) function is very broad.

[0004] NFC is a short-range wireless communication technology. Devices using NFC technology can exchange data when they are close to each other, such as swiping bus cards, recharging bus cards, and small payment services in shopping malls, making people's daily lives safer and faster.

[0005] When the NFC chip is working, it is required that the frequency signal output by the digital phase-locked loop (DPLL) has the same phase and frequency as the carrier signal, and is provided to the transceiver circuit for modulation and demodulation. Therefore, when the digital phase-locked loop is working, it will track the carrier frequency signal to output a frequency signal required by the system. However, in some cases, such as when the chip transmits a high-power signal, the carrier signal will be interfered, and in some cases, there will be no carrier signal temporarily. These situations will cause the digital phase-locked loop to fail to provide the frequency signal required by the system.

[0006] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. Summary of the invention

[0007] In order to solve the above technical problems, the present invention provides an all digital phase-locked loop (ADPLL) system and a frequency calibration method for the all digital phase-locked loop, which can track the crystal frequency and output a frequency signal that meets the system requirements, thereby reducing the risk of reduced frequency accuracy of the all digital phase-locked loop output when the carrier is interfered with or there is no carrier, and has low cost and is easy to implement.

[0008] According to a first aspect of the present disclosure, a fully digital phase-locked loop system is provided, comprising: a fully digital phase-locked loop, comprising a digital oscillator, for generating a first control code and a second control code corresponding to loop locking according to a carrier frequency signal and a crystal frequency signal respectively during a calibration phase, and for generating a target output frequency signal according to the crystal frequency signal and the second frequency gain during a normal working phase; a calibration unit, connected to the fully digital phase-locked loop, for calibrating a first frequency gain according to the first control code and the second control code to generate a second frequency gain, wherein the first frequency gain is a ratio of a frequency value corresponding to the target output frequency signal to a frequency value corresponding to the carrier frequency signal.

[0009] Optionally, the all-digital phase-locked loop system further includes: a first frequency divider connected to the all-digital phase-locked loop, and configured to divide the target output frequency signal according to system requirements to generate a system clock signal.

[0010] Optionally, the all-digital phase-locked loop system further includes: a first frequency generating unit, used for providing a carrier frequency signal; and a second frequency generating unit, used for providing a crystal frequency signal.

[0011] Optionally, the all-digital phase-locked loop system also includes: a selection unit, a first input end connected to the first frequency generating unit, a second input end connected to the second frequency generating unit, and an output end connected to the all-digital phase-locked loop, for providing the carrier frequency signal and the crystal frequency signal to the all-digital phase-locked loop in a time-sharing manner.

[0012] Optionally, the calculation formula of the second frequency amplification factor is: Among them, FDR2 is the second frequency magnification, FDR1 is the first frequency magnification, D1 is the first control code, D2 is the second control code, K V is the gain of the digital oscillator, and fc is the frequency value corresponding to the carrier frequency signal.

[0013] Optionally, the frequency value corresponding to the target output frequency signal is equal to the product of the frequency value corresponding to the crystal frequency signal and the second frequency amplification factor.

[0014] According to a second aspect of the present disclosure, a frequency calibration method for a fully digital phase-locked loop is provided, including: obtaining a first control code based on a carrier frequency signal; obtaining a second control code based on a crystal frequency signal; calibrating a first frequency gain based on the first control code and the second control code to obtain a second frequency gain; obtaining a target output frequency signal based on the crystal frequency signal and the second frequency gain, wherein the first frequency gain is a ratio of a frequency value corresponding to the target output frequency signal to a frequency value corresponding to the carrier frequency signal.

[0015] Optionally, after obtaining the target output frequency signal based on the crystal frequency signal and the second frequency magnification factor, the method further includes: dividing the target output frequency signal according to system requirements to obtain a system clock signal.

[0016] Optionally, the frequency value corresponding to the target output frequency signal is equal to the product of the frequency value corresponding to the crystal frequency signal and the second frequency amplification factor.

[0017] Optionally, obtaining the first control code based on the carrier frequency signal includes: inputting the carrier frequency signal into a fully digital phase-locked loop, and obtaining the first control code when the loop of the fully digital phase-locked loop is locked.

[0018] Optionally, obtaining the second control code based on the crystal frequency signal includes: inputting the crystal frequency signal into a fully digital phase-locked loop, and obtaining the second control code when the loop of the fully digital phase-locked loop is locked.

[0019] Optionally, the first frequency gain is calibrated based on the first control code and the second control code to obtain the second frequency gain, including: obtaining the difference between the first control code and the second control code; based on the difference, obtaining a change in the output frequency signal generated by the fully digital phase-locked loop when receiving the crystal frequency signal relative to the target output frequency signal; and calibrating the first frequency gain according to the change to obtain the second frequency gain.

[0020] The beneficial effects of the present invention are as follows: the present invention relates to a fully digital phase-locked loop system and a frequency calibration method for the fully digital phase-locked loop, which uses a crystal frequency signal instead of a carrier frequency signal as a reference frequency signal when the fully digital phase-locked loop is working normally. Due to the characteristics of the crystal frequency signal itself, such as high precision and high stability, the risk of a decrease in the frequency accuracy of the fully digital phase-locked loop output when the carrier frequency signal (referred to as carrier) is interfered with or there is no carrier frequency signal can be reduced, and the anti-interference ability of the fully digital phase-locked loop system can be enhanced. At the same time, the calibration unit is used for calibration, which can improve the accuracy of the output frequency signal generated by the fully digital phase-locked loop when the crystal frequency signal is used as the reference frequency signal.

[0021] On the other hand, the all-digital phase-locked loop system involved in the present disclosure has a simple structure, low cost, and is easy to implement.

[0022] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0024] Figure 1 A structural block diagram of a fully digital phase-locked loop system provided according to an embodiment of the present disclosure is shown;

[0025] Figure 2 A schematic diagram showing the structure of a fully digital phase-locked loop system provided according to an embodiment of the present disclosure is shown;

[0026] Figure 3 A schematic diagram of the structure of a fully digital phase-locked loop provided according to an embodiment of the present disclosure is shown;

[0027] Figure 4 A flow chart of a frequency calibration method for a fully digital phase-locked loop provided according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0028] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0030] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

[0031] refer to Figure 1 , Figure 1 A structural block diagram of a fully digital phase-locked loop system provided according to an embodiment of the present disclosure is shown.

[0032] like Figure 1 As shown, in the present disclosure, the full digital phase-locked loop system includes a full digital phase-locked loop 10 and a first frequency divider 20 .

[0033] The input end of the all-digital phase-locked loop 10 receives a reference frequency signal Fin. After the reference frequency signal Fin is loop-locked by the all-digital phase-locked loop 10, it is amplified by a settable gain (referred to as FDR in this article) to obtain an output frequency signal Fout with a higher frequency, which is output at the output end of the all-digital phase-locked loop 10. At this time, fout=fin*FDR...................(1). Where fin is the frequency value of the reference frequency signal Fin, and fout is the frequency value of the output frequency signal Fout.

[0034] The first frequency divider 20 is connected to the output end of the all-digital phase-locked loop 10, and is used to divide the output frequency signal Fout output by the all-digital phase-locked loop 10 according to the system requirements to generate a corresponding system clock signal Fref. When dividing the output frequency signal Fout, the first frequency divider 20 sets different first frequency division factors (in this article, denoted as N, and N is a positive number) according to different system requirements, and then divides the output frequency signal Fout according to the corresponding first frequency division factor N, so as to generate different system clock signals Fref based on the same output frequency signal Fout. At this time, fref=fout / N...............(2). Wherein, fref is the frequency value of the system clock signal Fref.

[0035] In the present disclosure, a plurality of first frequency dividers 20 can be set in the full digital phase-locked loop system, and the output frequency signal Fout can be divided simultaneously by the plurality of first frequency dividers 20 to simultaneously generate a plurality of different system clock signals Fref, thereby supporting the simultaneous operation of a plurality of systems with different requirements.

[0036] It should be understood that the fully digital phase-locked loop 10 in the present disclosure can be constructed using an existing fully digital phase-locked loop structure, so its internal structure can be regarded as known, and the internal structure of the fully digital phase-locked loop 10 will not be described in detail herein, but is only for reference. Figure 3 The internal structure of the fully digital phase-locked loop 10 is generally described to facilitate understanding of the technical solution disclosed in the present invention.

[0037] Figure 3 A schematic diagram of the structure of a fully digital phase-locked loop according to an embodiment of the present disclosure is shown. Figure 3 As shown, in the embodiment of the present disclosure, the all-digital phase-locked loop 10 includes: a phase detector 11, a time-to-digital converter 12, a digital loop filter 13, a digital oscillator 14 and a second frequency divider 15.

[0038] The first input terminal of the phase detector 11 receives the reference frequency signal Fin, the second input terminal of the phase detector 11 receives the feedback frequency signal Fdiv, and the output terminal of the phase detector 11 outputs an indication signal representing the phase difference between the reference frequency signal Fin and the feedback frequency signal Fdiv.

[0039] The time-to-digital converter 12 is connected to the phase detector 11 and is used to generate a corresponding digital signal according to the indication signal output by the phase detector 11 .

[0040] The digital loop filter 13 is connected to the time-to-digital converter 12 and is used for filtering the digital signal output by the time-to-digital converter 12 to obtain a control code for controlling the digital oscillator 14 .

[0041] The digital oscillator 14 is connected to the digital loop filter 13 and is used for receiving the control code output by the digital loop filter 13 and generating an oscillation signal as the output frequency signal Fout of the full digital phase-locked loop under the control of the control code.

[0042] The second frequency divider 15 is connected to the digital oscillator 14 and the phase detector 11 respectively, and is used to divide the output frequency signal Fout output by the digital oscillator 14 according to a second frequency division factor (represented as M, and M is a positive number) to generate a feedback frequency signal Fdiv.

[0043] It can be understood that in the fully digital phase-locked loop, the output frequency signal Fout is fed back to the input end of the phase detector 11 as the feedback frequency signal Fdiv after being divided by M. At this time, the output frequency signal Fout of the fully digital phase-locked loop 10 is equivalent to the multiplied output of M times the input reference frequency signal Fin. Therefore, the multiplication factor corresponding to the second frequency division factor M in the fully digital phase-locked loop corresponds to the frequency gain in this article. Correspondingly, by adjusting the second frequency division factor M of the second frequency divider 15, the frequency gain of the fully digital phase-locked loop system can be adjusted accordingly.

[0044] Further, in the present disclosure, both the first frequency divider 20 and the second frequency divider 15 in the full digital phase-locked loop system can be fractional frequency dividers capable of performing fractional frequency division.

[0045] It is understandable that the existing all-digital phase-locked loop system uses a carrier frequency signal as a reference frequency signal Fin to output a frequency signal required by the system, but because the carrier frequency signal is easily interfered in some situations, it will affect the precision and accuracy of the output system clock signal Fref. Therefore, in the technical solution disclosed in the present invention, a crystal frequency signal with characteristics such as high precision and high stability is used instead of the carrier frequency signal as the reference frequency signal Fin to output the frequency signal required by the system. However, since the frequency of the crystal frequency signal and the carrier frequency signal are different, a frequency calibration method is required to allow the frequency and phase of the system clock signal obtained by the all-digital phase-locked loop system when using a crystal frequency signal with a fixed frequency as the reference frequency signal Fin to be infinitely close to the frequency and phase of the system clock signal obtained when using the carrier frequency signal as the reference frequency signal Fin.

[0046] refer to Figure 2 , Figure 2 The structure diagram of the all-digital phase-locked loop system provided according to the embodiment of the present disclosure is further shown. Figure 2 As shown, in Figure 1 On the basis of, the all-digital phase-locked loop system in the present disclosure further includes a calibration unit 50, which can cooperate with the all-digital phase-locked loop 10 to implement the calibration function of the all-digital phase-locked loop 10 in the calibration phase.

[0047] Accordingly, in the calibration phase of the all-digital phase-locked loop 10, the all-digital phase-locked loop 10 generates the first control code D1 and the second control code D2 corresponding to the loop locking according to the carrier frequency signal Fc and the crystal frequency signal Fx. Figure 3 When the all-digital phase-locked loop 10 receives the carrier frequency signal Fc as the reference frequency signal Fin to lock the loop, the control code received by the digital oscillator 14 after locking is the first control code D1; and when the all-digital phase-locked loop 10 receives the crystal frequency signal Fx as the reference frequency signal Fin to lock the loop, the control code received by the digital oscillator 14 after locking is the second control code D2.

[0048] The calibration unit 50 is connected to the all-digital phase-locked loop 10 and is used to calibrate the first frequency gain (herein, FDR1) according to the first control code D1 and the second control code D2 to generate the second frequency gain (herein, FDR2).

[0049] Furthermore, in the normal operation stage of the all-digital phase-locked loop 10, the all-digital phase-locked loop 10 generates an output frequency signal Fout according to the crystal frequency signal Fx and the second frequency gain FDR2. At this time, the output frequency signal Fout is the target output frequency signal. Based on formula (1), the first frequency gain FDR1 at this time is the ratio of the frequency value corresponding to the target output frequency signal to the frequency value corresponding to the carrier frequency signal Fc, that is, FDR1 = fout / fc. After conversion, it can be obtained that: fout = fc*FDR1..............(3). Among them, fc is the frequency value corresponding to the carrier frequency signal Fc.

[0050] It is understandable that, combined with Figure 3 The aforementioned first frequency gain FDR1 and second frequency gain FDR2 both correspond to the second frequency division factor M of the second frequency divider 15 in the all-digital phase-locked loop 10. Therefore, the calibration unit 50 can also be understood as adjusting the second frequency division factor M of the second frequency divider 15 in the all-digital phase-locked loop 10 according to the first control code D1 and the second control code D2, so that the all-digital phase-locked loop 10 can output the crystal frequency signal Fx received by the all-digital phase-locked loop 10 based on the adjusted second frequency division factor M, and then obtain the system clock signal Fref required by the system after frequency division by the first frequency divider 20, and finally the system clock signal Fref can be sent to the corresponding transceiver for modulation and demodulation.

[0051] In this disclosure, the specific principle of frequency calibration is as follows:

[0052] The basic principle of the all-digital phase-locked loop 10 is that the input frequency (corresponding to the frequency of the aforementioned reference frequency signal Fin) multiplied by the gain factor FDR equals the output frequency (corresponding to the frequency of the aforementioned output frequency signal Fout), that is, formula (1), and then when the gain factor remains unchanged, the input frequency is proportional to the output frequency. It can be easily concluded that if you want to ensure that the frequency of the output frequency signal Fout output by the all-digital phase-locked loop 10 is infinitely close before and after calibration, you only need to make the input frequency inversely proportional to the gain factor FDR. Therefore, when performing frequency calibration, you should first obtain the percentage of output frequency change under different input frequencies (in this article, denoted as ΔFout), and then correct the obtained percentage to the gain factor FDR.

[0053] The calculation formula of the output frequency change percentage ΔFout is:

[0054]

[0055] Among them, FDR1 is the first frequency gain (the gain FDR before calibration), D1 is the first control code, D2 is the second control code, K Vis the gain of the digital oscillator 14, which is used to characterize the change in the frequency of the output frequency signal Fout caused by a change in one bit in the control code corresponding to the digital oscillator 14, and fc is the frequency value corresponding to the carrier frequency signal Fc. V , fc and FDR1 are all known quantities, so the percentage of output frequency change ΔFout can be obtained by simply recording the first control code D1 and the second control code D2.

[0056] Furthermore, the calculation formula for obtaining the second frequency gain FDR2 based on the percentage of the output frequency change ΔFout is: FDR2 = FDR1*(1+ΔFout) (5). Combining formulas (4) and (5) yields:

[0057]

[0058] Based on the second frequency gain FDR2 obtained after calibration, the fully digital phase-locked loop 10 can always select the crystal frequency signal Fx as the input reference frequency signal Fin, and can be in a closed-loop working state of tracking the crystal frequency signal Fx during the entire communication period, is not easily affected by external interference, and avoids potential risks when tracking the carrier frequency signal Fc.

[0059] Exemplarily, in combination with formula (4), formula (5) and formula (6), it can be known that when the first control code D1 is greater than the second control code D2, the percentage of the output frequency change ΔFout is a positive number, (1+ΔFout) is greater than 1, so that the second frequency gain FDR2 is greater than the first frequency gain FDR1; when the first control code D1 is less than the second control code D2, the percentage of the output frequency change ΔFout is a negative number, (1+ΔFout) is less than 1, so that the second frequency gain FDR2 is less than the first frequency gain FDR1. Ultimately, the output frequency signal Fout output by the fully digital phase-locked loop 10 can be approximately equal before and after calibration.

[0060] Furthermore, in the embodiment of the present disclosure, the all-digital phase-locked loop system further includes: a first frequency generating unit 30 and a second frequency generating unit 40. The first frequency generating unit 30 is used to provide a carrier frequency signal Fc, and the second frequency generating unit 40 is used to provide a crystal frequency signal Fx.

[0061] Furthermore, in the embodiment of the present disclosure, the all-digital phase-locked loop system further includes: a selection unit 60. The first input end of the selection unit 60 is connected to the first frequency generating unit 30, the second input end of the selection unit 60 is connected to the second frequency generating unit 40, and the output end of the selection unit 60 is connected to the all-digital phase-locked loop 10. The selection unit 60 is used to provide the carrier frequency signal Fc provided by the first frequency generating unit 30 and the crystal frequency signal Fx provided by the second frequency generating unit 40 to the all-digital phase-locked loop 10 in a time-sharing manner according to the corresponding control signal.

[0062] Optionally, the selection unit 60 is a two-choice selection switch.

[0063] Further, refer to Figure 4 , Figure 4 A flow chart of a frequency calibration method for a fully digital phase-locked loop provided according to an embodiment of the present disclosure is shown.

[0064] like Figure 4 As shown, in the embodiment of the present disclosure, the frequency calibration method of the full digital phase-locked loop includes executing step S1, step S2, step S3 and step S4.

[0065] Specifically, in step S1, a first control code is obtained based on a carrier frequency signal.

[0066] In this embodiment, obtaining the first control code based on the carrier frequency signal further includes: inputting the carrier frequency signal into a fully digital phase-locked loop, and obtaining the first control code when the loop of the fully digital phase-locked loop is locked.

[0067] refer to Figure 2 and Figure 3 Exemplarily, the control selection unit 60 connects the output end of the first frequency generating unit 30 and the input end of the full digital phase-locked loop 10, and inputs the carrier frequency signal Fc as the reference frequency signal Fin to the full digital phase-locked loop 10. The full digital phase-locked loop 10 tracks the carrier frequency signal Fc to perform loop locking, and after the loop is locked, records the control code received by the digital oscillator 14 at this time, which is the first control code D1.

[0068] In step S2, a second control code is obtained based on the crystal frequency signal.

[0069] In this embodiment, obtaining the second control code based on the crystal frequency signal further includes: inputting the crystal frequency signal into a fully digital phase-locked loop, and obtaining the second control code when the loop of the fully digital phase-locked loop is locked.

[0070] refer to Figure 2 and Figure 3Exemplarily, the control selection unit 60 connects the output end of the second frequency generating unit 40 and the input end of the full digital phase-locked loop 10, and inputs the crystal frequency signal Fx as the reference frequency signal Fin to the full digital phase-locked loop 10. The full digital phase-locked loop 10 tracks the crystal frequency signal Fx to perform loop locking, and after the loop is locked, records the control code received by the digital oscillator 14 at this time, which is the second control code D2.

[0071] In step S3, the first frequency gain is calibrated based on the first control code and the second control code to obtain the second frequency gain.

[0072] In this embodiment, the first frequency gain is calibrated based on the first control code and the second control code to obtain the second frequency gain, which includes: obtaining the difference between the first control code and the second control code; based on the difference, obtaining the change of the output frequency signal generated by the fully digital phase-locked loop when receiving the crystal frequency signal relative to the target output frequency signal; and calibrating the first frequency gain according to the change to obtain the second frequency gain.

[0073] refer to Figure 2 , exemplarily, after obtaining the first control code D1 and the second control code D2, the first control code D1 and the second control code D2 are sent to the calibration unit 40, and the calibration unit 40 performs calculations according to the above formulas (4), (5) and (6) to obtain a new frequency gain, namely, the second frequency gain FDR2. And in this embodiment, the percentage of the output frequency change is used as the change amount for calculation and analysis.

[0074] Furthermore, the first frequency gain FDR1 is a ratio of a frequency value corresponding to the target output frequency signal to a frequency value corresponding to the carrier frequency signal Fc, that is, FDR1 = fout / fc.

[0075] In step S4, a target output frequency signal is obtained based on the crystal frequency signal and the second frequency amplification factor.

[0076] refer to Figure 2 and Figure 3 After obtaining the second frequency magnification factor FDR2, the second frequency magnification factor FDR2 is written into the full digital phase-locked loop 10 to adjust the second frequency division factor M of the second frequency divider 15 in the full digital phase-locked loop 10. After that, only the crystal frequency signal Fx is input into the full digital phase-locked loop 10 as the reference frequency signal Fin, and the full digital phase-locked loop 10 tracks the crystal frequency signal Fx based on the adjusted second frequency division factor M of the second frequency divider 15 and performs loop locking. After the loop is locked, the output frequency signal Fout output by the digital oscillator 14 in the full digital phase-locked loop 10 is the target output frequency signal.

[0077] Furthermore, after obtaining the target output frequency signal based on the crystal frequency signal and the second frequency magnification factor, the method further includes: dividing the target output frequency signal according to system requirements to obtain a system clock signal. That is, the obtained target output frequency signal is input to the first frequency divider 20, and the first frequency divider 20 divides the target output frequency signal according to a preset first frequency division factor N to obtain the system clock signal Fref.

[0078] Based on the foregoing description, the all-digital phase-locked loop system and the frequency calibration method of the all-digital phase-locked loop in the present disclosure are simple and easy to implement, and can be used in NFC chip applications of mobile phones. At the same time, it can also be applied to applications such as CW radar systems, and applications that can benefit from being able to track variable frequency reference signals, such as tuners, which can be used in more applications such as satellite radio systems, televisions, vehicle intelligent transportation systems (ITS), Ethernet transceivers, Bluetooth and Bluetooth low energy (LE) applications.

[0079] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0080] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.

Claims

1. A fully digital phase-locked loop system, characterized in that: include: A fully digital phase-locked loop, comprising a digital oscillator, for generating a first control code and a second control code corresponding to loop locking according to a carrier frequency signal and a crystal frequency signal respectively during a calibration phase, and generating a target output frequency signal according to the crystal frequency signal and a second frequency magnification factor during a normal operation phase; a calibration unit connected to the all-digital phase-locked loop, and configured to calibrate the first frequency gain according to the first control code and the second control code to generate the second frequency gain, Wherein, the first frequency gain is the ratio of the frequency value corresponding to the target output frequency signal to the frequency value corresponding to the carrier frequency signal; The calculation formula of the second frequency magnification is: ， Wherein, FDR2 is the second frequency magnification factor, FDR1 is the first frequency magnification factor, D1 is the first control code, D2 is the second control code, K V is the gain of the digital oscillator, and fc is the frequency value corresponding to the carrier frequency signal.

2. The all-digital phase-locked loop system according to claim 1, characterized in that: The all-digital phase-locked loop system also includes: The first frequency divider is connected to the full digital phase-locked loop and is used to divide the target output frequency signal according to system requirements to generate a system clock signal.

3. The all-digital phase-locked loop system according to claim 2, characterized in that: The all-digital phase-locked loop system also includes: A first frequency generating unit, used for providing the carrier frequency signal; The second frequency generating unit is used to provide the crystal frequency signal.

4. The all-digital phase-locked loop system according to claim 3, characterized in that: The all-digital phase-locked loop system also includes: A selection unit, having a first input end connected to the first frequency generating unit, a second input end connected to the second frequency generating unit, and an output end connected to the full digital phase-locked loop, is used to provide the carrier frequency signal and the crystal frequency signal to the full digital phase-locked loop in a time-sharing manner.

5. A frequency calibration method for a fully digital phase-locked loop, characterized in that: include: Obtaining a first control code based on the carrier frequency signal; obtaining a second control code based on the crystal frequency signal; Calibrate the first frequency amplification factor based on the first control code and the second control code to obtain a second frequency amplification factor; Obtaining a target output frequency signal based on the crystal frequency signal and the second frequency amplification factor, Wherein, the first frequency gain is the ratio of the frequency value corresponding to the target output frequency signal to the frequency value corresponding to the carrier frequency signal; The calculation formula of the second frequency magnification is: ， Wherein, FDR2 is the second frequency magnification factor, FDR1 is the first frequency magnification factor, D1 is the first control code, D2 is the second control code, K V is the gain of the digital oscillator in the fully digital phase-locked loop, and fc is the frequency value corresponding to the carrier frequency signal.

6. The frequency calibration method of a fully digital phase-locked loop according to claim 5, characterized in that: After obtaining the target output frequency signal based on the crystal frequency signal and the second frequency magnification factor, the method further includes: The target output frequency signal is divided according to system requirements to obtain a system clock signal.

7. The frequency calibration method of a fully digital phase-locked loop according to claim 5, characterized in that: Obtaining a first control code based on the carrier frequency signal includes: The carrier frequency signal is input into a fully digital phase-locked loop, and the first control code is obtained when the loop of the fully digital phase-locked loop is locked.

8. The frequency calibration method of a fully digital phase-locked loop according to claim 5, characterized in that: Obtaining a second control code based on the crystal frequency signal includes: The crystal frequency signal is input into a fully digital phase-locked loop, and the second control code is obtained when the loop of the fully digital phase-locked loop is locked.

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