Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate, the substrate including a first region and a second region adjacent to each other; forming a first dielectric layer on the substrate, the first dielectric layer being located on the first region and the second region respectively, the first dielectric layer having one or more first plug structures, the first dielectric layer exposing the top surface of the first plug structure; forming a first conductive layer on the first dielectric layer, the first conductive layer being located on the second region; forming a second dielectric layer on the first dielectric layer in the first region and on the first conductive layer; forming a second plug structure in the second dielectric layer, the second plug structure being located on the first region, the bottom surface of the second plug structure being in contact with the top surface of the first plug structure. By directly connecting the first plug structure with the second plug structure, the steps of making a word line conductive layer WL and a power conductive layer Vss are omitted, and the production efficiency can be effectively improved while the production cost is reduced under the premise of satisfying the electrical structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the continuous advancement of ultra-large-scale integrated circuit process technology, the characteristic size of semiconductor devices continues to shrink, the performance of semiconductor devices is getting stronger and stronger, the integration of integrated circuit chips has reached the scale of hundreds of millions or even billions of devices, and multi-layer interconnection technology with more than two layers is widely used.

[0003] Traditional interconnect structures are made of aluminum metal, but as the size of semiconductors continues to shrink, smaller and smaller interconnect structures carry higher and higher currents, and the response time requirements of interconnect structures are getting shorter and shorter. Traditional aluminum interconnect structures can no longer meet the requirements; therefore, copper metal has replaced aluminum metal as the material for interconnect structures. Compared with aluminum, copper metal has lower resistivity and better resistance to electromigration. Copper interconnect structures can reduce the resistance and capacitance (RC) delay of interconnect structures, improve electromigration, and improve device reliability. Therefore, copper interconnect technology replacing aluminum interconnect technology has become a development trend.

[0004] However, the production cost of the interconnection structure formed by the prior art is high, and there is an urgent need to provide a new interconnection structure and a method for forming the same, which can reduce the production cost of the interconnection structure while ensuring the electrical performance of the interconnection structure. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve production efficiency and reduce manufacturing costs while satisfying electrical structure requirements by directly connecting a first plug structure with a second plug structure.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region adjacent to each other; forming a first dielectric layer on the substrate, the first dielectric layer being respectively located on the first region and the second region, the first dielectric layer having one or more first plug structures therein, the first dielectric layer exposing the top surface of the first plug structure; forming a first conductive layer on the first dielectric layer, the first conductive layer being located on the second region; forming a second dielectric layer on the first dielectric layer in the first region and on the first conductive layer; forming a second plug structure in the second dielectric layer, the second plug structure being located on the first region, and the bottom surface of the second plug structure being in contact with the top surface of the first plug structure.

[0007] Optionally, the first dielectric layer further includes a gate conductive layer and a plurality of source-drain conductive layers; and the first plug structure is located on the surface of one or both of the source-drain conductive layer and the gate conductive layer.

[0008] Optionally, the first dielectric layer further comprises a first pull-up gate, a first pull-down gate and a first transmission gate located on the surface of the substrate; the substrate on both sides of the first pull-up gate comprises a first source region and a first drain region respectively; the substrate on both sides of the first pull-down gate comprises a second source region and a second drain region respectively; the substrate on both sides of the first transmission gate comprises a third source region and a third drain region respectively; the gate conductive layer is located on the top surface of the first transmission gate, and the source-drain conductive layers are respectively located on the top surfaces of the first drain region, the second drain region and the third source region.

[0009] Optionally, the first conductive layer includes: a bit line conductive layer and a power conductive layer, the bit line conductive layer is electrically connected to the third source region through the first plug structure and the source-drain conductive layer, and the power conductive layer is electrically connected to the first drain region through the first plug structure and the source-drain conductive layer.

[0010] Optionally, the method for forming the first dielectric layer and the first plug structure includes: forming an initial first dielectric layer on the first area and the second area of ​​the substrate; forming a first mask layer on the initial first dielectric layer, the first mask layer having a first opening exposing a portion of the initial first dielectric layer; etching the initial first dielectric layer using the first mask layer as a mask to form the first dielectric layer, the first dielectric layer having a first dielectric opening; and forming the first plug structure in the first dielectric opening.

[0011] Optionally, when forming the second plug structure, the method further includes: forming a third plug structure in the second dielectric layer, the third plug structure is located on the second region, and the bottom surface of the third plug structure contacts the top surface of the first conductive layer.

[0012] Optionally, the method for forming the second dielectric layer, the second plug structure and the third plug structure includes: forming an initial second dielectric layer on the first dielectric layer in the first region and on the first conductive layer; forming a second mask layer on the initial second dielectric layer, the second mask layer having a second opening and a third opening exposing a portion of the initial second dielectric layer; etching the initial first dielectric layer using the second mask layer as a mask until the top surface of the first plug structure and the top surface of the first conductive layer are exposed to form the second dielectric layer, the second dielectric layer having a second dielectric opening and a third dielectric opening; forming the second plug structure in the second dielectric opening, and forming the third plug structure in the third dielectric layer opening.

[0013] Optionally, the process of etching the initial second dielectric layer includes one or more of a dry etching process and a wet etching process.

[0014] Optionally, the width of the second medium opening is 10 nm to 100 nm.

[0015] Optionally, after forming the second dielectric layer, it also includes: forming a second conductive layer on the second dielectric layer, the second conductive layer is located on the first region and the second region, and the top surface of the second plug structure and the top surface of the third plug structure are electrically connected to the bottom surface of the second conductive layer respectively.

[0016] Optionally, the material of the substrate includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0017] Optionally, the material of the source-drain conductive layer and the gate conductive layer includes metal, and the metal includes one or more of copper, cobalt, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, and ruthenium.

[0018] Optionally, the material of the first plug structure includes metal, and the metal includes one or more of copper, cobalt, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride and ruthenium.

[0019] Optionally, the material of the first dielectric layer includes silicon dioxide, a low-k dielectric material or an ultra-low-k dielectric material.

[0020] Optionally, the material of the second dielectric layer includes silicon dioxide, a low-k dielectric material or an ultra-low-k dielectric material.

[0021] Optionally, a material of the second plug structure includes one or more of ruthenium, copper, cobalt, tungsten, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, silver and platinum.

[0022] Optionally, the material of the third plug structure includes one or more of ruthenium, copper, cobalt, tungsten, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, silver and platinum.

[0023] Correspondingly, the present invention also provides a semiconductor structure formed by any of the above methods, comprising: a substrate, the substrate comprising a first region and a second region adjacent to each other; a first dielectric layer, the first dielectric layer being located on the first region and the second region of the substrate, the first dielectric layer having one or more first plug structures therein, the first dielectric layer located in the first region exposing the top surface of the first plug structure; a first conductive layer, the first conductive layer being located on the first dielectric layer on the first region; a second dielectric layer, the second dielectric layer being located on the first dielectric layer in the first region and on the first conductive layer in the second region; a second plug structure, located in the second dielectric layer in the first region, the bottom surface of the second plug structure being in contact with the top surface of the first plug structure.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the technical solution of the present invention, on the first region, the bottom surface of the second plug structure contacts the top surface of the first plug structure. By directly connecting the first plug structure with the second plug structure, the steps of making the word line conductive layer WL and the power conductive layer Vss are omitted. Under the premise of meeting the electrical structure, the production efficiency can be effectively improved while reducing the production cost.

[0026] Further, in the technical solution of the present invention, the width of the second dielectric opening is 10nm to 100nm. Since the steps of manufacturing the word line conductive layer WL and the power conductive layer Vss are omitted, the second plug structure is directly in contact with the first plug structure, which requires the length of the second plug structure to be correspondingly lengthened. Therefore, during the manufacturing process, the depth of the corresponding second dielectric opening should also be correspondingly deepened. However, the second dielectric opening formed by etching is generally in an inverted cone shape. Therefore, in order to ensure that the bottom of the second dielectric opening finally formed can expose the top surface of the first plug structure, the top opening width of the second dielectric opening needs to be increased accordingly. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 to Figure 2 It is a schematic diagram of the structure of a semiconductor structure;

[0028] Figures 3 to 11 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0029] As described in the background art, the production cost of the interconnection structure formed by the prior art is high, and there is an urgent need to provide a new interconnection structure and a method for forming the same, which can reduce the production cost of the interconnection structure while ensuring the electrical performance of the interconnection structure.

[0030] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes an adjacent first region I and a second region II; forming a first dielectric layer 101 on the substrate 100, wherein the first dielectric layer 101 is respectively located on the first region I and the second region II, wherein the first dielectric layer 101 has one or more first plug structures 102, and the first dielectric layer 101 exposes the top surface of the first plug structure 102.

[0031] Please refer to Figure 2 A first conductive layer 103 and a second conductive layer 104 are formed on the first dielectric layer 101, wherein the first conductive layer 103 is located on the first region I and includes a word line conductive layer WL and a power conductive layer Vss (not shown), and the second conductive layer 104 is located on the second region II and includes a bit line conductive layer BL and a power conductive layer Vcc; a second dielectric layer 105 is formed on the first conductive layer 103 and the second conductive layer 104, wherein the second dielectric layer 105 is located on the first region I and the second region II, respectively; a second plug structure 106 and a third plug structure 107 are formed in the second dielectric layer 105, wherein the second plug structure 106 is located on the first region I and the third plug structure 107 is located on the second region II, wherein the bottom surface of the second plug structure 106 contacts the top surface of the first conductive layer 103, and the bottom surface of the third plug structure 107 contacts the top surface of the second conductive layer 104.

[0032] In the above embodiment, the electrical design requirements are achieved by sequentially connecting the first plug structure 102, the first conductive layer 103 and the second plug structure 106. However, the word line conductive layer WL and the power conductive layer Vss in the first conductive layer 103 as a transition layer not only increase the number of steps in the process, but also in the electrical design, it is necessary to ensure that the word line conductive layer WL and the power conductive layer Vss are separated from each other. In this way, a metal segmentation process is required to separate the two, which increases the manufacturing cost while increasing the number of steps in the process.

[0033] On this basis, the present invention provides a semiconductor structure and a method for forming the same. By directly connecting a first plug structure with a second plug structure, the steps of making a word line conductive layer WL and a power conductive layer Vss are omitted. Under the premise of satisfying the electrical structure, the production efficiency can be effectively improved while reducing the production cost.

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figures 3 to 11, is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0036] Please refer to Figure 3 and Figure 4 , Figure 4 for Figure 3 A cross-sectional schematic diagram along the A-A1 direction with the isolation layer omitted is provided, wherein a substrate 200 is provided, and the substrate 200 includes a first region I and a second region II adjacent to each other.

[0037] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0038] In this embodiment, please continue to refer to Figure 3 and Figure 4 , forming a first pull-up fin (not labeled), a first pull-down fin (not labeled) and a first transmission fin (not labeled) on the substrate 200; forming an isolation layer 220 on the substrate 200, wherein the isolation layer 220 covers part of the sidewalls of the first pull-up fin, the first pull-down fin and the first transmission fin, and the top surfaces of the first pull-up fin, the first pull-down fin and the first transmission fin are higher than the top surface of the isolation layer 220; forming a first pull-up gate 201, a first pull-down gate 202 and a first transmission gate 203 on the substrate 200, wherein the first pull-up gate 201 covers .... The first pull-down gate 202 covers part of the sidewalls and top surface of the first pull-down fin, and the first transmission gate 203 covers part of the sidewalls and top surface of the first transmission fin; the substrate 200 on both sides of the first pull-up gate 201 has a first source region 204 and a first drain region 205 respectively; the substrate 200 on both sides of the first pull-down gate 202 has a second source region 206 and a second drain region 207 respectively; the substrate 200 on both sides of the first transmission gate 203 has a third source region 208 and a third drain region 209 respectively.

[0039] In this embodiment, the first pull-up gate 201 , the first pull-down gate 202 , and the first transmission gate 203 are specifically formed on the isolation layer 220 .

[0040] Among them, the first pull-up gate 201, the first pull-up fin, the first source region 204 and the first drain region 205 form a first pull-up transistor PU1, the first pull-down gate 202, the first pull-down fin, the second source region 206 and the second drain region 207 form a first pull-down transistor PD1, and the first transmission gate 203, the first transmission fin, the third source region 208 and the third drain region 209 form a first transmission transistor PG1.

[0041] Please continue to refer to Figure 3 and Figure 4 , a second pull-up transistor PU2, a second pull-down transistor PD2 and a second transfer transistor PG2 are formed in mirror image with the first pull-up transistor PU1, the first pull-down transistor PD1 and the first transfer transistor PG1. The first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, the second pull-down transistor PD2, the first transfer transistor PG1 and the second transfer transistor PG2 together form a minimum storage unit of the static memory.

[0042] Please refer to Figure 5 and Figure 6 , Figure 6 for Figure 5 A cross-sectional schematic diagram in which the isolation layer and the first dielectric layer are omitted along the B-B1 direction, wherein a first dielectric layer 210 is formed on the substrate 200, wherein the first dielectric layer 210 is respectively located on the first region I and the second region II, wherein the first dielectric layer 210 has one or more first plug structures 211, and the first dielectric layer 210 exposes the top surface of the first plug structure 211.

[0043] In this embodiment, the first dielectric layer 210 is specifically formed on the isolation layer 220 .

[0044] The method for forming the first dielectric layer 210 and the first plug structure 211 includes: forming an initial first dielectric layer (not shown) on the first region I and the second region II of the substrate 200; forming a first mask layer (not shown) on the initial first dielectric layer, the first mask layer having a first opening (not shown) exposing a portion of the initial first dielectric layer; etching the initial first dielectric layer using the first mask layer as a mask to form the first dielectric layer 210, the first dielectric layer 210 having a first dielectric opening; and forming the first plug structure 211 in the first dielectric opening.

[0045] In this embodiment, the material of the first dielectric layer 210 is silicon dioxide; in other embodiments, the material of the first dielectric layer can also be low-k dielectric material (referring to dielectric material with a relative dielectric constant lower than 3.9) or ultra-low-k dielectric material (referring to dielectric material with a relative dielectric constant lower than 2.5).

[0046] The material of the first plug structure 211 includes metal, and the metal includes one or more of copper, cobalt, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride and ruthenium. In this embodiment, the material of the first plug structure is tungsten.

[0047] In this embodiment, please continue to refer to Figure 5 and Figure 6Before forming the first plug structure 211, it also includes: forming a gate conductive layer 212 and a plurality of source-drain conductive layers 221 in the first dielectric layer 210, the gate conductive layer 212 is located on the top surface of the first transmission gate 203, and the plurality of source-drain conductive layers 221 are respectively located on the top surfaces of the first drain region 205, the second drain region 207 and the third source region 208.

[0048] The material of the source-drain conductive layer 221 and the gate conductive layer 212 includes metal, and the metal includes one or more of copper, cobalt, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, and ruthenium; in the present embodiment, the material of the gate conductive layer 212 is titanium nitride, and the material of the source-drain conductive layer 221 is titanium nitride.

[0049] The first plug structure 211 is formed on a surface of one or both of the source-drain conductive layer 221 and the gate conductive layer 212 .

[0050] Please refer to Figure 7 and Figure 8 , Figure 8 for Figure 7 A cross-sectional schematic diagram along the C-C1 direction omitting the isolation layer and the first dielectric layer, wherein a first conductive layer 214 is formed on the first dielectric layer 210, and the first conductive layer is located on the second region II.

[0051] The first conductive layer 214 includes a bit line conductive layer BL and a power conductive layer Vcc. The bit line conductive layer BL is electrically connected to the third source region 208 through the first plug structure 211 and the source-drain conductive layer 221 . The power conductive layer Vcc is electrically connected to the first drain region 205 through the first plug structure 211 and the source-drain conductive layer 221 .

[0052] Please refer to Fig. 9 It should be noted that Fig. 9 The viewing direction and Figure 8 In the same viewing direction, a second dielectric layer 215 is formed on the first dielectric layer 210 in the first region I and on the first conductive layer 214.

[0053] The method for forming the second dielectric layer includes: forming an initial second dielectric layer (not shown) on the first dielectric layer 210 of the first region I and on the first conductive layer 214; forming a second mask layer (not shown) on the initial second dielectric layer, wherein the second mask layer has a second opening (not shown) and a third opening (not shown) for exposing a portion of the initial second dielectric layer; etching the initial first dielectric layer using the second mask layer as a mask until the top surface of the first plug structure 211 and the top surface of the first conductive layer 214 are exposed, thereby forming the second dielectric layer 215, wherein the second dielectric layer 215 has a second dielectric opening 218 and a third dielectric opening 219.

[0054] The second dielectric layer 215 is made of silicon dioxide, low-k dielectric material (a dielectric material with a relative dielectric constant lower than 3.9), or ultra-low-k dielectric material (a dielectric material with a relative dielectric constant lower than 2.5).

[0055] When the material of the second dielectric layer is a low-k dielectric material or an ultra-low-k dielectric material, the material of the second dielectric layer is SiOH, SiCOH, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), BPSG (boron-phosphorus-doped silicon dioxide), hydrogenated silsesquioxane (HSQ, (HSiO1.5)n) or methyl silsesquioxane (MSQ, (CH3SiO1.5)n).

[0056] In this embodiment, the material of the second dielectric layer is SiCOH.

[0057] The process of etching the initial second dielectric layer includes one or more of a dry etching process and a wet etching process; in the present embodiment, the initial second dielectric layer is etched using a dry etching process, and the dry etching process includes: the gas includes an etching gas and a carrier gas, the etching gas includes one or more of CF4, CHF3, CH2F2, and CH3F, the carrier gas is an inert gas, the flow rate of the etching gas is 50 sccm to 100 sccm, and the flow rate of the carrier gas is 100 sccm to 1000 sccm.

[0058] Since the steps of making the word line conductive layer WL and the power conductive layer Vss are omitted, in the subsequent process, a second plug structure is formed in the second dielectric layer opening 218, and the second plug structure is directly in contact with the first plug structure 216, which requires the length of the second plug structure to be correspondingly lengthened. Therefore, in the manufacturing process, the depth of the corresponding second dielectric opening 218 should also be correspondingly deepened. However, the second dielectric opening 218 formed by etching is generally in an inverted cone shape. Therefore, in order to ensure that the bottom of the second dielectric opening 218 formed in the end can expose the top surface of the first plug structure 211, the top opening width of the second dielectric opening 218 needs to be correspondingly increased. In this embodiment, the width of the second dielectric opening 218 is 10nm to 100nm.

[0059] Please refer to Fig.10 A second plug structure 216 is formed in the second dielectric layer 215 , and the second plug structure 216 is located on the first region I. The bottom surface of the second plug structure 216 contacts the top surface of the first plug structure 211 .

[0060] In this embodiment, please continue to refer to Fig.10 When forming the second plug structure 216 , it also includes: forming a third plug structure 217 in the second dielectric layer 215 , the third plug structure 217 is located on the second region II, and the bottom surface of the third plug structure 217 is in contact with the top surface of the first conductive layer 214 .

[0061] The method for forming the second plug structure 216 and the third plug structure 217 includes: forming an initial second plug structure (not shown) and an initial third plug structure (not shown) in the second dielectric layer opening and the third dielectric layer opening; and planarizing the initial second plug structure and the initial third plug structure until the top surface of the second dielectric layer 215 is exposed to form the second plug structure 216 and the third plug structure 217.

[0062] In this embodiment, the process of planarizing the initial second plug structure and the initial third plug structure is a chemical mechanical polishing process.

[0063] By directly connecting the first plug structure 211 and the second plug structure 216 , the steps of manufacturing the word line conductive layer WL and the power conductive layer Vss are omitted. Under the premise of satisfying the electrical structure, the production efficiency can be effectively improved and the production cost can be reduced.

[0064] The material of the second plug structure 216 includes one or more of ruthenium, copper, cobalt, tungsten, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, silver and platinum. In this embodiment, the material of the second plug structure 216 is tungsten.

[0065] The material of the third plug structure 217 includes one or more of ruthenium, copper, cobalt, tungsten, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, silver and platinum. In this embodiment, the material of the third plug structure 217 is tungsten.

[0066] Please refer to Fig.11 After forming the second plug structure 216 and the third plug structure 217, a second conductive layer 213 is formed on the second dielectric layer 215, and the second conductive layer 213 is located on the first region I and the second region II. The top surface of the second plug structure 216 and the top surface of the third plug structure 217 are electrically connected to the bottom surface of the second conductive layer 213, respectively.

[0067] The material of the second conductive layer 213 includes one or more of ruthenium, copper, cobalt, tungsten, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, silver and platinum. In this embodiment, the material of the second conductive layer 213 is copper.

[0068] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 8 The semiconductor structure includes: a substrate 200, wherein the substrate 200 includes a first region I and a second region II adjacent to each other; a first dielectric layer 210, wherein the first dielectric layer 210 is located on the first region I and the second region II of the substrate 200, wherein the first dielectric layer 210 has one or more first plug structures 211 therein, wherein the first dielectric layer 210 located in the first region I exposes the top surface of the first plug structure 211; a first conductive layer 214, wherein the first conductive layer 214 is located on the first dielectric layer 210 on the first region I; a second dielectric layer 215, wherein the second dielectric layer 215 is located on the first dielectric layer 210 in the first region I and on the first conductive layer 214 in the second region II; and a second plug structure 216, wherein the second dielectric layer 215 in the first region I has a bottom surface in contact with a top surface of the first plug structure 211.

[0069] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region adjacent to each other; forming a first dielectric layer on the substrate, the first dielectric layer being respectively located on the first region and the second region, the first dielectric layer having one or more first plug structures, and the first dielectric layer exposing top surfaces of the first plug structures; The first dielectric layer also includes a gate conductive layer and a plurality of source-drain conductive layers; the first plug structure is located on the surface of one or both of the source-drain conductive layer and the gate conductive layer; The first dielectric layer also has a first pull-up gate, a first pull-down gate and a first transmission gate located on the surface of the substrate; the substrate on both sides of the first pull-up gate has a first source region and a first drain region respectively; the substrate on both sides of the first pull-down gate has a second source region and a second drain region respectively; the substrate on both sides of the first transmission gate has a third source region and a third drain region respectively; the gate conductive layer is located on the top surface of the first transmission gate, and the source-drain conductive layers are respectively located on the top surfaces of the first drain region, the second drain region and the third source region; forming a first conductive layer on the first dielectric layer, wherein the first conductive layer is located on the second region; A second dielectric layer is formed on the first dielectric layer in the first region and on the first conductive layer; a second plug structure is formed in the second dielectric layer, the second plug structure is located on the first region, and the bottom surface of the second plug structure contacts the top surface of the first plug structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: The first conductive layer includes: a bit line conductive layer and a power conductive layer, the bit line conductive layer is electrically connected to the third source region through the first plug structure and the source-drain conductive layer, and the power conductive layer is electrically connected to the first drain region through the first plug structure and the source-drain conductive layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first dielectric layer and the first plug structure includes: forming an initial first dielectric layer on the first area and the second area of ​​the substrate; forming a first mask layer on the initial first dielectric layer, the first mask layer having a first opening exposing a portion of the initial first dielectric layer; etching the initial first dielectric layer using the first mask layer as a mask to form the first dielectric layer, the first dielectric layer having a first dielectric opening; and forming the first plug structure in the first dielectric opening.

4. The method for forming a semiconductor structure according to claim 3, wherein: When forming the second plug structure, the method further includes: forming a third plug structure in the second dielectric layer, the third plug structure is located on the second region, and the bottom surface of the third plug structure contacts the top surface of the first conductive layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the second dielectric layer, the second plug structure and the third plug structure comprises: forming an initial second dielectric layer on the first dielectric layer in the first region and on the first conductive layer; forming a second mask layer on the initial second dielectric layer, wherein the second mask layer has a second opening and a third opening exposing a portion of the initial second dielectric layer; etching the initial first dielectric layer using the second mask layer as a mask until the top surface of the first plug structure and the top surface of the first conductive layer are exposed to form the second dielectric layer, wherein the second dielectric layer has a second dielectric opening and a third dielectric opening; forming the second plug structure in the second dielectric opening, and forming the third plug structure in the third dielectric layer opening.

6. The method for forming a semiconductor structure according to claim 5, wherein: The process of etching the initial second dielectric layer includes one or more of a dry etching process and a wet etching process.

7. The method for forming a semiconductor structure according to claim 5, wherein: The width of the second medium opening is 10 nm to 100 nm.

8. The method for forming a semiconductor structure according to claim 4, wherein: After forming the second dielectric layer, the method further includes: forming a second conductive layer on the second dielectric layer, wherein the second conductive layer is located on the first region and the second region, and the top surface of the second plug structure and the top surface of the third plug structure are electrically connected to the bottom surface of the second conductive layer respectively.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the substrate includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the source-drain conductive layer and the gate conductive layer includes metal, and the metal includes one or more of copper, cobalt, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, and ruthenium.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first plug structure includes metal, and the metal includes one or more of copper, cobalt, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride and ruthenium.

12. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first dielectric layer includes silicon dioxide, low-k dielectric material or ultra-low-k dielectric material.

13. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second dielectric layer includes silicon dioxide, low-k dielectric material or ultra-low-k dielectric material.

14. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second plug structure includes one or more of ruthenium, copper, cobalt, tungsten, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, silver and platinum.

15. The method for forming a semiconductor structure according to claim 4, wherein: The material of the third plug structure includes one or more of ruthenium, copper, cobalt, tungsten, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, silver and platinum.

16. A semiconductor structure formed by the method according to any one of claims 1 to 15, characterized in that: include: A substrate, the substrate comprising a first region and a second region adjacent to each other; A first dielectric layer, the first dielectric layer is located on the first region and the second region of the substrate, the first dielectric layer has one or more first plug structures, and the first dielectric layer located in the first region exposes the top surface of the first plug structure; The first dielectric layer also includes a gate conductive layer and a plurality of source-drain conductive layers; the first plug structure is located on the surface of one or both of the source-drain conductive layer and the gate conductive layer; The first dielectric layer also has a first pull-up gate, a first pull-down gate and a first transmission gate located on the surface of the substrate; the substrate on both sides of the first pull-up gate has a first source region and a first drain region respectively; the substrate on both sides of the first pull-down gate has a second source region and a second drain region respectively; the substrate on both sides of the first transmission gate has a third source region and a third drain region respectively; the gate conductive layer is located on the top surface of the first transmission gate, and the source-drain conductive layers are respectively located on the top surfaces of the first drain region, the second drain region and the third source region; a first conductive layer, the first conductive layer being located on the first dielectric layer on the first region; a second dielectric layer, the second dielectric layer being located on the first dielectric layer in the first region and on the first conductive layer in the second region; The second plug structure is located in the second dielectric layer of the first region, and the bottom surface of the second plug structure contacts the top surface of the first plug structure.

Images