High voltage semiconductor device and method for manufacturing the same

Abstract

A multi-unit MOSFET device is provided, which includes a MOSFET unit with an integrated Schottky diode. The MOSFET includes an n-type source region formed in a p-type well region, and the p-type well region is formed in an n-type drift layer. A p-type body contact region is formed at the periphery of the MOSFET. The source metallization of the device forms a Schottky contact in contact with an n-type semiconductor region, and the n-type semiconductor region is adjacent to the p-type body contact region of the device. A through hole can be formed through a dielectric material covering the source ohmic contact and / or Schottky region of the device, and a source metallization can be formed in the through hole. The n-type semiconductor region forming the Schottky contact and / or the n-type source region can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. A method for manufacturing the device is also provided.

Description

[0001] Divisional application

[0002] This application is a divisional application of application number 2016800168315, application date February 11, 2016, and titled “High Voltage Semiconductor Device and Method for Manufacturing the Same”.

[0003] Statement Regarding Federally Funded Research

[0004] This invention was made with Government support under Grant No. DEAR0000442 awarded by the Department of Energy. The Government has certain rights in this invention. Technical Field

[0005] The present application generally relates to a high voltage semiconductor device and a method for manufacturing the device, and more particularly to a high voltage semiconductor device including an integrated diode and a method for manufacturing the device. Background Art

[0006] Metal oxide semiconductor field effect transistors (MOSFETs) are commonly used in power electronic circuits, such as DC-DC converters. DC-DC converters use switches based on power MOSFETs to convert voltage from one level to another. In a typical DC-DC converter, the control circuit drives the gates of two power MOSFETs to regulate the power transfer from the power supply to the load. One of the power MOSFETs can work as a synchronous rectifier.

[0007] The properties of silicon carbide are well suited for use in high voltage power electronics applications, such as power MOSFETs for DC-DC converters. One of the main advantages of silicon carbide compared to silicon is its higher critical breakdown field strength. Silicon carbide has a breakdown field strength of approximately 3 MV / cm, compared to silicon's breakdown field strength of approximately 0.3 MV / cm. Silicon carbide's 10 times higher breakdown field strength enables semiconductor switches and rectifiers with higher reverse blocking voltages and lower on-state resistance, enabling higher power electronics system performance than silicon.

[0008] In a DC-DC converter, the power MOSFET needs to be turned off for a short period of time, where one MOSFET is on and the other is off, to prevent shoot-through current between the power supply and ground. During this dead time, the pn junction diode integrated into the power MOSFET structure can conduct current. Conducting current through a pn junction diode integrated into a SiC MOSFET is not preferred because the power conduction losses are higher compared to a Schottky diode. The higher power conduction losses of the SiC pn junction diode are due to the higher turn-on voltage and therefore the larger forward voltage drop of the diode. The pn junction diode also has higher switching power losses because it is a bipolar device and stores minority carriers that need to be removed to turn off the diode.

[0009] Therefore, in the DC-DC converter circuit, a Schottky diode can be connected in anti-parallel with the SiC power MOSFET as a freewheeling diode (D1). The Schottky diode has a lower turn-on voltage (about 0.9V) and therefore has lower conduction losses than an integrated pn junction diode with a forward voltage drop of about 3.5V. In addition, the Schottky diode is a majority carrier device, so the switching power losses are also lower compared to the pn junction diode because there are no minority carriers stored in the device.

[0010] While freewheeling Schottky diodes can be added to the converter circuit to improve conversion efficiency, the use of external Schottky diodes increases the cost of the converter unit due to the need for additional components. External Schottky diodes also take up space on the circuit board, hindering the realization of a smaller converter footprint. The reliability of the Schottky diode and its electrical connection on the circuit board may also reduce the overall reliability of the converter. In addition, the wire bonds in the Schottky diode create additional self-inductance, which plays a role in limiting the high-frequency operation of the converter.

[0011] Therefore, there remains a need for MOSFET devices, particularly SiC MOSFET devices, in which a Schottky diode is integrated within the power MOSFET structure. Summary of the invention

[0012] A multi-cell MOSFET device is provided, comprising:

[0013] an n-type drift layer on an n-type substrate;

[0014] A plurality of MOSFET cells, each MOSFET cell comprising:

[0015] first and second p-type well regions having a spaced relationship on the n-type drift layer;

[0016] an n-type JFET region located on the n-type drift layer between first and second p-type well regions, wherein each of the first and second p-type well regions has a channel region adjacent to the JFET region;

[0017] first and second n-type source regions on each of the first and second p-type well regions adjacent to the channel region opposite the JFET region, wherein the first and second n-type source regions have a higher dopant concentration than the n-type drift layer;

[0018] a source ohmic contact on each of the first and second n-type source regions;

[0019] A gate dielectric layer over the JFET region and the channel region;

[0020] a gate layer on the gate dielectric layer;

[0021] an interlayer dielectric layer on the gate layer; and

[0022] first and second p-type body contact regions on the n-type drift layer adjacent to the first and second n-type source regions opposite the channel region, wherein the first and second p-type body contact regions have a higher dopant concentration than the first and second p-type well regions;

[0023] an n-type Schottky region on the n-type drift layer adjacent to one or more MOSFET cells;

[0024] a source metal layer on and in contact with the source ohmic contact; and

[0025] A Schottky metal layer is on and in contact with the n-type Schottky region, the Schottky metal layer forming a Schottky contact in contact with the n-type Schottky region.

[0026] Also provided is a method of manufacturing a multi-cell MOSFET device, comprising:

[0027] forming first and second p-type well regions on an n-type drift layer, wherein the n-type drift layer is on an n-type substrate, and wherein the first and second p-type well regions are spaced apart to form an n-type Schottky region therebetween, and wherein an n-type region of the drift layer adjacent to each of the first and second well regions and opposite the n-type Schottky region forms first and second JFET regions;

[0028] forming an n-type source region in each of the first and second p-type well regions, wherein the n-type source region is spaced apart from the first and second JFET regions, leaving a p-type channel region between the n-type source region and the JFET regions;

[0029] forming first and second p-type body contact regions between the Schottky region and each of the first and second p-type well regions, respectively;

[0030] depositing a gate oxide layer over the first and second JFET regions and the adjacent channel region;

[0031] depositing a gate layer on the gate oxide layer;

[0032] depositing an interlayer dielectric material on the gate layer;

[0033] forming a source ohmic contact on the source region;

[0034] depositing a source metal layer over the source ohmic contact and the n-type Schottky region, wherein the source metal layer forms a Schottky contact to the n-type Schottky region; and

[0035] A final metal is deposited over the source metal layer.

[0036] Also provided is a method of manufacturing a multi-cell MOSFET device, comprising:

[0037] etching in the n-type drift layer to form first and second openings having a bottom and sidewalls, wherein the n-type drift layer is on the n-type substrate, and wherein the first and second openings are spaced apart and form an n-type Schottky region therebetween;

[0038] forming first and second p-type well regions adjacent to the first and second openings, respectively, in adjacent n-type drift layers, wherein the first and second p-type well regions are formed opposite to the n-type Schottky region, and wherein n-type regions of the drift layer adjacent to the first and second well regions form first and second JFET regions;

[0039] forming an n-type source region in each of the first and second p-type well regions, wherein the n-type source region is spaced apart from the first and second JFET regions, leaving a p-type channel region between the n-type source region and the JFET regions;

[0040] forming first and second p-type body contact regions adjacent to bottoms and sidewalls of the first and second openings;

[0041] depositing a dielectric material in the first and second openings;

[0042] depositing a gate oxide layer over the first and second JFET regions and the adjacent channel region;

[0043] depositing a gate layer on the gate oxide layer;

[0044] depositing an interlayer dielectric material on the gate layer;

[0045] forming a source ohmic contact on the source region;

[0046] depositing a source metal layer over the source ohmic contact and the n-type Schottky region, wherein the source metal layer makes a Schottky contact in contact with the n-type Schottky region; and

[0047] A final metal is deposited over the source metal layer.

[0048] A multi-unit MOSFET device is also provided, comprising:

[0049] A first MOSFET cell and an adjacent second MOSFET cell; and

[0050] A peripheral region includes a plurality of alternating p-type body contact regions and n-type Schottky regions between the first and second MOSFET cells. According to some embodiments, the peripheral region also includes: a first p-type body contact region extending along a periphery of the first MOSFET cell, the periphery of the first MOSFET cell being adjacent to the peripheral region; and a second p-type body contact region extending along a periphery of the second MOSFET cell, the periphery of the second MOSFET cell being adjacent to the peripheral region and opposite to the first p-type body contact region, and the alternating p-type body contact regions extending between the first and second p-type body contact regions. According to some embodiments, the first MOSFET cell includes a plurality of alternating p-type body contact regions and an n-type source region extending along a periphery of the first MOSFET cell, the periphery of the first MOSFET cell being adjacent to the peripheral region; and the second MOSFET cell includes a plurality of alternating p-type body contact regions and an n-type source region extending along a periphery of the second MOSFET cell, the periphery of the second MOSFET cell being adjacent to the peripheral region.

[0051] These and other features of the present teachings are set forth herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The skilled person will appreciate that the drawings described below are for illustration purposes only and are not intended to limit the scope of the present teachings in any way.

[0053] Figure 1A is a schematic cross-sectional view of a multi-cell MOSFET semiconductor device including an integrated Schottky diode;

[0054] Figure 1B is a schematic cross-sectional view of a multi-cell MOSFET semiconductor device including an integrated Schottky diode, wherein a Schottky region of the device has a different doping concentration than a drift layer;

[0055] Figure 1C is a schematic cross-sectional view of a multi-cell MOSFET semiconductor device including an integrated Schottky diode, wherein Schottky and JFET regions of the device have different doping concentrations than a drift layer;

[0056] Figure 1D is a schematic cross-sectional view of a MOSFET semiconductor device including an integrated Schottky diode and a current spreading layer on a drift layer;

[0057] Figure 2 is a schematic layout (i.e., top) view of a multi-unit MOSFET semiconductor device, which includes Figures 1A-1C The integrated Schottky diode shown;

[0058] Figure 3is a schematic cross-sectional view of a multi-cell MOSFET semiconductor device including an integrated Schottky diode and having a via formed through a dielectric material over a source ohmic contact and a Schottky region of the device, wherein a source metal contacts the source ohmic contact and the Schottky region at a bottom of the via;

[0059] Figure 4 Yes Figure 3 A schematic layout (i.e., top) view of a multi-cell MOSFET semiconductor device is shown, which includes a plurality of source vias arranged in a row on each source ohmic contact and a single elongated Schottky via on the Schottky region;

[0060] Figure 5 Yes Figure 3 A schematic layout (i.e., top) view of a multi-cell MOSFET semiconductor device is shown, which includes a plurality of source vias arranged in a row on each source ohmic contact and a plurality of Schottky vias arranged in a plurality of rows on the Schottky region;

[0061] Figure 6 Yes Figure 3 A schematic layout (i.e., top) view of a multi-cell MOSFET semiconductor device is shown, which includes a plurality of discontinuous Schottky contact regions arranged in a row and surrounded by a continuous p-type body contact region;

[0062] Fig. 7A is a schematic layout (i.e., top) view of a multi-cell MOSFET semiconductor device, wherein the Schottky region and the source region each include a plurality of discontinuous regions alternating with discontinuous p-type body contact regions, wherein the Schottky region is adjacent to the p-type body contact region in the x-direction;

[0063] Figure 7B is a schematic layout (i.e., top) view of a multi-cell MOSFET semiconductor device, wherein the Schottky region and the source region each include a plurality of discontinuous regions alternating with discontinuous p-type body contact regions, wherein the Schottky region is adjacent to the source region in the x-direction;

[0064] Figure 8 is a schematic cross-sectional view of a MOSFET device with an integrated Schottky diode, wherein a p-type body contact region (P+) is formed adjacent to the bottom and sidewalls of an oxide-filled trench;

[0065] Fig. 9 yes Figure 8 A schematic diagram of the layout (top view) of the device;

[0066] Fig.10is a schematic cross-sectional view of a MOSFET device with an integrated Schottky diode, wherein a p-type body contact region (P+) is formed adjacent to a bottom and sidewalls of an oxide-filled trench, and wherein a via is formed through a source ohmic contact and dielectric material over the Schottky region;

[0067] Fig.11 is a schematic layout diagram of a multi-unit MOSFET including a plurality of MOSFETs with integrated Schottky diodes;

[0068] Fig.12 is a schematic diagram of a layout of a multi-cell MOSFET including alternation of MOSFETs with integrated Schottky diodes and MOSFETs without integrated Schottky diodes;

[0069] Figures 13A-13I Shows the manufacturing Figure 3 The method of a multi-cell MOSFET device with an integrated Schottky diode is shown;

[0070] Figures 14A-14K Shows the manufacturing Figure 8 The method of a multi-cell MOSFET device with an integrated Schottky diode is shown;

[0071] Fig.15 A graph showing the operation of a DMOS with an integrated Schottky diode (◇) as described herein compared to a conventional DMOS device without an integrated Schottky diode (△), both operating in the third quadrant, where the gate-source voltage (V gs ) is 0V;

[0072] Fig.16 is a schematic diagram of a DC-DC converter circuit including a power MOSFET with an integrated Schottky diode. DETAILED DESCRIPTION

[0073] As used herein, a "peripheral area" of a cell is an area at or near the periphery of the cell. According to some embodiments, the peripheral area of ​​a cell may be adjacent to the periphery of the cell.

[0074] As used herein, a layer "on" a lower layer may be in direct contact with the lower layer or in indirect contact with the lower layer with one or more intervening layers therebetween.

[0075] Metal oxide semiconductor field effect transistor (MOSFET) devices can be used in power electronic circuits, such as DC-DC converters. A commonly used power semiconductor switch is the double diffused MOSFET or DMOSFET. Diffusion refers to the manufacturing process. In particular, the P-well and N-source regions are obtained by a double diffusion process (i.e., a p-type well diffusion followed by diffusion on an n-type source region).

[0076] Since the diffusion of dopants in SiC is negligible, dopants are introduced into SiC by an ion implantation process. Therefore, SiC DMOSFET is called a double ion implanted MOSFET. Conventional SiC DMOSFET devices include two P-type well regions implanted in an n-type drift layer on an N-type substrate. The n-type material between the p-type well regions forms the JFET region of the device. The N+ source region is implanted into the p-type well region and deviates from the inner edge of the p-type well region. The deviation forms the channel region of the device. A refractory gate electrode is formed on the JFET and channel regions.

[0077] In a multi-cell DMOSFET device, multiple spaced p-type well regions and N+ source regions are implanted in the drift layer. The P+ body contact region is implanted through the N+ source region and the underlying p-type well region to form separate source / well regions for adjacent cells. In a multi-cell device, the width of the unit cell (i.e., cell pitch) is defined as the center-to-center distance between adjacent JFET regions. A smaller cell pitch is generally required to ensure a large packing density of DMOS cells in a given area. The cells can be striped, "ladder" or "3DMOS" designs.

[0078] During the on-state of the DMOSFET, applying a gate bias greater than the threshold voltage causes current to flow from the drain terminal of the device to the source terminal of the device. During the off-state of the DMOSFET, the drain terminal is biased at a high voltage (for example, the drain-to-source voltage can be 1200 volts), and the gate and source terminals are biased at a ground potential corresponding to 0 volts. The barrier region of the PN junction diode formed by the P-well to the N-drift region supports a large reverse voltage. The DMOSFET has a built-in PN junction diode formed between the P-well to the N-drift region. Under certain operating conditions, the PN junction diode is forward biased and conducts current. As described above, current conduction through a SiC MOSFET integrated with a pn junction diode is not preferred because the conduction and switching power losses are higher compared to Schottky diodes. Therefore, different device structures and layouts that allow Schottky diodes to be integrated within the MOSFET structure are provided.

[0079] According to some embodiments, a MOSFET with an integrated Schottky diode is provided, wherein the source metallization of the device also forms a Schottky contact. Figure 1A 1A is a schematic cross-sectional view of a unit cell of this type of multi-cell device. As can be seen from 1A, the MOSFET device includes a Schottky diode between adjacent MOSFET cells. Figure 1AAs shown, the Schottky diode is formed between the Schottky metal and the N-type drift region and is surrounded by the body contact (P+) region on both sides. The Schottky metal is deposited on the N-type drift region to form a Schottky contact. The source metal is deposited on the ohmic contact to form a source contact. The final source metal is then deposited on the source metal and the Schottky metal and in contact with them. The Schottky metal and the source metal can be the same or different materials. When the MOSFET is in reverse blocking mode and a high voltage (e.g., 1200V) is applied to the drain terminal, the body contact (P+) region around the Schottky diode can shield the Schottky region from a high electric field. The body contact (P+) region can also play a role in reducing the current leakage of the Schottky diode in the reverse blocking state of the MOSFET. The cell pitch of the device is defined as the distance between the middle of the JFET region of the MOSFET cell and the middle of the JFET region of the adjacent MOSFET cell.

[0080] The doping concentration of the Schottky region may be different from the doping concentration of the N-type drift region. Figure 1B is a schematic diagram of a device having a different net doping concentration in the Schottky region than in the drift region. According to some embodiments, the doping concentration in the Schottky region may be 5×10 15 -5.0×10 16 cm -3 According to some embodiments, the Schottky region may be counter-doped such that the doping concentration in the Schottky region is lower than the doping concentration of the N-drift. Counter-doping may be used to reduce the electric field during the reverse blocking state. According to some embodiments, the doping concentration in the Schottky region may be higher than the doping concentration of the N-drift region. This may reduce the diode forward voltage drop.

[0081] The JFET region of the MOSFET device may also have a different doping concentration than the drift layer. According to some embodiments, the JFET region and the Schottky region may each have a different doping concentration, which may also be different from the doping concentration of the drift layer. For example, the JFET region doping concentration and the Schottky region doping concentration may be independently defined by ion implantation. According to some embodiments, an n-type epitaxial layer (i.e., an epitaxial layer) may be grown on the N-drift region to form a JFET and a Schottky region having a doping concentration different from that of the drift layer. Figure 1C is a schematic diagram of a device having an N-drift region grown on an n-type epitaxial layer. According to some embodiments, the thickness of the epitaxial layer is 0.2-3.0 μm. According to some embodiments, the doping concentration of the epitaxial layer can be 5×10 15 -1.0×10 17 cm -3The doping concentration of the epitaxial layer region may be higher or lower than the doping concentration of the drift region to help adjust the performance of the Schottky region and / or the JFET region of the MOSFET.

[0082] Figure 1D is a schematic cross-sectional view of a MOSFET semiconductor device according to some embodiments, which includes an integrated Schottky diode and a current diffusion layer on a drift layer. The current diffusion layer can diffuse current from the JFET region to the drain, thereby reducing the JFET resistance. The doping concentration of the current diffusion layer can be 5×10 15 -5.0×10 17 cm -3 .

[0083] The device may have a single continuous n-type Schottky region between adjacent body contact (P+) regions as shown in Figure 1. Also as shown in Figure 1, the upper surface of the JFET region may be aligned with the upper surface of the source and / or Schottky region, with the gate oxide on the upper surface of the JFET region.

[0084] exist Figure 1B , 1C In FIG. 1A and FIG. 1D , a single source metal layer is shown on the Schottky region and on the source ohmic contact region. For these embodiments, the metal on the Schottky region may also be different from Figure 1A The metal on the source region is shown in .

[0085] Figure 2 yes Figures 1A-1C The layout (i.e., top) view of the device is shown. Figure 2 As shown in Figure 1, the area between the dashed lines represents the source ohmic contact. The cell pitch (i.e., the distance between the centers of the JFET regions of adjacent MOSFET devices) is also Figure 2 Shown in.

[0086] The source metallization may be composed of one or more conductive layers including, but not limited to, titanium, titanium nitride, aluminum, tungsten, and combinations thereof.

[0087] According to some embodiments, the same source metallization layer or layers may be used to contact the source ohmic contact, to form a Schottky contact and to serve as the final source metallization for the wire bonding and assembly processes.

[0088] Figure 3 is a schematic cross-sectional view of a MOSFET device including an integrated Schottky diode, wherein one or more vias are used to make an electrical connection between the source ohmic contact and the source final metallization in the MOSFET. Figure 3As shown, one or more vias can also be used to make an electrical connection between the source metal (i.e., source pad) and the source final metallization. In particular, a dielectric material can be formed on the JFET region and the source ohmic contact. The dielectric material can be the same material as the interlayer dielectric layer (ILD) used to form the MOSFET. A via can then be formed on the source ohmic contact and the JFET region through the dielectric material. The source metal aligns the via and contacts the source ohmic contact and the Schottky region at the bottom of the via.

[0089] like Figure 3 As shown, at the bottom of the source via, the via liner material (ie, source metal layer) contacts the source ohmic contact. Figure 3 As shown, at the bottom of the via on the Schottky region, the via liner material (i.e., source metal) contacts the Schottky region to form a Schottky diode. According to some embodiments, the via liner material includes titanium (Ti) and titanium nitride (TiN). According to some embodiments, the via is filled in whole or in part with a via filling material. According to some embodiments, the via filling material is tungsten (W). The deposition of the via liner material and the filling of the via with tungsten can be completed using a standard tungsten (W) plug process.

[0090] According to some embodiments, the width of the full JFET region is 1.5-6 μm, the width of the P+ region surrounding the Schottky region is 0.6-3 μm and / or the width of the Schottky region is 1-4 μm.

[0091] Figure 4 Yes Figure 3 A schematic diagram of a layout (i.e., top) view of a device shown, including a single continuous via in the Schottky region, and multiple separate discontinuous vias arranged in a column on the source ohmic contact. Although rectangular source vias are shown on the source ohmic contact region, the source vias can be of any shape, including but not limited to square and rectangular. When square or rectangular source vias are used, typical dimensions of the vias are 0.5μm×0.5μm to 1μm×1μm. The via spacing on the source ohmic contact region may vary depending on the process technology. According to some embodiments, the via spacing may be 0.5-1μm.

[0092] Although in Figure 4 A single column of source vias is shown on the source ohmic contact region of FIG. 1 , but multiple columns of source vias may also be used. Figure 4 As shown, the via over the Schottky region may be a single elongated via extending along the length of the MOSFET cell.

[0093] Figure 5 It shows that Figure 3The layout diagram of the MOSFET device shown in FIG. 1 includes a plurality of source vias arranged in multiple columns in the Schottky region and a plurality of source vias arranged in a single column on each source ohmic contact. The via shapes, via sizes, and via spacing in the source ohmic contact region and the Schottky region may be different from those in FIG. Figure 4 The devices shown are the same as those described. Figure 5 Two columns of vias in the Schottky region and one column of vias in the source ohmic contact region are shown. The source ohmic contact region, the Schottky region, or both can have one or more columns of vias. Using vias of the same shape, size, and spacing on the ohmic contact region and the Schottky region allows for a more robust via process.

[0094] According to some embodiments, the ohmic contact material may be nickel, titanium, and aluminum.

[0095] According to some embodiments, the source via is square or rectangular in shape.

[0096] According to some embodiments, a MOSFET device includes a plurality of vias arranged in one or more columns on a source ohmic contact and a single elongated via on a Schottky region. According to some embodiments, a MOSFET device includes a plurality of vias arranged in one or more columns on a source ohmic contact and a single elongated via on a Schottky region.

[0097] Figure 6 FIG. 1 shows a layout diagram of a MOSFET device with an integrated Schottky diode, where the Schottky region is discontinuous along the length of the MOSFET cell. Figure 6 As shown, the device includes separate Schottky regions periodically arranged along the length of the DMOS cell. The separate Schottky regions can be of any shape, including square or rectangular (shown). Figure 6 As shown, the p-type body contact material (ie, Figure 6 The P+ in the Schottky region is completely surrounded by the Schottky region.

[0098] The use of separate discontinuous Schottky regions allows the percentage of Schottky area in the MOSFET cell to be independently controlled. For example, to increase the amount of Schottky diodes in the unit cell, the width of the Schottky region in the Y direction (Wsy) can be fixed, while the width of the Schottky region in the X direction (Wsx) can be increased. The width of the Schottky region in the Y direction (Wsy) can be fixed to an appropriate value for the P+ region to effectively shield the Schottky region from high voltages.

[0099] and Figure 4 and Figure 5 The device shown requires two photolithographic openings compared to using Figure 6The layout can achieve a smaller cell pitch because a single lithographic opening is required for implanting the p-type body contact region. In addition, depending on the size of the Schottky region, shielding of the Schottky region from high voltages during reverse blocking can be improved because there is a p-type body contact region surrounding the Schottky region.

[0100] Before depositing the final source metal, a Schottky metal is deposited on the Schottky region to form a Schottky contact. A via process similar to the process described above can also be used to form a Schottky contact and or electrical contact between the source metal and the source ohmic contact.

[0101] The source metallization of the device can also be used as a Schottky contact to the Schottky region of the device. The source metallization can include titanium, titanium nitride, aluminum, or tungsten. The same one or more metallization layers can be used to make electrical contact with the source ohmic contact and form a Schottky contact, and can also be used as the final source metallization for wire bonding and assembly processes.

[0102] Fig. 7A and 7B is a schematic diagram of the layout of the first and second MOSFET devices with integrated Schottky diodes, where the Schottky region and the source region are discontinuous along the length of the DMOS cell. Fig. 7A As shown, multiple separate Schottky regions are periodically arranged along the length of the DMOS cell. Although shown as rectangular regions, the Schottky regions can be any shape, including square or rectangular. Fig. 7A It can be seen that the source (N+) region is also discontinuous along the length of the unit cell (i.e., the y direction). Fig. 7A In the device shown, the source (N+) and body contact (P+) regions are arranged alternately along the length of the unit cell. Each separate Schottky region is arranged between the body contact (P+) regions of adjacent MOSFET cells. The body contact (P+) region also surrounds the Schottky region in the y direction. Figure 7B In the device shown, the Schottky regions separating the devices are between the source regions (N+) in the x-direction, rather than between the p-type body contact regions of adjacent MOSFETs. The p-type body contact regions (P+) are arranged as a single row of separated regions spaced apart in the y-direction and extend between the p-type channel regions of adjacent MOSFET devices. Fig. 7A and 7B The layout shown allows the Schottky areas within a cell to be adjusted independently. Figure 6 These layouts also allow for smaller cell pitches than the devices shown.

[0103] Figure 8is a schematic cross-sectional view of a MOSFET device with an integrated Schottky diode, wherein a p-type body contact region (P+) is formed adjacent to the bottom and sidewalls of a trench filled with a dielectric material (e.g., oxide). After the trench is formed, the p-type body contact region can be formed by ion implantation, resulting in a deeper p-type implant region. When a high voltage is applied to the drain of the SiC MOSFET, the deeper p-type implant region can provide better shielding of the Schottky region from the high voltage. The structure also enables a higher doping concentration in the Schottky region to further reduce the forward voltage drop of the diode. The lower forward voltage results in lower power losses in the diode.

[0104] Fig. 9 Schematically shows Figure 8 Layout diagram of the device in. Fig. 9 As can be seen, the trench and Schottky region extend along the length of the DMOS unit cell (i.e., the y-direction). As described above, the Schottky metal can be deposited on the Schottky region before depositing the source metal. The p-type body contact region (P+) is also shown adjacent to the trench in the width or x-direction. Fig. 9 The cell spacing is also shown in .

[0105] Fig.10 is a schematic cross-sectional view of a MOSFET device having an integrated Schottky diode, wherein a p-type body contact region (P+) is formed adjacent to the bottom and sidewalls of a trench, the trench is filled with an oxide, and wherein a via is formed over the source ohmic contact region and the Schottky region. Fig.10 As shown, the via liner material acts as a Schottky metal as described above.

[0106] Fig.11 and 12 Layout diagrams showing different arrangements of multi-cell MOSFET devices, including MOSFETs with integrated Schottky diodes. Fig.11 In , the multi-cell MOSFET layout consists of unit cells of MOSFETs, each of which has an integrated Schottky diode. Fig.12 In the embodiment, the multi-cell MOSFET layout includes MOSFETs with integrated Schottky diodes and MOSFETs without integrated Schottky diodes. Fig.12 Alternating cells of MOSFETs with and without integrated Schottky diodes are shown, other arrangements of these unit cells may also be used. For example, every second, third, etc. unit cell may be a unit cell with or without an integrated Schottky diode.

[0107] Figures 13A-13I The preparation is shown as Figure 3A method for providing a multi-cell MOSFET device with an integrated Schottky diode is shown. Fig.13A As shown, the starting material includes an N-type drift region on an N-type substrate. The N-drift thickness can vary from a few microns (e.g., 2 μm) to over 100 μm. The thickness of the substrate can also vary. The thickness of the substrate can be 350 μm. An n-type buffer layer is also shown between the n-type drift layer and the substrate. The buffer layer is optional, and the drift layer can be formed directly on the substrate.

[0108] like Fig. 13B As shown, an implant mask (e.g., silicon dioxide) is deposited, patterned, and etched to define openings for the P-well implant. The P-type well is then implanted in the drift layer. Fig. 13C As shown, after the P-well implant, a layer of mask material (e.g., silicon dioxide) is deposited and etched back to define spacers at the edges of the P-well implant mask material. Fig.13D As shown, an N+ implant is then performed to define an N+ source region. The spacer offsets the source region from the edge of the p-type well region, thereby defining a p-type channel between the source region and the adjacent JFET region.

[0109] like Fig.13E As shown, an implant mask (e.g., silicon dioxide) is then deposited, patterned, and etched to define openings for the P+ implant. The P+ region serves as the body contact for the MOSFET. Fig.13F The body contact region is formed as shown. Figure 13G As shown, after removing the implant mask, the implant can then be activated by annealing at high temperature (eg, 1650° C.).

[0110] A gate oxide may then be formed, followed by polysilicon gate deposition, patterning and etching, and interlayer dielectric (e.g., silicon dioxide) deposition, patterning and etching. A source ohmic contact is then formed, etched and annealed. A dielectric material (e.g., silicon dioxide) is then deposited over the source ohmic contact, p+ region, and Schottky region, and patterned and etched to form the source and Schottky vias. A source metal / via liner material is then deposited. An electrical contact is formed to the ohmic contact through the via liner material. The via liner material also contacts the Schottky region to form a Schottky contact. The material may be titanium (Ti) and titanium nitride (TiN) layers. The via is then filled with a filling material (e.g., tungsten). The device after these process steps may look like Fig.13H The final source metal (e.g., aluminum) can then be deposited. The device after these process steps is shown in FIG. Fig.13I shown.

[0111] Can be used Figures 13A-13I The device is manufactured using a slightly modified process in the source and Schottky regions of the device. Figures 1A-1C The buffer layer and substrate layer are Figures 13B-13I Not shown.

[0112] Figures 14A-14K A method of manufacturing a multi-cell MOSFET device is shown, which has Figure 8 The integrated Schottky diode shown in FIG. Fig.14A As shown, the starting material can be an N-type drift region on an N-substrate. The thickness of the n-type drift layer can vary, and exemplary thicknesses range from 2 microns to over 100 microns. The thickness of the substrate can also vary. An exemplary substrate thickness is 350 microns. An optional n-type buffer layer can be used between the substrate and the drift layer.

[0113] like Fig. 14B As shown, the trench is anisotropically etched in the n-type drift layer. The trench can be defined using the same etching process as that used to define the alignment marks required for the photolithography process. Fig. 14C As shown, an implant mask (e.g., silicon dioxide) is deposited, patterned, and etched to define openings for the P-well implant. The P-well region is then implanted into the drift layer. Fig.14D As shown, after the P-well implant, a layer of mask material (eg, silicon dioxide) is deposited and anisotropically etched back to define spacers on the edges of the P-well implant mask oxide.

[0114] like Fig.14E As shown, an N+ implant is then performed through the opening in the mask to define an N+ source region. The spacer allows the implanted source region to be spaced apart from the edge of the p-well region, thereby defining a via in the well region between the source region and the adjacent JFET region.

[0115] like Fig.14F As shown, an implant mask material (e.g., silicon dioxide) is deposited, patterned, and etched to define an opening for the P+ implant. The P+ region serves as the body contact region of the DMOSFET. The device after the P+ implant is shown in FIG. Figure 14G As shown. Figure 14G As can be seen in FIG. 1 , the P+ implant is deeper below the trench.

[0116] Fig.14H The device is shown after removal of the implant mask.At this stage of the process, the implants may be activated by annealing at high temperature (eg 1650°C). Fig.14I Figure 2 shows the device after implant annealing and activation. Fig.14I As shown, the trenches have been filled with silicon dioxide and planarized. Oxidation and planarization can be accomplished using well-established deposition (eg, chemical vapor deposition) and polishing processes (eg, chemical mechanical polishing or dry etch planarization).

[0117] After the trenches are filled and planarized, a gate oxide can be formed, followed by polysilicon gate deposition, patterning, and etching, and interlayer dielectric (e.g., silicon dioxide) deposition, patterning, and etching. Then a source ohmic contact can be formed, etched, and annealed. After these process steps, the device is Fig.14J shown.

[0118] Then a Schottky metal (e.g., titanium) may be deposited, followed by a final source metal (e.g., aluminum). After these process steps, the device may be Figure 14K shown.

[0119] Figures 14B-14K The buffer layer and the substrate layer are not shown.

[0120] Fig.15 A graph showing the operation of a DMOS with an integrated Schottky diode as described herein (◇) compared to a conventional DMOS device without an integrated Schottky diode (△), which operates in the third quadrant, where the gate-source voltage (V gs ) is 0 V. In the third quadrant, current conduction in conventional devices is mainly through the built-in P-well to N-drift pn junction diode. In the device described in this article, current conduction is dominated by the integrated Schottky diode. Fig.15 As can be seen in Figure 1, at any given current, the integrated Schottky diode has a much lower voltage drop compared to the built-in diode. The lower forward voltage drop translates into better performance in the power electronics system.

[0121] Fig.16 is a schematic diagram of a DC-DC converter circuit including a power MOSFET with an integrated Schottky diode. Fig.16 As shown, the circuit includes two power MOSFETs T1 and T2, which have integrated Schottky junctions as described herein. The gates of the power MOSFETs are driven by a gate control circuit to regulate the power transfer from the power supply to the load. Since the power MOSFETs have integrated Schottky junctions, a freewheeling diode D1 (shown in hatching) is not required.

[0122] While the foregoing description teaches the principles of the present invention and provides examples for purposes of illustration, those skilled in the art will appreciate that upon reading the present invention, various changes in form and details may be made without departing from the true scope of the invention.

Claims

1. A multi-unit MOSFET device, comprising: an n-type drift layer on an n-type substrate; A plurality of MOSFET cells, each MOSFET cell comprising: a first p-type well region and a second p-type well region having a spaced relationship on the n-type drift layer; an n-type JFET region on the n-type drift layer, the n-type JFET region being between the first p-type well region and the second p-type well region, wherein each of the first p-type well region and the second p-type well region has a channel region adjacent to the JFET region; a first n-type source region and a second n-type source region on each of the first p-type well region and the second p-type well region, the first n-type source region and the second n-type source region being adjacent to the channel region opposite to the JFET region, wherein the first n-type source region and the second n-type source region have a higher dopant concentration than the n-type drift layer; a source ohmic contact on each of the first n-type source region and the second n-type source region; a gate dielectric layer over the JFET region and the channel region; a gate layer on the gate dielectric layer; an interlayer dielectric layer on the gate layer; and a first p-type body contact region and a second p-type body contact region on the n-type drift layer, the first p-type body contact region and the second p-type body contact region being adjacent to the first n-type source region and the second n-type source region opposite to the channel region, wherein the first p-type body contact region and the second p-type body contact region have a higher dopant concentration than the first p-type well region and the second p-type well region; one or more n-type Schottky regions on the n-type drift layer, the n-type Schottky regions being adjacent to one or more MOSFET cells; a source metal layer on and in contact with the source ohmic contact and the one or more n-type Schottky regions; and a dielectric material over the source ohmic contact and the one or more n-type Schottky regions, the device further comprising: one or more source vias formed through a dielectric material on the source ohmic contact; and one or more Schottky vias formed through the dielectric material on the one or more n-type Schottky regions; wherein the source metal layer is on the dielectric material and in the source via and the Schottky via, and wherein the source metal layer contacts the Schottky region at the bottom of the Schottky via and contacts the source ohmic contact at the bottom of the source via, wherein each of the one or more n-type Schottky regions is adjacent to and between the p-type body contact regions of the adjacent cells; and The gate layer extends over the JFET region and the adjacent channel region in the device plane. 2 . The multi-cell MOSFET device of claim 1 , wherein one or more n-type Schottky regions have a different dopant concentration than the n-type drift layer.

3. The multi-cell MOSFET device of claim 1, wherein the n-type JFET region has a different dopant concentration than the n-type drift layer.

4. The multi-cell MOSFET device of claim 1, wherein: The first p-type well region and the second p-type well region are elongated regions spaced apart from each other in the x-direction and extend in the y-direction perpendicular to the x-direction; and The n-type JFET region is an elongated region extending along the x-direction between the first and second p-type well regions.

5. The multi-cell MOSFET device of claim 4, wherein the Schottky region comprises a single continuous elongated region extending along the y-direction between the p-type body contact regions of adjacent MOSFET cells.

6. The multi-cell MOSFET device of claim 5, wherein the first and second p-type body contact regions are elongated regions extending along the y-direction.

7. The multi-cell MOSFET device of claim 1 further comprising a dielectric material in the first and second p-type body contact regions.

8. The multi-cell MOSFET device of claim 1 further comprising a dielectric material in the first and second p-type body contact regions.

9. The multi-cell MOSFET device of claim 1, wherein the device includes one n-type Schottky region for each MOSFET cell.

10. The multi-cell MOSFET device of claim 1, wherein the device includes less than one n-type Schottky region per MOSFET cell.

11. The multi-cell MOSFET device of claim 1, wherein the device comprises an even number of MOSFET cells and comprises one n-type Schottky region for every two MOSFET cells.

12. The multi-cell MOSFET device of claim 1, wherein the device is a SiC device.

13. The multi-cell MOSFET device of claim 1, wherein the source ohmic contact is on first and second p-type body contact regions adjacent to first and second source regions, respectively.

14. A method of manufacturing a multi-cell MOSFET device, the method comprising: forming a first p-type well region and a second p-type well region in an n-type drift layer, wherein the n-type drift layer is on an n-type SiC substrate, and wherein the first p-type well region and the second p-type well region are spaced apart and an n-type Schottky region is formed therebetween; and wherein the n-type region of the drift layer is adjacent to the first well region and the second well region and an n-type region opposite to the n-type Schottky region forms a first JFET region and a second JFET region; forming a first n-type source region and a second n-type source region in each of the first p-type well region and the second p-type well region, respectively, wherein the n-type source region is spaced apart from the first JFET region and the second JFET region, leaving a p-type channel region between the n-type source region and the JFET region; forming first and second p-type body contact regions between the Schottky region and the first and second n-type source regions and adjacent to the Schottky region and the first and second n-type source regions, respectively; depositing a gate oxide layer on the first and second JFET regions and an adjacent channel region; depositing a gate layer on the gate oxide layer; depositing an interlayer dielectric material on the gate layer; forming a source ohmic contact on the first n-type source region and the second n-type source region and on the adjacent first p-type body contact region and the second p-type body contact region; depositing a source metal layer on the source ohmic contact and the n-type Schottky region, wherein the source metal layer forms a Schottky contact in contact with the n-type Schottky region; depositing a final metal on the source metal layer; forming a dielectric material on the source ohmic contact and the Schottky region; forming one or more source vias through the dielectric material on the source ohmic contact; and One or more Schottky vias are formed through the dielectric material on the Schottky region.

15. The multi-cell MOSFET device of claim 14, wherein depositing the source metal layer comprises depositing source metal in the source via and Schottky via, wherein the source metal layer contacts the source metal and Schottky region at the bottom of the source via and Schottky via, respectively.

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