Method for preparing three-dimensional packaging structure

Abstract

The present disclosure relates to a method for preparing a three-dimensional packaging structure, which belongs to the field of packaging and can achieve high-efficiency heat dissipation of the prepared three-dimensional packaging structure. A method for preparing a three-dimensional packaging structure, the three-dimensional packaging structure includes a plurality of stacked chips, microchannels located between the stacked chips, and a micropump that promotes the circulation of coolant in the microchannels to bring heat from the inside of the three-dimensional packaging structure to the outside, the method comprising: preparing the microchannels and interlayer electrical interconnections on at least one surface of each layer of chips; bonding the layers of chips to obtain a three-dimensional package; and connecting the three-dimensional package to the micropump.

Description

Technical Field

[0001] The present disclosure relates to the field of wafer-level packaging, and in particular, to a method for preparing a three-dimensional packaging structure. Background Art

[0002] Currently, the mainstream heat dissipation method for 3D packaging relies on thermal conduction to transfer heat generated by the chip inside the package to the surface, where it is then dissipated through convection or conduction. To ensure effective heat dissipation, this technology requires the thermal resistance of the heat dissipation path to be minimized. However, in 3D packaging, the interfacial thermal resistance is difficult to control, resulting in low heat dissipation efficiency with existing solutions. Summary of the Invention

[0003] The purpose of the present disclosure is to provide a method for preparing a three-dimensional packaging structure, which can achieve high-efficiency heat dissipation of the prepared three-dimensional packaging structure.

[0004] According to a first embodiment of the present disclosure, a method for preparing a three-dimensional packaging structure is provided. The three-dimensional packaging structure includes a plurality of stacked chips, microchannels located between the stacked chips, and a micropump that promotes the circulation of coolant in the microchannels to bring heat from the interior of the three-dimensional packaging structure to the outside. The method includes: preparing the microchannels and interlayer electrical interconnections on at least one side of each layer of chips; bonding the layers of chips to obtain a three-dimensional package; and connecting the three-dimensional package to the micropump.

[0005] Optionally, the preparation of the microfluidic channels and interlayer electrical interconnections on at least one surface of each layer of the chip includes: temporarily bonding the chip to a carrier to obtain a temporarily bonded package; forming a mold on the temporarily bonded package and preparing a redistribution layer and through holes; and preparing the microfluidic channels and interlayer electrical interconnections on the temporarily bonded package having the redistribution layer and the through holes formed thereon.

[0006] Optionally, bonding the chips in each layer to obtain the three-dimensional package includes: bonding the chips in each layer to obtain the three-dimensional package by using metal bonding or hybrid bonding.

[0007] Optionally, the microchannel is prepared by at least one of electroplating, etching, and physical vapor deposition.

[0008] Optionally, the microfluidic channel prepared on at least one surface of each chip layer is a part of the microfluidic channel of that layer, and after bonding the two chip layers, a complete and closed microfluidic channel of that layer is obtained.

[0009] Optionally, the method further comprises: before bonding the layers of chips to obtain a three-dimensional package, filling a dielectric between the microchannel and the interlayer electrical interconnection.

[0010] Optionally, the micropump is located at the top or bottom of the three-dimensional packaging structure.

[0011] Optionally, the method further includes: combining the micro pump with a heat sink of the three-dimensional packaging structure.

[0012] Optionally, the microchannels between different layers are connected via the through holes and are commonly connected to a coolant inlet and outlet connected to the micropump.

[0013] Optionally, the through hole is a mold through hole and / or a chip through hole.

[0014] By adopting this technical solution, the integration of microchannels within the 3D packaging structure enables the creation of more layers of 3D stacking and significantly improves the heat dissipation capacity of the 3D packaging structure, effectively reducing the operating temperature of the functional chip and increasing its power ceiling. Compared to other existing heat dissipation methods, it offers advantages such as a lower form factor, lower cost, and greater versatility. Furthermore, the microchannel pattern design allows for the integration of IPDs, providing a solution for enhancing heat dissipation at "hot spots." This 3D packaging structure can be fabricated using a wafer-level process compatible with silicon-based fabrication, ensuring mass production capability and process stability.

[0015] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0017] Figure 1 A schematic side view of a three-dimensional packaging structure according to an embodiment of the present disclosure is shown.

[0018] Figure 2 Another schematic side view of a three-dimensional packaging structure according to an embodiment of the present disclosure is shown.

[0019] Figure 3 A flow chart of a method for preparing a three-dimensional packaging structure according to an embodiment of the present disclosure is shown.

[0020] Figures 4a-4h A flow chart of a method for preparing a three-dimensional packaging structure according to an embodiment of the present disclosure is shown in a side view. DETAILED DESCRIPTION

[0021] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0022] Figure 1 FIG. 1 shows a schematic side view of a three-dimensional packaging structure according to an embodiment of the present disclosure. Figure 1 As shown, the three-dimensional packaging structure includes multiple stacked chips 1, a microchannel 2 and a micropump 3. The microchannel 2 is located between the stacked chips 1. It is a microchannel in which the coolant can circulate and flow, and can dissipate heat for the chips 1 on both sides of the microchannel 2. Figure 1 The three-dimensional package structure is shown in a side view, so the microchannels 2 are interconnected in a planar direction. A micropump 3 is used to circulate coolant through the microchannels 2, removing heat from the interior of the three-dimensional package structure to the exterior. Micropump 3 can be implemented using microelectromechanical systems (MEMS) technology or, depending on the package size, a microelectronic pump.

[0023] Figure 1 The three-dimensional packaging structure shown in the example includes three layers of chips, but those skilled in the art should understand that the present disclosure does not limit the number of layers of chips included in the three-dimensional packaging structure. In addition, each layer of chips can be a package body packaged by any packaging method, such as a package body packaged by a fan-out (Fan-out), chip scale package (CSP) or other packaging methods. Each package body can be made separately, and each package body can include one or more chips; it can also be an unpackaged bare chip. As long as the size is appropriate and the conditions are met, it can be compatible with the three-dimensional packaging structure according to the embodiment of the present disclosure.

[0024] Microchannel 2 is made of a thermally conductive material so that the coolant flowing in microchannel 2 can absorb heat from chip 1 through microchannel 2, thereby dissipating heat from chip 1 through the circulation of the coolant. For example, microchannel 2 can be made of at least one of the following materials: metal, semiconductor material, etc. The metal can be copper, nickel, gold, silver, or a metal alloy, and the semiconductor material can be silicon, silicon carbide, etc.

[0025] The size of the microchannel 2 is comparable to the size of the interlayer electrical interconnections of the stacked chips 1. Thus, the fabrication of the microchannel 2, the interlayer electrical interconnections, and even the fabrication of the integrated passive device (IPD) structure do not conflict with each other and can be performed in tandem.

[0026] The thickness of the microchannel 2 can be in the range of 1 micron to 100 microns, for example, from less than 10 microns to tens of microns. In this way, the preparation process of the microchannel 2 can be compatible with existing silicon-based processes and wafer-level processes.

[0027] The microchannels 2 between different stacks can be connected through mold through holes (TMV) and / or chip through holes (TDV), and are connected to the coolant inlet and outlet connected to the micro pump 3. In this way, the microchannels 2 between different stacks form a circulation loop as a whole, which is beneficial to the heat dissipation of the three-dimensional packaging structure. Figure 1 In the figure, the black area is the mold, and the gray area is the metal layer used to form the electrical interconnection between the layers. Through holes are formed in the mold, and the microchannels between the layers are interconnected with the micropump 3 through the through holes. However, it should be understood by those skilled in the art that Figure 1 The through-hole structure shown is only an example and does not constitute a limitation of the present disclosure.

[0028] The micropump 3 can be integrated at the top or bottom of the three-dimensional packaging structure. In this way, the micropump 3 can promote the circulation of the coolant in all microchannels 2, and is also conducive to the optimization of the three-dimensional packaging structure, making the three-dimensional packaging structure more compact.

[0029] The micro pump 3 can be combined with a heat sink of the three-dimensional packaging structure, thus making the three-dimensional packaging structure more compact.

[0030] By adopting this technical solution, the integration of microchannels within the 3D packaging structure enables the creation of more layers of 3D stacking and significantly improves the heat dissipation capacity of the 3D packaging structure, effectively reducing the operating temperature of the functional chip and increasing its power ceiling. Compared to other existing heat dissipation methods, it offers advantages such as a lower form factor, lower cost, and greater versatility. Furthermore, the microchannel pattern design allows for the integration of IPDs, providing a solution for enhancing heat dissipation at "hot spots." This 3D packaging structure can be fabricated using a wafer-level process compatible with silicon-based fabrication, ensuring mass production capability and process stability.

[0031] Figure 2 FIG. 1 shows another schematic side view of a three-dimensional packaging structure according to an embodiment of the present disclosure. Figure 2 As shown, the three-dimensional packaging structure further includes a dielectric 4 filled between the microchannels 2 and the interlayer electrical interconnections of the stacked chips 1 to prevent short circuits or crosstalk. The dielectric 4 can be made of any non-conductive material.

[0032] Further references Figure 2 The three-dimensional packaging structure also includes a carrier 5 for carrying the entire three-dimensional packaging structure.

[0033] Figure 3 A flow chart showing a method for preparing a three-dimensional packaging structure according to an embodiment of the present disclosure is shown. Figure 1 and Figure 2 The three-dimensional packaging structure described. Figure 3 As shown, the method includes:

[0034] In step S31, microfluidic channels and interlayer electrical interconnections are prepared on at least one surface of each chip layer;

[0035] In step S32, the chips of each layer are bonded to obtain a three-dimensional package; and

[0036] In step S33 , the three-dimensional package is connected to the micro pump.

[0037] By adopting the above technical solution, the integration of microchannels in the three-dimensional packaging structure makes it possible to stack more layers of three-dimensional packaging and significantly improve the heat dissipation capacity of the three-dimensional packaging structure, thereby effectively reducing the operating temperature of the functional chip and increasing the power limit of the functional chip. Compared with other existing heat dissipation methods, it has the advantages of lower form factor, lower cost, and greater versatility. In addition, the microchannel graphic design allows for the integration of IPDs and also provides a solution for enhancing heat dissipation capacity for "hot spots." This three-dimensional packaging structure preparation method uses a wafer-level manufacturing process compatible with silicon-based preparation processes, ensuring mass production capabilities and process stability.

[0038] Figures 4a-4h A flow chart of a method for preparing a three-dimensional packaging structure according to an embodiment of the present disclosure is shown in a side view.

[0039] First, if Figure 4a As shown, the chip 1 is temporarily bonded to the first carrier 5 to obtain a temporarily bonded package. Metal bonding or hybrid bonding can be used to temporarily bond the chip 1 to the first carrier 5. The first carrier 5 is used to support the chip 1 during the three-dimensional packaging process.

[0040] Then, if Figure 4b As shown, a mold 6 is formed on the temporary bonded package body and a redistribution layer 7 and a through hole 8 are prepared. The mold 6, redistribution layer 7, through hole 8, etc. can all be prepared using existing preparation processes, making the three-dimensional packaging structure preparation method according to the embodiment of the present disclosure more compatible.

[0041] Then, if Figure 4c As shown, microchannels 2 and interlayer electrical interconnections are prepared on a temporary bonding package having a redistribution layer and through holes. Figure 4c In the process, only a part of the microchannel 2, for example, half of the microchannel 2, is prepared. When the layers of chips are bonded in the subsequent steps, the microchannels prepared on the layers of chips will also bond with each other, thus forming a complete closed microchannel structure. Figure 4cIt is also feasible to prepare a complete closed microchannel structure on each chip layer. The microchannel 2 can be prepared using at least one of electroplating, etching, and physical vapor deposition.

[0042] Further references Figure 4c In this step, a dielectric 4 may be filled between the microchannel 2 and the interlayer electrical interconnection to prevent short circuits and crosstalk. The dielectric 4 may be prepared by at least one of electroplating, etching, and physical vapor deposition.

[0043] Then, if Figure 4d As shown, a second carrier is bonded on the micro-channels and inter-layer electrical interconnections.

[0044] Then, if Figure 4e As shown, the first carrier is debonded from the chip. Figure 4d and Figure 4e The temporary bonded package is transferred from the first carrier to the second carrier, so that microchannels, interlayer electrical interconnections, etc. can be continuously prepared on the other side of the chip 1.

[0045] Then, if Figure 4f As shown, microfluidic channels and interlayer electrical interconnections are prepared on the other side of the chip 1.

[0046] Then, if Figure 4g As shown, it will be completed Figure 4c and Figure 4f By bonding the two structures, it is possible to achieve bonding of chips of different layers. After bonding, the second carrier is debonded and the debonded structure is continued to be bonded to the Figure 4f or Figure 4c By bonding the structure shown in the figure, and repeating this process, multi-layer chips can be stacked.

[0047] Then, as shown in 4h, the stacked chip is connected to the micro pump 3 to complete the preparation of the three-dimensional packaging structure. Figure 4h The three-dimensional packaging structure shown includes three stacked chips 1. Figure 4h In the figure, micropump 3 is located at the top of the three-dimensional package structure. Microchannels 2 between different layers are connected by through-holes (e.g., mold through-holes and / or chip through-holes), and are collectively connected to the coolant inlet and outlet connected to micropump 3. However, in actual applications, the position of micropump 3 can be arranged according to the actual three-dimensional package structure, for example, it can be located at the bottom, middle, etc. of the three-dimensional package structure. In addition, micropump 3 can also be combined with a heat sink of the three-dimensional package structure.

[0048] pass Figures 4a to 4hThe preparation process can complete the three functions of mechanical connection, electrical interconnection and heat dissipation structure preparation in one step through wafer-level bonding, making the three-dimensional packaging structure preparation method according to the embodiment of the present disclosure more applicable.

[0049] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details of the above embodiments. Within the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the scope of protection of the present disclosure.

[0050] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

[0051] In addition, the various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.

Claims

1. A method for preparing a three-dimensional packaging structure, characterized in that: The three-dimensional packaging structure includes a plurality of stacked chips, microchannels located between the stacked chips, and a micropump that promotes a coolant to circulate in the microchannels to bring heat from the inside of the three-dimensional packaging structure to the outside. The method includes: Preparing the microfluidic channels and interlayer electrical interconnections on at least one surface of each layer of the chip; Bonding the chips in each layer to obtain a three-dimensional package; and Connecting the three-dimensional package to the micropump; The step of preparing the microfluidic channel and the interlayer electrical interconnection on at least one surface of each layer of the chip comprises: Temporarily bonding the chip to a carrier to obtain a temporarily bonded package; forming a mold on the temporary bonding package and preparing a redistribution layer and a through hole; The micro-channel and the inter-layer electrical interconnection are prepared on the temporary bonded package on which the redistribution layer and the through-hole are formed.

2. The method according to claim 1, characterized in that The step of bonding the chips in each layer to obtain a three-dimensional package includes: The three-dimensional package is obtained by bonding the chips in each layer by metal bonding or hybrid bonding.

3. The method according to claim 1 or 2, characterized in that: The microchannel is prepared by at least one of electroplating, etching and physical vapor deposition.

4. The method according to claim 1 or 2, characterized in that: The microfluidic channel prepared on at least one surface of each layer of the chip is a part of the microfluidic channel of this layer, and after bonding the two layers of chips, a completely closed microfluidic channel of this layer is obtained.

5. The method according to claim 1 or 2, characterized in that: The method further comprises: before bonding the chips of each layer to obtain a three-dimensional package, filling a dielectric between the microchannel and the inter-layer electrical interconnection.

6. The method according to claim 1 or 2, characterized in that: The micro pump is located at the top or the bottom of the three-dimensional packaging structure.

7. The method according to claim 6, characterized in that The method further includes combining the micro pump with a heat sink of the three-dimensional packaging structure.

8. The method according to claim 1, characterized in that The micro channels between different layers are connected through the through holes and are commonly connected to the coolant inlet and outlet connected to the micro pump.

9. The method according to claim 8, characterized in that The through hole is a mold through hole and / or a chip through hole.

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