Storage device and storage device operation method

Abstract

A storage device and an operation method of the storage device are disclosed. A storage device includes a nonvolatile memory device and a memory controller. The memory controller receives first data from the nonvolatile memory device based on a first read command, and performs error correction on the first data. When the error correction fails, the memory controller sends a second read command and second read voltage information to the nonvolatile memory device, receives second data from the nonvolatile memory device, sends a third read command and third read voltage information to the nonvolatile memory device, and receives third data from the nonvolatile memory device. The memory controller adjusts an offset based on the second data and the third data, sends a fourth read command, fourth read voltage information, and offset to the nonvolatile memory device, receives fourth data from the nonvolatile memory device, and performs soft decision processing based on the fourth data.

Description

Technical Field

[0001] Embodiments of the inventive concepts described herein relate to a semiconductor device. More particularly, embodiments of the inventive concepts described herein relate to a memory device that performs a read operation with improved reliability and an operating method of the memory device. Background Art

[0002] A storage device is a device that stores data under the control of a host device such as a computer, a smart phone, or a smart tablet. One example of a storage device is a device that stores data on a magnetic disk such as a hard disk drive (HDD). Another example of a storage device is a device that stores data in a semiconductor memory, specifically, a non-volatile memory such as a solid state drive (SSD) or a memory card.

[0003] A non-volatile memory includes memory cells configured to store data. In order to increase the amount of data to be stored in a storage device storing data in a non-volatile memory, methods are sought to increase the number of bits to be stored in each of the memory cells. As the number of bits stored in each of the memory cells increases, the probability of errors occurring in the data stored in the memory cells may increase.

[0004] A reading method capable of restoring original data even when an error occurs in the data stored in the memory cell is needed to ensure the integrity of the data stored in the memory cell. Summary of the invention

[0005] The inventive concepts described herein include a memory device that provides a read operation with improved reliability and a method of operating the memory device.

[0006] According to an exemplary embodiment, a memory device includes: a nonvolatile memory device including a plurality of memory cells; and a memory controller, which sends a first read command and a first read voltage information associated with the plurality of memory cells to the nonvolatile memory device, receives first data from the nonvolatile memory device based on the first read command, and performs error correction on the first data. When the error correction fails, the memory controller sends a second read command and a second read voltage information associated with the plurality of memory cells to the nonvolatile memory device, receives second data from the nonvolatile memory device based on the second read command, sends a third read command and a third read voltage information associated with the plurality of memory cells to the nonvolatile memory device, and receives third data from the nonvolatile memory device based on the third read command. The memory controller adjusts an offset based on the second data and the third data, sends an offset, a fourth read command and a fourth read voltage information associated with the plurality of memory cells to the nonvolatile memory device, receives fourth data from the nonvolatile memory device based on the fourth read command, and performs soft decision processing based on the fourth data.

[0007] According to an exemplary embodiment, a storage device includes a nonvolatile memory device having a plurality of memory cells and a memory controller. The memory controller sends a first read command and a first read voltage information associated with the plurality of memory cells to the nonvolatile memory device, receives first data from the nonvolatile memory device based on the first read command, and performs error correction on the first data. When the error correction fails, the memory controller sends a first offset, a second read command and a second read voltage information associated with the plurality of memory cells to the nonvolatile memory device, receives second data from the nonvolatile memory device based on the second read command, and performs a first soft decision process based on the second data. When the first soft decision process fails, the memory controller sends a third read command and a third read voltage information associated with the plurality of memory cells to the nonvolatile memory device, receives third data from the nonvolatile memory device based on the third read command, sends a fourth read command and a fourth read voltage information associated with the plurality of memory cells to the nonvolatile memory device, and receives fourth data from the nonvolatile memory device based on the fourth read command. The memory controller adjusts the first offset to a second offset based on the third data and the fourth data, sends the second offset, a fifth read command associated with the plurality of memory cells, and fifth read voltage information to the nonvolatile memory device, receives fifth data from the nonvolatile memory device based on the fifth read command, and performs a second soft decision process based on the fifth data.

[0008] According to an exemplary embodiment, a method for operating a storage device includes a nonvolatile memory device and a controller for controlling the nonvolatile memory device, the method including: at the controller, reading first data and second data from the nonvolatile memory device by using a first read voltage and a second read voltage, respectively; at the controller, adjusting an offset based on the first data and the second data; at the controller, reading third data from the nonvolatile memory device using a third read voltage and the adjusted offset; and at the controller, performing soft decision processing based on the third data. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the present disclosure will become apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0010] Figure 1 A storage device according to an embodiment of the present disclosure is shown.

[0011] Figure 2 An example of a hard decision based read operation is shown.

[0012] Figure 3 An example of an uncorrectable error occurring in a hard decision-based read operation is shown.

[0013] Figure 4 An example of a soft-decision based read operation is shown.

[0014] Figure 5 is a flowchart illustrating an operating method of a storage device according to an embodiment of the present disclosure.

[0015] Figure 6 is a diagram illustrating an example in which a pre-read operation and modeling are performed.

[0016] Figure 7 Threshold voltage distributions of memory cells when three bits are written to one memory cell are shown.

[0017] Figure 8 A soft decision controller according to an embodiment of the present disclosure is shown.

[0018] Fig. 9 is a flowchart illustrating an operating method of a storage device according to another embodiment of the present disclosure.

[0019] Fig.10 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present disclosure.

[0020] Fig.11 An example of a memory block according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0021] Below, embodiments of the present disclosure are described in detail and clearly so that one of ordinary skill in the relevant art can easily implement the inventive concepts described herein.

[0022] Figure 1 1 shows a storage device 100 according to an embodiment of the present disclosure. Figure 1 , the memory device 100 may include a nonvolatile memory device 110, a memory controller 120, and an external buffer 130. The nonvolatile memory device 110 may include a plurality of memory cells. Each of the plurality of memory cells may store two or more bits.

[0023] For example, the nonvolatile memory device 110 may be or may include at least one of various nonvolatile memory devices, such as a flash memory device, a phase change memory device, a ferroelectric memory device, a magnetic memory device, and a resistive memory device. In order to easily convey one or more technical aspects of the inventive concept described herein, it is assumed that the nonvolatile memory device 110 is a flash memory device.

[0024] The memory controller 120 may receive various requests from an external host device for writing data to the nonvolatile memory device 110 or for reading data from the nonvolatile memory device 110. The memory controller 120 may store (or buffer) user data communicated with the external host device to the external buffer 130, and may store metadata for managing the memory device 100 to the external buffer 130.

[0025] The memory controller 120 may access the nonvolatile memory device 110 through the first channel CH1 and the second channel CH2. For example, the memory controller 120 may send commands and addresses to the nonvolatile memory device 110 through the first channel CH1. The memory controller 120 may exchange data with the nonvolatile memory device 110 through the first channel CH1.

[0026] The memory controller 120 may transmit the first control signal to the nonvolatile memory device 110 through the second channel CH2. The memory controller 120 may receive the second control signal from the nonvolatile memory device 110 through the second channel CH2.

[0027] In an embodiment, the memory controller 120 may be configured to control two or more nonvolatile memory devices, each of which is individually controlled by the nonvolatile memory device 110. The memory controller 120 may provide a designated first channel and a designated second channel for each of the two or more nonvolatile memory devices, respectively.

[0028] For another example, the memory controller 120 may share a first channel with respect to two or more nonvolatile memory devices. The memory controller 120 may provide a second channel to two or more nonvolatile memory devices that share a portion of the second channel. The memory controller 120 may provide different portions of the second channel to two or more nonvolatile memory devices.

[0029] The external buffer 130 may include a random access memory. For example, the external buffer 130 may include at least one of a dynamic random access memory, a phase change random access memory, a ferroelectric random access memory, a magnetic random access memory, and a resistive random access memory.

[0030] Memory controller 120 may include bus 121, host interface 122, internal buffer 123, processor 124, buffer controller 126, memory manager 127, and error correction code (ECC) block 128. Processor 124 may execute software instructions to fully or partially implement one or more aspects of the processes described herein.

[0031] The bus 121 may provide a communication channel between components in the memory controller 120 . The host interface 122 may receive various requests from an external host device and may parse the received requests. The host interface 122 may store the parsed requests in the internal buffer 123 .

[0032] The host interface 122 may send various responses to an external host device. The host interface 122 may exchange signals with an external host device according to a given communication protocol. The internal buffer 123 may include a random access memory. For example, the internal buffer 123 may include a static random access memory or a dynamic random access memory.

[0033] The processor 124 may drive an operating system or firmware for driving the memory controller 120. The processor 124 may read the parsed request stored in the internal buffer 123, and may generate a command and an address for controlling the nonvolatile memory device 110. The processor 124 may transfer the generated command and address to the memory manager 127.

[0034] The processor 124 may store various metadata for managing the storage device 100 to the internal buffer 123. The processor 124 may access the external buffer 130 through the buffer controller 126. The processor 124 may control the buffer controller 126 and the memory manager 127 so that user data stored in the external buffer 130 is transmitted to the nonvolatile memory device 110.

[0035] The processor 124 may control the host interface 122 and the buffer controller 126 so that the data stored in the external buffer 130 is transmitted to the external host device. The processor 124 may control the buffer controller 126 and the memory manager 127 so that the data received from the nonvolatile memory device 110 is stored in the external buffer 130. The processor 124 may control the host interface 122 and the buffer controller 126 so that the data received from the external host device is stored in the external buffer 130.

[0036] The buffer controller 126 may write data to the external buffer 130 or may read data from the external buffer 130 under the control of the processor 124. The memory manager 127 may communicate with the nonvolatile memory device 110 through the first channel CH1 and the second channel CH2 under the control of the processor 124.

[0037] The error correction code block 128 may perform error correction encoding on data to be transmitted to the nonvolatile memory device 110 by using the error correction code ECC. The error correction code block 128 may perform error correction decoding on data received from the nonvolatile memory device 110 by using the error correction code ECC.

[0038] The processor 124 may include a soft decision controller (SDC) 125. The soft decision controller (SDC) 125 may be implemented by the processor 124 executing a set of defined software instructions. When the error correction code block 128 fails to correct the error of the data read from the non-volatile memory device 110 by the memory manager 127 under the control of the processor 124, the soft decision controller 125 may be activated.

[0039] The soft decision controller 125 may support a read operation that provides improved reliability and data integrity by recovering the original data from the data stored in the nonvolatile memory device 110 when the data includes errors.

[0040] In an embodiment, the memory device 100 may not include the external buffer 130 and the buffer controller 126. When the external buffer 130 and the buffer controller 126 are not included in the memory device 100, the above functions of the external buffer 130 and the buffer controller 126 may be performed by the internal buffer 123.

[0041] Figure 2 An example of a hard decision based read operation is shown. Figure 2 , the horizontal axis represents the threshold voltage VTH of the memory cells of the nonvolatile memory device 110 , and the vertical axis represents the number of memory cells of the nonvolatile memory device 110 . Figure 2An example in which each of the memory cells is programmed to have one of an erased state “E” and a programmed state “P” is shown in FIG. A hard decision in a hard decision-based read operation may refer to a binary decision based on whether a memory cell has a threshold voltage lower than a read voltage VR or has a threshold voltage higher than the read voltage VR.

[0042] exist Figure 2 In the write operation, the first line L1 may correspond to memory cells that are not programmed in the write operation and have an erase state “E.” The second line L2 may correspond to memory cells that are programmed in the write operation to have a program state “P.”

[0043] Reference Figure 1 and Figure 2 In a read operation, the nonvolatile memory device 110 may perform a read operation by using a read voltage VR. Memory cells having a threshold voltage lower than the read voltage VR may be turned on, and memory cells having a threshold voltage higher than the read voltage VR may be turned off.

[0044] The nonvolatile memory device 110 may identify the turned-on memory cells as an erase state “E” and may identify the turned-off memory cells as a program state “P.” The nonvolatile memory device 110 may transmit the identified data to the memory controller 120 .

[0045] like Figure 2 As shown, a portion of the memory cells corresponding to the first line L1 may have a threshold voltage higher than the read voltage VR. That is, a portion of the memory cells intended to have an erase state "E" may be recognized as a program state "P".

[0046] Similarly, a portion of the memory cells corresponding to the second line L2 may have a threshold voltage lower than the read voltage VR. That is, a portion of the memory cells intended to have a program state "P" may be recognized as an erase state "E".

[0047] The error correction code block 128 may attempt to perform error correction decoding on the data received from the nonvolatile memory device 110. Data identified as a programmed state “P” among the data read from the memory cells corresponding to the first line L1 may be corrected to data of an erased state “E” through error correction decoding. In addition, data identified as an erased state “E” among the data read from the memory cells corresponding to the second line L2 may be corrected to data of a programmed state “P” through error correction decoding.

[0048] As reference Figure 2, the hard decision based read operation may be a read operation that performs error correction decoding on read data once data is read from memory cells in an “E” state and a “P” state by using a read voltage VR.

[0049] Figure 3 An example of an uncorrectable error occurring in a hard decision-based read operation is shown. Figure 1 and Figure 3 ,and Figure 2 In contrast, the number of data recognized as the program state “P” among the data read from the memory cells corresponding to the first line L1 and intended to have the erase state “E” may increase.

[0050] In addition, Figure 2 In comparison, the number of data recognized as the erased state "E" among the data read from the memory cell corresponding to the second line L2 and intended to have the programmed state "P" can be increased. Due to various reasons such as retention, interference, and coupling, the threshold voltage of the memory cell may be inadvertently changed. This change can be understood as causing degradation of the data written in the memory cell.

[0051] As the degradation of the data written in the memory cell continues, the number of errors increases. When the number of errors exceeds the range that can be corrected by the error correction code block 128, uncorrectable errors occur. When uncorrectable errors occur in a read operation based on hard decisions, the memory controller 120 may perform a subsequent read operation for recovering data. For example, the soft decision controller 125 of the processor 124 may be activated, and a read operation based on soft decisions may be performed.

[0052] Figure 4 An example of a soft decision based read operation is shown. As explained below, soft decision processing in a soft decision based read operation may refer to processing that includes multiple determinations based on multiple inputs, wherein the multiple determinations may, but do not necessarily, conflict with each other.

[0053] Reference Figure 1 and Figure 4 , the memory controller 120 may control the nonvolatile memory device 110 to perform a first read operation by using a first offset read voltage VRO1 that is lower than the read voltage VR by a first offset OFF1. The memory controller 120 may also control the nonvolatile memory device 110 to perform a second read operation by using a second offset read voltage VRO2 that is higher than the read voltage VR by a first offset OFF1. Figure 4 Each label along the horizontal axis VTH in FIG generally corresponds to the appropriate label for L1. Figure 4 An appropriate label for L2 on the horizontal axis VTH is usually Figure 4 The labels are shown in reverse order and generally correspond to the appropriate labeling for L1.

[0054] The nonvolatile memory device 110 may perform an XOR operation on a first read result using the first offset read voltage VRO1 and a second read result using the second offset read voltage VRO2. The XOR operation generates a positive result such as "1" only when two inputs such as the first read result and the second read result are different. The nonvolatile memory device 110 may send the operation result to the memory controller 120.

[0055] The operation result of the XOR operation showing that the memory cells are in the same state (e.g., "E" or "P") using the first offset read voltage VR01 and the second offset read voltage VR02 may be "0", and the operation result showing that the memory cells are in different states using the first offset read voltage VR01 and the second offset read voltage VR02 may be "1". For example, the operation result corresponding to the memory cells determined to be in the same state in the first offset read operation using the first offset read voltage VRO1 and the second offset read operation using the second offset read voltage VRO2 may be "0". The operation result corresponding to the memory cells determined to be in different states in the first offset read operation using the first offset read voltage VRO1 and the second offset read operation using the second offset read voltage VRO2 may be "1". That is, the operation result of the XOR operation may indicate whether each of the plurality of memory cells is identified as having the same state in the first offset read operation or a different state in the second offset read operation.

[0056] First, the threshold voltages of memory cells corresponding to the first line L1, which are identified as having the erased state “E” in the hard decision-based read operation, are explained, and these threshold voltages are generally Figure 4 The labels along the horizontal axis VTH in the hard decision-based read operation correspond to the labels along the horizontal axis VTH in the hard decision-based read operation. The threshold voltage of the memory cell identified as having the erased state "E" in the hard decision-based read operation and identified as having the same state in the operation result may be lower than the first offset read voltage VRO1. For the first line L1, these memory cells are located above the horizontal axis VTH in the portion labeled SC. The data of the memory cell having a threshold voltage lower than the first offset read voltage VRO1 among the memory cells corresponding to the first line L1 can be identified as a strong correct (SC) bit.

[0057] The threshold voltage of the memory cell identified as having the erased state "E" in the hard decision-based read operation and identified as having a different state in the operation result may be higher than the first offset read voltage VRO1 and may be lower than the read voltage VR. For the first line L1, these memory cells are located above the horizontal axis VTH of the portion marked with WC. Data of the memory cell having a threshold voltage higher than the first offset read voltage VRO1 and lower than the read voltage VR among the memory cells corresponding to the first line L1 may be identified as a weakly correct (WC) bit (or an unreliable correct (UC) bit).

[0058] The threshold voltage of the memory cell identified as having the programming state "P" in the hard decision-based read operation and identified as having a different state in the operation result may be higher than the read voltage VR and may be lower than the second offset read voltage VRO2. For the first line L1, these memory cells are located above the horizontal axis VTH in the portion marked with WE. Data of the memory cell having a threshold voltage higher than the read voltage VR and lower than the second offset read voltage VRO2 among the memory cells corresponding to the first line L1 may be identified as a weak error (WE) bit.

[0059] The threshold voltage of the memory cell identified as having the programmed state "P" in the hard decision-based read operation and identified as having the same state in the operation result may be higher than the second offset read voltage VRO2. For the first line L1, these memories are located above the horizontal axis VTH in the portion marked with SE. Data of the memory cell having a threshold voltage higher than the second offset read voltage VRO2 among the memory cells corresponding to the first line L1 may be identified as a strong error (SE) bit (or a hard error (HE) bit).

[0060] The data of the memory cells having a threshold voltage higher than the second offset read voltage VRO2 in the memory cells corresponding to the second line L2 can be identified as a strong correct (SC) bit. For the second line L2, these memory cells are located above the horizontal axis VTH in the portion marked with SE instead of SC. The data of the memory cells having a threshold voltage higher than the read voltage VR and lower than the second offset read voltage VRO2 in the memory cells corresponding to the second line L2 can be identified as a weak correct (WC) bit (or an unreliable correct (UC) bit). For the second line L2, these memory cells are located above the horizontal axis VTH in the portion marked with WE instead of WC. The data of the memory cells having a threshold voltage higher than the first offset read voltage VRO1 and lower than the read voltage VR in the memory cells corresponding to the second line L2 can be identified as a weak error (WE) bit. For the second line L2, these memory cells are located above the horizontal axis VTH in the portion marked with WC instead of WE. The data of the memory cells having a threshold voltage lower than the first offset read voltage VRO1 in the memory cells corresponding to the second line L2 can be identified as a strong error (SE) bit (or a hard error (HE) bit). For the second line L2, the memory cells are located above the horizontal axis VTH in the portion labeled SC instead of SE.

[0061] As mentioned above Figure 4 As described, the strongly correct (SC) bit for the first line L1 is the portion above the horizontal segment marked with SC, while the strongly correct (SC) bit for the second line L2 is the portion above the horizontal segment marked with SE. The weakly correct (WC) bit for the first line L1 is the portion above the horizontal segment marked with WC, while the weakly correct (WC) bit for the second line is the portion above the horizontal segment marked with WE. The weakly error (WE) bit for the first line L1 is the portion above the horizontal segment marked with WE, while the weakly error (WE) bit for the second line L2 is the portion above the horizontal segment marked with WC. The strongly error (SE) bit for the first line L1 is the portion above the horizontal segment marked with SE, while the strongly error (SE) bit for the second line is the portion above the horizontal segment marked with SC.

[0062] The memory controller 120 may identify bits based on data read by using the read voltage VR and data read by using the first and second offset read voltages VRO1 and VRO2 , and may allow the error correction code block 128 to perform a soft decision process by using the identification result.

[0063] For example, the error correction code block 128 can assign scores to strongly correct (SC) bits, weakly correct (WC) bits, weakly errored (WE) bits, and strongly errored (SE) bits, respectively. The error correction code block 128 can correct errors by performing low-density parity check (LDPC) decoding on the scored bits, and can restore the original data.

[0064] The memory device 100 according to an embodiment of the present disclosure may also be configured to perform a fine soft decision process. The fine soft decision process may be performed by the following steps: modeling the distribution state of memory cells such as the first line L1 and the second line L2; adjusting the offset based on the modeling result; performing a read operation including at least two offset read operations based on the adjusted offset; and performing a soft decision process.

[0065] Figure 5 1 is a flowchart showing an operation method of the storage device 100 according to an embodiment of the present disclosure. Figure 1 and Figure 5 , in operation S110 , the memory controller 120 may receive a read request including a logical address LBA from an external host device.

[0066] The memory controller 120 can manage the mapping information between the logical address LBA of the external host device and the physical address PBA of the nonvolatile memory device 110 as metadata. For example, if necessary, the mapping information can be backed up to the nonvolatile memory device 110 and can be loaded to the external buffer 130 or the internal buffer 123.

[0067] The memory controller 120 may convert the logical address LBA into the physical address PBA by using the mapping information. In operation S115 , the memory controller 120 may transmit a first read command CMD_R1 together with the physical address PBA and read voltage information IVR including information of a read level to the nonvolatile memory device 110 .

[0068] In operation S120, as shown in FIG. Figure 3 As described above, the nonvolatile memory device 110 may read data from the memory cell indicated by the physical address PBA by using the read level indicated by the read voltage information IVR. In operation S125, the nonvolatile memory device 110 may send the first data D1 thus read to the memory controller 120. Operations S115 to S125 may correspond to one read operation. The operation at S115 may therefore include sending a first read command (CMD_R1) and first read voltage information (IVR). The operation at S125 may therefore include receiving the first data (D1) based on the first read command (CMD_R1 from S115).

[0069] In operation S130, the memory controller 120 may perform a hard decision process. For example, the memory controller 120 may perform error correction decoding on the first data D1 read by using the read voltage information IVR. In an embodiment, the error correction decoding may fail. Then, the memory controller 120 may enter a procedure for recovering the data stored in the memory cell.

[0070] In operation S135, the memory controller 120 may send a first read command CMD_R1, a physical address PBA, and first read voltage information IVR1 to the nonvolatile memory device 110. The read level indicated by the first read voltage information IVR1 may be lower or higher than the read level indicated by the read voltage information IVR.

[0071] In operation S140, the nonvolatile memory device 110 may perform a read operation by using the read level indicated by the first read voltage information IVR1. In operation S145, the nonvolatile memory device 110 may send the second data D2 read in operation S140 to the memory controller 120. The operation of S135 may therefore include sending a second read command (CMR_R1) and the second read voltage information (IVR1). The operation at S145 may therefore include receiving the second data (D2) based on the second read command (CMR_R1 from S135).

[0072] In operation S150, the memory controller 120 may send a first read command CMD_R1, a physical address PBA, and second read voltage information IVR2 to the nonvolatile memory device 110. The read level indicated by the second read voltage information IVR2 may be higher or lower than the read level indicated by the read voltage information IVR.

[0073] In operation S155, the nonvolatile memory device 110 may perform a read operation by using the read level indicated by the second read voltage information IVR2. In operation S160, the nonvolatile memory device 110 may send the third data D3 read in operation S155 to the memory controller 120. The operation of S150 may therefore include sending a third read command (CMR_R1) and the third read voltage information (IVR2). The operation at S160 may therefore include receiving the third data (D3) based on the third read command (CMR_R1 from S150).

[0074] Operations S135 to S145 may correspond to one read operation and may be included in a pre-read operation for fine soft decision processing. Operations S150 to S160 may correspond to one read operation and may be included in a pre-read operation for fine soft decision processing.

[0075] In operation S165, the memory controller 120 may model the threshold voltage distribution of the memory cell based on the second data D2 and the third data D3 read by the pre-read operation. The memory controller 120 may identify or adjust an offset based on the modeling of the threshold voltage distribution of the memory cell according to the second data D2 and the third data D3, and may send the offset to the nonvolatile memory device 110 at S175 explained below.

[0076] Figure 6 is a diagram showing an example in which a pre-reading operation and modeling are performed. Figure 1 , Figure 5 and Figure 6 , shows a first line L1 indicating memory cells that want to be in an erase state “E” and a second line L2 indicating memory cells that want to be in a program state “P”, but threshold voltages actually identified from the memory cells may not be classified into the first line L1 and the second line L2.

[0077] like Figure 6 As shown by the solid line of , the threshold voltage actually identified from the memory cell may not be classified into the first line L1 and / or the second line L2, respectively. However, it is known that the opposite ends of the threshold voltage distribution of the memory cell have an exponentially decreasing shape.

[0078] Therefore, the first function F1 can be modeled from one side of the valley of the first line L1 (corresponding to the threshold voltage distribution for the erased state "E") (to the right side of the valley of the first line) to a portion of the threshold voltage distribution of the memory cell that coincides with the programmed state "P". In addition, the second function F2 can be modeled from one side of the valley of the second line L2 (corresponding to the threshold voltage for the programmed state "P") (to the left side of the valley of the second line L2) to a portion of the threshold voltage distribution of the memory cell that coincides with the erased state "E".

[0079] A read operation may be performed by using a first read voltage VR1 indicated by the first read voltage information IVR1, and the number of turned-on cells (or turned-on memory cells) or turned-off cells (or turned-off memory cells) may be counted as a first count. Similarly, a read operation may be performed by using a second read voltage VR2 indicated by the second read voltage information IVR2, and the number of turned-on cells or turned-off cells may be counted as a second count.

[0080] The memory controller 120 may model the first function F1 and the second function F2 based on the first count and the second count. For example, the memory controller 120 may manage the count value and the exponential function corresponding to the count value as metadata. The memory controller 120 may model the exponential function with reference to the metadata.

[0081] In an embodiment, the level of the first read voltage VR1 and the level of the second read voltage VR2 may be fixed. For another example, the memory controller 120 may manage a range of at least one of environmental variables such as temperature, humidity, the number of erases of a memory cell, the time elapsed after writing data, the number of read operations performed after writing data, and the levels of the first read voltage VR1 and the second read voltage VR2 corresponding to the range as metadata. The memory controller 120 may determine the levels of the first read voltage VR1 and the second read voltage VR2 with reference to the metadata.

[0082] The number of times the pre-read operation is performed is not limited to "2". The number of times the pre-read operation is performed may be fixed. Instead, the memory controller 120 may manage the range of at least one of the above environment variables and the number of pre-read operations corresponding to the range as metadata, and may determine the number of times the pre-read operation is performed with reference to the metadata.

[0083] In an embodiment, the memory controller 120 may model one exponential function commonly applicable to the erased state “E” and the programmed state “P”, or may model separate exponential functions corresponding to the erased state “E” and the programmed state “P”, respectively.

[0084] Return to reference Figure 1 and Figure 5 In operation S170, the memory controller 120 may determine an offset. For example, the offset may be determined based on brute force. The memory controller 120 may set various offsets, and may calculate the number of strongly correct (SC) bits, weakly correct (WC) bits, weakly errored (WE) bits, and strongly errored (SE) bits for each of the offsets.

[0085] The memory controller 120 may select an offset whose calculated number belongs to a specific range from the offsets. For example, the memory controller 120 may select an offset based on a ratio of the number of strongly correct (SC) bits to the number of strongly correct (SC) bits and weakly correct (WC) bits (e.g., a first ratio) and a ratio of the number of strongly error (SE) bits to the number of weak error (WE) bits and strongly error (SE) bits (e.g., a second ratio).

[0086] For example, as the offset increases, the number of weakly correct (WC) bits and weakly errored (WE) bits may increase, and the difference between the error bits and the correct bits may decrease. As the offset decreases, the difference from the hard decision-based read operation may become smaller. The memory controller 120 may select an offset that can ensure the difference from the hard decision-based read operation while being able to obtain the difference. For example, the memory controller 120 may select an offset with a first ratio close to 90% and a second ratio of approximately 4%.

[0087] For another example, the memory controller 120 may include a machine learning algorithm trained to infer the offset. The memory controller 120 may infer the offset by using the machine learning algorithm. In operation S175, the memory controller 120 may send the second read command CMD_R2, the physical address PBA, the read voltage information IVR, and the second offset OFF2 determined in operation S170 to the nonvolatile memory device 110.

[0088] In an embodiment, the second offset OFF2 may include one offset that may be commonly applied to the erased state “E” and the programmed state “P”, or may include two offsets corresponding to the erased state “E” and the programmed state “P”, respectively. The two offsets may be the same or different.

[0089] In operation S180, as shown in FIG. Figure 4 As described above, the nonvolatile memory device 110 may perform an offset read operation by using the read level indicated by the read voltage information IVR and the second offset OFF2, and may perform an XOR operation on the result of the offset read operation. In operation S185, the nonvolatile memory device 110 may send the result of the XOR operation as the fourth data D4 to the memory controller 120. The operation at S175 may therefore include sending the second offset OFF2, the fourth read command (CMD_R2), and the fourth read voltage information (IVR). The operation at S185 may therefore include receiving the fourth data (D2) based on the fourth read command (CMD_R2 from S175).

[0090] In operation S190, the memory controller 120 may perform a soft decision process for a soft decision (SD). Figure 4 , the memory controller 120 may assign scores to strongly correct (SC) bits, weakly correct (WC) bits, weakly error (WE) bits, and strongly error (SE) bits, respectively, and may perform LDPC decoding.

[0091] In an embodiment, when the soft decision process is successful, the original data may be restored. In operation S195, the memory controller 120 may provide the restored original data as fifth data D5 to the external host device.

[0092] As described above, the memory controller 120 may perform a pre-read operation and may model the threshold voltage distribution of the memory cell. The memory controller 120 may determine an offset based on the modeling result and may perform a soft decision process. Since the offset is determined based on the state of the threshold voltage distribution of the memory cell, the reliability of the soft decision process may be improved.

[0093] In an embodiment, the first read command CMD_R1 may be sent together with the read voltage information (e.g., IVR, IVR1, or IVR2) and may have the same code. The second read command CMD_R2 may be sent together with the read voltage information (e.g., IVR) and an offset (e.g., OFF2) and may have a code different from that of the first read command CMD_R1.

[0094] In an embodiment, in operation S170 of determining the offset, the read level indicated by the read voltage information IVR may also be changed (or modified). For example, the read level indicated by the read voltage information IVR may be changed to a level corresponding to the intersection of the first function F1 and the second function F2. That is, the read level indicated by the read voltage information IVR in operation S115 may be different from the read level indicated by the read voltage information IVR in operation S175.

[0095] As described above, the pre-read operation is used to model the first function F1 and the second function F2. Therefore, the error correction code block 128 can omit the error correction decoding associated with the second data D2 and the third data D3 as a result of the pre-read operation. In an embodiment, Figure 5 The physical address PBA mentioned in may indicate the same memory cell.

[0096] In an embodiment, in the case where at least a portion of the first count and the second count are collected in advance during the execution of an algorithm (e.g., a defense code) for recovering a read error, at least a portion of the operation for collecting the first count and the second count may be omitted. The portion of the operation that may be omitted may correspond to the portion collected in advance. In an embodiment, after successfully recovering the original data in operation S190, the memory controller 120 may perform a read recovery operation to write the recovered data to other memory cells of the nonvolatile memory device 110. Because the data is rewritten by the read recovery operation, the degradation of the data may be recovered.

[0097] As mentioned above, in Figure 5In the context of, S115 may be appropriately characterized as including sending a first read command and a first read voltage information, S135 may be appropriately characterized as including sending a second read command and a second read voltage information, S150 may be appropriately characterized as including sending a third read command and a third read voltage information, and S175 may be appropriately characterized as including sending an offset, a fourth read command, and a fourth read voltage information. S125 may be appropriately characterized as including receiving a first data, S145 may be appropriately characterized as including receiving a second data, S160 may be appropriately characterized as including receiving a third data, and S185 may be appropriately characterized as including receiving a fourth data. The offset sent by S175 is based on the modeling at S165, which is performed based on the second data received at S145 and the third data received at S160. Therefore, the offset sent at S175 is set or adjusted based on the second data received at S145 and the third data received at S160.

[0098] Figure 7 2 shows the threshold voltage distribution of a memory cell when three bits are written to one memory cell. Figure 1 , Figure 5 and Figure 7 Each of the memory cells of the nonvolatile memory device 110 may be intended to be (e.g., programmed to) belong to a threshold voltage range corresponding to the erased state "E" and one of the first to seventh programming states P1 to P7. For the purpose of reading data from the memory cells, 7 read voltages VR may be used between the 8 states.

[0099] When writing n bits to each of the memory cells, each of the memory cells may want to belong to 2 n In a read operation, you can use (2 n -1) read voltage to identify the state of the memory cell.

[0100] Each of the read voltage information IVR, IVR1, and IVR2 in operation S115, operation S135, and operation S150 may include information about (2 n -1) read level information. Alternatively, each of the read voltage information IVR, IVR1, and IVR2 in operation S115, operation S135, and operation S150 may include an indication that each includes (2 n -1) read level set. In each of operations S120 and S140, the information of one of the sets of (2 n -1) read level execution (2 n -1) read operations.

[0101] In operation S165, in the case where different functions are modeled in two overlapping distribution states, “2×(2 n -1)" function. Alternatively, in operation S165, in the case where the same function is modeled in two overlapping distribution states, "2 n -1" function.

[0102] In operation S170, “2×(2 n Alternatively, in operation S170, in the case where the same offset is determined in two overlapping distribution states, “2 n -1” offset.

[0103] The read voltage information IVR in operation S175 may include information about (2 n -1) read level information or indication includes (2 n -1) read level sets. In operation S175, in the case where different offsets are determined in two overlapping distribution states, the second offset OFF2 may include “2×(2 n Alternatively, in operation S175, in the case where the same offset is determined in two overlapping distribution states, the second offset OFF2 may include “2 n -1” offset.

[0104] For another example, in operation S175, in the case where different offsets are determined in two overlapping distribution states, the second offset OFF2 may include an indication that both include “2×(2 n -1)" offsets. Alternatively, in operation S175, in the case where the same offset is determined in two overlapping distribution states, the second offset OFF2 may include both "2 n -1" offset. In operation S180, the nonvolatile memory device 110 may perform "2×(2 n -1)” read operations.

[0105] Figure 8 FIG. 1 shows a soft decision controller 125 according to an embodiment of the present disclosure. Figure 1 , Figure 5 and Figure 8, the soft decision controller 125 may include a counter 210, an exponent calculator 220, an offset determiner 230, and an error correction code (ECC) modifier 240. The counter 210, the exponent calculator 220, the offset determiner 230, and the error correction code (ECC) modifier 240 may each be implemented by a combination of a processor and software executed by the processor, or by a specific circuit such as an application specific integrated circuit (ASIC).

[0106] The counter 210 may count the number of turned-on cells or turned-off cells according to the data (eg, the second data D2 and the third data D3) read by the pre-read operation. The exponential calculator 220 may calculate one or more exponential functions according to the count value of the counter 210.

[0107] For example, the exponential calculator 220 may manage the count value and the exponential function corresponding to the count value as metadata. The exponential calculator 220 may select the exponential function with reference to the metadata. For another example, the exponential calculator 220 may include a machine learning algorithm trained to infer the exponential function from the count value.

[0108] The offset determiner 230 may determine the second offset OFF2 according to an exponential function. For example, the offset determiner 230 may calculate the number of (strongly correct, weakly correct or strongly wrong, weakly wrong) bits corresponding to the offset based on brute force, and may select the offset based on the number of (strongly correct, weakly correct or strongly wrong, weakly wrong) bits.

[0109] For another example, the offset determiner 230 may manage the parameters of the exponential function and the offsets corresponding to the parameters as metadata. The offset determiner 230 may select the offset with reference to the metadata. For example, the exponential function may be in the form of “e ax+b " Here, "x" may correspond to the horizontal axis (ie, the threshold voltage VTH). In the exponential function, the parameters may include "a" and "b".

[0110] For another example, the offset determiner 230 may include a machine learning algorithm trained to infer the second offset OFF2 from the parameters of the exponential function. The offset determiner 230 may determine the second offset OFF2 by using the machine learning algorithm. For another example, the exponent calculator 220 and the offset determiner 230 may be integrated into a machine learning algorithm trained to infer the second offset OFF2 from the count value.

[0111] The offset determiner 230 may transfer strength information SI about the second offset OFF2 to the ECC modifier 240. For example, the strength information SI may include a ratio of the number of strongly correct (SC) bits to the number of strongly correct (SC) bits and weakly correct (WC) bits (e.g., a first ratio), and a ratio of the number of strongly error (SE) bits to the number of weakly error (WE) bits and strongly error (SE) bits (e.g., a second ratio).

[0112] The ECC modifier 240 can modify the internal operating parameters of the error correction code block 128 based on the first ratio and the second ratio. For example, when the number of weak bits (WE and WC bits) is lower than the first reference value, the score assigned to the weak bits can be increased. When the number of weak bits is higher than the second reference value, the score assigned to the weak bits can be reduced.

[0113] In an embodiment, the ECC modifier 240 may be optionally provided. The ECC modifier 240 may be provided in the soft decision controller 125 and may be selectively activated or deactivated. The ECC modifier 240 may not be included in the soft decision controller 125 and may be omitted.

[0114] Fig. 9 is a flowchart showing an operation method of the storage device 100 according to another embodiment of the present disclosure. Figure 1 and Fig. 9 In operation S211, the memory controller 120 may receive a read request including a logical address LBA from an external host device. Operation S211 may be performed with Figure 5 The same as operation S110. Figure 5 The description provided for operation S110 may be equally applied to operation S211.

[0115] In operation S212, the memory controller 120 may send a first read command CMD_R1, a physical address PBA, and read voltage information IVR to the nonvolatile memory device 110. In operation S213, the nonvolatile memory device 110 may perform a read operation. In operation S214, the nonvolatile memory device 110 may send the first data D1 thus read to the memory controller 120. Operations S212 to S214 may be performed in conjunction with the nonvolatile memory device 110. Figure 5 Operations S115 to S125 are the same as those of FIG. Figure 5The description provided for operations S115 to S125 of the present invention may be equally applied to operations S212 to S214. The operation of S212 may thus include sequentially sending a first read command (CMR_R1) and first read voltage information (IVR). The operation of S214 may thus include sequentially receiving first data (D1) based on the first read command (CMR_R1 from S212).

[0116] In operation S215, the memory controller 120 may perform error correction decoding. In an embodiment, the error correction decoding may fail. Operation S215 may be performed with Figure 5 The same as operation S130. Figure 5 The description provided in operation S130 may be equally applicable to Fig. 9 Operation S215.

[0117] As the error correction decoding fails, in operation S216, the memory controller 120 may send a second read command CMD_R2, a physical address PBA, read voltage information IVR, and a first offset OFF1 to the nonvolatile memory device 110. The second read command CMD_R2 may point to a read operation for soft decision processing. The first offset OFF1 may have a fixed value or a default value.

[0118] In operation S217, as shown in FIG. Figure 4 As described above, the nonvolatile memory device 110 may perform an offset read operation by using a first offset read voltage VRO1, and may perform an offset read operation by using a second offset read voltage VRO2. In operation S218, the nonvolatile memory device 110 may send the result of the XOR operation performed on the read result to the memory controller 120 as the sixth data D6. The operation of S216 may therefore include sending a second read command (CMR_R2) and second read voltage information (IVR) in sequence. The operation of S218 may therefore include receiving the second data (D6) in sequence based on the second read command (CMR_R2 from S216).

[0119] In operation S219, the memory controller 120 may perform a soft decision process for a soft decision (SD) based on the first data D1 and the sixth data D6. The memory controller 120 may identify a strongly correct (SC) bit, a weakly correct (WC) bit, a weakly errored (WE) bit, and a strongly errored (SE) bit, and may assign scores to the strongly correct (SC) bit, the weakly correct (WC) bit, the weakly errored (WE) bit, and the strongly errored (SE) bit, respectively. The memory controller 120 may then perform LDPC decoding. For example, the soft decision process for a soft decision (SD) may fail.

[0120] As the soft decision process for the soft decision fails, the memory controller 120 may perform a pre-read operation. In operation S220 , the memory controller 120 may transmit a first read command CMD_R1 , a physical address PBA, and first read voltage information IVR1 to the nonvolatile memory device 110 .

[0121] In operation S221, the nonvolatile memory device 110 may perform a read operation by using a read level indicated by the first read voltage information IVR1. In operation S222, the nonvolatile memory device 110 may send the data read in operation S221 to the memory controller 120 as second data D2. The operation of S220 may therefore include sending a third read command (CMR_R1) and third read voltage information (IVR1) in sequence. The operation at S222 may therefore include receiving the third data (D2) in sequence based on the third read command (CMR_R1 from S220).

[0122] In operation S223, the memory controller 120 may send a first read command CMD_R1, a physical address PBA, and a second read voltage information IVR2 to the nonvolatile memory device 110. In operation S224, the nonvolatile memory device 110 may perform a read operation by using a read level indicated by the second read voltage information IVR2. In operation S225, the nonvolatile memory device 110 may send the data read in operation S224 to the memory controller 120 as third data D3. The operation of S223 may therefore include sending a fourth read command (CMR_R1) and a fourth read voltage information (IVR2) in sequence. The operation of S225 may therefore include receiving fourth data (D3) in sequence based on the fourth read command (CMD_R1 from S223).

[0123] In operation S226, the memory controller 120 may model the exponential function. The memory controller 120 may identify or adjust the offset based on the modeling of the threshold voltage distribution of the memory cell according to the second data D2 and the third data D3, and may send the offset to the nonvolatile memory device 110 in S228, as explained below. In operation S227, the memory controller 120 may decide the offset. In operation S228, the memory controller 120 may send the second read command CMD_R2, the physical address PBA, the read voltage information IVR, and the second offset OFF2 to the nonvolatile memory device 110.

[0124] In operation S229, as shown in FIG. Figure 4, the nonvolatile memory device 110 may perform an offset read operation by using two offset read voltages indicated by the read voltage information IVR and the second offset OFF2, respectively. In operation S230, the nonvolatile memory device 110 may send the data read in operation S229 to the memory controller 120 as fourth data D4. The operation of S228 may therefore include sending a fifth read command (CMR_R2) and fifth read voltage information (IVR) in sequence. The operation of S230 may therefore include receiving fifth data (D4) in sequence based on the fifth read command (CMR_R2 from S228).

[0125] Operations S220 to S230 may be performed with Figure 5 Operations S135 to S185 are the same as those of FIG. Figure 5 The description provided in operations S135 to S185 of the present invention may be equally applied to Fig. 9 Operation S220 to operation S230.

[0126] In operation S231, the memory controller 120 may perform a soft decision process for soft decision (SD). Figure 5 As described in operation S190 of the present invention, the memory controller 120 may identify a strongly correct (SC) bit, a weakly correct (WC) bit, a weakly errored (WE) bit, and a strongly errored (SE) bit based on the first data D1 and the fourth data D4, and may assign scores to the strongly correct (SC) bit, the weakly correct (WC) bit, the weakly errored (WE) bit, and the strongly errored (SE) bit, respectively. Then, the memory controller 120 may perform LDPC decoding.

[0127] For another example, the memory controller 120 may additionally identify bits as six types of correct bits and error bits based on the sixth data D6, and may assign scores to the six types of correct bits and error bits, respectively. The memory controller 120 may then perform LDPC decoding. For example, the soft decision process for soft decision (SD) may succeed. In operation S232, the memory controller 120 may provide the recovered data as the fifth data D5 to the external host device.

[0128] As described above, when the read operation based on hard decision fails, the memory device 100 may perform soft decision processing for soft decision. In the case where the soft decision processing fails, the memory device 100 may perform a refined soft decision processing including a pre-read operation. In an embodiment, unless the context clearly indicates otherwise, reference is made to Figure 5 The description provided can be applied equally to Fig. 9 .

[0129] As mentioned above, Fig. 9can be appropriately characterized as including a sending operation and a receiving operation, and the sending operation and the receiving operation can be characterized as Fig. 9 In the sequence of different markers. For example, Fig. 9 In the context of , S212 may be appropriately characterized as including sending a first read command and first read voltage information, S216 may be appropriately characterized as including sending a first offset, a second read command, and a second read voltage information, S220 may be appropriately characterized as including sending a third read command and a third read voltage information, S223 may be appropriately characterized as including sending a fourth read command and a fourth read voltage information, and S228 may be appropriately characterized as including sending a second offset, a fifth read command, and a fifth read voltage information. S214 may be appropriately characterized as including receiving first data, S218 may be appropriately characterized as including receiving second data, S222 may be appropriately characterized as including receiving third data, S225 may be appropriately characterized as including receiving fourth data, and S230 may be appropriately characterized as including receiving fifth data. The second offset sent at S228 is based on the modeling at S226, which is performed based on the third data received at S222 and the fourth data received at S225. Therefore, based on the third data received at S222 and the fourth data received at S225 , the second offset sent at S228 is set or adjusted according to the first offset sent at S216 .

[0130] Fig.10 is a block diagram showing a nonvolatile memory device 300 according to an embodiment of the present disclosure. Fig.10 , the nonvolatile memory device 300 includes a memory cell array 310 , a row decoder block 320 , a page buffer block 330 , a data input and output block 340 , a buffer block 350 , and a control logic block 360 .

[0131] The memory cell array 310 includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. Each of the memory blocks BLK1 to BLKz may be connected to a row decoder block 320 through at least one ground selection line GSL, a word line WL, and at least one string selection line SSL. Some of the word lines WL may be used as pseudo word lines. Each of the memory blocks BLK1 to BLKz may be connected to a page buffer block 330 through a plurality of bit lines BL. A plurality of memory blocks BLK1 to BLKz may be connected to the plurality of bit lines BL in common.

[0132] In an embodiment, each of the memory blocks BLK1 to BLKz may be a unit of erase operation. Memory cells belonging to each of the memory blocks BLK1 to BLKz may be erased at the same time. For another example, each of the plurality of memory blocks BLK1 to BLKz may be divided into a plurality of sub-blocks. Each of the plurality of sub-blocks may correspond to a unit of erase operation.

[0133] The row decoder block 320 is connected to the memory cell array 310 through the ground selection lines GSL, the word lines WL, and the string selection lines SSL. The row decoder block 320 operates under the control of the control logic block 360.

[0134] The row decoder block 320 may decode the row address RA received from the buffer block 350 , and may control voltages to be applied to the string selection line SSL, the word line WL, and the ground selection line GSL based on the decoded row address.

[0135] The page buffer block 330 is connected to the memory cell array 310 through a plurality of bit lines BL. The page buffer block 330 is connected to the data input and output block 340 through a plurality of data lines DL. The page buffer block 330 operates under the control of the control logic block 360.

[0136] In a write operation, the page buffer block 330 may store data to be written to the memory cell. The page buffer block 330 may apply a voltage to a plurality of bit lines BL based on the stored data. In a read operation or a verification read operation performed in a write operation or an erase operation, the page buffer block 330 may sense the voltage of the bit line BL and may store the sensing result.

[0137] The data input and output block 340 is connected to the page buffer block 330 through a plurality of data lines DL. The data input and output block 340 may receive a column address CA from the buffer block 350. The data input and output block 340 may output data read by the page buffer block 330 to the buffer block 350 based on the column address CA. The data input and output block 340 may provide data received from the buffer block 350 to the page buffer block 330 based on the column address CA.

[0138] The buffer block 350 may receive a command CMD and an address ADDR from an external device through a first channel CH1, and may exchange data “DATA” with the external device through the first channel CH1. The buffer block 350 may operate under the control of the control logic block 360. The buffer block 350 may provide the command CMD to the control logic block 360. The buffer block 350 may provide a row address RA of the address ADDR to the row decoder block 320, and may provide a column address CA of the address ADDR to the data input and output block 340. The buffer block 350 may exchange data “DATA” with the data input and output block 340.

[0139] The control logic block 360 may exchange a control signal CTRL from an external device through the second channel CH2. The control logic block 360 may allow the buffer block 350 to route a command CMD, an address ADDR, and data “DATA”. The control logic block 360 may decode the command CMD received from the buffer block 350, and may control the nonvolatile memory device 300 based on the decoded command.

[0140] In an embodiment, the nonvolatile memory device 300 may further include a calculator for performing an exclusive OR operation on a result of performing a read operation by using the read voltage information and the read voltage indicated by the offset. The calculator may be included in the data input and output block 340, the buffer block 350, or the control logic block 360. For another example, the calculator may be interposed between the page buffer block 330 and the data input and output block 340 or between the data input and output block 340 and the buffer block 350.

[0141] In an embodiment, the nonvolatile memory device 300 may be manufactured in a bonding manner. The memory cell array 310 may be manufactured at a first wafer, and the row decoder block 320, the page buffer block 330, the data input and output block 340, the buffer block 350, and the control logic block 360 may be manufactured at a second wafer. The nonvolatile memory device 300 may be implemented by coupling the first wafer and the second wafer so that the upper surface of the first wafer and the upper surface of the second wafer face each other.

[0142] For another example, the nonvolatile memory device 300 may be manufactured in a cell-on-periphery (COP) manner. A peripheral circuit including a row decoder block 320, a page buffer block 330, a data input and output block 340, a buffer block 350, and a control logic block 360 may be implemented on a substrate. The memory cell array 310 may be implemented on the peripheral circuit. The peripheral circuit and the memory cell array 310 may be connected by using a through-piece.

[0143] Fig.11An example of a memory block BLK1 according to an embodiment of the present disclosure is shown. Fig.11 , a plurality of cell strings CS may be arranged in rows and columns on a substrate SUB along a first direction, a second direction, and a third direction. The plurality of cell strings CS may be commonly connected to a common source line CSL formed on (or in) the substrate SUB. Fig.11 , the position of the substrate SUB is illustrated to help understand the structure of the memory block BLK1.

[0144] The cell strings of the rows may be connected in common to the ground selection line GSL, and the cell strings of each row may be connected to a corresponding one of the first upper string selection line SSLu1 to the fourth upper string selection line SSLu4 and a corresponding one of the first lower string selection line SSL11 to the fourth lower string selection line SSLl4. The cell strings of each column may be connected to a corresponding one of the first bit line BL1 to the fourth bit line BL4. For simple illustration, the cell strings connected to the second string selection lines SSL12 and SSLu2 and the third string selection lines SSLl3 and SSLu3 are depicted as blurred.

[0145] Each cell string may include at least one ground selection transistor GST connected to a ground selection line GSL, a first pseudo memory cell DMC1 connected to a first pseudo word line DWL1, first to tenth memory cells MC1 to MC10 connected to first to tenth word lines WL1 to WL10, respectively, a second pseudo memory cell DMC2 connected to a second pseudo word line DWL2, and a lower string selection transistor SSTl and an upper string selection transistor SSTu connected to corresponding lower string selection lines and upper string selection lines, respectively.

[0146] In each cell string, the ground selection transistor GST, the first pseudo memory cell DMC1, the first memory cell MC1 to the tenth memory cell MC10, the second pseudo memory cell DMC2, the lower string selection transistor SSTl and the upper string selection transistor SSTu can be connected in series along a third direction perpendicular to the substrate SUB, and can be stacked in sequence along the third direction perpendicular to the substrate SUB.

[0147] The memory block BLK1 may be configured as a three-dimensional (3D) memory array. The 3D memory array is integrally formed in one or more physical levels of an array of memory cells MC, the memory cells MC having active regions disposed above a silicon substrate and circuits associated with the operation of those memory cells MC. The circuits associated with the operation of the memory cells MC may be located above or within the substrate. The term "integral" means that the layers of each level of the array are deposited directly on the layers of each underlying level of the 3D memory array.

[0148] In an embodiment of the present disclosure, a 3D memory array includes a vertical cell string CS (or NAND string) oriented vertically, such that at least one memory cell is located above another memory cell. At least one memory cell may include a charge trapping layer. Each cell string may also include at least one selection transistor disposed above a memory cell MC. At least one selection transistor may have the same structure as the memory cell MC and may be formed in unison with the memory cell MC.

[0149] The following patent documents, incorporated herein by reference, describe suitable configurations for a three-dimensional memory array, wherein the three-dimensional memory array is configured as multiple levels with word lines and / or bit lines shared between levels: U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0150] In the above description, components according to various embodiments of the present disclosure are described by using the terms "first", "second", "third", etc. However, the terms "first", "second", "third", etc. may be used to distinguish components from each other and do not limit the inventive concepts described herein. For example, the terms "first", "second", "third", etc. do not necessarily refer to any form of order or numerical meaning unless otherwise clearly specified in the context in which the terms are used.

[0151] In the above embodiments, the components according to the embodiments of the present disclosure are described by using blocks. The blocks can be implemented by various hardware devices (such as integrated circuits, application specific ICs (ASICs), field programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs)), firmware driven in the hardware devices, software such as applications, or a combination of hardware devices and software. In addition, the blocks may include circuits implemented by semiconductor elements in integrated circuits or circuits registered as intellectual property (IP).

[0152] According to the inventive concept described herein, an offset is determined based on the distribution of threshold voltages of memory cells and a soft decision process is performed. Therefore, a memory device has improved reliability and an operating method of the memory device is provided to include performance of a read operation adapted to the state of the memory cell.

[0153] While the inventive concept of the present disclosure has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A storage device, comprising: A non-volatile memory device comprising a plurality of memory cells; as well as a memory controller configured to: send a first read command and first read voltage information associated with the plurality of memory cells to the nonvolatile memory device, receive first data from the nonvolatile memory device based on the first read command, and perform error correction on the first data, Wherein, when the error correction fails, the memory controller is further configured to: send a second read command and a second read voltage information associated with the plurality of memory cells to the nonvolatile memory device, receive second data from the nonvolatile memory device based on the second read command, send a third read command and a third read voltage information associated with the plurality of memory cells to the nonvolatile memory device, and receive third data from the nonvolatile memory device based on the third read command, and The memory controller is further configured to: adjust the offset based on the second data and the third data, send the offset, a fourth read command associated with the plurality of memory cells, and fourth read voltage information to the non-volatile memory device, receive fourth data from the non-volatile memory device based on the fourth read command, and perform soft decision processing based on the fourth data.

2. The storage device according to claim 1, wherein: The first read command, the second read command, and the third read command include the same code.

3. The storage device according to claim 1, wherein: The code of the fourth read command is different from the codes of the first read command, the second read command, and the third read command.

4. The storage device according to claim 1, wherein: In response to receiving one of the first read command, the second read command, and the third read command, the nonvolatile memory device is configured to perform a read operation on the plurality of memory cells by using a read level indicated by read voltage information corresponding to the received one of the first read voltage information, the second read voltage information, and the third read voltage information.

5. The storage device according to claim 1, wherein: Each of the first read voltage information, the second read voltage information, and the third read voltage information includes information about two or more read levels.

6. The storage device according to claim 1, wherein: In response to the fourth read command, the nonvolatile memory device is configured to perform a read operation by using a first read level and a second read level, wherein the first read level is obtained by subtracting the offset from the read level indicated by the fourth read voltage information, and the second read level is obtained by adding the offset from the read level indicated by the fourth read voltage information.

7. The storage device according to claim 6, wherein: In response to the fourth read command, the nonvolatile memory device is also configured to perform an XOR operation on a result of performing a read operation using the first read level and a result of performing a read operation using the second read level, and provide the result of the XOR operation to the memory controller as the fourth data.

8. The storage device according to claim 1, wherein: The memory controller calculates an equation for at least a portion of the threshold voltage distribution of the plurality of memory cells based on the second data and the third data to calculate a first number of strong error bits, a second number of weak error bits, a third number of strong correct bits, and a fourth number of weak correct bits based on the equation, and adjusts the offset based on the first number, the second number, the third number, and the fourth number.

9. The storage device according to claim 8, wherein: The memory controller adjusts the offset so that a ratio of a sum of the second number and the fourth number to a sum of the first number, the second number, the third number, and the fourth number falls within a target range.

10. The storage device according to claim 1, wherein: The memory controller is further configured to adjust the offset by using the second data and the third data based on machine learning.

11. The storage device according to claim 1, wherein: After the soft decision process is successful, the memory controller is further configured to write the data read and recovered from the plurality of memory cells to a plurality of other memory cells.

12. The storage device according to claim 1, wherein: The memory controller is also configured to omit error correction associated with the second data and the third data.

13. The storage device according to claim 1, wherein: The memory controller is also configured to omit error correction associated with the fourth data.

14. The storage device according to claim 1, wherein: The memory controller is also configured to modify parameters to be used in the soft decision processing based on a first number of strongly erroneous bits predicted at the offset, a second number of weakly erroneous bits predicted at the offset, a third number of strongly correct bits predicted at the offset, and a fourth number of weakly correct bits predicted at the offset.

15. The storage device according to claim 14, wherein: The soft decision processing is performed by low density parity check decoding, and The memory controller is further configured to adjust scores assigned to the strong error bits, the weak error bits, the strong correct bits, and the weak correct bits based on the first number, the second number, the third number, and the fourth number.

16. A storage device, comprising: A non-volatile memory device comprising a plurality of memory cells; as well as a memory controller configured to: send a first read command and first read voltage information associated with the plurality of memory cells to the nonvolatile memory device, receive first data from the nonvolatile memory device based on the first read command, and perform error correction on the first data, Wherein, when the error correction fails, the memory controller is further configured to: send a first offset, a second read command associated with the plurality of memory cells, and second read voltage information to the non-volatile memory device, receive second data from the non-volatile memory device based on the second read command, and perform a first soft decision process based on the second data, Wherein, when the first soft decision processing fails, the memory controller is further configured to: send a third read command and third read voltage information associated with the plurality of memory cells to the non-volatile memory device, receive third data from the non-volatile memory device based on the third read command, send a fourth read command and fourth read voltage information associated with the plurality of memory cells to the non-volatile memory device, and receive fourth data from the non-volatile memory device based on the fourth read command, and The memory controller is further configured to: adjust the first offset to a second offset based on the third data and the fourth data, send the second offset, a fifth read command associated with the plurality of memory cells, and fifth read voltage information to the non-volatile memory device, receive fifth data from the non-volatile memory device based on the fifth read command, and perform a second soft decision process based on the fifth data.

17. The storage device according to claim 16, wherein: A first read level indicated by one of the second read voltage information and the third read voltage information is lower than a read level indicated by the first read voltage information, and a second read level indicated by the other of the second read voltage information and the third read voltage is higher than a read level indicated by the first read voltage information.

18. The storage device according to claim 16, wherein: The nonvolatile memory device includes a plurality of memory blocks, each of the plurality of memory blocks including memory cells stacked on a substrate in a direction perpendicular to the substrate, wherein the memory cells placed at the same height from the substrate are connected to a plurality of sub-word lines, and The plurality of memory cells are connected to a sub-word line.

19. The storage device according to claim 16, wherein: The second offset includes two offsets corresponding to one read level indicated by the fifth read voltage information.

20. A method for operating a storage device, the storage device comprising a non-volatile memory device and a controller for controlling the non-volatile memory device, the method comprising the steps of: at the controller, reading first data and second data from the nonvolatile memory device by using a first read voltage and a second read voltage, respectively; At the controller, adjusting an offset based on the first data and the second data; reading, at the controller, third data from the nonvolatile memory device by using a third read voltage and the adjusted offset; as well as At the controller, soft decision processing is performed based on the third data.

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