Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising a substrate, a magnetic tunnel junction stacked structure located on the substrate, and a first cap material layer located on the magnetic tunnel junction stacked structure; performing a first etching process on the first cap material layer to form a cap layer; forming a first sidewall layer on the sidewall of the cap layer; performing a second etching process on the magnetic tunnel junction stacked structure exposed by the cap layer and the first sidewall layer to form a magnetic tunnel junction unit. In an embodiment of the present invention, during the second etching process, the first sidewall layer can prevent the second etching process from causing damage to the sidewall of the cap layer; usually, during the first etching process, a second electrode layer is also formed on the cap layer, and when the semiconductor structure is working, the cap layer can protect the free magnetic layer in the magnetic tunnel junction unit from being easily affected by the carriers in the second electrode layer, so that the electron spin direction of the free magnetic layer is stable, and the magnetic tunnel junction unit has good performance.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Magnetic Random Access Memory (MRAM) is a non-volatile magnetic random access memory. "Non-volatility" means that the memory remains intact even after the power is turned off. MRAM devices combine the high-speed read and write capabilities of static random access memory (SRAM) with the high integration density of dynamic random access memory (DRAM). Furthermore, they can be rewritten virtually unlimited times, making MRAM a "full-energy" solid-state memory. Therefore, its application prospects are very promising and it is expected to dominate the next-generation memory market.

[0003] MRAM is a memory device that includes an array of MRAM cells, each of which uses resistance rather than charge to store data bits. Each MRAM cell includes a magnetic tunnel junction (MTJ) cell, the resistance of which can be adjusted to represent logic "0" or logic "1". The MTJ cell includes a fixed magnetic layer, a tunnel barrier layer, and a magnetic free layer. The resistance of the MTJ cell can be adjusted by changing the direction of the magnetic moment of the magnetic free layer relative to the fixed magnetic layer. In particular, when the magnetic moment of the magnetic free layer is parallel to the magnetic moment of the fixed magnetic layer, the resistance of the MTJ cell is low, corresponding to logic 0, and conversely, when the magnetic moment of the magnetic free layer is not parallel to the magnetic moment of the fixed magnetic layer, the resistance of the MTJ cell is high, corresponding to logic 1. The MTJ cell is connected between top and bottom electrodes, and the current flowing through the MTJ cell from one electrode to the other can be detected to determine the resistance and, therefore, the logic state.

[0004] The tunnel magnetoresistance (TMR) effect in magnetic tunnel junctions (MTJs) is key to the development of magnetoresistive random access memory (MRAM), magnetic sensors, and novel programmable logic devices. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor and a method for forming the same, so as to improve the magnetoresistance ratio of a magnetic tunnel junction unit in a semiconductor structure, thereby improving the electrical performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a base, the base comprising a substrate, a magnetic tunnel junction stack structure located on the substrate, and a first cap material layer located on the magnetic tunnel junction stack structure; performing a first etching process on the first cap material layer to form a cap layer; forming a first sidewall layer on the sidewall of the cap layer; performing a second etching process on the magnetic tunnel junction stack structure exposed by the cap layer and the first sidewall layer to form a magnetic tunnel junction unit.

[0007] Optionally, in the step of providing a substrate, a first electrode material layer is formed between the substrate and the magnetic tunnel junction stack structure; the method for forming the semiconductor structure also includes: after forming the magnetic tunnel junction unit, etching the first electrode material layer using an anisotropic physical etching process to form a first electrode layer.

[0008] Optionally, the anisotropic physical etching process includes an ion beam etching process.

[0009] Optionally, in the step of providing a substrate, a first electrode material layer is formed between the substrate and the magnetic tunnel junction stack structure; an etch stop material layer is formed on the first cap material layer; a second electrode material layer is formed on the etch stop material layer; the step of the first etching treatment includes: taking the top of the etch stop material layer as the etching stop position, etching the second electrode material layer to form a second electrode layer; after forming the second electrode layer, taking the top of the first cap material layer as the etching stop position, etching the etch stop material layer to form an etch stop layer; taking the top of the magnetic tunnel junction stack structure as the etching stop position, etching the first cap material layer to form the cap layer; the step of the second etching treatment includes: in the process of etching the magnetic tunnel junction stack structure, taking the top of the first electrode material layer as the etching stop position.

[0010] Optionally, the thickness of the first sidewall layer is to

[0011] Optionally, the material of the first spacer layer includes silicon oxide and silicon oxynitride.

[0012] Optionally, the step of forming the first side wall layer includes: forming a first side wall material layer that conformally covers the cap layer and the magnetic tunnel junction stack structure between the cap layers; removing the first side wall material layer on the magnetic tunnel junction stack structure and directly above the cap layer, and the remaining first side wall material layer located on the side wall of the cap layer serves as the first side wall layer.

[0013] Optionally, the first sidewall material layer is formed by atomic layer deposition or chemical vapor deposition.

[0014] Optionally, the first etching process adopts an anisotropic reactive ion etching process.

[0015] Optionally, the process parameters of the first etching treatment include: the reaction gas includes carbon fluorine gas or chlorine gas, the flow rate of the reaction gas is 10 sccm to 200 sccm, and the chamber pressure is 3 mTorr to 50 mTorr.

[0016] Optionally, the second etching process adopts an anisotropic reactive ion etching process.

[0017] Optionally, the process parameters of the ion beam etching process include: etching ions include one or more of Ar, Kr, He and Xe, the angle between the ion beam etching direction and the normal of the substrate surface is less than 30°, and the bias voltage is 200V to 1000V.

[0018] Optionally, in the step of the first etching treatment, after forming the second electrode layer, before etching the etching stop material layer, a second sidewall layer is formed on the side wall of the second electrode layer; in the process of forming the cap layer, the first cap material layer exposed by the second electrode layer and the second sidewall layer is etched to form the cap layer.

[0019] Optionally, the material of the second spacer layer includes one or more of Ta, Cu, Au, TaN, TiN, Co and Pt.

[0020] Optionally, the thickness of the second sidewall layer is to

[0021] Optionally, the method for forming the semiconductor structure further includes: after forming the first electrode layer; forming a second capping material layer on the sidewalls and top surfaces of the capping layer and the magnetic tunnel junction unit.

[0022] Accordingly, an embodiment of the present invention further provides a semiconductor structure, comprising: a substrate; a plurality of discrete magnetic tunnel junction units located on the substrate; a cap layer located on the magnetic tunnel junction units; and a first sidewall layer located on the sidewall of the cap layer.

[0023] Optionally, the second electrode layer is located on the cap layer; and the first sidewall layer is also located on the sidewall of the second electrode layer.

[0024] Optionally, the thickness of the first sidewall layer is to

[0025] Optionally, the material of the first spacer layer includes silicon oxide and silicon oxynitride.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0027] In the method for forming a semiconductor structure provided by an embodiment of the present invention, during the second etching process of the magnetic tunnel junction stack structure exposed by the cap layer and the first sidewall layer, the first sidewall layer can prevent the second etching process from causing damage to the sidewalls of the cap layer; usually during the first etching process, a second electrode layer is formed on the cap layer, so that when the semiconductor structure is working, the cap layer can better protect the free magnetic layer in the magnetic tunnel junction unit from being easily affected by the carriers in the second electrode layer, so that the electron spin direction in the free magnetic layer is stable. In addition, during the etching process of the magnetic tunnel junction stack structure, polymer impurities with metal ions are usually formed. The first sidewall layer can prevent the polymer impurities with metal ions from being directly formed on the sidewalls of the cap layer, so that the polymer impurities with metal ions are not easy to conduct the magnetic tunnel junction unit with the outside, which is beneficial to improving the magnetoresistance ratio of the magnetic tunnel junction unit. In summary, the first sidewall layer can make the magnetic tunnel junction unit have good performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 and Figure 2 A schematic structural diagram corresponding to each step in a method for forming a semiconductor structure is shown;

[0029] Figures 3 to 10 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0030] The semiconductor structures currently formed still have the problem of poor performance. The reasons for the poor performance of semiconductor structures are now analyzed based on the structural diagram of a semiconductor structure.

[0031] Figure 1 and Figure 2 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0032] like Figure 1 As shown, a substrate is provided, which includes a dielectric layer 10 (not shown in the figure), a first electrode material layer 11 located on the dielectric layer 10, a magnetic tunnel junction stacked structure 12 located on the first electrode material layer 11, a cap material layer 13 located on the magnetic tunnel junction stacked structure 12, a second electrode material layer 14 located on the cap material layer 13, and a mask layer 15 located on the second electrode material layer 14, and the dielectric layer 10 has an interconnection structure 16.

[0033] like Figure 2As shown, the mask layer 15 (as Figure 1 As shown in the figure, the second electrode material layer 14 is etched using a mask to form a second electrode layer 17; the cap material layer 13 is etched to form a cap layer 18; the magnetic tunnel junction stacked structure 12 is etched to form a magnetic tunnel junction unit 19; and the first electrode material layer 11 is etched to form a first electrode layer 20.

[0034] Usually, the mask layer 15 is used as a mask and a reactive ion etching (RIE) process is adopted to perform the etching. After the second electrode layer 17 and the cap layer 18 are etched to form the magnetic tunnel junction unit 19 and the first electrode layer 20, the side wall of the cap layer 18 is easily damaged. When the semiconductor structure is working, the cap layer 18 cannot effectively avoid the free magnetic layer (Free layer) in the magnetic tunnel junction unit 19, and is affected by the carriers in the second electrode layer 17, which easily causes the electron spin direction in the free magnetic layer to change.

[0035] In addition, during the etching process of the second electrode material layer 14 and the tunnel junction stacked structure 12, unstable polymer impurities with metal ions are likely to exist on the side walls of the second electrode material layer 14 and the tunnel junction stacked structure 12. The polymer impurities with metal ions are deposited (re-deposition) on the side walls of the cap layer 18, which can easily connect the second electrode layer 17 and the magnetic tunnel junction unit 19. The polymer impurities with metal ions are deposited on the side walls of the tunneling barrier layer (tunneling layer) in the magnetic tunnel junction unit 19, which can easily connect the free magnetic layer (Free layer) and the fixed magnetic layer (Pinning layer) in the magnetic tunnel junction unit 19, resulting in poor electrical performance of the magnetic random access memory (MRAM).

[0036] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a dielectric layer, a magnetic tunnel junction stack structure located on the dielectric layer, and a first cap material layer located on the magnetic tunnel junction stack structure; performing a first etching process on the first cap material layer to form a cap layer; forming a first sidewall layer on the sidewall of the cap layer; and performing a second etching process on the magnetic tunnel junction stack structure exposed by the cap layer and the first sidewall layer to form a magnetic tunnel junction unit.

[0037] In the method for forming a semiconductor structure provided by an embodiment of the present invention, during the second etching process of the magnetic tunnel junction stacked structure exposed by the cap layer and the first sidewall layer, the first sidewall layer can prevent the second etching process from causing damage to the sidewalls of the cap layer; usually during the first etching process, a second electrode layer is formed on the cap layer, so that when the semiconductor structure is working, the cap layer can better protect the free magnetic layer in the magnetic tunnel junction unit from being easily affected by the carriers in the second electrode layer, so that the electron spin direction in the free magnetic layer is stable. In addition, during the etching process of the magnetic tunnel junction stacked structure, polymer impurities with metal ions are usually formed. The first sidewall layer can prevent the polymer impurities with metal ions from being directly formed on the sidewalls of the cap layer, so that the polymer impurities with metal ions are not easy to conduct the magnetic tunnel junction unit with the outside, which is beneficial to improving the magnetoresistance ratio of the magnetic tunnel junction unit. In summary, the first sidewall layer can make the magnetic tunnel junction unit have good performance.

[0038] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 3 to 10 It is a structural schematic diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0040] refer to Figure 3 , providing a substrate, the substrate including a substrate 100, a magnetic tunnel junction stacked structure 101 located on the substrate 100, and a first cap material layer 102 located on the magnetic tunnel junction stacked structure 101.

[0041] The substrate includes a device area I (cell area) and a logic area II (logic area). The device area I provides a process platform for the subsequent formation of a magnetic tunnel junction (MTJ) unit, and the logic area II is used to isolate adjacent device areas.

[0042] Specifically, in this embodiment, the substrate 100 includes a dielectric layer.

[0043] In this embodiment, functional structures such as transistors, resistor structures, and conductive structures may be formed at the bottom of the dielectric layer. The transistors may be one or both of NMOS and PMOS transistors. Specifically, the transistors include a gate structure, source and drain doped regions located on both sides of the gate structure, and other functional structures.

[0044] The dielectric layer is used to achieve electrical isolation between the device at the bottom of the dielectric layer and the subsequently formed magnetic tunnel junction unit.

[0045] In this embodiment, the dielectric layer is made of a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), which helps reduce parasitic capacitance between back-end interconnect structures, thereby helping to reduce back-end RC delay. In other embodiments, depending on the actual process, the dielectric layer can also be an inter-metal dielectric (IMD) layer.

[0046] It should be noted that a conductive structure 103 is formed in the dielectric layer.

[0047] The bottom end of the conductive structure 103 is connected to the source and drain doped regions in the transistor at the bottom of the dielectric layer, and the top end of the conductive structure 103 is used for electrical connection to a magnetic tunnel junction unit formed subsequently.

[0048] In this embodiment, the conductive structure 103 is made of copper. In other embodiments, the conductive structure 103 may be made of other conductive materials such as cobalt and tungsten.

[0049] The magnetic tunnel junction stack structure 101 includes a fixed magnetic material layer 1011 , a tunneling barrier material layer 1012 located on the fixed magnetic material layer 1011 , and a magnetic free material layer 1013 located on the tunneling barrier material layer 1012 .

[0050] The magnetic tunnel junction stack structure 101 is prepared for subsequent patterning to form a magnetic tunnel junction unit.

[0051] The fixed magnetic material layer 1011 has a fixed magnetic direction.

[0052] Specifically, the material of the fixed magnetic material layer 1011 includes one or more of FeCoB, CoFeTa, NiFe, and FePt. In this embodiment, the material of the fixed magnetic material layer 1011 includes FeCoB.

[0053] The tunneling barrier material layer 1012 is used to electrically isolate the fixed magnetic material layer 1011 from the magnetically free material layer 1013 , while allowing electrons to tunnel through the tunneling barrier material layer 1012 under appropriate conditions.

[0054] Specifically, the material of the tunneling barrier material layer 1012 includes MgO, AlO, AlN or AlON. In this embodiment, the material of the tunneling barrier material layer 1012 includes MgO.

[0055] The magnetic free material layer 1013 has a free magnetic orientation. In the subsequent process of patterning the magnetic tunnel junction stack structure 101 to form a magnetic tunnel junction unit, the magnetic free material layer 1013 is patterned to form a magnetic free layer. When the magnetic tunnel junction unit is working, the spin transfer torque (STT) effect is usually used to change or switch the magnetization direction of the magnetic free layer.

[0056] Specifically, the material of the magnetic free material layer 1013 includes one or more of FeCoB, CoFeTa, NiFe, and FePt. In this embodiment, the material of the magnetic free material layer 1013 includes FeCoB.

[0057] The first capping material layer 102 is prepared for the subsequent formation of a capping layer.

[0058] Specifically, the material of the first capping material layer 102 includes MgO, AlO, AlN or AlON. In this embodiment, the material of the first capping material layer 102 includes MgO.

[0059] In the step of providing the substrate, an etch stop material layer 105 is formed on the first cap material layer 102 , and a second electrode material layer 106 is formed on the etch stop material layer 105 .

[0060] The second electrode material layer 106 is prepared for the subsequent formation of the top electrode (TE).

[0061] In this embodiment, the material of the second electrode material layer 106 includes one or more of tantalum nitride (TaN), tantalum (Ta), titanium (Ti), and titanium nitride (TiN). In this embodiment, the second electrode material layer 106 has a single-layer structure, and the material of the second electrode material layer 106 is tantalum.

[0062] In the subsequent process of etching the second electrode material layer 106 to form the second electrode layer, the top of the etch stop material layer 105 serves as an etching stop.

[0063] Specifically, the material of the etch-stop material layer 105 includes one or more of silicon oxide, silicon nitride, titanium nitride, and tantalum nitride. In this embodiment, the material of the etch-stop material layer 105 includes silicon oxide. Silicon oxide is a commonly used, low-cost dielectric material with high process compatibility, which helps reduce the process difficulty and cost of forming the etch-stop material layer 105.

[0064] In the step of providing a base, a first electrode material layer 104 is formed between the substrate 100 and the magnetic tunnel junction stacked structure 101 .

[0065] The first electrode material layer 104 is prepared for the subsequent formation of a bottom electrode (BE).

[0066] In this embodiment, the material of the first electrode material layer 104 is one or more of tantalum nitride (TaN), tantalum (Ta), titanium (Ti), and titanium nitride (TiN). In this embodiment, the first electrode material layer 104 is a single-layer structure, and the material of the first electrode material layer 104 is tantalum.

[0067] It should also be noted that, in the step of providing the substrate, a mask layer 107 is formed on the second electrode material layer 106 , and the mask layer 107 serves as an etching mask for subsequently etching the first cap material layer 102 .

[0068] In this embodiment, the material of the mask layer 107 includes silicon nitride. In other embodiments, the material of the mask layer may also include silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron nitride carbon.

[0069] refer to Figures 4 to 6 , the first capping material layer 102 is subjected to a first etching process to form a capping layer 108 (eg Figure 6 shown).

[0070] In subsequent processes, the fixed magnetic material layer 1011 is etched to form the fixed magnetic layer; the tunneling barrier material layer 1012 is etched to form a tunneling barrier layer; and the magnetically free material layer 1013 is etched to form a magnetically free layer. The fixed magnetic layer, tunneling barrier layer, and magnetically free layer serve as a magnetic tunnel junction unit. When the semiconductor structure is operating, the cap layer 108 can prevent the spin of electrons in the subsequently formed magnetically free layer from being affected by carriers in the film structure above the cap layer 108 and from being altered. Furthermore, the magnetic field and electric field can be contained between the magnetically free layer and the fixed magnetic layer.

[0071] Specifically, the material of the capping layer 108 includes MgO, AlO, AlN or AlON. In this embodiment, the material of the capping layer 108 includes MgO.

[0072] In this embodiment, the first etching process is a dry etching process, which has anisotropic etching characteristics and good etching profile control, and is conducive to making the morphology of the capping layer 108 meet process requirements.

[0073] Specifically, the dry etching process includes an anisotropic reactive ion etching (RIE) process. During the anisotropic RIE process, a large number of chemically active gas ions are generated in the plasma produced by gas discharge. These ions interact with the material surface, causing surface atoms to undergo chemical reactions, resulting in an etching effect. The RIE process is beneficial in reducing damage to the magnetic tunnel junction stack structure 101 during the etching of the first cap material layer 102.

[0074] It should be noted that, in the step of forming the capping layer 108 , the mask layer 107 is used as a mask and the top of the magnetic tunnel junction stacked structure 101 is used as an etching stop position to etch the first capping material layer 102 to form the capping layer 108 .

[0075] The material of the first capping material layer 102 is different from that of the magnetic free material layer 1013. During the etching process of the first capping material layer 102, by selecting a suitable reaction gas, the etching rate of the first capping material layer 102 can be made greater than the etching rate of the first capping material layer 102. In other words, the etching stop position is the top of the magnetic tunnel junction stack structure 101. Using the top of the magnetic tunnel junction stack structure 101 as the etching stop position can avoid the problem of over-etching or under-etching caused by inconsistent etching rates in different regions, which helps to reduce the loading effect of etching the logic area II and the device area I.

[0076] Specifically, during the process of etching the first capping material layer 102 using an anisotropic reactive ion etching process, the reaction gas includes carbon fluorine gas or chlorine gas.

[0077] It should be noted that, in the process of etching the first cap material layer 102 using an anisotropic reactive ion etching process, the chamber pressure should not be too large or too small. If the chamber pressure is too large, the decomposition rate of the byproducts generated by etching the first cap material layer 102 will be too slow. Correspondingly, the rate at which the byproducts are discharged from the chamber will be too slow. In addition, if the chamber pressure is too large, it will also easily lead to the flow of the reaction gas being non-anisotropic, causing lateral etching of the side wall of the cap layer 108. When the semiconductor structure is working, the cap layer 108 cannot effectively prevent the free magnetic layer from being affected by the carriers in the second electrode layer, resulting in unstable electron spin in the free magnetic layer. If the chamber pressure is too small, the density of the plasma of the reaction gas in the chamber is low, which is not conducive to increasing the formation rate of the cap layer 108. In this embodiment, the chamber pressure is 3mTorr to 50mTorr.

[0078] It should be noted that during the etching of the first cap material layer 102 using an anisotropic reactive ion etching process, the flow rate of the reaction gas should not be too large or too small. If the flow rate of the reaction gas is too large, the process controllability and reaction rate uniformity of the etching process are easily reduced, and the sidewalls of the cap layer 108 formed are severely damaged. When the semiconductor structure is operating, the cap layer 108 cannot effectively prevent the free magnetic layer from being affected by the carriers in the second electrode layer, resulting in unstable electron spin in the free magnetic layer and easily leading to a loading effect in the logic area II and the device area I. If the flow rate of the reaction gas is too small, the flow direction of the reaction gas is not anisotropic, which can easily cause lateral etching of the sidewalls of the cap layer 108. When the semiconductor structure is operating, the cap layer 108 cannot effectively prevent the free magnetic layer from being affected by the carriers in the second electrode layer, resulting in unstable electron spin in the free magnetic layer. In this embodiment, the flow rate of the reaction gas is 10 sccm to 200 sccm.

[0079] In this embodiment, during the process of etching the first capping material layer 102 to form the capping layer 108 , a partial thickness of the magnetic free material layer 1013 is etched in order to completely etch through the first capping material layer 102 in each region.

[0080] It should be noted that, during the first etching process, the etch stop material layer 105 is also etched to form the etch stop layer 110 .

[0081] It should be noted that, during the etching process of the etch stop material layer 105 , the mask layer 107 is used as a mask and the top of the first cap material layer 102 is used as an etching stop position to etch the etch stop material layer 105 to form an etch stop layer 110 .

[0082] The material of the etch stop material layer 105 is different from that of the first cap material layer 102. By selecting a suitable reaction gas, the etching rate of the etch stop material layer 105 can be greater than the etching rate of the first cap material layer 102, so that the top of the first cap material layer 102 has a good etching stop effect, which can avoid the problem of excessive or insufficient etching caused by inconsistent etching rates in different regions, and is beneficial to reducing the load effect of etching in the logic area II and the device area I.

[0083] It should be noted that, in this embodiment, the mask layer 107 is removed by etching the first capping material layer 102 to form the capping layer 108. In other embodiments, after the capping layer is formed, the mask layer may not be completely removed by etching.

[0084] It should be noted that if Figure 4As shown, the first etching step further includes: before forming the cap layer 108 , etching the second electrode material layer 106 using the mask layer 107 as a mask to form a second electrode layer 109 .

[0085] The second electrode layer 109 serves as a top electrode (TE), and is used to electrically connect a subsequently formed magnetic tunnel junction unit with a metal layer subsequently formed on the magnetic tunnel junction unit.

[0086] In this embodiment, the second electrode material layer 106 is etched using the mask layer 107 as a mask using a dry etching process to form the second electrode layer 109. The dry etching process has anisotropic etching characteristics and good controllability of the etching profile, which helps ensure that the morphology of the second electrode layer 109 meets process requirements.

[0087] Specifically, the dry etching process includes an anisotropic reactive ion etching process.

[0088] It should be noted that, during the process of etching the second electrode material layer 106 , the top of the etch stop material layer 105 is used as the etching stop position, and the second electrode material layer 106 is etched to form the second electrode layer 109 .

[0089] The material of the second electrode material layer 106 is different from the material of the etching stop material layer 105. By selecting a suitable reaction gas, the etching rate of the second electrode material layer 106 can be greater than the etching rate of the etching stop material layer 105. That is to say, the top of the etching stop material layer 105 is used as the etching stop position, which can avoid the problem of excessive or insufficient etching caused by inconsistent etching rates in different regions, and is beneficial to reducing the load effect of etching of the logic area II and the device area I.

[0090] like Figure 5 As shown, it should be noted that, in the step of the first etching process, after forming the second electrode layer 109 and before etching the etch stop material layer 105 , a second spacer layer 110 is formed on the sidewall of the second electrode layer 109 .

[0091] Accordingly, during the process of forming the capping layer, the first capping material layer 102 exposed by the second electrode layer 109 and the second spacer layer 110 is etched to form the capping layer. The second spacer layer 110 can increase the lateral size of the formed capping layer.

[0092] Specifically, the material of the second spacer 110 includes one or more of Ta, Cu, Au, TaN, TiN, Co, and Pt. In this embodiment, the material of the second spacer 110 includes Ta. The material of the second spacer 110 is the same as that of the second electrode layer 109, which can ensure good adhesion between the second spacer 110 and the second electrode layer 109. When the semiconductor structure is operating, the second spacer 110 can also reduce the on-resistance of the semiconductor structure, which is beneficial to reducing the power consumption of the semiconductor structure. In other embodiments, the second spacer can also be made of other conductive materials.

[0093] The steps of forming the second sidewall layer 110 include: forming a second sidewall material layer (not shown in the figure) that conformally covers the second electrode layer 109 and the etch stop material layer 105 between the second electrode layer 109, removing the second sidewall material layer on the etch stop material layer 105 and directly above the second electrode layer 109, and the remaining second sidewall material layer located on the side wall of the second electrode layer 109 serves as the second sidewall layer 110.

[0094] In this embodiment, the second spacer material layer is formed using an atomic layer deposition (ALD) process. The ALD process involves multiple ALD cycles, which helps improve the thickness uniformity of the second spacer material layer, allowing the second spacer material layer to conformally cover the second electrode layer 109 and the etch-stop material layer 105 between the second electrode layer 109. Furthermore, the ALD process offers excellent gap-filling performance and step coverage. In other embodiments, the second spacer material layer can also be formed using a chemical vapor deposition process.

[0095] It should be noted that the second sidewall layer 110 should not be too thick or too thin. In the process of etching the first cap material layer 102 to form the cap layer, polymer impurities (polymer) will be generated. If the second sidewall layer 110 is too thick, the spacing between the adjacent second electrode layers 109 in the corresponding device area I is small, and the polymer impurities are not easy to be removed in time, which may easily lead to the risk of etching stopping in the subsequent etching process. Even if the cap layer can be formed, the angle between the sidewall of the cap layer and the normal of the surface of the substrate 100 is too large, resulting in poor formation quality of the magnetic tunnel junction unit formed subsequently. If the second sidewall layer 110 is too thin, during the etching process, the second sidewall layer 110 is not easy to significantly increase the lateral size of the formed cap layer. In this embodiment, the thickness of the second sidewall layer 110 is to

[0096] refer to Figure 7 , forming a first spacer layer 111 on the sidewall of the cap layer 108 .

[0097] During the subsequent second etching process of the magnetic tunnel junction stack structure 101 exposed by the cap layer 108 and the first sidewall layer 111, the first sidewall layer 111 can prevent the second etching process from causing damage to the sidewalls of the cap layer 108; thus, when the semiconductor structure is working, the cap layer 108 can better protect the free magnetic layer in the magnetic tunnel junction unit from being easily affected by the carriers in the second electrode layer 109, so that the electron spin direction in the free magnetic layer is stable. In addition, in the process of etching the magnetic tunnel junction stack structure 101, polymer impurities with metal ions are usually formed. The first sidewall layer 111 can prevent the polymer impurities with metal ions from being directly formed on the sidewalls of the cap layer 108, so that the polymer impurities with metal ions are not easy to conduct the magnetic tunnel junction unit with the outside, which is beneficial to improving the magnetoresistance ratio of the magnetic tunnel junction unit. In summary, the first sidewall layer can make the magnetic tunnel junction unit have good performance.

[0098] Specifically, the material of the first spacer layer 111 includes silicon oxide and silicon oxynitride. In this embodiment, the material of the first spacer layer 111 includes silicon oxide. Silicon oxide is a commonly used dielectric material with low cost, high hardness, and etching resistance. It also has high process compatibility, which helps reduce the process difficulty and cost of forming the first spacer layer 111.

[0099] The steps of forming the first side wall layer 111 include: forming a first side wall material layer (not shown in the figure) that conformally covers the cap layer 108 and the magnetic tunnel junction stack structure 101 between the cap layer 108; removing the first side wall material layer on the magnetic tunnel junction stack structure 101 and directly above the cap layer 108, and the remaining first side wall material layer located on the side wall of the cap layer 108 serves as the first side wall layer 111.

[0100] In this embodiment, the first spacer material layer is formed using an atomic layer deposition (ALD) process. The ALD process includes multiple ALD cycles, which helps improve the thickness uniformity of the first spacer material layer, allowing the first spacer material layer to conformally cover the second electrode layer 109 and the etch-stop material layer 105 between the second electrode layer 109. Furthermore, the ALD process offers excellent gap-filling performance and step coverage. In other embodiments, the first spacer material layer can also be formed using a chemical vapor deposition process.

[0101] It should be noted that the first spacer layer 111 is also formed on the sidewalls of the second electrode layer 109 and the etch stop layer 110 .

[0102] It should be noted that the first sidewall layer 111 should not be too thick or too thin. If the first sidewall layer 111 is too thick, it is easy to spend too much process time to form the first sidewall layer 111, and it is also easy to cause the spacing between the adjacent second electrode layer 109, the etching stop layer 110 and the stacked structure composed of the cap layer 108 to be too small. Therefore, the subsequent etching of the magnetic tunnel junction stacked structure 101 to form a magnetic tunnel junction unit has a small process window. The polymer impurities generated in the process of etching the magnetic tunnel junction stacked structure 101 accumulate between the adjacent cap layers 108, which hinders the etching of the magnetic tunnel junction stacked structure 101, resulting in poor etching profile of the magnetic tunnel junction unit, and the bottom lateral dimension of the magnetic tunnel junction unit is larger than the top lateral dimension of the magnetic tunnel junction unit. If the first sidewall layer 111 is too thin, the first sidewall layer 111 is easily removed too early, and the sidewalls of the cap layer 108 are easily damaged. When the semiconductor structure is working, the cap layer 108 cannot effectively prevent the free magnetic layer from being affected by the carriers in the second electrode layer 109, resulting in unstable electron spin in the free magnetic layer. Moreover, if the first sidewall layer 111 is removed too early, the cap layer 108 and the second electrode layer 109 are exposed, and after the second electrode layer 109, the polymer impurities with metal ions generated during the etching process will be deposited (Re-deposition) on the sidewalls of the cap layer 108. The polymer impurities with metal ions can easily connect the second electrode layer 109 with the subsequently formed magnetic tunnel junction unit, resulting in a relatively small magnetic resistance of the subsequently formed magnetic tunnel junction unit. In this embodiment, the thickness of the first sidewall layer 111 is to

[0103] refer to Figure 8 , a second etching process is performed on the exposed portion of the cap layer 108 and the first spacer layer 111 of the magnetic tunnel junction stack structure 101 to form a magnetic tunnel junction unit 112 .

[0104] The magnetic tunnel junction unit 112 is used as a basic storage unit.

[0105] Specifically, the fixed magnetic material layer 1011 is etched to form a fixed magnetic layer 1121; the tunneling barrier material layer 1012 is etched to form a tunneling barrier layer 1122; and the magnetic free material layer 1013 is etched to form a magnetic free layer 1123. The fixed magnetic layer 1121, the tunneling barrier layer 1122, and the magnetic free layer 1123 serve as the magnetic tunnel junction unit 112.

[0106] In this embodiment, the second etching process is a dry etching process. The dry etching process has anisotropic etching characteristics and good etching profile controllability, which is conducive to making the morphology of the magnetic tunnel junction unit 112 meet process requirements.

[0107] Specifically, the dry etching process includes an anisotropic reactive ion etching process. During the anisotropic reactive ion etching process, a large number of chemically active gas ions are generated in the plasma produced by gas discharge. These ions interact with the material surface, causing surface atoms to chemically react, thereby producing an etching effect.

[0108] It should be noted that, during the etching process of the magnetic tunnel junction stacked structure 101 , the top of the first electrode material layer 104 is used as the etching stop position, and the magnetic tunnel junction stacked structure 101 is etched to form the magnetic tunnel junction unit 112 .

[0109] The material of the magnetic tunnel junction stacked structure 101 is different from the material of the first electrode material layer 104. During the etching of the magnetic tunnel junction stacked structure 101, by selecting a suitable reaction gas, the etching rate of the magnetic tunnel junction stacked structure 101 can be greater than the etching rate of the first electrode material layer 104. That is to say, the top of the first electrode material layer 104 is used as the etching stop position, which can avoid the problem of excessive or insufficient etching caused by inconsistent etching rates in various regions, and is beneficial to reducing the load effect of etching of the logic area II and the device area I.

[0110] Specifically, during the process of etching the magnetic tunnel junction stack structure 101 using an anisotropic reactive ion etching process, the reaction gas includes carbon fluorine gas and oxygen, or chlorine gas and oxygen, the reaction gas flow rate is 10 sccm to 300 sccm, and the chamber pressure is 3 mTorr to 40 mTorr.

[0111] It should be noted that, during the process of etching the magnetic tunnel junction stack structure 101 to form the magnetic tunnel junction unit 112 , unstable polymer impurities containing metal ions are easily formed on the sidewalls of the magnetic tunnel junction unit 112 .

[0112] refer to Figure 9 The method for forming the semiconductor structure further includes: after forming the magnetic tunnel junction unit 112 , etching the first electrode material layer 104 using an anisotropic physical etching process to form a first electrode layer 113 .

[0113] The first electrode layer 113 serves as a bottom electrode (BE) and is used to electrically connect the conductive structure 103 and the magnetic tunnel junction unit 112 .

[0114] In this embodiment, the anisotropic physical etching process enables better controllability of the etching profile when forming the first electrode layer 113 , which is beneficial for ensuring that the morphology of the first electrode layer 113 meets process requirements.

[0115] In this embodiment, the anisotropic physical etching process includes an ion beam etching process (IBE), which is non-selective to the processed material and has good etching directionality.

[0116] It should be noted that, in the process of etching the first electrode material layer 104 to form the first electrode layer 113, the polymer impurities containing metal ions deposited on the side walls of the magnetic tunnel junction unit 112 are also removed to prevent the polymer impurities containing metal ions from connecting the fixed magnetic layer 1121 and the magnetic free layer 1123, which is beneficial to improving the magnetoresistance ratio of the magnetic tunnel junction unit 112.

[0117] During the ion beam etching process, etching ions include one or more of Ar, Kr, He and Xe.

[0118] It should be noted that the angle between the ion beam etching direction and the surface normal of the substrate 100 should not be too large. If the angle is too large, the shadow effect during the anisotropic physical etching process will make it difficult to remove polymer impurities with metal ions on the sidewalls of the magnetic tunnel junction unit 112. The fixed magnetic layer 1123 and the magnetic free layer 1121 are electrically connected, which can easily lead to a relatively low magnetic resistance of the magnetic tunnel junction unit 112. In this embodiment, the angle between the ion beam etching direction and the surface normal of the substrate 100 is less than 30°.

[0119] It should be noted that during the anisotropic physical etching process, the bias voltage should not be too large or too small. If the bias voltage is too large, the etching rate of the first electrode material layer 104 will be too fast, the process controllability and reaction rate uniformity of the etching process will be reduced, and the conductive structure 103 in the substrate 100 will be easily damaged. It is also easy to damage the cap layer 108 and the sidewalls of the magnetic tunnel junction unit 112. When the semiconductor structure is operating, the cap layer 108 cannot effectively prevent the free magnetic layer 1123 from being affected by the carriers in the second electrode layer 109, resulting in unstable electron spin in the free magnetic layer 1123. It is also easy to form polymer impurities with metal ions on the sidewalls of the tunnel barrier layer 1122, which can easily connect the second electrode layer 109 to the magnetic tunnel junction unit 112 and the fixed magnetic layer 1123 to the magnetic free layer 1121. In both cases, the magnetic resistance of the magnetic tunnel junction unit 112 is relatively low. If the bias voltage is too low, the formation rate of the first electrode layer 113 may be too slow, which may make it difficult to improve the formation efficiency of the semiconductor structure. In this embodiment, during the anisotropic physical etching process, the bias voltage is 200V to 1000V.

[0120] It should be noted that, during the process of etching the first electrode material layer 104 to form the first electrode layer 113 , a portion of the thickness of the substrate 100 is also etched to ensure that the first electrode material layer 104 at the bottom of each magnetic tunnel junction unit 112 is etched through.

[0121] It should be noted that, during the second etching process, the thickness of the substrate 100 etched should not be too large or too small. If, during the second etching process, the thickness of the substrate 100 etched is too small, more polymer impurities with metal ions are likely to remain on the side walls of the magnetic tunnel junction unit 112. Correspondingly, it is easy to electrically connect the second electrode layer 109 to the magnetic tunnel junction unit 112, and it is also easy to electrically connect the fixed magnetic layer 1123 to the magnetic free layer 1121. Both of the above situations will result in a relatively small magnetic resistance of the magnetic tunnel junction unit 112. If the process time is too long, although the polymer impurities with metal ions on the side walls of the magnetic tunnel junction unit 112 can be removed, the conductive structure 103 in the substrate 100 is easily mistakenly etched, resulting in poor electrical performance of the semiconductor structure. In this embodiment, during the second etching process, the thickness of the substrate 100 etched is to

[0122] It should be noted that the anisotropic physical etching process is physical etching. During the etching of the first electrode material layer 104, even if the magnetic tunnel junction units 112 in the device area I are densely distributed, the etching rate of the substrate 100 in the device area I is similar to the etching rate of the substrate 100 in the logic area II, which is beneficial to reducing the load effect of etching of the logic area II and the device area I.

[0123] It should also be noted that in this embodiment, the second spacer layer 110 and the first spacer layer 111 are also etched away during the etching of the first electrode material layer 104 to form the first electrode layer 113. In other embodiments, the second spacer layer and the first spacer layer may also be retained.

[0124] refer to Figure 10 The method for forming the semiconductor structure further includes: after forming the first electrode layer 113 ; forming a second cap material layer 114 on the sidewalls and top surfaces of the cap layer 108 and the magnetic tunnel junction unit 112 .

[0125] The second cap material layer 114 is used to protect the first electrode layer 113, the magnetic tunnel junction unit 112, the cap layer 108, the second sidewall layer 110 and the second electrode layer 109, so that the first electrode layer 113, the magnetic tunnel junction unit 112, the cap layer 108, the second sidewall layer 110 and the second electrode layer 109 are not easily damaged during the subsequent etching process, thereby improving the electrical performance of the semiconductor structure.

[0126] In this embodiment, the second capping material layer 114 is formed using an atomic layer deposition (ALD) process. The ALD process includes multiple ALD cycles, which is beneficial for improving the thickness uniformity of the second capping material layer 114. The ALD process has good gap filling performance and step coverage. In other embodiments, the second capping material layer can also be formed using a chemical vapor deposition process.

[0127] In this embodiment, the material of the second capping material layer 114 includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0128] Accordingly, an embodiment of the present invention further provides a semiconductor structure. Figure 8 , showing a structural schematic diagram of an embodiment of a semiconductor structure of the present invention.

[0129] The semiconductor structure includes: a substrate 100 ; a discrete magnetic tunnel junction unit 112 located on the substrate 100 ; a cap layer 108 located on the magnetic tunnel junction unit 112 ; and a first spacer 111 located on a sidewall of the cap layer 108 .

[0130] In the semiconductor structure provided by the embodiment of the present invention, the magnetic tunnel junction stacked structure 101 (eg, Figure 7 As shown), in the process of forming the magnetic tunnel junction unit 112, the first sidewall layer 111 can prevent the sidewalls of the cap layer 108 from being damaged; usually the semiconductor structure also includes a second electrode layer 109 located on the cap layer 108. When the semiconductor structure is working, the cap layer 108 can better protect the free magnetic layer 1123 in the magnetic tunnel junction unit 112 from being easily affected by the carriers in the second electrode layer 109, so that the electron spin direction in the free magnetic layer 1123 is stable. In addition, in the process of etching the magnetic tunnel junction stack structure 101, polymer impurities with metal ions are usually formed. The first sidewall layer 111 can prevent the polymer impurities with metal ions from being directly formed on the sidewalls of the cap layer 108, so that the polymer impurities with metal ions are not easy to conduct the magnetic tunnel junction unit 112 with the outside, so that the magnetic tunnel junction unit 112 has a higher magnetoresistance ratio. In summary, the first sidewall layer 111 can make the magnetic tunnel junction unit 112 have good performance.

[0131] The substrate includes a logic region II and a device region I. The logic region II is used to isolate the adjacent device region I. The magnetic tunnel junction unit 112 is located on the device region I.

[0132] Specifically, in this embodiment, the substrate 100 includes a dielectric layer.

[0133] In this embodiment, functional structures such as transistors, resistor structures, and conductive structures may be formed at the bottom of the dielectric layer. The transistors may be one or both of NMOS and PMOS transistors. Specifically, the transistors include a gate structure, source and drain doped regions located on both sides of the gate structure, and other functional structures.

[0134] The dielectric layer is used to achieve electrical isolation between the device at the bottom of the dielectric layer and the magnetic tunnel junction unit 112 .

[0135] In this embodiment, the dielectric layer is made of a low-k dielectric material, which is beneficial for reducing parasitic capacitance between back-end interconnect structures, thereby reducing back-end RC delay. In other embodiments, depending on the actual process, the dielectric layer can also be an inter-metal dielectric (IMD) layer.

[0136] It should be noted that a conductive structure 103 is formed in the dielectric layer.

[0137] The bottom end of the conductive structure 103 is connected to the source / drain doped region of the transistor at the bottom of the dielectric layer, and the top end of the conductive structure 103 is used to be electrically connected to the magnetic tunnel junction unit 112 .

[0138] In this embodiment, the conductive structure 103 is made of copper. In other embodiments, the conductive structure 103 may be made of other conductive materials such as cobalt and tungsten.

[0139] The magnetic tunnel junction unit 112 includes a fixed magnetic layer 1121 , a tunneling barrier layer 1122 located on the fixed magnetic layer 1121 , and a magnetic free layer 1123 located on the tunneling barrier layer 1122 .

[0140] The magnetic tunnel junction unit 112 serves as a storage unit.

[0141] The fixed magnetic layer 1121 has a fixed magnetic direction.

[0142] Specifically, the material of the fixed magnetic layer 1121 includes one or more of FeCoB, CoFeTa, NiFe, and FePt. In this embodiment, the material of the fixed magnetic layer 1121 includes FeCoB.

[0143] The tunneling barrier layer 1122 is used to electrically isolate the fixed magnetic layer 1121 from the magnetic free layer 1123 , while allowing electrons to tunnel through the tunneling barrier layer 1122 under appropriate conditions.

[0144] Specifically, the material of the tunneling barrier layer 1122 includes MgO, AlO, AlN or AlON. In this embodiment, the material of the tunneling barrier layer 1122 includes MgO.

[0145] The magnetic free layer 1123 has a free magnetic orientation. When the magnetic tunnel junction unit is working, the spin transfer torque (STT) effect is usually used to change or switch the magnetization direction of the magnetic free layer 1123 so that it is parallel to or opposite to the magnetization direction of the fixed magnetic layer 1121. Therefore, the magnetic tunnel junction unit 112 can be in a low resistance state or a high resistance state.

[0146] Specifically, the material of the magnetic free layer 1123 includes one or more of FeCoB, CoFeTa, NiFe, and FePt. In this embodiment, the material of the magnetic free layer 1123 includes FeCoB.

[0147] When the semiconductor structure is operating, the cap layer 108 prevents the spin of electrons in the magnetic free layer 1123 from being affected by carriers in the film structure above the cap layer 108 and from changing. Furthermore, the magnetic field and electric field are contained between the magnetic free layer 1123 and the fixed magnetic layer 1121.

[0148] Specifically, the material of the capping layer 108 includes MgO, AlO, AlN or AlON. In this embodiment, the material of the capping layer 108 includes MgO.

[0149] The second electrode layer 109 is located on the capping layer 108 .

[0150] The second electrode layer 109 is an upper electrode, and is used to electrically connect the magnetic tunnel junction unit 112 with a metal layer subsequently formed on the magnetic tunnel junction unit 112 .

[0151] In this embodiment, the material of the second electrode layer 109 includes one or more of tantalum nitride (TaN), tantalum (Ta), titanium (Ti), and titanium nitride (TiN). In this embodiment, the second electrode layer 109 has a single-layer structure, and the material of the second electrode layer 109 is tantalum.

[0152] It should be noted that the semiconductor structure further includes an etch stop layer 110 located between the second electrode layer 109 and the cap layer 108 .

[0153] During the process of etching to form the second electrode layer 109 , the top of the etch stop layer 110 serves as an etch stop.

[0154] Specifically, the material of the etch stop layer 110 includes one or more of silicon oxide, silicon nitride, titanium nitride, and tantalum nitride. In this embodiment, the material of the etch stop layer 110 includes silicon oxide. Silicon oxide is a commonly used, low-cost dielectric material with high process compatibility, which helps reduce the process difficulty and cost of forming the etch stop layer 110.

[0155] It should be noted that the semiconductor structure further includes: a first electrode material layer 104 located between the substrate 100 and the magnetic tunnel junction unit 112 .

[0156] The first electrode material layer 104 is prepared for the subsequent formation of a bottom electrode.

[0157] In this embodiment, the material of the first electrode material layer 104 is one or more of tantalum nitride (TaN), tantalum (Ta), titanium (Ti), and titanium nitride (TiN). In this embodiment, the first electrode material layer 104 is a single-layer structure, and the material of the first electrode material layer 104 is tantalum.

[0158] During the process of forming the magnetic tunnel junction unit 112 and the subsequent process of etching the first electrode material layer 104 to form the first electrode layer, the first spacer layer 111 can protect the sidewalls of the cap layer 108 from being damaged.

[0159] Specifically, the material of the first spacer layer 111 includes silicon oxide and silicon oxynitride. In this embodiment, the material of the first spacer layer 111 includes silicon oxide. Silicon oxide is a commonly used dielectric material with low cost, high hardness, and etching resistance. It also has high process compatibility, which helps reduce the process difficulty and cost of forming the first spacer layer 111.

[0160] It should be noted that the first sidewall layer 111 should not be too thick or too thin. If the first sidewall layer 111 is too thick, it may lead to a small spacing between adjacent stacked structures formed by the second electrode layer 109, the etch stop layer 110, and the cap layer 108. During the process of etching the magnetic tunnel junction stacked structure 101 to form the magnetic tunnel junction unit 112, polymer impurities generated may accumulate between adjacent cap layers 108, hindering the etching process and resulting in a poor etching profile of the magnetic tunnel junction unit 112. If the first sidewall layer 111 is too thin, during the subsequent etching of the first electrode material layer 104 to form the first electrode, the first sidewall layer 111 may be removed prematurely, and the sidewalls of the cap layer 108 may be damaged. When the semiconductor structure is in operation, the cap layer 108 may not be able to effectively protect the free magnetic layer 1123 from being affected by carriers in the second electrode layer 109, resulting in unstable electron spin in the free magnetic layer 1123. If the first spacer layer 111 is removed too early, the polymer impurities containing metal ions generated during the formation of the second electrode layer 109 will be deposited (re-deposition) on the sidewalls of the cap layer 108, which can easily connect the second electrode layer 109 to the magnetic tunnel junction unit 112, resulting in a relatively small magnetic resistance of the magnetic tunnel junction unit 112. In this embodiment, the thickness of the first spacer layer 111 is to

[0161] It should be noted that the first spacer layer 111 is also located on the sidewalls of the second electrode layer 109 and the etch stop layer 110 .

[0162] The semiconductor structure further includes a second spacer layer 110 located between the second electrode layer 109 and the first spacer layer 111 .

[0163] The capping layer 108 is formed by etching the first capping material layer exposed by the second electrode layer 109 and the second spacer layer 110. The second spacer layer 110 can increase the lateral size of the capping layer 108.

[0164] Specifically, the material of the second spacer 110 includes one or more of Ta, Cu, Au, TaN, TiN, Co, and Pt. In this embodiment, the material of the second spacer 110 includes Ta. The material of the second spacer 110 is the same as that of the second electrode layer 109, which can ensure good adhesion between the second spacer 110 and the second electrode layer 109. When the semiconductor structure is operating, the second spacer 110 can also reduce the on-resistance of the semiconductor structure, which is beneficial to reducing the power consumption of the semiconductor structure. In other embodiments, the second spacer can also be made of other conductive materials.

[0165] It should be noted that the second sidewall layer 110 should not be too thick or too thin. In the process of etching the first cap material layer to form the cap layer 108, polymer impurities (polymer) will be generated. If the second sidewall layer 110 is too thick, the spacing between adjacent second electrode layers 109 in the corresponding device area I is small, and the polymer impurities are not easy to be removed in time, which may easily lead to the risk of etching stopping in the subsequent etching process. Even if the cap layer 108 can be formed, the angle between the sidewall of the cap layer 108 and the normal of the surface of the substrate 100 is too large. If the second sidewall layer 110 is too thin, during the etching process, the second sidewall layer 110 is not easy to significantly increase the lateral size of the cap layer 108. In this embodiment, the thickness of the second sidewall layer 110 is to

[0166] Accordingly, during the process of forming the capping layer 108 , the first capping material layer 102 exposed by the second electrode layer 109 and the second spacer layer 110 is etched to form the capping layer.

[0167] The semiconductor structure of this embodiment can be formed by the formation method described in the previous embodiment, or by other formation methods. For the detailed description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the previous embodiment, and this embodiment will not be repeated here.

[0168] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate having a conductive structure, a first electrode material layer located on the substrate, a magnetic tunnel junction stacked structure located on the first electrode material layer, and a first cap material layer located on the magnetic tunnel junction stacked structure; Performing a first etching process on the first cap material layer to form a cap layer; during the first etching process, a magnetic free material layer with a partial thickness in the magnetic tunnel junction stacked structure is also etched away; forming a first spacer layer on the sidewall of the cap layer, wherein the first spacer layer also covers a portion of the sidewall of the magnetic free material layer of the magnetic tunnel junction stacked structure; Performing a second etching process on the magnetic tunnel junction stacked structure exposed by the cap layer and the first spacer layer to form a magnetic tunnel junction unit; After forming the magnetic tunnel junction unit, etching the first electrode material layer using an anisotropic physical etching process to form a first electrode layer; After forming the first electrode layer, on a projection plane parallel to the substrate, a projection of the first electrode layer exceeds a projection of the conductive structure; After forming the first electrode layer, a second capping material layer is formed on the sidewalls and top surfaces of the capping layer, the magnetic tunnel junction unit and the first electrode layer, wherein the bottom surface of the second capping material layer is located on the substrate and is lower than the top surface of the conductive structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: The anisotropic physical etching process includes an ion beam etching process.

3. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing a substrate, a first electrode material layer is formed between the substrate and the magnetic tunnel junction stacked structure; An etch stop material layer is formed on the first cap material layer; A second electrode material layer is formed on the etch stop material layer; The first etching process comprises: etching the second electrode material layer with the top of the etching stop material layer as the etching stop position to form a second electrode layer; after forming the second electrode layer, etching the etching stop material layer with the top of the first cap material layer as the etching stop position to form an etching stop layer; etching the first cap material layer with the top of the magnetic tunnel junction stacked structure as the etching stop position to form the cap layer; The second etching step includes: in the process of etching the magnetic tunnel junction stacked structure, taking the top of the first electrode material layer as the etching stop position.

4. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the first sidewall layer is to 5. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first spacer layer includes silicon oxide and silicon oxynitride.

6. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the first spacer layer includes: Forming a first spacer material layer conformally covering the cap layer and the magnetic tunnel junction stacked structure between the cap layers; The first spacer material layer on the magnetic tunnel junction stacked structure and directly above the cap layer is removed, and the remaining first spacer material layer on the side wall of the cap layer is used as the first spacer layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The first spacer material layer is formed by atomic layer deposition or chemical vapor deposition process.

8. The method for forming a semiconductor structure according to claim 1, wherein: The first etching process adopts an anisotropic reactive ion etching process.

9. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters of the first etching treatment include: the reaction gas includes carbon fluorine gas or chlorine gas, the flow rate of the reaction gas is 10 sccm to 200 sccm, and the chamber pressure is 3 mTorr to 50 mTorr.

10. The method for forming a semiconductor structure according to claim 1, wherein: The second etching process adopts an anisotropic reactive ion etching process.

11. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters of the ion beam etching process include: etching ions include one or more of Ar, Kr, He and Xe, the angle between the ion beam etching direction and the normal line of the substrate surface is less than 30°, and the bias voltage is 200V to 1000V.

12. The method for forming a semiconductor structure according to claim 3, wherein: In the step of the first etching process, after forming the second electrode layer and before etching the etching stop material layer, a second sidewall layer is formed on the sidewall of the second electrode layer; During the process of forming the capping layer, the first capping material layer exposed by the second electrode layer and the second sidewall layer is etched to form the capping layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The material of the second spacer layer includes one or more of Ta, Cu, Au, TaN, TiN, Co and Pt.

14. The method for forming a semiconductor structure according to claim 12, wherein: The thickness of the second sidewall layer is to 15. A semiconductor structure, characterized in that: include: a substrate comprising a conductive structure; a first electrode layer, located on the substrate and covering the conductive structure, wherein a projection of the first electrode layer exceeds a projection of the conductive structure on a projection plane parallel to the substrate; A plurality of discrete magnetic tunnel junction units are located on the substrate, and the magnetic tunnel junction units are located on the first electrode layer; A cap layer, located on the magnetic tunnel junction unit; A first spacer layer, located on the side wall of the cap layer and also covering a portion of the side wall of the magnetic free layer of the magnetic tunnel junction unit; A second capping material layer is located on the side walls and top surfaces of the capping layer, the magnetic tunnel junction unit and the first electrode layer, and a bottom surface of the second capping material layer is located on the substrate and is lower than a top surface of the conductive structure.

16. The semiconductor structure according to claim 15, wherein: The second electrode layer is located on the cap layer; the first sidewall layer is also located on the sidewall of the second electrode layer.

17. The semiconductor structure according to claim 15 or 16, characterized in that: The thickness of the first sidewall layer is to 18. The semiconductor structure according to claim 15 or 16, characterized in that: The material of the first spacer layer includes silicon oxide and silicon oxynitride.

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