Optoelectronic component and method for producing an optoelectronic component

Abstract

An optoelectronic component (1) is proposed, comprising: an optoelectronic semiconductor chip (2) which generates electromagnetic radiation during operation, and a metal layer (3) arranged on the semiconductor chip (2), wherein an outer surface (4) of the metal layer has a structuring (5), an identification component (1) is realized by means of the structuring (5), and the metal layer (3) is designed to be continuous. A method for producing the optoelectronic component (1) is also proposed.

Description

[0001] An optoelectronic component is specified. Furthermore, a method for producing such an optoelectronic component is specified.

[0002] The object to be achieved is to specify an optoelectronic component which has a particularly effective heat dissipation. Another object to be achieved is to specify a method for producing such an optoelectronic component.

[0003] An optoelectronic component is, for example, a radiation-emitting component which emits electromagnetic radiation during operation. For example, the optoelectronic component is a laser diode or a light-emitting diode. Furthermore, the optoelectronic component can also be a component which receives electromagnetic radiation, for example a photodiode.

[0004] The optoelectronic component has a main extension plane. The lateral direction is oriented, for example, parallel to the main extension plane and the vertical direction is oriented perpendicular to the lateral direction.

[0005] According to at least one embodiment, the optoelectronic component comprises a semiconductor chip which generates or receives electromagnetic radiation during operation. The optoelectronic semiconductor chip is, for example, a laser diode chip or a light emitting diode chip (LED chip for short), or a photodiode chip.

[0006] The optoelectronic semiconductor chip has, for example, a first main face and a second main face lying opposite one another.

[0007] For example, the optoelectronic semiconductor chip is a laser diode, in particular a semiconductor laser diode. The semiconductor laser diode emits electromagnetic radiation, for example monochromatic and coherent laser light, during operation. The laser light is preferably coupled out via the side surfaces of the semiconductor laser diode. The side surfaces of the semiconductor laser diode are preferably substantially perpendicular to the main extension plane. Substantially perpendicular means that the side surfaces are inclined by at most 5° relative to the normal to the main extension plane.

[0008] Alternatively, the optoelectronic semiconductor chip is a light emitting diode chip. The light emitting diode chip is preferably designed to emit electromagnetic radiation, in particular visible light. The emitted light is then preferably coupled out from the semiconductor chip via the radiation exit surface. The radiation exit surface is formed, for example, by the second main surface of the semiconductor chip.

[0009] According to at least one embodiment, the optoelectronic component comprises a metal layer arranged on an optoelectronic semiconductor chip. The metal layer can be in direct contact with the optoelectronic semiconductor chip, for example, with a bottom surface. The side surface of the metal layer connects the bottom surface to the opposite cover surface. For example, the metal layer is arranged on the first main surface of the optoelectronic semiconductor chip. In addition, the metal layer covers, for example, a large part of the optoelectronic semiconductor chip. The metal layer covers the first main surface of the optoelectronic semiconductor chip, for example, at least 70%, in particular at least 95%.

[0010] The thickness of the metal layer in the vertical direction is, for example, at least 0.05 micrometers and at most 15 micrometers. The metal layer, for example, includes or consists of one or more of the following metals: Cu, Ti, Pt, Au, Ni, ZnO, TiWN, Rh, Pd, Cr, ITO.

[0011] According to at least one embodiment, the outer surface of the metal layer has a structuring portion. The outer surface of the metal layer is an exposed outer surface not covered by the optoelectronic semiconductor chip. That is, the outer surface is formed by the side surfaces of the metal layer and the cover surface of the metal layer.

[0012] The structuring is preferably machine-readable. That is, information for identifying the optoelectronic component can be read, for example, by means of a reading device. The reading device is preferably designed to detect and identify the structuring. Thus, the optoelectronic component can be clearly identified by means of the structuring.

[0013] According to at least one embodiment, the identification component can be realized by means of a structuring. The structuring is formed, for example, by a recess in the metal layer. Alternatively or additionally, it is possible that the structuring is formed by a roughened region of the metal layer.

[0014] The metal layer in the region of the recess can be distinguished from the metal layer in the region without the recess, for example. In addition, for example, the roughened region can also be distinguished from the non-roughened region of the metal layer. Thus, for example, a reader device provided for this purpose can be identified, thereby realizing the structured part of the identification component.

[0015] In accordance with at least one embodiment, the metal layer is formed continuously, so that the metal layer is arranged without interruption above the optoelectronic semiconductor chip.

[0016] If the metal layer has a recess, the recess is arranged, for example, at the edge region of the metal layer. Furthermore, the metal layer does not have, for example, a recess which is completely surrounded by the metal layer and passes completely through the metal layer. Due to the lack of such a recess which is completely surrounded by the metal layer, a cavity is prevented from forming in such a recess, at which cavity a heat build-up could occur when the component is applied, for example, to a soldering surface.

[0017] In this case, the metal layer is, for example, formed in a simple continuous manner. Additionally, in this case, the outer surface of the metal layer can be formed integrally with the structuring.

[0018] It is also possible that the metal layer has a recess which is completely surrounded by the metal layer. In this case, the recess can completely penetrate the metal layer.

[0019] If the outer surface of the metal layer has a roughened region, the roughened region is formed, for example, from the same material as the metal layer. That is, the outer surface of the metal layer having the structured portion can be formed in one piece.

[0020] In at least one embodiment, the optoelectronic component comprises an optoelectronic semiconductor chip which generates electromagnetic radiation during operation and a metal layer which is arranged on the semiconductor chip, wherein an outer surface of the metal layer has a structuring by means of which an identification component can be realized and the metal layer is formed continuously.

[0021] One idea of ​​the optoelectronic component described here is, in particular, that the structured part for identifying the component is arranged on the outer surface of the metal layer. In addition, the metal layer is designed to be continuous. As a result, the current fed into the metal layer can be distributed evenly over the entire metal layer. Likewise, the heat that occurs can advantageously be distributed evenly over the metal layer. Thus, advantageously, during operation of the component, the metal layer does not have any areas with increased current density or heat density.

[0022] According to at least one embodiment, no non-metallic elements are applied to the outer surface of the metal layer. The metal layer is thus, for example, freely accessible at the outer surface. The structuring is therefore not formed by non-metallic elements arranged on the layer.

[0023] According to at least one embodiment, the metal layer is designed as a heat sink. The heat generated in the optoelectronic semiconductor chip can preferably be removed via the metal layer. Since the metal layer is formed continuously and no non-metallic elements are applied to the outer surface of the metal layer, the heat can be removed from the optoelectronic semiconductor chip particularly well via the metal layer. In addition, the structuring advantageously increases the surface of the metal layer compared to a metal layer without a structuring. This also leads to better removal of heat from the optoelectronic semiconductor chip.

[0024] In accordance with at least one embodiment, the metal layer is designed as a contact layer for electrically contacting the semiconductor chip. For example, the optoelectronic semiconductor chip can be energized by means of the metal layer.

[0025] Typically, non-metallic elements are not designed to be electrically non-conductive and have a relatively low thermal conductivity. Since no such non-conductive elements are arranged on the metal layer, the metal layer can advantageously remove heat generated in the semiconductor chip particularly well and uniformly. Furthermore, the described metal layer can also feed current into the semiconductor chip particularly uniformly.

[0026] According to at least one embodiment, the metal layer is a functional layer of the optoelectronic component and assumes multiple functions. The metal layer serves, for example, as an identification component. In addition, the metal layer can be formed as a heat sink and / or a contact layer for the electrical conversion of the semiconductor chip.

[0027] The metal layer thus advantageously combines a plurality of different properties. The component can therefore be manufactured particularly simply, since only the metal layer has to be applied. Additional heat sinks and contact layers are not absolutely necessary. Such an optoelectronic component is particularly cost-effective.

[0028] According to at least one embodiment, the semiconductor chip has a ridge waveguide having a top surface and a side surface adjacent to the top surface. The semiconductor chip in this embodiment is therefore a laser diode. The optoelectronic semiconductor chip comprises, for example, a semiconductor layer sequence. The ridge waveguide is preferably formed by a ridge-shaped raised region of the semiconductor layer sequence. For example, the ridge waveguide protrudes as a protrusion from the concave outer surface of the semiconductor layer sequence. The ridge waveguide preferably extends in a lateral direction.

[0029] The cover surface of the ridge waveguide is directly connected to the recessed outer surface of the semiconductor layer sequence via the side surface adjacent thereto, and the outer surface is arranged lateral to the ridge waveguide. Here, the side surface establishes a spacing in the vertical direction between the recessed outer surface lateral to the ridge waveguide and the cover surface of the ridge waveguide. For example, the cover surface and the side surface of the ridge waveguide and the recessed outer surface of the semiconductor layer lateral to the ridge waveguide form a stepped profile. In addition, the first main surface of the semiconductor chip includes the cover surface and the side surface of the ridge waveguide and the recessed outer surface of the semiconductor layer sequence lateral to the ridge waveguide.

[0030] For example, the active layer is arranged between the side faces of the ridge waveguide. Alternatively, it is possible to arrange the active layer in the semiconductor layer sequence below the ridge waveguide. In this case, the active layer therefore also extends below the recessed outer surface of the semiconductor layer sequence.

[0031] Additionally, a contact can be arranged on the top surface of the ridge waveguide, which is in direct contact with the top surface of the ridge waveguide and preferably completely covers the top surface. In this case, the contact is electrically conductive and is electrically conductively connected to the top surface of the ridge waveguide.

[0032] According to at least one embodiment, the passivation layer covers the side surfaces of the ridge waveguide. Furthermore, the passivation layer preferably covers the outer surface of the recess of the semiconductor layer sequence that is laterally to the ridge waveguide. For example, the passivation layer in particular completely covers the side surfaces of the ridge waveguide. Furthermore, the passivation layer, for example, completely covers the outer surface of the recess. The top surface of the ridge waveguide is in particular not covered with the passivation layer and is therefore free of the passivation layer.

[0033] If the optoelectronic semiconductor chip has a contact, the passivation layer can cover the side surfaces of the contact. For example, the passivation layer completely covers the side surfaces of the contact. The top surface of the contact is preferably not covered by the passivation layer.

[0034] The passivation layer is preferably formed electrically insulatingly. The passivation layer comprises, for example, an oxide, a nitride or an oxynitride or consists of one of these materials. Suitable oxides, nitrides or oxynitrides are, for example, silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, rhodium oxide, niobium oxide and / or titanium dioxide. Other oxides, nitrides and oxynitrides having one or more of the following materials can be suitable as materials for one of the passivation layers: Al, Ce, Ga, Hf, In, Mg, Nb, Rh, Sb, Si, Sn, Ta, Ti, Zn, Zr.

[0035] According to at least one embodiment, the metal layer is in direct contact with the top surface of the ridge waveguide. The semiconductor layer sequence of the optoelectronic semiconductor chip is, for example, in direct contact with the metal layer. Thus, the semiconductor layer sequence can be electrically conductively connected via the metal layer at the top surface of the ridge waveguide. The metal layer also covers, for example, the passivation layer above the semiconductor layer sequence.

[0036] According to at least one embodiment, the structured portion extends in a plan view without overlapping the cover area of ​​the ridge waveguide. The lateral extension of the structured portion does not extend over the side surfaces of the ridge waveguide, for example. Thus, a particularly compact configuration of the optoelectronic component is advantageously achieved.

[0037] According to at least one embodiment, the structuring comprises a recess.

[0038] According to at least one embodiment, at least a portion of the recess completely passes through the metal layer. The recess passes through the metal layer in a vertical direction. The bottom of the recess is formed by the optoelectronic semiconductor chip. For example, the bottom surface of the recess can be formed by a passivation layer.

[0039] According to at least one embodiment, at least a portion of the recess partially passes through the metal layer. In this case, the bottom surface of the recess is formed by the metal layer.

[0040] In this case, in the edge region of the metal layer, the thickness of the metal layer between the recesses is less than the thickness of the metal layer in the region without the recesses. For example, the covering surface of the metal layer in the region without the recesses and the side surfaces adjacent thereto and the bottom surface of the recesses form a stepped profile.

[0041] The thickness in the edge region of the metal layer in the region of the recess is preferably less than 10 micrometers and at least 0.05 micrometers.

[0042] In addition, the structuring can be formed, for example, by cutouts which pass completely through the metal layer and cutouts which do not pass completely through the metal layer.

[0043] According to at least one embodiment, the structured portion comprises a roughened region. The roughened region preferably has elevations and depressions. In addition, the thickness of the roughened region can be less than the thickness of the metal layer without the roughened region. Alternatively, the thickness of the roughened region can be greater than the thickness of the second metal layer without the roughened region, for example. The two different regions can advantageously be better distinguished by a height difference.

[0044] The thickness of the metal layer in the edge region in the region of the roughened region is preferably less than 5 micrometers and at least 0.05 micrometers.

[0045] In addition, the structuring can be formed, for example, by recesses and roughened regions.

[0046] According to at least one embodiment, the structuring forms a barcode for identifying the component. For example, if the metal layer has recesses, the recesses form a plurality of bars, each of which has a certain width and a certain length.

[0047] If the structuring comprises a roughened region, the roughened region forms a plurality of strips which each have a certain width and a certain length.

[0048] The plurality of strips each have a quadrilateral shape, for example. The edges of the quadrilateral shape can be rounded. The strips in the plurality of strips preferably have the same length. For example, the strips in the plurality of strips have a length of 5 μm to 100 μm (including 5 μm and 100 μm), preferably a length of 6 μm to 20 μm (including 6 μm and 20 μm).

[0049] The widths of the strips in the plurality of strips are preferably configured differently. For example, the strips in the plurality of strips each have a width of 1 μm to 100 μm (including 1 μm and 100 μm), preferably a width of 2 μm to 15 μm (including 2 μm and 15 μm), and particularly preferably a width of 3 μm to 10 μm.

[0050] Alternatively, it is possible that the lengths of the strips in a plurality of strips can also differ from one another. In this case, it is possible that the widths of the strips in a plurality of strips are respectively the same.

[0051] By means of the different widths of the bars in the plurality of bars, for example, a barcode is formed. For example, it is possible that during the method for producing an optoelectronic component, the optoelectronic component is arranged on a wafer with a plurality of further optoelectronic components. For example, the barcode encodes the lateral position of the optoelectronic component and the further components in the plurality of further optoelectronic components, respectively. For example, the barcode is formed as a 2 / 5 interleaving, code 128, code 11, code 39, code 93 or MSI code (English "modified Plessey code" modified Plessey code).

[0052] Alternatively, the structuring forms a QR code (English “Quick Response Code”) for identifying the component. If the structuring is formed by recesses, the recesses are arranged, for example, along rows and columns and form a QR matrix. In order to avoid undesired heat accumulation, in this case, the recesses do not pass through the metal layer.

[0053] If the structuring is formed by roughened regions, the roughened regions are arranged, for example, along rows and columns and form a QR matrix. The QR matrix can include, for example, recesses and roughened regions.

[0054] According to at least one embodiment, the metal layer is a metallic layer stack. For example, the metallic layer stack comprises a plurality of layers.

[0055] According to at least one embodiment, the layer stack comprises a first metal layer and a second metal layer. For example, if the optoelectronic semiconductor chip has a ridge waveguide, the first metal layer covers the side faces and the top face of the ridge waveguide. Furthermore, the first metal layer is partially arranged over the outer surface of the recess of the semiconductor layer sequence. In this case, the first metal layer is embedded in the ridge waveguide.

[0056] The second metal layer can be embedded in the first metal layer, for example. In this case, embedding means that the second metal layer completely covers the outer surface of the first metal layer facing away from the semiconductor layer sequence. The second metal layer also covers the recessed outer surface of the semiconductor layer sequence that is not covered by the first metal layer. In this case, the second metal layer has recesses and / or roughened areas. For example, in a top view, the recesses do not overlap with the first metal layer.

[0057] The first metal layer is advantageously encapsulated by the second metal layer and results in a better protection of the ridge waveguide.

[0058] If the roughened area forms a structured portion, the first metal layer can be arranged completely above the recessed outer surface of the semiconductor layer sequence. In this case, in a top view, the roughened area can overlap with the first metal layer. For example, the second metal layer is also embedded in the first metal layer and advantageously encapsulates it.

[0059] If the metal layer comprises a layer stack, the first metal layer is, for example, different from the second metal layer. The first metal layer comprises, for example, a different material than the second metal layer.

[0060] According to at least one embodiment, the first metal layer comprises a metallic adhesion promoter layer and a metallic barrier layer. For example, the metallic adhesion promoter layer provides particularly good adhesion to the cover surface of the passivation layer and the ridge waveguide or to the cover surface of the contact of the metallic barrier layer to be arranged thereon. The metallic barrier layer advantageously prevents the migration of chemical substances in the semiconductor chip.

[0061] The protection of the semiconductor chip from external chemical influences is further improved if the metallic adhesion promoter layer and the metallic barrier layer are also encapsulated by a second metallic layer.

[0062] Alternatively, the first metal layer can include a plurality of metal layers. The first metal layer includes, for example, three layers. In this case, the layer sequence of the first metal layer is, for example, as follows: Ti—Pt—Pd, wherein the second metal layer is applied on the Pd layer.

[0063] Furthermore, a method for producing an optoelectronic component is proposed. The method is preferably also suitable for producing the optoelectronic component described herein. That is, the optoelectronic component described herein can be produced by means of the described method or can be produced by means of the described method. Therefore, all features disclosed in conjunction with the optoelectronic component are also disclosed in conjunction with the method, and vice versa.

[0064] According to at least one embodiment of the method, an optoelectronic semiconductor chip is provided.

[0065] According to at least one embodiment of the method, a metal layer is applied to the optoelectronic semiconductor chip. The metal layer is applied, for example, by means of chemical vapor deposition (CVD) or physical vapor deposition (PVD). It is also possible that the metal layer is applied by means of atomic layer deposition (ALD).

[0066] According to at least one embodiment of the method, the metal layer is a metallic layer stack. For example, it is possible to apply the metal layer of the metallic layer stack by means of different deposition methods.

[0067] According to at least one embodiment of the method, the first metal layer and the second metal layer are subsequently applied one above the other to the optoelectronic semiconductor chip. For example, it is possible to apply the metal layer at least in places to the passivation layer of the optoelectronic semiconductor chip and to the top surface of the semiconductor layer sequence of the optoelectronic semiconductor chip.

[0068] For example, a recess is produced in the metal layer. For example, the recess is produced in the region of the recess of the metal layer by material removal. For example, the recess can be produced by means of a laser process or by means of a plasma-based dry etching method or a wet chemical etching method. Furthermore, the recess can be produced by means of a lift-off technique.

[0069] According to at least one embodiment of the method, at least a portion of the recesses passes through the second metal layer as far as the first metal layer. In this case, the recesses do not completely pass through the metal layer. Therefore, the recesses expose the first metal layer in the region of the recesses.

[0070] According to at least one embodiment of the method, an interference layer is applied to the exposed first metal layer. For example, the interference layer comprises an oxide. For example, the interference layer can be applied by means of a deposition process. In addition, the exposed first metal layer can be oxidized, for example, by means of an oxygen plasma treatment. Alternatively, it is feasible to heat the exposed first metal layer in an oxygen environment. Thus, the surface of the exposed first metal layer is oxidized and, for example, an interference layer is formed.

[0071] If, for example, a second metal layer is applied on the interfering layer, it has an increased defect density compared to a second metal layer applied on the first metal layer, thereby interfering with, for example, a relatively uniform growth of the second metal layer.

[0072] According to at least one embodiment of the method, a further second metal layer is applied to the interference layer. The outer surface of the further second metal layer applied to the interference layer has an increased roughness compared to the second metal layer. Preferably, the metal layer of the metal-containing layer stack comprises a further second metal layer.

[0073] For example, the other second metal layer can be formed of the same material as the second metal layer. Alternatively, the other second metal layer can be formed of a material different from that of the second metal layer.

[0074] Furthermore, the thickness of the further second metal layer can, for example, be smaller than the thickness of the second metal layer. Alternatively, the thickness of the further second metal layer can, for example, be greater than the thickness of the second metal layer.

[0075] According to at least one embodiment of the method, a stop layer is applied locally to the metal layer. For example, the stop layer is applied locally to the second metal layer. The stop layer, for example, prevents another metal layer from growing on the stop layer. The area of ​​the metal layer covered by the stop layer then does not have any structuring.

[0076] According to at least one embodiment of the method, a further metal layer is electroplated onto the area not covered by the stop layer. For example, a further second metal layer is electroplated onto the area not covered by the stop layer. The outer surface of the further metal layer deposited electroplatingly has an increased roughness compared to the metal layer.

[0077] The stop layer can be removed in a further method step.

[0078] The optoelectronic component described here and the method described here are explained in more detail below with reference to exemplary embodiments and the associated figures. The figures show:

[0079] Figure 1A and 1B each shows a schematic top view of an exemplary embodiment of an optoelectronic component described here,

[0080] Figure 2A and 2B shows a schematic cross-sectional view of an exemplary embodiment of an optoelectronic component described here,

[0081] Figure 3 shows a schematic cross-sectional view of an exemplary embodiment of an optoelectronic component described here,

[0082] Figure 4 A schematic sectional view is shown in a top view of an exemplary embodiment of an optoelectronic component described here,

[0083] Figure 5 shows a schematic cross-sectional view of an exemplary embodiment of an optoelectronic component described here,

[0084] Fig. 6A , 6B , 6C, 6D show schematic sectional views of method steps of an exemplary embodiment of a method described herein for producing an optoelectronic component,

[0085] Fig. 7A , 7B 7C and 7D show schematic sectional views of method steps of an exemplary embodiment of a method described herein for producing an optoelectronic component.

[0086] Figure 8 A schematic top view of an exemplary embodiment of an optoelectronic component described here is shown.

[0087] Identical, similar or identically functioning elements are provided with the same reference numerals in the drawings. The drawings and the size ratios of the elements shown in the drawings to one another are not to be regarded as true to scale. Rather, individual elements may be shown exaggeratedly for better visibility and / or for better understanding.

[0088] Figure 1A and 1B The schematic top views each show an exemplary embodiment of an optoelectronic component described here.

[0089] according to Figure 1A, an optoelectronic component 1 has an optoelectronic semiconductor chip 2, which generates electromagnetic radiation during operation. A metal layer 3 is arranged on the semiconductor chip 2. An outer surface 4 of the metal layer has a structuring 5. The structuring 5 is arranged above an edge region 17 of the optoelectronic semiconductor chip or in an edge region 18 of the metal layer. In a top view, the optoelectronic semiconductor chip 2 and the metal layer 3 completely overlap. The component 1 can be identified by means of the structuring 5.

[0090] The structuring is formed by a recess 11 in the metal layer 3. The recess 11 passes completely through the metal layer 3 in the vertical direction. The bottom of the recess is formed by the optoelectronic semiconductor chip 2. In this case, the metal layer does not have a recess 11 which is completely surrounded by the metal layer 3 and passes completely through the metal layer 3. In other words, the metal layer is formed in a simple continuous manner. Furthermore, the outer surface 4 of the metal layer is formed integrally with the structuring 5.

[0091] The recess 11 forms a plurality of strips 19, each having a certain width and a certain length. The plurality of strips 19 each have a quadrilateral shape, wherein the lengths of the plurality of strips 19 are respectively the same. For example, the plurality of strips have a length of 5 μm to 100 μm (including 5 μm and 100 μm), preferably a length of 6 μm to 20 μm (including 6 μm and 20 μm).

[0092] The widths of the strips 19 are designed differently. For example, the strips have a width of 1 μm to 50 μm (including 1 μm and 50 μm), preferably a width of 2 μm to 15 μm (including 2 μm and 15 μm), and in particular a width of 3 μm to 10 μm.

[0093] By means of the different widths of the bars in the plurality of bars 19 , a bar code is formed, by means of which the component 1 can be unambiguously identified.

[0094] and Figure 1A different, Figure 1B The embodiment of FIG. 4 shows a recess that does not completely pass through the metal layer 3 . In this case, the bottom of the recess 11 is formed by the metal layer 3 .

[0095] Figure 2A A schematic cross-section of Figure 1B The section line AA shown in illustrative figures shows an exemplary embodiment of an optoelectronic component 1 described here.

[0096] According to FIG2 , the semiconductor chip 2 of the optoelectronic component 1 is a laser diode having a semiconductor layer sequence 8 and an active layer 9. The semiconductor chip 2 also has a ridge waveguide 6 having a top surface 6a and a side surface 6b adjoining thereto. The ridge waveguide 6 is formed by a ridge-shaped raised region of the semiconductor layer sequence 8. The ridge waveguide 6 protrudes as a protrusion from a concave outer surface 8a of the semiconductor layer sequence.

[0097] The cover surface 6a of the ridge waveguide is directly connected to the recessed outer surface 8a of the semiconductor layer sequence arranged laterally to the ridge waveguide 6 via the side surface 6b adjacent thereto. The cover surface 6a and the side surface 6b of the ridge waveguide and the recessed outer surface 8a of the semiconductor layer sequence laterally to the ridge waveguide 6 form a stepped profile. In addition, the first main surface 2a of the semiconductor chip includes the cover surface 6a and the side surface 6b of the ridge waveguide and the recessed outer surface 8a of the semiconductor layer sequence laterally to the ridge waveguide 6. The second main surface 2a is arranged opposite to the first main surface 2a.

[0098] Furthermore, the semiconductor chip 2 has a passivation layer 7 which completely covers the side surface 6b of the ridge waveguide. A contact 9 is arranged on the top surface 6a of the ridge waveguide, the side surface of which is likewise covered by the passivation layer 7. The passivation layer 7 additionally covers the recessed outer surface 8a of the semiconductor layer sequence laterally to the ridge waveguide 6. The top surface of the contact 9 is not covered by the passivation layer 7.

[0099] The metal layer 3 is in direct contact with the cover surface of the contact element 9. In addition, the metal layer 3 completely covers the passivation layer 7 of the semiconductor chip 2. The thickness of the metal layer in the vertical direction is, for example, at least 1 micron and at most 5 microns. The thickness along the section line AA is substantially constant over the entire metal layer. Substantially constant means that the thickness can vary due to manufacturing tolerances.

[0100] Figure 2B The schematic cross-section diagram along Figure 1B The section line BB shown in FIG. 1 shows an exemplary embodiment of an optoelectronic component 1 described here.

[0101] In the edge region 18 of the metal layer, the metal layer between the recesses 11 (i.e. along the section line BB) has a thickness that is less than the thickness of the metal layer 3 in the region without the recesses 11. The coverage of the metal layer in the region of the recesses 11 and the side surfaces adjacent thereto and the bottom surface of the recess 11 form a stepped profile.

[0102] Figure 3 A schematic cross-sectional view of Figure 1B The section line BB shown in FIG. 1 shows an exemplary embodiment of an optoelectronic component 1 described here.

[0103] Different from the embodiment in combination with FIG. 2b, according to Figure 3The metal layer 3 of the optoelectronic component 1 is a metal layer stack. The metal layer stack comprises a first metal layer 13 and a second metal layer 14. Furthermore, the metal layer 3 is in direct contact with the cover surface 6a of the ridge waveguide.

[0104] The first metal layer 13 covers the side surface 6b and the cover surface 6a of the ridge waveguide. Furthermore, the first metal layer is partially arranged on the passivation layer 7 over the recessed outer surface 8a of the semiconductor layer sequence. The first metal layer 13 embeds the ridge waveguide 6.

[0105] The second metal layer 14 is embedded in the first metal layer. The second metal layer 14 also covers the passivation layer 7 on the recessed outer surface 8a of the semiconductor layer sequence, which is not covered by the first metal layer 13. In this case, the second metal layer 14 has a recess 11. In a top view, the recess 11 extends without overlapping with the first metal layer 13.

[0106] exist Figure 4 The schematic sectional illustration in a top view of FIG. 1 shows an exemplary embodiment of an optoelectronic component 1 described here.

[0107] according to Figure 4 , combined with Figure 1A and 1B In contrast to the exemplary embodiment of FIG. 1 , the structuring is formed by a roughened region 12 of the metal layer 3 . The roughened region 12 is formed from the same material as the metal layer 3 .

[0108] Figure 5 A schematic cross-sectional view of Figure 4 The section line CC shown in FIG. 1 shows an exemplary embodiment of an optoelectronic component 1 described here.

[0109] Combined with Figure 3 In a different embodiment, the first metal layer 13 comprises a metallic adhesion promoter layer 15 and a metallic barrier layer 16. The interference layer in the edge region 18 of the metal layer is arranged on the first metal layer 13. The roughened region 12 is arranged above the interference layer 20. In these regions, the second metal layer 14 is roughened and has elevations and depressions.

[0110] Fig. 6A , 6B , 6C and 6D show method steps of an exemplary embodiment of a method described here for producing an optoelectronic component 1 .

[0111] First, an optoelectronic semiconductor chip 2 (not shown here) is provided. Fig. 6A , a metal layer 3 is subsequently applied onto the semiconductor chip 2 . The metal layer 2 is a metallic layer stack and comprises a first metal layer 13 and a second metal layer 14 . The second metal layer 14 is arranged on the first metal layer 13 .

[0112] In this embodiment, the first metal layer 13 can include three layers, for example. The layer sequence of the first metal layer 13 is, for example, as follows: Ti—Pt—Pd, wherein the second metal layer is applied on the Pd layer. In this embodiment, the second metal layer 14 can contain Au or be formed of Au, for example.

[0113] In the next method step, the structuring 5 is produced on the outer surface of the second metal layer 14. Figure 6B As shown, recess 11 is produced in second metal layer 14 in an edge region 18 of second metal layer 14. Recess 11 passes completely through second metal layer 14 as far as first metal layer 13.

[0114] according to Figure 6C , the interference layer 20 is applied to the exposed first metal layer 13. For example, the exposed first metal layer 13 can be oxidized by means of an oxygen plasma treatment. Alternatively, it is possible to heat the exposed first metal layer 13 in an oxygen environment. The surface of the exposed first metal layer 13 is thus oxidized and forms, for example, an interference layer 20.

[0115] In a further method step, a further second metal layer 14a is applied to the interference layer 20. The outer surface of the further second metal layer 14a applied to the interference layer 20 has an increased roughness compared to the outer surface of the second metal layer 14. The further second metal layer 14a can be formed from the same metal as the second metal layer 14. Alternatively, the further second metal layer 14a can be formed, for example, from TiPtAu.

[0116] In accordance with Fig.6D In the embodiment of FIG. 1 , the thickness of the other second metal layer 14 a is designed to be smaller than the thickness of the second metal layer 14 .

[0117] Fig. 7A , 7B , 7C and 7D show method steps of an exemplary embodiment of a method described here for producing an optoelectronic component 1 .

[0118] Similar to combining Fig. 6A According to an embodiment of the present invention, an optoelectronic semiconductor chip 2 (not shown here) is provided, on which a Fig. 7A A metal layer 3 is applied.

[0119] Subsequently, according to Figure 7B , the stop layer 21 is applied locally to the metal layer 3 or locally to the second metal layer 14 .

[0120] according to Figure 7CIn the next method step, a further metal layer or further second metal layer 14a is applied electrolytically to the regions not covered by stop layer 21. Compared to the outer surface of second metal layer 14, the outer surface of electrolytically deposited further second metal layer 14a has an increased roughness.

[0121] Afterwards ( Fig.7D ) Remove the stop layer 21. In this embodiment, the thickness of the other second metal layer 14 is greater than the thickness of the second metal layer 14.

[0122] and Figure 1A In contrast to the embodiment in Figure 8 The metal layer 3 has a recess 11 which is completely surrounded by the metal layer 3 and which completely penetrates the metal layer 3 .

[0123] This application claims the priority of German patent application DE 10 2018 131 579.1, the disclosure content of which is incorporated herein by reference.

[0124] The invention is not limited to the description based on the embodiments. Rather, the invention includes each novel feature and each combination of features, which in particular includes each combination of features in the claims, even if the feature or the combination itself is not explicitly described in the claims or embodiments.

[0125] Reference numerals

[0126] 1 Optoelectronic components

[0127] 2 Optoelectronic semiconductor chips

[0128] 2a First main surface of semiconductor chip

[0129] 2b Second main surface of the semiconductor chip

[0130] 3 Metal Layer

[0131] 4 Outer surface of the metal layer

[0132] 5 Structural Department

[0133] 6 Ridge waveguide

[0134] 6a Coverage of ridge waveguide

[0135] 6b Side view of ridge waveguide

[0136] 7 Passivation layer

[0137] 8 Semiconductor layer sequence

[0138] 8a Recessed outer surface of the semiconductor layer sequence

[0139] 9 Active layer

[0140] 10 Contact

[0141] 11 recess

[0142] 12 Coarsening area

[0143] 13. First Metal Layer

[0144] 14 Second Metal Layer

[0145] 14a Another second metal layer

[0146] 15 Metal Adhesion Promoter Layer

[0147] 16 Metal Barrier Layer

[0148] 17 Edge area of ​​semiconductor chip

[0149] 18 Edge area of ​​metal layer

[0150] 19 More than one

[0151] 20 Interference Layer

[0152] 21 Stop layer

Claims

1. An optoelectronic component (1), comprising: an optoelectronic semiconductor chip (2) which generates electromagnetic radiation during operation, and - a metal layer (3) arranged on the semiconductor chip (2), wherein - the outer surface (4) of the metal layer has a structuring (5), - the component (1) can be identified by means of the structuring (5), - the metal layer (3) is formed continuously, - the metal layer (3) is a metallic layer stack, - the layer stack comprises a first metal layer (13) and a second metal layer (14), - the second metal layer (14) comprises a roughened area (12), - an interference layer (20) is arranged between the roughened region (12) and the first metal layer (13), The roughened region (12) forms the structuring (5), and - The metal layer (3) is designed as a heat sink.

2. The optoelectronic component (1) according to claim 1, Therein, no non-metallic elements are applied to the outer surface (4) of the metal layer.

3. The optoelectronic component (1) according to claim 1, The metal layer (3) is designed as a contact layer for electrically contacting the semiconductor chip (2).

4. The optoelectronic component (1) according to claim 1, The metal layer (3) is a functional layer of the component (1) and performs multiple functions.

5. The optoelectronic component (1) according to claim 1, wherein: The semiconductor chip (2) has a ridge waveguide (6), the ridge waveguide having a top surface (6a) and side surfaces (6b) adjoining the top surface, and - A passivation layer (7) covers the side surfaces (6b) of the ridge waveguide.

6. The optoelectronic component (1) according to claim 5, The metal layer (3) is in direct contact with the cover surface (6a) of the ridge waveguide.

7. The optoelectronic component (1) according to claim 5, In this case, in a plan view, the structuring (5) extends without overlapping the top surface (6a) of the ridge waveguide.

8. The optoelectronic component (1) according to claim 1, The structured portion (5) comprises a recess (11).

9. The optoelectronic component (1) according to claim 8, At least a portion of the recess (11) completely passes through the metal layer (3).

10. The optoelectronic component (1) according to claim 8, At least a portion of the recess (11) partially passes through the metal layer (3).

11. The optoelectronic component (1) according to claim 1, The structuring (5) forms a barcode for identifying the component.

12. The optoelectronic component (1) according to claim 1, The first metal layer includes a metal adhesion promoter layer (15) and a metal barrier layer (16).

13. A method for producing an optoelectronic component (1) according to claim 1, comprising the following steps: - providing an optoelectronic semiconductor chip (2), - applying a metal layer (3) on the optoelectronic semiconductor chip (2), and - Producing a structuring (5) on the outer surface (4) of the metal layer.

Images