Semiconductor transistor device and method for forming the same

Abstract

A semiconductor transistor device includes a channel structure, a gate structure, a first source / drain epitaxial structure, a second source / drain epitaxial structure, a gate contact, and a back source / drain contact. The gate structure wraps the channel structure. The first source / drain epitaxial structure and the second source / drain epitaxial structure are arranged on opposite ends of the channel structure. The gate contact is arranged on the gate structure. The back source / drain contact is arranged below the first source / drain epitaxial structure. The first source / drain epitaxial structure has a concave bottom surface in contact with the back source / drain contact. Embodiments of the present application also relate to a method for forming a semiconductor transistor device.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor transistor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be manufactured using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor transistor device, including: a channel structure; a gate structure wrapping the channel structure; a first source / drain epitaxial structure and a second source / drain epitaxial structure, arranged on opposite ends of the channel structure; a gate contact, arranged on the gate structure; and a back source / drain contact, arranged below the first source / drain epitaxial structure; wherein the first source / drain epitaxial structure has a concave bottom surface in contact with the back source / drain contact.

[0004] Other embodiments of the present application provide a semiconductor transistor device, including: a channel structure; a gate structure wrapping the channel structure; a first source / drain epitaxial structure and a second source / drain epitaxial structure, arranged on opposite ends of the channel structure; a gate contact arranged on the gate structure; and a back source / drain contact arranged below the first source / drain epitaxial structure and in contact with the first source / drain epitaxial structure; and a back dielectric cap arranged below the second source / drain epitaxial structure and the gate structure and in contact with the second source / drain epitaxial structure and the gate structure.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor transistor device, the method comprising: forming a fin structure above a substrate by alternately stacking a first semiconductor layer and a second semiconductor layer; forming a dummy gate structure above the fin structure; removing a portion of the fin structure not covered by the dummy gate structure; forming an internal spacer on opposite sides of the remaining portion of the first semiconductor layer; forming a first source / drain epitaxial structure and a second source / drain epitaxial structure on opposite ends of the fin structure; replacing the dummy gate structure and the first semiconductor layer with a metal gate structure; removing the substrate and forming a back-side covering trench to expose the bottom surface of the metal gate structure and the bottom surface of the second source / drain epitaxial structure, wherein the bottom surface of the second source / drain epitaxial structure is recessed; forming a back-side dielectric cap in the back-side covering trench; and forming a back-side source / drain contact in contact with the first source / drain epitaxial structure below the first source / drain epitaxial structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of semiconductor transistor devices having backside power rails are shown.

[0008] Figure 2 Cross-sectional views of some additional embodiments of semiconductor transistor devices having backside power rails are shown.

[0009] Figure 3 Cross-sectional views of some additional embodiments of semiconductor transistor devices having backside power rails are shown.

[0010] Figure 4 Cross-sectional views of some additional embodiments of semiconductor transistor devices having backside power rails are shown.

[0011] Figure 5 A perspective view of some embodiments of a semiconductor transistor device having a backside power rail is shown.

[0012] Fig. 6A It is along Figure 5 A cross-sectional view of some embodiments of a semiconductor transistor device taken along line AA'.

[0013] Figure 6B It is along Figure 5 A cross-sectional view of some embodiments of a semiconductor transistor device taken along line BB'.

[0014] Figure 6C It is along Figure 5 A cross-sectional view of some embodiments of a semiconductor transistor device taken along line CC'.

[0015] Figures 7 to 27B Various views of some embodiments of a method of forming a semiconductor transistor device having a backside power rail are shown at various stages.

[0016] Fig.28 Shows the corresponding Figures 7 to 27B Flowcharts of some embodiments of the method. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0019] As used herein, "approximately," "about," "approximately," or "substantially" shall generally mean within 20% or within 10% or within 5% of a given value or a given range. The numerical values ​​given herein are approximate, meaning that if not explicitly stated, the term "approximately," "about," "approximately," or "substantially" can be inferred.

[0020] The all-around gate (GAA) transistor structure can be patterned by any suitable method. For example, these structures can be patterned using one or more lithography processes, including a double patterning process or a multi-patterning process. Typically, the double patterning or multi-patterning process combines the lithography process with a self-alignment process to enable the formation of a pattern having a spacing smaller than the spacing that could be obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure. After the GAA transistor structure is formed, an interconnect structure can be formed thereover, the interconnect structure including power rails and signal lines arranged in an interlayer dielectric (ILD) layer.

[0021] As semiconductor processes continue to shrink (e.g., beyond 3nm), current power rail designs will suffer from complex metal layer routing in the back end of line (BEOL). Due to the complex metal layer routing, more masks are required, and voltage drop (also known as IR drop) is affected when metal lines become thinner.

[0022] In view of the above, the present invention is directed to a semiconductor transistor device with a backside power rail and a method for manufacturing the same. By moving the power rail from the front side to the back side of the semiconductor transistor device, metal layer wiring becomes easy in the BEOL. Therefore, fewer masks are required, IR drop is improved, and both the power rail area and the active area can be enlarged.

[0023] More specifically, some embodiments of the present invention relate to a GAA device. The GAA device includes: a channel structure; a gate structure, the gate structure wrapping the channel structure; a first source / drain epitaxial structure and a second source / drain epitaxial structure, the first source / drain epitaxial structure and the second source / drain epitaxial structure being arranged on opposite ends of the channel structure; and a gate contact, the gate contact being arranged on the gate structure. The GAA device also includes: a backside source / drain contact, the backside source / drain contact falling on the recessed bottom surface of the first source / drain epitaxial structure; and a backside power rail, the backside power rail being arranged below the backside source / drain contact and connected thereto. The backside source / drain contact and the backside power rail may include, for example, a metal material. In some embodiments, the bottom surface of the first source / drain epitaxial structure may be recessed to a position vertically deeper than the bottom surface of the gate structure or the channel structure. Therefore, the cell capacitance may be reduced.

[0024] In some embodiments, before forming the first source / drain epitaxial structure, a backside source / drain contact is self-alignedly formed by forming a sacrificial backside contact. Later, the dummy backside contact is selectively removed and replaced with a backside source / drain contact, thereby eliminating the overlay offset of the contact landing.

[0025] In some additional embodiments, the GAA device further comprises a backside dielectric cap disposed below the gate structure and the second source / drain epitaxial structure. The backside dielectric cap may comprise an oxide, a nitride, a carbonitride, or a low-κ dielectric material. The backside dielectric cap replaces the original semiconductor body material and thereby reduces the cell capacitance, thereby eliminating current leakage issues, such as leakage between the gate structure and the backside source / drain contacts.

[0026] In addition, the second source / drain epitaxial structure may have a recessed bottom surface. The bottom surface of the second source / drain epitaxial structure may be recessed to a position vertically aligned with the bottom surface of the gate structure or even deeper. Therefore, the cell capacitance may be further reduced.

[0027] The GAA devices proposed herein include p-type GAA devices or n-type GAA devices. In addition, the GAA device may have one or more channel regions (e.g., semiconductor nanowires, nanodots, etc.) associated with a single continuous gate structure or multiple gate structures. A person of ordinary skill in the art may recognize other examples of semiconductor transistor devices that may benefit from various aspects of the present invention. The GAA device may be part of an integrated circuit (IC) and may include static random access memory (SRAM), logic circuits, passive components such as resistors, capacitors, and inductors) and / or active components such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof.

[0028] Figure 1A cross-sectional view of a semiconductor transistor device 100 according to some embodiments is shown. The semiconductor transistor device 100 includes a channel structure 102 and a gate structure 104 that wraps the channel structure 102. The channel structure 102 may include a stack of semiconductor layers separated and surrounded by a stack of metal features of the gate structure 104. A first source / drain epitaxial structure 106 and a second source / drain epitaxial structure 108 are arranged on opposite ends of the channel structure 102. An internal spacer 128 is arranged on opposite ends of the metal features of the gate structure 104 to isolate the gate structure 104 from the first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108. In some embodiments, the gate spacer 134 is arranged along opposite sidewalls of the upper portion of the gate structure 104. The outer surface of the inner spacer 128 may be substantially coplanar with the outer surface of the channel structure 102 and / or the gate spacer 134. In some embodiments, an upper isolation structure 220 is arranged in a trench between the gate spacers 134. The upper isolation structure 220 provides electrical insulation between the gate structures 104. As an example, the channel structure 102 can be a pure silicon layer without doping p-type impurities and n-type impurities. The thickness range of the channel structure 102 can be in the range between about 3nm and about 15nm. As an example, the gate structure 104 can include a gate dielectric material such as a high κ material (κ is greater than 7), a work function metal material, and a fill metal material such as tungsten or aluminum. The thickness of the gate structure 104 can be in the range between about 2nm and about 10nm. In some embodiments, the first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108 include semiconductor materials such as silicon, germanium or silicon germanium. The first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108 can be hexagonal or rhombus-shaped. In some embodiments, the first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108 have different conductivity types. For example, the first source / drain epitaxial structure 106 may be an N-type epitaxial structure and the second source / drain epitaxial structure 108 may be a P-type epitaxial structure, or vice versa. The first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108 may be the source and drain of the semiconductor transistor device 100, respectively.

[0029] On the front side of the semiconductor transistor device 100, a front side interconnect structure 114 can be arranged above the gate structure 104 and the first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108. The front side interconnect structure 114 may include a plurality of front side metal layers 116, which are arranged in and surrounded by the front side interlayer dielectric layer 112. The front side metal layer 116 includes vertical interconnects such as vias or contacts, and horizontal interconnects such as metal lines. The front side interconnect structure 114 electrically connects various features or structures of the semiconductor transistor device. For example, a gate contact 110 can be arranged on the gate structure 104 and connected to an external circuit through the front side metal layer 116.

[0030] In some embodiments, on the back side of the semiconductor transistor device 100, a back side source / drain contact 120 is arranged below the first source / drain epitaxial structure 106 and connects the first source / drain epitaxial structure 106 to a back side power rail 122 arranged below the back side source / drain contact 120. In some embodiments, a dielectric sidewall spacer 118 is arranged along the sidewall of the back side source / drain contact 120 and separates the back side source / drain contact 120 from the back side dielectric cap 126. The back side source / drain contact 120 and the back side power rail 122 may include, for example, a metal material. For example, the back side source / drain contact 120 may include a metal such as tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), copper (Cu), or other suitable materials. Therefore, the first source / drain epitaxial structure 106 may be connected to an external circuit from the back side of the semiconductor transistor device 100 through the back side source / drain contact 120. Thus, greater metal routing flexibility is provided and cell capacitance can be reduced.

[0031] Furthermore, the backside source / drain contact 120 may fall on the recessed bottom surface 106b of the first source / drain epitaxial structure 106. In some embodiments, the bottom surface 106b of the first source / drain epitaxial structure 106 may be recessed into a convex shape, reaching a position vertically deeper than the bottom surface 104b of the gate structure 104.

[0032] Also in some embodiments, on the back side of the semiconductor transistor device 100, a backside dielectric cap 126 is disposed under the gate structure 104. The backside dielectric cap 126 may also extend under the second source / drain epitaxial structure 108. The backside dielectric cap 126 replaces the original semiconductor body material, helps to separate and insulate the gate structure 104 and the backside source / drain contacts 120, thereby reducing cell capacitance and eliminating current leakage issues, such as leakage between the gate structure 104 and the backside source / drain contacts 120. The backside dielectric cap 126 may include oxide, nitride, carbonitride, or low-κ dielectric material.

[0033] Figure 2 2 shows a cross-sectional view of a semiconductor transistor device 200 having a backside power rail according to some embodiments. Figure 1 In addition to the disclosed features, in some other embodiments, the bottom surface 106b of the first source / drain epitaxial structure 106 may be more deeply recessed to a position vertically exceeding the bottom surface 102b of the channel structure 102. Figure 1 Compared with the semiconductor transistor device 100 of FIG. 1 , the cell capacitance is further reduced, wherein the bottom surface 106 b of the first source / drain epitaxial structure 106 is below the bottom of the channel structure 102 .

[0034] Figure 3 0 shows a cross-sectional view of a semiconductor transistor device 300 having a backside power rail according to some embodiments. Figure 1 and Figure 2 In addition to the disclosed features, in some other embodiments, the bottom surface 108b of the second source / drain epitaxial structure 108 may be recessed back to a position flush with the bottom surface 104b of the gate structure 104 and have a Figure 1 and Figure 2 The concave shape shown. Figure 1 and Figure 2 Compared with the semiconductor transistor devices 100 and 200, the cell capacitance can be further reduced.

[0035] Figure 4 4 shows a cross-sectional view of a semiconductor transistor device 400 with a backside power rail according to some embodiments. In addition to the features disclosed above, in some other embodiments, the bottom surface 108b of the second source / drain epitaxial structure 108 can be recessed to a position vertically deeper than the bottom surface 104b of the gate structure 104 and aligned with the bottom surface 104b of the gate structure 104. Figure 1 and Figure 2 Compared with the semiconductor transistor devices 100, 200, and 300, the cell capacitance can be further reduced.

[0036] Figure 5 According to some embodiments Figure 4 A perspective view of a semiconductor transistor device 400 is shown. Figure 4 can be considered as following Figure 5 Cross-sectional view taken in the x direction. FIG. 6A to FIG. 6C can be considered as Figure 5 A cross-sectional view taken along the y direction in the gate region, the first source / drain region and the second source / drain region of the transistor. Optionally, Figures 4 to 6C Other figures below may also individually illustrate different embodiments, and features discussed in association with one figure may be incorporated into another figure where applicable.

[0037] like Figures 5 to 6C As shown, in some embodiments, the lower isolation structure 160, the middle isolation structure 132 and the hard mask 136 can be used together as an insulating structure to separate the two semiconductor transistor devices 400a and 400b along the y direction. Fig. 6A As shown, in some embodiments, the gate structure 104 includes a gate dielectric layer 232 and a gate electrode 230. The gate electrode 230 includes one or more work function metal layers and a fill metal. The gate dielectric layer 232 lining the outer surface of the gate electrode 230 may be conformally formed. The gate dielectric layer 232 may contact the lower isolation structure 160 and the channel structure 102. In some embodiments, the gate dielectric layer 232 includes a high-κ material (κ greater than 7), such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum hafnium oxide (HfAlO2), silicon hafnium oxide (HfSiO2), aluminum oxide (Al2O3) or other suitable materials.

[0038] like Figure 5 and Figure 6C As shown, the first source / drain epitaxial structure 106 may have a recessed bottom surface (eg, convex) and a backside source / drain contact 120 electrically coupled to the recessed bottom surface. Figure 5 , Fig. 6A and Figure 6B As shown, the second source / drain epitaxial structure 108 may have a recessed bottom surface (e.g., convex) and a backside dielectric cap 126 disposed directly below the second source / drain epitaxial structure 108 and the gate structure 104. The backside dielectric cap 126 may be surrounded by a lower isolation structure 160. In some embodiments, an air gap 192 may be formed around the lower portions of the first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108.

[0039] Figures 7 to 27B A method for manufacturing a semiconductor transistor device at various stages according to some embodiments of the present invention is shown. In some embodiments, Figures 7 to 27B The semiconductor transistor devices shown in the figure may be intermediate devices fabricated during processing of an integrated circuit (IC) or a portion thereof, which intermediate devices may include static random access memory (SRAM), logic circuits, passive components such as resistors, capacitors and inductors and / or active components such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof.

[0040] like Figure 7As shown in the perspective view of FIG. 1 , in some embodiments, a stacked structure 150 is formed on a substrate 140. In some embodiments, the substrate 140 may be a portion of a wafer and may include silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or other suitable semiconductor materials. In some embodiments, the substrate 140 is a semiconductor on insulator (SOI) structure, which includes a bulk substrate 142, an insulator substrate layer 144 on the bulk substrate 142, and a semiconductor substrate layer 146 on the insulator substrate layer 144. In various embodiments, the substrate 140 may include any of a variety of substrate structures and materials.

[0041] The stacked structure 150 includes alternately stacked first semiconductor layers 152 and second semiconductor layers 154. The first semiconductor layer 152 will be used as a channel region of a semiconductor transistor device, and the second semiconductor layer 154 is a sacrificial layer that will be subsequently removed and replaced with a gate material. The first semiconductor layer 152 and the second semiconductor layer 154 are made of materials with different lattice constants, and may include one or more Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP layers. In some embodiments, the first semiconductor layer 152 and the second semiconductor layer 154 are made of Si, Si compounds, SiGe, Ge, or Ge compounds. The stacked structure 150 may be formed on the substrate 140 by epitaxy, so that the stacked structure 150 forms a crystalline layer. Although Figure 7 Four layers of the first semiconductor layer 152 and three layers of the second semiconductor layer 154 are shown, but the number of layers is not limited thereto, and the number of layers of each layer can be as small as 1. In some embodiments, 2-10 layers of each of the first semiconductor layer and the second semiconductor layer are formed. By adjusting the number of stacked layers, the drive current of the semiconductor transistor device can be adjusted.

[0042] In some embodiments, the first semiconductor layer 152 may be a pure silicon layer without germanium. The first semiconductor layer 152 may also be a substantially pure silicon layer, for example, with a germanium atomic percentage of less than about 1%. In addition, the first semiconductor layer 152 may be intrinsic, which is not doped with p-type impurities and n-type impurities. In some embodiments, the thickness of the first semiconductor layer 152 is in a range between about 3 nm and about 15 nm.

[0043] In some embodiments, the second semiconductor layer 154 may be a SiGe layer having a germanium atomic percentage greater than zero. In some embodiments, the germanium percentage of the second semiconductor layer 154 is in a range between about 10% and about 50%. In some embodiments, the thickness of the second semiconductor layer 154 is in a range between about 2 nm and about 10 nm.

[0044] like Figure 8As shown in the perspective view, in some embodiments, the stacked structure 150 (see Figure 7 ) is patterned to form a fin structure 156 and a trench 158 extending in the X direction. In some embodiments, the stacked structure 150 is patterned by performing an etching process using the patterned mask layer 157 as an etching mask, thereby removing the portion of the stacked structure 150 not covered by the mask layer 157. In this process, the semiconductor substrate layer 146 may also be partially removed or completely removed. The mask layer 157 may include a first mask layer and a second mask layer. The first mask layer may be a pad oxide layer made of silicon oxide, which may be formed by thermal oxidation. The second mask layer may be made of silicon nitride (SiN), which is formed by chemical vapor deposition (CVD), including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes. The mask layer 157 may be patterned using a variety of patterning techniques. Figure 8 Two fin structures 156 arranged in the Y direction and parallel to each other are shown, but the number of fin structures is not limited thereto and may be as small as one and three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structure 156 to improve pattern fidelity during patterning operations.

[0045] like Fig. 9 As shown in the perspective view of FIG. 1 , in some embodiments, a lower isolation structure 160 is formed above the insulator substrate layer 144 in the lower portion of the trench 158, which is also referred to as a shallow trench isolation (STI) structure. The upper portion of the fin structure 156 is exposed from the lower isolation structure 160. The lower isolation structure 160 may be formed by forming an insulating material above the insulator substrate layer 144 and then performing a planarization operation. Then, the insulating material is recessed to form the lower isolation structure 160, thereby exposing the upper portion of the fin structure 156. The insulating material may include a dielectric material such as a nitride (e.g., silicon nitride, silicon oxynitride, silicon oxycarbon nitride, silicon carbon nitride), a carbide (e.g., silicon carbide, silicon oxycarbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-κ dielectric constant material having a dielectric constant less than 7 (e.g., carbon-doped oxide, SiCOH), and the like. In some embodiments, the lower isolation structure 160 is formed by various steps including thermal oxidation or a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PECVD, atomic layer deposition (ALD), sputtering, etc.) and a removal process (e.g., wet etching, dry etching, chemical mechanical planarization (CMP), etc.).

[0046] like Fig.10As shown in the perspective view of FIG. 1 , in some embodiments, a cladding semiconductor layer 161 is formed over the outer surface of the fin structure 156. In some embodiments, the cladding semiconductor layer 161 includes a semiconductor material such as germanium, silicon germanium, etc. In some embodiments, the cladding semiconductor layer 161 includes the same material as the second semiconductor layer 154. In addition, in some embodiments, the cladding semiconductor layer 161 can be formed by an epitaxial growth process or a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.).

[0047] like Fig.11 As shown in the perspective view of FIG. 1 , in some embodiments, an intermediate isolation structure 132 is formed above the lower isolation structure 160 between the fin structures 156. A dielectric liner 130 may be formed between the intermediate isolation structure 132 and the lower isolation structure 160 along the sidewalls of the capping semiconductor layer 161 and the lower isolation structure 160. A hard mask 136 may then be formed on top of the intermediate isolation structure 132 and the dielectric liner 130. The intermediate isolation structure 132 and the dielectric liner 130 provide electrical insulation between the fin structures 156, and the hard mask 136 prevents the intermediate isolation structure 132 from being lost during future patterning steps.

[0048] In some embodiments, dielectric liner 130, intermediate isolation structure 132, and hard mask 136 are formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.) and a removal process (e.g., etching, chemical mechanical planarization (CMP), etc.). The top surface of intermediate isolation structure 132 may be below the top surface of fin structure 156. Fig.11 In some embodiments not shown in FIG. 1 , the planarization process of the hard mask 136 may also remove the capping semiconductor layer 161 from above the fin structure 156. The top surface of the hard mask 136 may be coplanar with the top surface of the fin structure 156. In some embodiments, the dielectric liner 130 and the intermediate isolation structure 132 and the lower isolation structure 160 may each include a low-κ dielectric material having a dielectric constant less than 7, such as silicon oxynitride, carbon silicon nitride, silicon oxycarbide, silicon oxycarbon nitride, silicon nitride, or other suitable low-k dielectric materials. The dielectric liner 130 may include a different material than the intermediate isolation structure 132 for a selective removal process. The hard mask 136 may include a high-κ dielectric material having a dielectric constant greater than 7, such as hafnium oxide, zirconium oxide, aluminum hafnium oxide, silicon hafnium oxide, aluminum oxide, or some other suitable high-κ dielectric material.

[0049] like Fig.12As shown in the perspective view of FIG. 1 , in some embodiments, the hard mask 136 is selectively removed from the top of the fin structure 156. The top surfaces of the first semiconductor layer 152 and the cladding semiconductor layer 161 can be exposed from the removal process. In some embodiments, the hard mask 136 is selectively etched by, for example, a dry etching process and / or a wet etching process.

[0050] like Fig.13 As shown in the perspective view of FIG. 1 , in some embodiments, a dummy gate structure 170 spaced apart from each other in the x direction is formed over the fin structure 156 along the y direction. In some embodiments, the dummy gate structure 170 may include a sacrificial gate dielectric layer 162, a sacrificial gate electrode layer 164, a pad layer 166, and a mask layer 168, which are stacked one above the other in the stated order. Fig.13 Two dummy gate structures 170 are shown in FIG. 1 , but the number of dummy gate structures 170 is not limited thereto and may be greater than or less than two. In some embodiments, the sacrificial gate dielectric layer 162 may include, for example, a dielectric material such as a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), or other suitable materials. The sacrificial gate electrode layer 164 may include, for example, polysilicon. The pad layer 166 and the mask layer 168 may include thermal oxide, nitride, and / or other hard mask materials and may be formed by a photolithography process.

[0051] Subsequently, gate spacers 134 are formed along opposite sidewalls of the dummy gate structure 170. For example, a blanket layer of insulating material for sidewall spacers is conformally formed to cover the dummy gate structure 170 by using plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), etc. The blanket layer is deposited in a conformal manner so that it is formed to have substantially equal thickness on vertical surfaces, such as on the sidewalls, horizontal surfaces, and top of the dummy gate structure 170. In some embodiments, the insulating material of the blanket layer may include a silicon nitride-based material. Then, the blanket layer is etched using an anisotropic process to form gate spacers 134 on opposite sidewalls of the dummy gate structure 170.

[0052] like Fig.14A Stereoscopic image, Fig. 14B The x-direction cross-sectional view, Fig. 14C A cross-sectional view in the y direction in the gate region and Fig.14DAs shown in the y-direction cross-sectional view in the source region or the drain region, in some embodiments, a removal process is performed according to the dummy gate structure 170 to remove the fin structure 156 from the first source / drain region 176 and the second source / drain region 178. Therefore, the first semiconductor layer 152 and the second semiconductor layer 154 are shortened along the x-direction and can be vertically aligned with the gate spacer 134. As an example, the exposed portion of the fin structure 156 is removed by using a strained source / drain (SSD) etching process. The SSD etching process can be performed in a variety of ways. In some embodiments, the SSD etching process can be performed by dry chemical etching using a plasma source and a reactive gas. The plasma source can be an inductively coupled plasma (ICR) etching, a transformer coupled plasma (TCP) etching, an electron cyclotron resonance (ECR) etching, a reactive ion etching (RIE), etc., and the reactive gas can be a fluorine-based gas, chloride (Cl2), hydrogen bromide (HBr), oxygen (O2), etc. or a combination thereof. In some other embodiments, the SSD etching process may be performed by wet chemical etching, such as ammonium peroxide mixture (APM), ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), combinations thereof, and the like. In yet other embodiments, the SSD etching step may be performed by a combination of dry chemical etching and wet chemical etching. In addition, in some embodiments, the removal process may also remove the upper portion of the semiconductor substrate layer 146 between the dummy gate structures 170 after removing the bottommost first semiconductor layer 152. The semiconductor substrate layer 146 or the bottommost first semiconductor layer 152 may have a concave top surface along the x-direction in the first source / drain region 176 and the second source / drain region 178. The top surface may be recessed between the lower isolation structures 160.

[0053] In addition, the removal process may further include an isotropic etchant to further remove the end of the second metal layer 154 below the gate spacer 134 and / or the dummy gate structure 170. Therefore, after the removal process, the first semiconductor layer 152 is wider than the second semiconductor layer 154 in the x-direction. After the removal process, the first semiconductor layer 152 may be formed into a channel structure of a transistor device. It should be understood that the channel structure may exhibit a stacked rectangular shape, such as Fig. 14B As shown in the cross-sectional views of other figures, in other embodiments, the channel structure may have other shapes, such as circle, octagon, ellipse, diamond, etc.

[0054] like Fig.15A The stereogram and Fig. 15BAs shown in the x-direction cross-sectional view of FIG. 1 , in some embodiments, an inner spacer 128 having an outermost wall in the x-direction is formed on the end of the second semiconductor layer 154. The outermost wall of the inner spacer 128 may be substantially coplanar with the outer surface of the first semiconductor layer 152 and / or the gate spacer 134. In some embodiments, the inner spacer 128 is formed by a deposition process (e.g., CVD, PVD, PE-CVD, ALD, sputtering, etc.), and then a selective removal process (e.g., etching) may be performed. For example, in some embodiments, a continuous layer may first be formed along the sidewall and over the dummy gate structure 170. Then, a vertical etching process may be performed to remove the portion of the continuous layer that is not vertically covered by the gate spacer 134 to form the inner spacer 128. In addition, in some embodiments, the inner spacer 128 comprises a low-k dielectric material (i.e., a dielectric constant less than 7), such as silicon oxynitride, silicon carbide, silicon oxycarbon, silicon oxynitride carbon, silicon nitride or other suitable materials.

[0055] like Fig.16A Stereoscopic image, Fig. 16B The x-direction cross-sectional view and Fig. 16C As shown in the y-direction cross-sectional view of the first source / drain region, in some embodiments, a first sacrificial source / drain contact 180 is formed below the first source / drain region 176, wherein the hard mask layer 182 covers the second source / drain region 178. In some embodiments, a trench is first formed by etching a portion of the first semiconductor layer 152 and / or the semiconductor substrate layer 146 directly below the first source / drain region 176. Then, a sacrificial material is filled in the trench to form the first sacrificial source / drain contact 180. In some embodiments, the first sacrificial source / drain contact 180 may include a SiGe material having a germanium atomic percentage greater than zero. In some embodiments, the germanium percentage of the first sacrificial source / drain contact 180 is in a range between about 10% and about 50%. In some embodiments, the first sacrificial source / drain contact 180 includes the same material as the second semiconductor layer 154. Furthermore, in some embodiments, the first sacrificial source / drain contact 180 may be formed by an epitaxial growth process or a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.) By forming the trench and the first sacrificial source / drain contact 180 therein, a source / drain contact may be self-alignedly formed later by replacing the first sacrificial source / drain contact 180, thereby eliminating an overlay offset of the contact landing.

[0056] like Fig.17A Stereoscopic image, Fig. 17B The x-direction cross-sectional view, Fig. 17C A y-direction cross-sectional view of the first source / drain region and Fig.17DAs shown in the y-direction cross-sectional view of the second source / drain region, in some embodiments, a first source / drain epitaxial structure 106 and a second source / drain epitaxial structure 108 are formed on opposite sides of the dummy gate structure 170 (see Fig. 17B ). In some embodiments, the first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108 may directly contact the end of the first semiconductor layer 152. The first source / drain epitaxial structure 106 may be formed on the first sacrificial source / drain contact 180 (see Fig. 17C A second source / drain epitaxial structure 108 may be formed on the bottom first semiconductor layer 152 or the semiconductor substrate layer 146 (see Fig.17D ). The first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108 may be the source and drain of the semiconductor transistor device, respectively. In some embodiments, the first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108 include semiconductor materials. For example, the first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108 may include silicon, germanium, or silicon germanium. In some embodiments, the first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108 are formed by an epitaxial growth process. The first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108 may be hexagonal in shape or diamond in shape. An air gap 192 may be formed around the lower portion of the first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108.

[0057] like Fig.18A Stereoscopic image, Fig.18B The x-direction cross-sectional view, Fig.18C A y-direction cross-sectional view of the first source / drain region and Fig.18DAs shown in the y-direction cross-sectional view in the second source / drain region, in some embodiments, an upper isolation structure 220 is formed above a previously formed structure covering the first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108. A planarization process is then performed to lower the gate spacer 134 and expose the sacrificial gate dielectric layer 162 and the sacrificial gate electrode layer 164 on the same horizontal plane. Although not shown in the figure, an etch stop liner that lines the structure previously formed before forming the upper isolation structure 220 can be conformally formed. The etch stop liner can have tensile stress and can be formed of Si3N4. In some other embodiments, the etch stop liner includes a material such as oxynitride. In some other embodiments, the etch stop liner can have a composite structure including multiple layers, such as a silicon nitride layer covering a silicon oxide layer. The etch stop liner can be formed using plasma enhanced CVD (PECVD), but other suitable methods such as low pressure CVD (LPCVD), atomic layer deposition (ALD), etc. can also be used. The upper isolation structure 220 may be formed by chemical vapor deposition (CVD), high density plasma CVD, spin coating, sputtering, or other suitable methods. In some embodiments, the upper isolation structure 220 includes silicon oxide. In some other embodiments, the upper isolation structure 220 may include silicon oxynitride, silicon nitride, a compound including Si, O, C, and / or H (e.g., silicon oxide, SiCOH, and SiOC), a low-κ material, or an organic material (e.g., a polymer). The planarization operation may include a chemical mechanical process (CMP).

[0058] like Fig.19A Stereoscopic image, Fig.19B The x-direction cross-sectional view, Fig.19C As shown in the y-direction cross-sectional view in the gate region, in some embodiments, a replacement gate process is performed to form the gate structure 104. The sacrificial gate dielectric layer 162 and the sacrificial gate electrode layer 164 are removed, thereby exposing the first semiconductor layer 152 and the second semiconductor layer 154. During the removal of the sacrificial gate dielectric layer 162 and the sacrificial gate electrode layer 164, the upper isolation structure 220 protects the first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108. The sacrificial gate electrode layer 164 can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 164 is polysilicon and the upper isolation structure 220 is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer 164. The sacrificial gate electrode layer 164 can be removed using plasma dry etching and / or wet etching. Subsequently, the sacrificial gate dielectric layer 162 is also removed. In this way, the first semiconductor layer 152 and the second semiconductor layer 154 are exposed.

[0059] Then, the second semiconductor layer 154 and the cladding semiconductor layer 161 are removed or etched using an etchant that can selectively etch the second semiconductor layer 154 and the cladding semiconductor layer 161 at a faster etching rate than etching the first semiconductor layer 152 (see Fig. 14C The inner spacer 128 protects the first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108 from the etchant used to etch the second semiconductor layer 154 and the cladding semiconductor layer 161 because the inner spacer 128 is made of a material having an etching selectivity to the material of the second semiconductor layer 154 and the cladding semiconductor layer 161.

[0060] Then, a gate structure 104 is formed and / or filled between the gate spacer 134 and the inner spacer 128. That is, the gate structure 104 surrounds (or surrounds or wraps) the first semiconductor layer 152, wherein the first semiconductor layer 152 is referred to as a channel of a semiconductor transistor device. The gate spacer 134 is arranged on opposite sides of the gate structure 104. The gate structure 104 includes a gate dielectric layer 232 and a gate electrode 230. The gate electrode 230 includes one or more work function metal layers and a filling metal. The gate dielectric layer 232 can be formed conformally. That is, the gate dielectric layer 232 contacts the lower isolation structure 160 and the first semiconductor layer 152. In some embodiments, the gate dielectric layer 232 contains a high κ material (κ greater than 7), such as hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum hafnium oxide (HfAlO2), silicon hafnium oxide (HfSiO2), aluminum oxide (Al2O3) or other suitable materials. In some embodiments, the gate dielectric layer 232 may be formed by performing an ALD process or other suitable process.

[0061] The work function metal layer of the gate electrode 230 is formed on the gate dielectric layer 232, and in some embodiments, the work function metal layer surrounds the first semiconductor layer 152. The work function metal layer may include materials such as titanium nitride (TiN), tantalum (TaN), titanium aluminum silicon (TiAlSi), titanium silicon nitride (TiSiN), titanium aluminum (TiAl), tantalum aluminum (TaAl) or other suitable materials. In some embodiments, the work function metal layer may be formed by performing an ALD process or other suitable process. The filling metal of the gate electrode 230 fills the remaining space between the gate spacers 134 and between the internal spacers 128. That is, the work function metal layer is in contact with the gate dielectric layer 232 and the filling metal and between them. The filling metal may include materials such as tungsten or aluminum. After the gate dielectric layer 232 and the gate electrode 230 are deposited, a planarization process such as a CMP process may then be performed to remove excess portions of the gate dielectric layer 232 and the gate electrode 230 to form the gate structure 104.

[0062] In some embodiments, an interfacial layer (not shown) is optionally formed before forming the gate structure 104 to surround the exposed surface of the first semiconductor layer 152 and the exposed surface of the semiconductor substrate layer 146. In various embodiments, the interfacial layer may include a dielectric material such as silicon oxide (SiO2) or silicon oxynitride (SiON), and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods.

[0063] like Fig. 20 As shown in the perspective view of FIG. 1 , in some embodiments, a front-side interconnect structure 114 is formed above the gate structure 104 and the first source / drain epitaxial structure 106 and the second source / drain epitaxial structure 108. The front-side interconnect structure 114 may include a plurality of front-side metal layers 116, which are arranged in and surrounded by the front-side interlayer dielectric layer 112. The front-side interconnect structure 114 electrically connects various features or structures (e.g., gate contacts 110 and / or other contacts) of the semiconductor transistor device. The front-side metal layer 116 includes vertical interconnects such as vias or contacts, and horizontal interconnects such as metal lines. Various interconnect features can be implemented with various conductive materials including copper, tungsten, and silicide. In some examples, a damascene process is used to form a copper multilayer interconnect structure. Subsequently, a carrier substrate 240 is formed above the front-side interconnect structure 114. For example, the carrier substrate 240 is bonded to the front-side interconnect structure 114. In some embodiments, the carrier substrate 240 is sapphire. In some other embodiments, the carrier substrate 240 is silicon, a thermoplastic polymer, an oxide, a carbide, or other suitable material.

[0064] like Fig.21 , in some embodiments, the workpiece is "flipped" upside down and thinned to expose the first sacrificial source / drain contact 180 and the semiconductor substrate layer 146 from the back side. At least the upper portion of the bulk substrate 142, the insulator substrate layer 144, and the lower isolation structure 160 is removed. The bulk substrate 142 and the lower isolation structure 160 can be removed in multiple process operations, for example, first removing the bulk substrate 142 and then removing the lower isolation structure 160. In some embodiments, the removal process includes removing the bulk substrate 142 and the lower isolation structure 160 using, for example, CMP, HNA, and / or TMAH etching.

[0065] like Fig.22A Stereoscopic image, Fig. 22B The x-direction cross-sectional view and Fig. 22CAs shown in the y-direction cross-sectional view of the first source / drain region of FIG. 1 , in some embodiments, the first sacrificial source / drain contact 180 is removed and the underlying first source / drain epitaxial structure 106 is recessed from its back side to form a backside source / drain contact trench 234 recessed in the upper portion of the first source / drain epitaxial structure 106. The first source / drain epitaxial structure 106 may be recessed or etched using an etchant that can selectively etch the first source / drain epitaxial structure 106 at a faster etching rate than the surrounding dielectric material.

[0066] like Fig.23A Stereoscopic image, Fig. 23B The x-direction cross-sectional view and Fig.23C As shown in the y-direction cross-sectional view of the first source / drain region, in some embodiments, a second sacrificial source / drain contact 236 is filled in the back source / drain contact trench 234. In some embodiments, the second sacrificial source / drain contact 236 is formed by depositing a dielectric material such as silicon nitride in the back source / drain contact trench 234 and then performing a planarization process to remove excess portions, so that the second sacrificial source / drain contact 236 can be coplanar with the lower isolation structure 160 and the semiconductor substrate layer 146.

[0067] like Fig.24A Stereoscopic image, Fig. 24B The x-direction cross-sectional view and Fig.24C As shown in the y-direction cross-sectional view of the second source / drain region, in some embodiments, the semiconductor substrate layer 146 is removed to form a backside capping trench 238 above the second source / drain epitaxial structure 108 and the gate structure 104. The second source / drain epitaxial structure 108 and the gate structure 104 below can be exposed. In some embodiments, the second source / drain epitaxial structure 108 is recessed from the backside into the upper portion of the second source / drain epitaxial structure 108.

[0068] like Fig.25A Stereoscopic image, Fig.25B The x-direction cross-sectional view, Fig.25C A cross-sectional view in the y direction in the gate region and Fig.25D As shown in the y-direction cross-sectional view of the second source / drain region, in some embodiments, a backside dielectric cap 126 is formed in the backside capping trench 238 (see Fig.24A). A backside dielectric cap 126 may be formed directly above the second source / drain epitaxial structure 108 and the gate structure 104. The backside dielectric cap 126 may be formed by, for example, a deposition process to deposit a dielectric material in the backside capping trench 238, followed by a CMP process to remove excess dielectric material outside the backside capping trench 238. In some embodiments, the backside dielectric cap 126 comprises a dielectric material such as silicon oxide that is different from the second sacrificial source / drain contact 236. Other suitable materials may include SiO2, SiN, SiCN, SiOCN, Al2O3, AlON, ZrO2, HfO2, combinations thereof, and the like. In some embodiments, the backside dielectric cap 126 has a convex top surface 126s at the interface between the backside dielectric cap 126 and the second source / drain epitaxial structure 108.

[0069] like Fig.26A Stereoscopic image, Fig.26B The x-direction cross-sectional view and Fig.26C As shown in the y-direction cross-sectional view of the first source / drain region, in some embodiments, a back source / drain contact 120 is formed in at least a portion of the back source / drain contact trench 234 to replace the second sacrificial source / drain contact 236 (see Fig.23A ). In some embodiments, the outer portion of the second sacrificial source / drain contact 236 remains in the back source / drain contact trench 234, serving as a dielectric sidewall spacer 118 separating the back source / drain contact 120 from the back dielectric cap 126. The back source / drain contact 120 reaches onto the recessed bottom surface 106b of the first source / drain epitaxial structure 106. The bottom surface 106b may be recessed in a previous step, such as, for example FIG. 22A to FIG. 22C As shown. In some embodiments, before forming the back side source / drain contact 120, a back side metal alloy layer may be formed on the first source / drain epitaxial structure 106. The back side metal alloy layer may be a silicide layer formed by a self-aligned silicide process. The back side metal alloy layer may include a material selected from titanium silicide, cobalt silicide, nickel silicide, platinum silicide, nickel platinum silicide, silicide, palladium silicide, a combination thereof, or other suitable materials. In some embodiments, the back side metal alloy layer may include germanium. In some embodiments, the back side source / drain contact 120 may be made of a metal, such as W, Co, Ru, Al, Cu, or other suitable materials. After depositing the back side source / drain contact 120, a planarization process, such as a chemical mechanical planarization (CMP) process, may then be performed. In some embodiments, a barrier layer may be formed in the back side source / drain contact trench 234 before forming the back side source / drain contact 120. The barrier layer may be made of TiN, TaN, or a combination thereof.

[0070] like Fig.27A The stereogram and Fig.27B As shown in the x-direction cross-sectional view of FIG. 1 , in some embodiments, a backside power rail 122 and a backside interconnect structure 124 are formed to be electrically coupled to the backside source / drain contacts 120 .

[0071] Fig.28 A flow chart illustrating some embodiments of a method 2800 of forming an integrated chip having multiple transistor devices with high device density due to air spacer structures and high-κ dielectric spacer structures.

[0072] Although method 2800 is illustrated and described below as a series of steps or events, it should be understood that the illustrated order of such steps or events should not be interpreted in a limiting sense. For example, some operations may occur in different orders and / or occur simultaneously with other operations or events other than those shown and / or described herein. In addition, not all illustrated operations are required to implement one or more aspects or embodiments described herein. In addition, one or more of the steps depicted herein may be performed in one or more separate steps and / or stages.

[0073] At step 2802, a plurality of fin structures of a stacked first semiconductor layer and a second semiconductor layer are formed on a substrate. An isolation structure (eg, see Figures 7 to 12 ). Figures 7 to 12 A perspective view corresponding to some embodiments of step 2802 is shown.

[0074] At step 2804 , a plurality of dummy gate structures are formed overlying the fin structure. Fig.13 A perspective view corresponding to some embodiments of step 2804 is shown.

[0075] At step 2806, portions of the fin structure not covered by the dummy gate structure are etched and removed from opposite sides of the dummy gate structure. The second semiconductor layer is horizontally recessed from the first semiconductor layer. FIG. 14A to FIG. 14C Various views corresponding to some embodiments of step 2806 are shown.

[0076] At step 2808, inner spacers are formed on opposite ends of the second semiconductor layer. FIG. 15A to FIG. 15B Various views corresponding to some embodiments of step 2808 are shown.

[0077] At step 2810, a first dummy backside contact is formed in a substrate. FIG. 16A to FIG. 16C Various views corresponding to some embodiments of step 2810 are shown.

[0078] At step 2812 , a first source / drain epitaxial structure and a second source / drain epitaxial structure are formed on opposite sides of the recessed fin structure. 17A to 17DVarious views corresponding to some embodiments of step 2812 are shown.

[0079] At step 2814, the second semiconductor layer is replaced with a metal gate structure. FIG. 18A to FIG. 19C Various views corresponding to some embodiments of step 2814 are shown.

[0080] At step 2816, gate contacts and frontside interconnect structures are formed. Fig. 20 A perspective view corresponding to some embodiments of step 2816 is shown.

[0081] At step 2818, a bottom surface of the first source / drain epitaxial structure is recessed. Figures 21 to 22C Various views corresponding to some embodiments of step 2818 are shown.

[0082] At step 2820, a second dummy backside contact is formed to the recessed bottom surface of the first source / drain epitaxial structure. FIG. 23A to FIG. 23C Various views corresponding to some embodiments of step 2820 are shown.

[0083] At step 2822, a bottom surface of the second source / drain epitaxial structure is recessed. FIG. 24A to FIG. 24D Various views corresponding to some embodiments of step 2822 are shown.

[0084] At step 2824, a backside dielectric cap is formed on a bottom surface of the second source / drain epitaxial structure. FIG. 25A to FIG. 25D Various views corresponding to some embodiments of step 2824 are shown.

[0085] At step 2826, backside source / drain contacts are formed to the bottom surface of the first source / drain epitaxial structure. FIG. 26A to FIG. 26C Various views corresponding to some embodiments of step 2826 are shown.

[0086] At step 2828, backside power rails and backside interconnect structures are formed. FIG. 27A to FIG. 27B Various views corresponding to some embodiments of step 2828 are shown.

[0087] Therefore, in some embodiments, the present invention relates to a semiconductor transistor device. The semiconductor transistor device includes a channel structure and a gate structure wrapping the channel structure. The semiconductor transistor device also includes: a first source / drain epitaxial structure and a second source / drain epitaxial structure, the first source / drain epitaxial structure and the second source / drain epitaxial structure are arranged on opposite ends of the channel structure; and a back source / drain contact, the back source / drain contact is arranged below the first source / drain epitaxial structure. The first source / drain epitaxial structure has a concave bottom surface in contact with the back source / drain contact. The semiconductor transistor device also includes a gate contact arranged on the gate structure.

[0088] In other embodiments, the present invention relates to a semiconductor transistor device. The semiconductor transistor device includes a channel structure and a gate structure wrapping the channel structure. The semiconductor transistor device also includes: a first source / drain epitaxial structure and a second source / drain epitaxial structure, the first source / drain epitaxial structure and the second source / drain epitaxial structure are arranged on opposite ends of the channel structure; and a back source / drain contact, the back source / drain contact is arranged below the first source / drain epitaxial structure and contacts therewith. The semiconductor transistor device also includes: a gate contact, the gate contact is arranged on the gate structure; and a back dielectric cap, the back dielectric cap is arranged below the second source / drain epitaxial structure and the gate structure and contacts therewith.

[0089] In some further embodiments, the present invention relates to a method for manufacturing a semiconductor transistor device. The method includes: forming a fin structure above a substrate by alternately stacking a first semiconductor layer and a second semiconductor layer; and forming a dummy gate structure above the fin structure. The method also includes: removing a portion of the fin structure that is not covered by the dummy gate structure; and forming an internal spacer on the opposite side of the remaining portion of the first semiconductor layer. The method also includes forming a first source / drain epitaxial structure and a second source / drain epitaxial structure on opposite ends of the fin structure. The method also includes replacing the dummy gate structure and the first semiconductor layer with a metal gate structure. The method also includes: removing the substrate; and forming a backside covering trench to expose the bottom surface of the metal gate structure and the bottom surface of the second source / drain epitaxial structure. The bottom surface of the second source / drain epitaxial structure is recessed. The method also includes: forming a backside dielectric cap in the backside covering trench; and forming a backside source / drain contact below and in contact with the first source / drain epitaxial structure.

[0090] Some embodiments of the present application provide a semiconductor transistor device, including: a channel structure; a gate structure, wrapping the channel structure; a first source / drain epitaxial structure and a second source / drain epitaxial structure, arranged on opposite ends of the channel structure; a gate contact, arranged on the gate structure; and a back source / drain contact, arranged below the first source / drain epitaxial structure; wherein the first source / drain epitaxial structure has a concave bottom surface in contact with the back source / drain contact. In some embodiments, the semiconductor transistor device also includes a back dielectric cap, which is arranged below the second source / drain epitaxial structure and in direct contact with the second source / drain epitaxial structure. In some embodiments, the second source / drain epitaxial structure has a concave bottom surface in contact with the back dielectric cap. In some embodiments, the back dielectric cap extends below the gate structure. In some embodiments, the back dielectric cap is in direct contact with the gate structure. In some embodiments, the semiconductor transistor device further comprises an intermediate isolation structure surrounding the gate structure, the first source / drain epitaxial structure, and the second source / drain epitaxial structure. In some embodiments, the semiconductor transistor device further comprises a lower isolation structure disposed below the intermediate isolation structure and surrounding the back dielectric cap. In some embodiments, the semiconductor transistor device further comprises a dielectric sidewall spacer disposed along the sidewall of the back source / drain contact. In some embodiments, the semiconductor transistor device further comprises an internal spacer separating the gate structure from the first source / drain epitaxial structure and the second source / drain epitaxial structure. In some embodiments, the channel structure comprises a semiconductor nanowire stack.

[0091] Some other embodiments of the present application provide a semiconductor transistor device, including: a channel structure; a gate structure, wrapping the channel structure; a first source / drain epitaxial structure and a second source / drain epitaxial structure, arranged on opposite ends of the channel structure; a gate contact, arranged on the gate structure; and a back source / drain contact, arranged below the first source / drain epitaxial structure and in contact with the first source / drain epitaxial structure; and a back dielectric cap, arranged below the second source / drain epitaxial structure and the gate structure and in contact with the second source / drain epitaxial structure and the gate structure. In some embodiments, the bottom surface of the second source / drain epitaxial structure is located at a higher position than the bottom surface of the gate structure. In some embodiments, the top surface of the back source / drain contact is located at a higher position than the bottom surface of the gate structure. In some embodiments, the semiconductor transistor device further includes a dielectric sidewall spacer, which is arranged between the back source / drain contact and the back dielectric cap. In some embodiments, the gate structure includes: a gate electrode; and a gate dielectric, the gate dielectric between the gate electrode and the channel structure. In some embodiments, the channel structure includes a semiconductor nanowire stack. In some embodiments, the semiconductor transistor device further includes an internal spacer, the internal spacer separating the gate structure from the first source / drain epitaxial structure and the second source / drain epitaxial structure. In some embodiments, the backside dielectric cap comprises SiO2, SiN, SiCN, SiOCN, Al2O3, AlON, ZrO2, HfO2, or a combination thereof.

[0092] Some other embodiments of the present application provide a method for forming a semiconductor transistor device, the method comprising: forming a fin structure above a substrate by alternately stacking a first semiconductor layer and a second semiconductor layer; forming a dummy gate structure above the fin structure; removing a portion of the fin structure not covered by the dummy gate structure; forming an internal spacer on opposite sides of the remaining portion of the first semiconductor layer; forming a first source / drain epitaxial structure and a second source / drain epitaxial structure on opposite ends of the fin structure; replacing the dummy gate structure and the first semiconductor layer with a metal gate structure; removing the substrate and forming a back-side covering trench to expose the bottom surface of the metal gate structure and the bottom surface of the second source / drain epitaxial structure, wherein the bottom surface of the second source / drain epitaxial structure is recessed; forming a back-side dielectric cap in the back-side covering trench; and forming a back-side source / drain contact in contact with the first source / drain epitaxial structure below the first source / drain epitaxial structure. In some embodiments, forming the back side source / drain contact includes: forming a back side contact trench after forming the internal spacer; filling the back side contact trench with a sacrificial semiconductor material; removing the sacrificial semiconductor material and replacing it with a sidewall spacer dielectric material before forming the back side cap trench; removing at least a portion of the sidewall spacer dielectric material; and replacing it with the back side source / drain contact after forming the back side dielectric cap.

[0093] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor transistor device, comprising: Channel structure; A gate structure wrapping the channel structure; a first source / drain epitaxial structure and a second source / drain epitaxial structure disposed on opposite ends of the channel structure; a gate contact disposed on the gate structure; as well as a back side source / drain contact, arranged below the first source / drain epitaxial structure; wherein the first source / drain epitaxial structure has a concave bottom surface in contact with the back source / drain contact, The semiconductor transistor device further includes a backside dielectric cap disposed below and in direct contact with the second source / drain epitaxial structure.

2. The semiconductor transistor device according to claim 1, the backside dielectric cap comprises SiO2, SiN, SiCN, SiOCN, Al2O3, AlON, ZrO2, HfO2 or a combination thereof.

3. The semiconductor transistor device according to claim 2, wherein: The second source / drain epitaxial structure has a concave bottom surface in contact with the backside dielectric cap.

4. The semiconductor transistor device according to claim 2, wherein: The backside dielectric cap extends under the gate structure.

5. The semiconductor transistor device according to claim 4, wherein: The backside dielectric cap is in direct contact with the gate structure. 6 . The semiconductor transistor device of claim 2 , further comprising an intermediate isolation structure surrounding the gate structure, the first source / drain epitaxial structure, and the second source / drain epitaxial structure. 7 . The semiconductor transistor device of claim 6 , further comprising a lower isolation structure disposed below the intermediate isolation structure and surrounding the backside dielectric cap. 8 . The semiconductor transistor device of claim 1 , further comprising dielectric sidewall spacers disposed along sidewalls of the backside source / drain contacts. 9 . The semiconductor transistor device of claim 1 , further comprising an inner spacer separating the gate structure from the first source / drain epitaxial structure and the second source / drain epitaxial structure.

10. The semiconductor transistor device of claim 1, wherein the channel structure comprises a semiconductor nanowire stack.

11. A semiconductor transistor device, comprising: Channel structure; A gate structure wrapping the channel structure; a first source / drain epitaxial structure and a second source / drain epitaxial structure disposed on opposite ends of the channel structure; a gate contact, arranged on the gate structure; as well as a back side source / drain contact, arranged below the first source / drain epitaxial structure and in contact with the first source / drain epitaxial structure; as well as A backside dielectric cap is disposed below and in contact with the second source / drain epitaxial structure and the gate structure.

12. The semiconductor transistor device according to claim 11, wherein: A bottom surface of the second source / drain epitaxial structure is located at a higher position than a bottom surface of the gate structure.

13. The semiconductor transistor device according to claim 11, wherein: A top surface of the back side source / drain contact is located at a higher position than a bottom surface of the gate structure. 14 . The semiconductor transistor device of claim 11 , further comprising a dielectric sidewall spacer disposed between the backside source / drain contacts and the backside dielectric cap.

15. The semiconductor transistor device according to claim 11, wherein the gate structure comprises: a gate electrode; as well as A gate dielectric is between the gate electrode and the channel structure.

16. The semiconductor transistor device according to claim 11, wherein: The channel structure includes a semiconductor nanowire stack. 17 . The semiconductor transistor device of claim 11 , further comprising an inner spacer separating the gate structure from the first source / drain epitaxial structure and the second source / drain epitaxial structure.

18. The semiconductor transistor device according to claim 11, wherein: The backside dielectric cap includes SiO2, SiN, SiCN, SiOCN, Al2O3, AlON, ZrO2, HfO2 or a combination thereof.

19. A method of forming a semiconductor transistor device, the method comprising: forming a fin structure over a substrate by alternately stacking a first semiconductor layer and a second semiconductor layer; forming a dummy gate structure above the fin structure; removing a portion of the fin structure not covered by the dummy gate structure; forming inner spacers on opposite sides of the remaining portion of the first semiconductor layer; forming a first source / drain epitaxial structure and a second source / drain epitaxial structure on opposite ends of the fin structure; replacing the dummy gate structure and the first semiconductor layer with a metal gate structure; removing the substrate and forming a backside capping trench to expose a bottom surface of the metal gate structure and a bottom surface of the second source / drain epitaxial structure, wherein the bottom surface of the second source / drain epitaxial structure is recessed; forming a backside dielectric cap in the backside cover trench; as well as A backside source / drain contact is formed below the first source / drain epitaxial structure and in contact with the first source / drain epitaxial structure.

20. The method according to claim 19, wherein: Forming the back side source / drain contact comprises: forming a backside contact trench after forming the inner spacer; filling the backside contact trench with a sacrificial semiconductor material; removing the sacrificial semiconductor material and replacing it with a sidewall spacer dielectric material prior to forming the backside capping trench; removing at least a portion of the sidewall spacer dielectric material; and The backside dielectric cap is formed and then replaced with the backside source / drain contacts.

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