A high electron mobility transistor and a method for manufacturing the same

Abstract

The present invention provides a high electron mobility transistor and a preparation method thereof, which relates to the field of semiconductor technology, including depositing metal on a second N+ type doped layer to form a source and a drain respectively. A first groove is formed on the second N+ type doped layer. A second groove is formed on an indium gallium arsenide etching barrier layer and a first N-type doped layer. A third groove is formed on an aluminum arsenide etching barrier layer, wherein the first groove, the second groove and the third groove are connected to serve as a gate groove. Metal is deposited in the gate groove to form a gate in contact with a low energy gap tunneling layer. Since a low energy gap tunneling layer is inserted between the gate and the barrier layer, and an indium gallium arsenide etching barrier layer is provided between the first N-type doped layer and the second N+ type doped layer, the resistance of the ohmic contact of the source and the drain can be effectively reduced, thereby further reducing the on-resistance of the device, which is convenient for improving the performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high electron mobility transistor and a preparation method thereof. Background Art

[0002] High electron mobility transistor (HEMT), also known as modulation doped field effect transistor, uses two materials with different energy gaps to form a heterojunction to provide a channel for carriers. High electron mobility transistors can operate at extremely high frequencies, so they are widely used in mobile phones, satellite TV and radar.

[0003] When used as a power device, an existing high electron mobility transistor usually adopts a double groove structure, that is, after a first etch barrier layer, an N-doped layer, a second etch barrier layer and an N+ doped layer are sequentially formed on the barrier layer, two connected grooves are formed on the first etch barrier layer, the N-doped layer, the second etch barrier layer and the N+ doped layer, and an ohmic contact source and drain are also provided on the N+ doped layer. However, since the first etch barrier layer and the second etch barrier layer are both high energy band gap layers, the ohmic contact resistance is large, which affects the device performance. Summary of the invention

[0004] The object of the present invention is to provide a high electron mobility transistor and a method for manufacturing the same, in order to reduce the on-resistance of the device, in view of the above-mentioned deficiencies in the prior art.

[0005] To achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0006] According to one aspect of an embodiment of the present invention, a method for preparing a high electron mobility transistor is provided, the method comprising: sequentially forming a channel layer, a first isolation layer, a first doping layer, a barrier layer, a low energy gap tunneling layer, an aluminum arsenide etch barrier layer, a first N-type doping layer, an indium gallium arsenide etch barrier layer and a second N+ type doping layer on a substrate; depositing metal on the second N+ type doping layer to form a source and a drain, respectively; etching the second N+ type doping layer in the area between the source and the drain and terminating at the indium gallium arsenide etch barrier layer to form a first groove; sequentially etching the indium gallium arsenide etch barrier layer and the first N-type doping layer in the first groove and terminating at the aluminum arsenide etch barrier layer to form a second groove; etching the aluminum arsenide etch barrier layer in the second groove and terminating at the low energy gap tunneling layer to form a third groove, wherein the first groove, the second groove and the third groove are connected to serve as a gate groove; and depositing metal in the gate groove to form a gate in contact with the low energy gap tunneling layer.

[0007] Optionally, a buffer layer is formed between the substrate and the channel layer.

[0008] Optionally, a second doping layer and a second isolation layer located on the buffer layer are sequentially formed between the buffer layer and the channel layer.

[0009] Optionally, the low energy gap tunneling layer is a gallium arsenide layer or an indium gallium arsenide layer.

[0010] Optionally, etching the second N+ type doped layer in the area between the source and the drain and terminating at the InGaAs etching barrier layer to form a first groove includes: etching the second N+ type doped layer in the area between the source and the drain by citric acid and terminating at the InGaAs etching barrier layer to form a first groove.

[0011] Optionally, sequentially etching the indium gallium arsenide etch barrier layer and the first N-type doped layer in the first groove and terminating at the aluminum arsenide etch barrier layer to form a second groove includes: sequentially etching the indium gallium arsenide etch barrier layer and the first N-type doped layer in the first groove by succinic acid and terminating at the aluminum arsenide etch barrier layer to form the second groove.

[0012] Optionally, the thickness of the aluminum arsenide etch stop layer and the indium gallium arsenide etch stop layer are both 1 nm to 5 nm.

[0013] Optionally, the thickness of the channel layer is 5nm to 15nm; the thickness of the first isolation layer is 3nm to 8nm; the thickness of the barrier layer is 12nm to 20nm; the thickness of the low energy gap tunneling layer is 1nm to 5nm; the thickness of the first N-type doping layer is 10nm to 40nm; the thickness of the second N+ type doping layer is 30nm to 80nm;

[0014] Optionally, the first doping layer and the second doping layer are both planar doping layers.

[0015] According to another aspect of an embodiment of the present invention, a high electron mobility transistor is provided, comprising a substrate and a channel layer, a first isolation layer, a first doping layer, a barrier layer, a low energy gap tunneling layer, an aluminum arsenide etch barrier layer, a first N-type doping layer, an indium gallium arsenide etch barrier layer and a second N+ type doping layer sequentially arranged on the substrate; a gate groove is formed on the surface of the first N-type doping layer, the gate groove sequentially penetrates the second N+ type doping layer, the indium gallium arsenide etch barrier layer, the first N-type doping layer and the aluminum arsenide etch barrier layer to expose the low energy gap tunneling layer, a source and a drain in contact with the second N+ type doping layer are arranged on both sides of the gate groove, and a gate in contact with the low energy gap tunneling layer is arranged in the gate groove.

[0016] The beneficial effects of the present invention include:

[0017] The present invention provides a high electron mobility transistor and a preparation method thereof, comprising sequentially forming a channel layer, a first isolation layer, a first doping layer, a barrier layer, a low energy gap tunneling layer, an aluminum arsenide etching barrier layer, a first N-type doping layer, an indium gallium arsenide etching barrier layer and a second N+ type doping layer on a substrate. Depositing metal on the second N+ type doping layer to form a source and a drain, respectively. Forming a first groove on the second N+ type doping layer. Forming a second groove on the indium gallium arsenide etching barrier layer and the first N-type doping layer. Forming a third groove on the aluminum arsenide etching barrier layer, wherein the first groove, the second groove and the third groove are connected to serve as a gate groove. Depositing metal in the gate groove to form a gate in contact with the low energy gap tunneling layer. Thus, a Schottky contact is formed with the barrier layer below the low energy gap tunneling layer. Since the low energy gap tunneling layer is inserted between the gate and the barrier layer, the on-resistance between the source and the drain can be reduced. On this basis, by setting the layer between the first N-type doped layer and the second N+-type doped layer as an InGaAs etching barrier layer, the InGaAs etching barrier layer can not only play a blocking role when etching the second N+-type doped layer, but also, after the device structure is formed, since the InGaAs etching barrier layer is a low-bandgap material, it can effectively reduce the resistance of the ohmic contact between the source and the drain, thereby further reducing the on-resistance of the device, thereby facilitating the improvement of device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic flow chart of a method for preparing a high electron mobility transistor provided by an embodiment of the present invention;

[0020] Figure 2 One of the state schematic diagrams of a high electron mobility transistor provided by an embodiment of the present invention;

[0021] Figure 3 A second state schematic diagram of a high electron mobility transistor provided by an embodiment of the present invention;

[0022] Figure 4 A third state diagram of a high electron mobility transistor provided by an embodiment of the present invention;

[0023] Figure 5 A fourth state schematic diagram of a high electron mobility transistor provided by an embodiment of the present invention;

[0024] Figure 6 A fifth state diagram of a high electron mobility transistor provided by an embodiment of the present invention;

[0025] Figure 7 A sixth state diagram of a high electron mobility transistor provided by an embodiment of the present invention;

[0026] Figure 8 A schematic structural diagram of a high electron mobility transistor provided in an embodiment of the present invention.

[0027] Icon: 100-substrate; 210-buffer layer; 220-second doped layer; 230-second isolation layer; 240-channel layer; 250-first isolation layer; 260-first doped layer; 270-barrier layer; 280-low energy gap tunneling layer; 290-aluminum arsenide etch barrier layer; 310-first N-type doped layer; 320-indium gallium arsenide etch barrier layer; 330-second N+ type doped layer; 340-source; 350-drain; 360-gate groove; 361-first groove; 362-second groove; 370-gate; 410-first patterned photoresist layer; 420-second patterned photoresist layer. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0029] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. It should be noted that, in the absence of conflict, the various features in the embodiments of the present invention can be combined with each other, and the combined embodiments are still within the scope of protection of the present invention.

[0030] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0031] In the description of the present invention, it should be noted that the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0032] In order to achieve better device performance, existing high electron mobility transistors usually use two layers of etch barrier layers to achieve a double groove structure. However, since these two layers of etch barrier layers are both high energy band gap layers, the formed ohmic contact resistance is also large, which affects the device performance. Therefore, one aspect of the embodiment of the present application is to provide a method for preparing a high electron mobility transistor (HEMT) to reduce the on-resistance of the device and improve the performance of the device. Figure 1 As shown, the steps of the preparation method are schematically given, including:

[0033] S010: forming a channel layer, a first isolation layer, a first doping layer, a barrier layer, a low energy gap tunneling layer, an aluminum arsenide etch stop layer, a first N-type doping layer, an indium gallium arsenide etch stop layer and a second N+ type doping layer in sequence on the substrate.

[0034] like Figure 2 As shown, a substrate 100 is provided, and the substrate 100 can be a base material for carrying semiconductor integrated circuit components, such as gallium arsenide, silicon carbide, etc. In order to form an epitaxial layer of a pseudo modulation doped heterojunction field effect transistor (pHEMT), a channel layer 240, a first isolation layer 250, a first doping layer 260, a barrier layer 270, a low energy gap tunneling layer 280, an aluminum arsenide etch stop layer 290, a first N-type doping layer 310, an indium gallium arsenide etch stop layer 320, and a second N+ type doping layer 330 can be sequentially formed on the above substrate 100. The formation of each layer in the epitaxial layer can be carried out by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) and other processes, which are not limited in this application and can be reasonably selected according to actual needs.

[0035] S020: Depositing metal on the second N+ type doped layer to form a source and a drain respectively.

[0036] When forming the epitaxial layer of the pHEMT device in S010, as Figure 2 As shown, metal can continue to be deposited on the top layer of the epitaxial layer, i.e., the second N+ type doped layer 330, to form a source 340 and a drain 350, respectively. In this way, an ohmic contact of the device is formed by the contact between the source 340 and the second N+ type doped layer 330, and the contact between the drain 350 and the second N+ type doped layer 330. In order to ensure the performance of the device, the source 340 and the drain 350 can be arranged at intervals.

[0037] S030: Etching the second N+ type doping layer in the region between the source and the drain and stopping at the InGaAs etching stop layer to form a first groove.

[0038] like Figure 3As shown, the etching method can be to coat a whole layer of photoresist layer on the upper surface of the second N+ doped layer 330 and the source 340 and the drain 350, and form a patterned photoresist layer with a window area after exposure, development, and hard baking, wherein the window area is located in the area between the source 340 and the drain 350, and remove the second N+ doped layer 330 exposed in the window area by etching liquid or physical etching until it stops at the InGaAs etching barrier layer 320, wherein during etching, an etching liquid with a relatively high etching selectivity can be selected according to the second N+ doped layer 330 and the InGaAs etching barrier layer 320, so that the etching depth can be controlled when etching the second N+ doped layer 330, thereby forming a first groove 361 structure on the second N+ doped layer 330. After the first groove 361 is formed, the patterned photoresist layer can be stripped and removed to form a structure as shown in FIG. Figure 3 The structure shown.

[0039] S040: etching the InGaAs etching stop layer and the first N-type doping layer in sequence in the first groove and stopping at the AlAs etching stop layer to form a second groove.

[0040] like Figure 4 As shown, a photoresist layer is continuously coated on the structure formed in S030, and then a first patterned photoresist layer 410 is formed through exposure, development and other processes. The window area of ​​the first patterned photoresist is located in the first groove 361, so that the InGaAs etching stop layer 320 is exposed in the window area. The InGaAs etching stop layer 320 exposed in the window area in the first groove 361 is removed by etching liquid or the like, and then the first N-type doped layer 310 below is exposed, and then the exposed first N-type doped layer 310 is continuously etched until the AlAs etching stop layer 290 is terminated. In this way, as shown in FIG. Figure 6 As shown, a second groove 362 is formed on the InGaAs etch barrier layer 320 and the first N-type doped layer 310, wherein when the InGaAs etch barrier layer 320 and the first N-type doped layer 310 are etched in sequence, the etching may be performed by the same etching solution or by two etching solutions. However, when etching the first N-type doped layer 310, an etching solution with a relatively high etching selectivity should be selected based on the first N-type doped layer 310 and the AlAs etch barrier layer 290 to etch the first N-type doped layer 310, so that the etching depth of the first N-type doped layer 310 can be controlled through the AlAs etch barrier layer 290.

[0041] S050: Etching the aluminum arsenide etching barrier layer in the second groove and terminating at the low energy gap tunneling layer to form a third groove, wherein the first groove, the second groove and the third groove are connected to serve as a gate groove.

[0042] In S040, Figure 6After the structure shown in FIG. 1 is formed, the aluminum arsenide barrier layer is removed in the second groove 362 by etching until the low energy gap tunneling layer 280 under the aluminum arsenide barrier layer is exposed, forming a structure as shown in FIG. Figure 7 The structure shown in the figure can be etched in the manner described above to form the first groove 361 and the second groove 362, and will not be described in detail here. In this way, a third groove can be formed on the aluminum arsenide barrier layer. Since the second groove 362 is formed in the first groove 361 and the third groove is formed in the second groove 362, the three grooves are connected in sequence in the order of formation, and the connected grooves as a whole can be used as the gate groove 360. In this way, by sequentially etching the second N+ doped layer 330, the indium gallium arsenide etching barrier layer 320, the first N-type doped layer 310 and the aluminum arsenide etching barrier layer 290, a dual-groove device structure can be formed, thereby increasing the breakdown voltage and making the device have better performance. It should be noted that when etching the first N-type doped layer 310 and the aluminum arsenide etching barrier layer 290, the etching should be divided into two steps. In this way, the aluminum arsenide etching barrier layer 290 can play a blocking role when etching the first N-type doped layer 310. Similarly, when etching the second N+ type doped layer 330 and the indium gallium arsenide etching barrier layer 320, the etching should also be divided into two steps.

[0043] S060: depositing metal in the gate groove to form a gate in contact with the low-gap tunneling layer.

[0044] After the gate groove 360 ​​is formed in S050, a metal may be deposited in the gate groove 360 ​​to form a gate 370 of the pHEMT device, and the gate 370 contacts the low-gap tunneling layer 280, thereby forming a Schottky contact with the barrier layer 270 below the low-gap tunneling layer 280. Since the low-gap tunneling layer 280 is inserted between the gate 370 and the barrier layer 270, the on-resistance between the source 340 and the drain 350 may be reduced. On this basis, by setting the layer between the first N-type doped layer 310 and the second N+-type doped layer 330 as the InGaAs etching barrier layer 320, the InGaAs etching barrier layer 320 can not only play a blocking role when etching the second N+-type doped layer 330, but also, after the device structure is formed, since the InGaAs etching barrier layer 320 is a low-bandgap material, the resistance of the ohmic contact between the source 340 and the drain 350 can be effectively reduced, thereby further reducing the device on-resistance, thereby facilitating the improvement of device performance.

[0045] In the embodiment of the present application, the low energy gap tunneling layer 280 can be a gallium arsenide layer or an indium gallium arsenide layer, so that the resistance of the ohmic contact formed by the source 340 and the drain 350 is reduced. The aluminum arsenide etching stop layer 290 is a high energy gap material, which can effectively increase the breakdown voltage of the device. The first N-type doped layer 310 can be an N-doped layer.

[0046] like Figure 5 As shown, in order to form a T-shaped gate 370 in the gate groove 360, a second patterned photoresist layer 420 may be further formed on the first patterned photoresist layer 410. Thus, the second patterned photoresist layer 420 may be trimmed to form a concave shape. Figure 5 The T-shaped area in the formation Figure 7 After the gate groove 360 ​​is formed, the second patterned photoresist layer 420 and the first patterned photoresist layer are stripped off by gate metal evaporation to form a T-shaped gate 370, thereby further improving the performance of the device.

[0047] Optional, such as Figure 2 As shown, in order to improve the performance of the pHEMT device, a buffer layer 210 may be formed between the substrate 100 and the channel layer 240 , so that the subsequent second doping layer 220 or the second isolation layer 230 can be better formed on the substrate 100 .

[0048] Optionally, a second doped layer 220 and a second isolation layer 230 are sequentially formed on the buffer layer 210 between the buffer layer 210 and the channel layer 240. The channel layer 240 and the first doped layer 260 can be isolated by the first isolation layer 250. Similarly, the second doped layer 220 and the channel layer 240 can be isolated by the second isolation layer 230, thereby ensuring the performance of the device. The first isolation layer 250 and the second isolation layer 230 are undoped layers.

[0049] Optionally, since citric acid can etch the second N+ doped layer 330, and the InGaAs etching barrier layer 320 has good etching stopping properties for citric acid, when the second N+ doped layer 330 is etched in the area between the source 340 and the drain 350 and terminated at the InGaAs etching barrier layer 320 to form a first groove 361: the second N+ doped layer 330 can be etched by citric acid and terminated at the InGaAs etching barrier layer 320 to form a first groove 361 on the second N+ doped layer 330.

[0050] Optionally, similarly, since succinic acid can etch the InGaAs etching barrier layer 320 and the first N-type doping layer 310 at the same time, and the aluminum arsenide layer can have a good etching stop property for succinic acid, when the InGaAs etching barrier layer 320 and the first N-type doping layer 310 can be sequentially etched in the first groove 361 and terminated at the aluminum arsenide etching barrier layer 290 to form the second groove 362, the InGaAs etching barrier layer 320 and the first N-type doping layer 310 can be sequentially etched by succinic acid and terminated at the aluminum arsenide etching barrier layer 290 to form the second groove 362. In this way, the InGaAs etching barrier layer 320 and the first N-type doping layer 310 can be etched in one step by succinic acid, saving etching steps.

[0051] By using citric acid and succinic acid in different stages, the gate groove 360 ​​can be effectively formed when the etching barrier layer between the first N-type doping layer 310 and the second N+-type doping layer 330 is an InGaAs etching barrier layer 320 .

[0052] Optionally, the thickness of the aluminum arsenide etch stop layer 290 is set to 1nm to 5nm, such as 2, 3, 4nm, etc., and the thickness of the indium gallium arsenide etch stop layer 320 is set to 1nm to 5nm, such as 2, 3, 4nm, etc., which can effectively improve the performance of the device.

[0053] Optionally, the thickness of the channel layer 240 of the pHEMT device can also be set to 5nm to 15nm, for example, 8, 11, 13nm, etc.; the thickness of the first isolation layer 250 is 3nm to 8nm, for example, 5nm, 7nm, etc.; the thickness of the barrier layer 270 is 12nm to 20nm, for example, 15, 18nm, etc.; the thickness of the low-bandgap tunneling layer 280 is 1nm to 5nm, for example, 2, 3, 4nm, etc.; the thickness of the first N-type doping layer 310 is 10nm to 40nm; the thickness of the second N+ type doping layer 330 is 30nm to 80nm. In this way, the performance of the device can be effectively improved, so that the pHEMT device can have a lower on-resistance.

[0054] Optionally, the first doping layer 260 and the second doping layer 220 are both planar doping layers, which can effectively weaken the trap effect, while being beneficial to the control of the pinch-off voltage, improving the breakdown voltage of the gate 370 , and increasing the carrier concentration in the channel layer 240 .

[0055] Another aspect of the present invention provides a high electron mobility transistor, such as Figure 8As shown, it includes a substrate 100 and a channel layer 240, a first isolation layer 250, a first doping layer 260, a barrier layer 270, a low-gap tunneling layer 280, an aluminum arsenide etch barrier layer 290, a first N-type doping layer 310, an indium gallium arsenide etch barrier layer 320 and a second N+ type doping layer 330 sequentially arranged on the substrate 100; a gate groove 360 ​​is formed on the surface of the first N-type doping layer 310, and the gate groove 360 ​​sequentially penetrates the second N+ type doping layer 330, the indium gallium arsenide etch barrier layer 320, the first N-type doping layer 310 and the aluminum arsenide etch barrier layer 290 to expose the low-gap tunneling layer 280, and a source 340 and a drain 350 in contact with the second N+ type doping layer 330 are arranged on both sides of the gate groove 360, and a gate 370 in contact with the low-gap tunneling layer 280 is arranged in the gate groove 360. Since the low energy gap tunneling layer 280 is inserted between the gate 370 and the barrier layer 270, the on-resistance between the source 340 and the drain 350 can be reduced. On this basis, by setting the layer between the first N-type doping layer 310 and the second N+-type doping layer 330 as the InGaAs etching barrier layer 320, the InGaAs etching barrier layer 320 can not only play a blocking role when etching the second N+-type doping layer 330, but also, after forming the device structure, since the InGaAs etching barrier layer 320 is a low energy gap material, the resistance of the ohmic contact between the source 340 and the drain 350 can be effectively reduced, thereby further reducing the on-resistance of the device, which is convenient for improving the device performance.

[0056] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for preparing a high electron mobility transistor, characterized in that: The method comprises: A channel layer, a first isolation layer, a first doping layer, a barrier layer, a low energy gap tunneling layer, an aluminum arsenide etch stop layer, a first N-type doping layer, an indium gallium arsenide etch stop layer and a second N+-type doping layer are sequentially formed on the substrate; Depositing metal on the second N+ type doped layer to form a source electrode and a drain electrode respectively; Etching the second N+ type doped layer in a region between the source and the drain and terminating at the indium gallium arsenide etching stop layer to form a first groove; Sequentially etching the InGaAs etching stop layer and the first N-type doping layer in the first groove and ending at the AlAs etching stop layer to form a second groove; Etching the aluminum arsenide etch barrier layer in the second groove and terminating at the low energy gap tunneling layer to form a third groove, wherein the first groove, the second groove and the third groove are connected to serve as a gate groove; A metal is deposited in the gate groove to form a gate in contact with the low-gap tunneling layer.

2. The method for preparing a high electron mobility transistor according to claim 1, wherein: A buffer layer is also formed between the substrate and the channel layer.

3. The method for preparing a high electron mobility transistor according to claim 2, characterized in that: A second doping layer and a second isolation layer located on the buffer layer are sequentially formed between the buffer layer and the channel layer.

4. The method for preparing a high electron mobility transistor according to any one of claims 1 to 3, characterized in that: The low energy gap tunneling layer is a gallium arsenide layer or an indium gallium arsenide layer.

5. The method for preparing a high electron mobility transistor according to any one of claims 1 to 3, characterized in that: The etching of the second N+ type doped layer in the region between the source and the drain and terminating at the indium gallium arsenide etching stop layer to form a first groove comprises: The second N+ type doped layer is etched in a region between the source and the drain by using citric acid and terminated at the indium gallium arsenide etching stop layer to form a first groove.

6. The method for preparing a high electron mobility transistor according to any one of claims 1 to 3, characterized in that: The step of sequentially etching the InGaAs etching barrier layer and the first N-type doping layer in the first groove and terminating at the AlAs etching barrier layer to form a second groove comprises: The indium gallium arsenide etch barrier layer and the first N-type doping layer are sequentially etched in the first groove by succinic acid and terminated at the aluminum arsenide etch barrier layer to form a second groove.

7. The method for preparing a high electron mobility transistor according to any one of claims 1 to 3, characterized in that: The thickness of the aluminum arsenide etching stop layer and the indium gallium arsenide etching stop layer are both 1 nm to 5 nm.

8. The method for preparing a high electron mobility transistor according to claim 7, characterized in that: The thickness of the channel layer is 5nm to 15nm; the thickness of the first isolation layer is 3nm to 8nm; the thickness of the barrier layer is 12nm to 20nm; the thickness of the low energy gap tunneling layer is 1nm to 5nm; the thickness of the first N-type doping layer is 10nm to 40nm; the thickness of the second N+ type doping layer is 30nm to 80nm.

9. The method for preparing a high electron mobility transistor according to claim 3, characterized in that: The first doping layer and the second doping layer are both planar doping layers.

10. A high electron mobility transistor, characterized in that: The invention comprises a substrate and a channel layer, a first isolation layer, a first doping layer, a barrier layer, a low-gap tunneling layer, an aluminum arsenide etch barrier layer, a first N-type doping layer, an indium gallium arsenide etch barrier layer and a second N+ type doping layer which are sequentially arranged on the substrate; a gate groove is formed on the surface of the first N-type doping layer, the gate groove sequentially penetrates the second N+ type doping layer, the indium gallium arsenide etch barrier layer, the first N-type doping layer and the aluminum arsenide etch barrier layer to expose the low-gap tunneling layer, a source and a drain contacting the second N+ type doping layer are arranged on both sides of the gate groove, a gate contacting the low-gap tunneling layer is arranged in the gate groove, and the gate is a T-shaped gate.

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