A display substrate, a driving method thereof, a display panel and a display device

Abstract

The present invention provides a display substrate, a driving method thereof, a display panel and a display device, wherein the display substrate comprises: a base substrate, a plurality of sub-pixels arranged in an array on the base substrate, a plurality of data lines extending along a first direction, a plurality of gate lines extending along a second direction intersecting the first direction, a plurality of first-type control switches and a plurality of second-type control switches, wherein one sub-pixel, one first-type control switch coupled to the sub-pixel and one second-type control switch coupled to the sub-pixel are arranged in a minimum area surrounded by the data lines and the gate lines; wherein one data line is arranged between two adjacent columns of sub-pixels; and in the same column of sub-pixels, the first-type control switch coupled to each sub-pixel is alternately coupled to two adjacent data lines in sequence, and the second-type control switch coupled to each sub-pixel is coupled to the same data line of the two adjacent data lines.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate, a driving method thereof, a display panel and a display device. Background Art

[0002] The pixel architecture in existing display products adopts either a column architecture or a Z inversion architecture. In the Z inversion architecture, the polarities of two adjacent sub-pixels in the display screen are opposite, and the Z inversion architecture has a better display effect. However, when it is applied to a display screen with a high refresh rate, high resolution, and large size, insufficient charging will occur, resulting in differences in the charging of pixels by adjacent data lines (Data) in certain images (generally mixed color images), which is manifested as uneven pixel brightness under the same grayscale voltage, and visible horizontal or vertical fine lines on the screen, namely Fine Pitch. The Fine Pitch problem caused by insufficient charging can be solved under the column architecture. In addition, when the column architecture is applied to a display screen with a low refresh rate, the problem of bad shaking head lines will occur, while the Z inversion architecture can avoid bad shaking head lines. In other words, the column architecture and the Z inversion architecture each have their advantages and disadvantages. At present, once the display device is prepared, it can only be a pixel architecture, such as a column architecture or a Z inversion architecture, and it cannot be changed. If the function of another architecture is required, the mask plate can only be changed and re-prepared, which is very expensive. Summary of the invention

[0003] The invention provides a display substrate, a driving method thereof, a display panel and a display device, which are used to be compatible with two pixel architectures.

[0004] In a first aspect, an embodiment of the present invention provides a display substrate, comprising:

[0005] A base substrate, a plurality of sub-pixels arranged in an array on the base substrate, a plurality of data lines extending along a first direction, a plurality of gate lines extending along a second direction intersecting the first direction, a plurality of first-type control switches and a plurality of second-type control switches, wherein one sub-pixel, one first-type control switch coupled to the sub-pixel and one second-type control switch coupled to the sub-pixel are arranged in a minimum area surrounded by the data lines and the gate lines;

[0006] Among them, one data line is set between two adjacent columns of sub-pixels; in the same column of sub-pixels, the first type of control switch coupled to each sub-pixel is alternately coupled to the two adjacent data lines in sequence, and the second type of control switch coupled to each sub-pixel is coupled to the same data line among the two adjacent data lines.

[0007] In a possible implementation, two of the gate lines are arranged between two adjacent rows of sub-pixels in the multiple sub-pixels, and the gate of the first type of control switch coupled to each row of sub-pixels in the multiple sub-pixels is coupled in sequence to the odd-numbered gate lines arranged along the first direction among the multiple gate lines; the gate of the second type of control switch coupled to each row of sub-pixels in the multiple sub-pixels is coupled in sequence to the even-numbered gate lines arranged along the first direction among the multiple gate lines.

[0008] In one possible implementation, the display substrate also includes a display area and a non-display area surrounding the display area, the non-display area includes a plurality of cascaded even-level shift registers and a plurality of cascaded odd-level shift registers, each of the even-level shift registers is coupled to the even-numbered gate lines, and each of the odd-level shift registers is coupled to the odd-numbered gate lines.

[0009] In one possible implementation, each of the odd-numbered shift registers is used to control the conduction of the first type of control switch unit coupled to the odd-numbered gate lines, and each of the even-numbered shift registers is used to control the cutoff of the second type of control switch coupled to the even-numbered gate lines, and the polarities of two adjacent sub-pixels among the multiple sub-pixels are opposite.

[0010] In one possible implementation, each of the even-numbered shift registers is used to control the conduction of the second-type control switch coupled to the even-numbered gate lines, and each of the odd-numbered shift registers is used to control the cutoff of the first-type control switch coupled to the odd-numbered gate lines, and the polarity of each sub-pixel in the same column of the multiple sub-pixels is the same, and the polarities of the sub-pixels in two adjacent columns are opposite.

[0011] In one possible implementation, the display substrate includes a pixel electrode located on the base substrate, and a common electrode located between the base substrate and the pixel electrode, the two common electrodes corresponding to two adjacent sub-pixels in the same row of sub-pixels are disconnected, and the orthographic projection of the data line between the two adjacent sub-pixels on the base substrate does not overlap with the orthographic projection of the two common electrodes on the base substrate.

[0012] In one possible implementation, the common electrodes corresponding to the same row of sub-pixels are arranged without interruption throughout the entire layer, and the orthographic projection of the data line between two adjacent sub-pixels in the same row of sub-pixels on the base substrate completely falls within the area of ​​the orthographic projection of the common electrodes corresponding to the same row of sub-pixels on the base substrate.

[0013] In a possible implementation manner, a transparent organic film is disposed between the data line between two adjacent sub-pixels in the same row of sub-pixels and the common electrode.

[0014] In a second aspect, an embodiment of the present invention provides a display panel, including:

[0015] A display substrate as described in any one of the above items.

[0016] In a third aspect, an embodiment of the present invention provides a display device, including:

[0017] A display panel as described above.

[0018] In a fourth aspect, an embodiment of the present invention provides a method for driving a display substrate as described in any one of the above items, comprising:

[0019] At a first refresh frequency, the first type of control switch is controlled to be turned on and the second type of control switch is controlled to be turned off, and first data signals with opposite polarities are alternately loaded to the plurality of data lines, so that the polarities of two adjacent sub-pixels in the plurality of sub-pixels are opposite;

[0020] At a second refresh frequency greater than the first refresh frequency, the second type of control switch is controlled to be turned on and the first type of control switch is controlled to be turned off, and second data signals with opposite polarities are alternately loaded to the multiple data lines, so that the polarity of each sub-pixel in the same column of the multiple sub-pixels is the same, and the polarities of the sub-pixels in two adjacent columns are opposite.

[0021] In a possible implementation manner, at the first refresh frequency, the method further includes:

[0022] A first scanning signal is loaded onto the odd-numbered gate lines arranged along the first direction among the plurality of gate lines through a plurality of cascaded odd-numbered shift registers, and each sub-pixel is charged under the loading of the first data signal and the first scanning signal.

[0023] In a possible implementation manner, at the second refresh frequency, the method further includes:

[0024] A second scanning signal is loaded onto even-numbered gate lines arranged along the first direction among the plurality of gate lines through a plurality of cascaded even-numbered shift registers, and each sub-pixel is charged under the loading of the second data signal and the second scanning signal.

[0025] The beneficial effects of the present invention are as follows:

[0026] The embodiment of the present invention provides a display substrate, a driving method thereof, a display panel and a display device, wherein in the display substrate, a sub-pixel, a first-type control switch coupled to the sub-pixel and a second-type control switch coupled to the sub-pixel are arranged in the minimum area surrounded by a data line and a gate line, a data line is arranged between two adjacent columns of sub-pixels, in the same column of sub-pixels, the first-type control switch coupled to each sub-pixel is alternately coupled to the two adjacent data lines in sequence, and the second-type control switch coupled to each sub-pixel is coupled to the same data line of the two adjacent data lines, so that the polarities of two adjacent sub-pixels in a plurality of sub-pixels can be opposite by controlling the first-type control switch to be turned on and the second-type control switch to be turned off, that is, the display substrate realizes a Z-inversion architecture, and the polarities of each sub-pixel in the same column of sub-pixels in a plurality of sub-pixels can be the same and the polarities of sub-pixels in two adjacent columns can be opposite by controlling the first-type control switch to be turned off and the second-type control switch to be turned on, that is, the display substrate realizes a column architecture, that is, the display substrate can be compatible with two pixel architectures including the Z-inversion architecture and the column architecture, thereby ensuring the performance of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of the structure of the display panel for the existing column architecture;

[0028] Figure 2 It is a structural schematic diagram of an existing Z-inversion structure display panel;

[0029] Figure 3 A schematic diagram of a structure of a display substrate provided by an embodiment of the present invention;

[0030] Figure 4 A schematic diagram of a structure of a display substrate provided by an embodiment of the present invention;

[0031] Figure 5 A schematic diagram of a structure of a display substrate provided by an embodiment of the present invention;

[0032] Figure 6 A schematic diagram of a structure of a display substrate provided by an embodiment of the present invention;

[0033] Figure 7 A schematic diagram of a structure of a display substrate provided by an embodiment of the present invention;

[0034] Figure 8 for Figure 4 A schematic diagram of one structure of a display substrate realizing a Z-inversion architecture is shown;

[0035] Fig. 9 for Figure 4 A schematic diagram of one structure of a display substrate realizing a column architecture is shown;

[0036] Fig.10 For along Figure 3 A schematic diagram of one of the cross-sectional structures in the middle MM direction;

[0037] Fig.11 For along Figure 3 A schematic diagram of one of the cross-sectional structures in the middle MM direction;

[0038] Fig.12 For along Figure 3 A schematic diagram of one of the cross-sectional structures in the middle MM direction;

[0039] Fig.13 A schematic diagram of a structure of a display panel provided by an embodiment of the present invention;

[0040] Fig.14 A schematic diagram of a structure of a display device provided by an embodiment of the present invention;

[0041] Fig.15 A method flow chart of a method for driving a display substrate provided by an embodiment of the present invention.

[0042] Description of reference numerals:

[0043] Spx-sub-pixel; Gate-gate line; Data-data line; 1-substrate; 2-first type control switch; 3-second type control switch; R-red sub-pixel; G-green sub-pixel; B-blue sub-pixel; A-display area; B-non-display area; 4-even-level shift register; 5-odd-level shift register; 6-pixel electrode; 7-common electrode; 8-gate insulating layer; 9-passivation layer; 10-transparent organic film; 100-display substrate; 200-display panel. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. And in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0045] Unless otherwise defined, the technical terms or scientific terms used in the present invention shall have the common meanings understood by people with ordinary skills in the field to which the present invention belongs. The words "include" or "comprise" and the like used in the present invention mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, but do not exclude other elements or objects.

[0046] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0047] In the prior art, existing display panels either use Figure 1 The column structure shown in FIG. 1 is a structure in which a gate line Gate is arranged between two adjacent rows of sub-pixels Spx, a data line Data is arranged between two adjacent columns of sub-pixels Spx, the polarity of each sub-pixel Spx in the same column of sub-pixels Spx is the same, and the polarity of sub-pixels Spx in two adjacent columns is opposite. Figure 2 The Z inversion architecture shown in the figure, wherein a gate line Gate is arranged between two adjacent rows of sub-pixels Spx, a data line Data is arranged between two adjacent columns of sub-pixels Spx, and the polarities of the two adjacent sub-pixels Spx are opposite. However, in high refresh rate, high resolution, and large-size display screens, the Z inversion architecture will cause the Fine Pitch problem, and in low refresh rate display screens, the column architecture will cause the shaking head problem. In other words, the column architecture and the Z inversion architecture each have their shortcomings. Currently, once the display device is prepared, it is either a column architecture or a Z inversion architecture. If the function of another architecture is required, the mask plate can only be changed and re-prepared.

[0048] In view of this, embodiments of the present invention provide a display substrate, a driving method thereof, a display panel and a display device, which are used to be compatible with two pixel architectures.

[0049] like Figure 3 FIG. 1 is a schematic diagram of a structure of a display substrate provided by an embodiment of the present invention. Specifically, the display substrate includes:

[0050] A base substrate 1, a plurality of sub-pixels Spx arranged in an array on the base substrate 1, a plurality of data lines Data extending along a first direction, a plurality of gate lines Gate extending along a second direction intersecting the first direction, a plurality of first-type control switches 2 and a plurality of second-type control switches 3, one sub-pixel Spx is arranged in a minimum area surrounded by the data lines Data and the gate lines Gate, one first-type control switch 2 coupled to the sub-pixel Spx, and one second-type control switch 3 coupled to the sub-pixel Spx;

[0051] Among them, a data line Data is set between two adjacent columns of sub-pixels Spx, and in the same column of sub-pixels Spx, the first-type control switch 2 coupled to each sub-pixel Spx is alternately coupled to the two adjacent data lines Data in sequence, and the second-type control switch 3 coupled to each sub-pixel Spx is coupled to the same data line Data among the two adjacent data lines Data.

[0052] In a specific implementation process, the base substrate 1 can be a rigid substrate such as glass or silicon, or a flexible substrate, which is not limited here. A plurality of sub-pixels Spx are arranged in an array on the base substrate 1, and the number of the plurality of sub-pixels Spx can be set according to the size of the display substrate, the pixel resolution, and the size of a single sub-pixel Spx in actual applications, which is not limited here.

[0053] Still combined Figure 3 As shown, the first direction may be the direction indicated by arrow X, the second direction may be the direction indicated by arrow Y, the first direction and the second direction intersect, so that a plurality of data lines Data extending along the first direction and a plurality of gate lines Gate extending along the second direction intersect with each other to enclose a plurality of pixel regions. In practical applications, there may be a plurality of minimum regions enclosed by the data lines Data and the gate lines Gate, and a sub-pixel Spx is arranged in each minimum region, that is, the minimum region corresponds to a pixel region, and the minimum region is as shown in FIG. Figure 3 As shown in the dashed box a.

[0054] Still combined Figure 3As shown, the display substrate further includes a plurality of first-type control switches 2 and a plurality of second-type control switches 3, and the number of the first-type control switches 2 and the number of the second-type control switches 3 are both equal to the number of the sub-pixels Spx. One data line Data is arranged between every two adjacent columns of sub-pixels Spx. In the same column of sub-pixels Spx, the first-type control switch 2 coupled to each sub-pixel Spx is alternately coupled to two adjacent data lines Data in sequence, and the second-type control switch 3 coupled to each sub-pixel Spx is coupled to the same data line Data of the two adjacent data lines Data. In this way, when data signals with opposite polarities are alternately loaded to the multiple data lines Data, the first-type control switch 2 can be turned on and the second-type control switch 3 can be turned off so that the polarities of two adjacent sub-pixels Spx in the multiple sub-pixels Spx are opposite, thereby realizing a Z inversion architecture of the display substrate. The first-type control switch 2 can also be turned off and the second-type control switch 3 can be turned on so that the polarity of each sub-pixel Spx in the same column of sub-pixels Spx in the multiple sub-pixels Spx is the same, and the polarities of sub-pixels Spx in two adjacent columns are opposite, thereby realizing a column architecture of the display substrate.

[0055] In the embodiment of the present invention, the sub-pixels Spx in the same column in the array substrate have the same color, and the sub-pixels Spx in two adjacent columns have different colors. Figure 3 As shown, the plurality of sub-pixels Spx include sub-pixels Spx of three different colors, namely, a red sub-pixel, a green sub-pixel and a blue sub-pixel.

[0056] In the embodiment of the present invention, Figure 4 The figure shows a structural schematic diagram of one of the display substrates. Specifically, two gate lines Gate are arranged between two adjacent rows of sub-pixels Spx in the multiple sub-pixels Spx, and the gate of the first type of control switch 2 coupled to the sub-pixels Spx in each row of the multiple sub-pixels Spx is sequentially coupled to the odd-numbered gate lines Gate arranged along the first direction among the multiple gate lines Gate; the gate of the second type of control switch 3 coupled to the sub-pixels Spx in each row of the multiple sub-pixels Spx is sequentially coupled to the even-numbered gate lines Gate arranged along the first direction among the multiple gate lines Gate.

[0057] In a specific implementation process, two gate lines Gate are set between two adjacent rows of sub-pixels Spx in the plurality of sub-pixels Spx, and the gate of the first type of control switch 2 coupled to each row of sub-pixels Spx in the plurality of sub-pixels Spx is sequentially coupled to the odd-numbered gate lines Gate arranged along the first direction in the plurality of gate lines Gate, and still combined with Figure 4As shown, the gate of each of the first-type control switches 2 coupled to each sub-pixel Spx in the first row of sub-pixels Spx is coupled to the first gate line Gate, the gate of each of the first-type control switches 2 coupled to each sub-pixel Spx in the second row of sub-pixels Spx is coupled to the third gate line Gate, the gate of each of the first-type control switches 2 coupled to each sub-pixel Spx in the third row of sub-pixels Spx is coupled to the fifth gate line Gate, and the coupling method of the gate of each of the first-type control switches 2 coupled to each sub-pixel Spx in other rows of pixels and the odd-numbered gate lines Gate will not be described in detail. Correspondingly, the gate of the second-type control switch 3 coupled to each row of sub-pixels Spx in the multiple sub-pixels Spx is sequentially coupled to the even-numbered gate lines Gate arranged along the first direction among the multiple gate lines Gate, still combined with Figure 4 As shown, the gate of each second-type control switch 3 coupled to each sub-pixel Spx in the first row of sub-pixels Spx is coupled to the second gate line Gate, the gate of each second-type control switch 3 coupled to each sub-pixel Spx in the second row of sub-pixels Spx is coupled to the fourth gate line Gate, the gate of each second-type control switch 3 coupled to each sub-pixel Spx in the third row of sub-pixels Spx is coupled to the sixth gate line Gate, and the coupling method of each second-type control switch 3 coupled to each sub-pixel Spx in other rows of pixels and the even-numbered gate line Gate will not be described in detail.

[0058] In a specific implementation process, the coupling method between the first type control switch 2 and the second type control switch 3 and the plurality of gate lines Gate can also be as follows: Figure 5 As shown, the specific application can be based on the actual application needs Figure 4 or Figure 5 The coupling relationship between the two types of control switches and the plurality of gate lines Gate is set in the manner shown, which is not limited here.

[0059] In the embodiment of the present invention, Figure 6 The figure shows a schematic diagram of the structure of a display substrate. Specifically, the display substrate also includes a display area A and a non-display area B surrounding the display area A. The non-display area B includes a plurality of cascaded even-numbered shift registers 4 and a plurality of cascaded odd-numbered shift registers 5. Each of the even-numbered shift registers 4 is coupled to the even-numbered gate line Gate, and each of the odd-numbered shift registers 5 is coupled to the odd-numbered gate line Gate.

[0060] In a specific implementation process, the specific distribution of the display area A and the non-display area B surrounding the display area A in the display substrate can be as follows: Figure 6One of the situations shown in , the distribution between the display area A and the non-display area B can also be set according to the actual application needs, which is not limited here. The non-display area B includes a plurality of cascaded even-numbered shift registers 4 and a plurality of cascaded odd-numbered shift registers 5, and each of the even-numbered gate lines Gate in the plurality of gate lines Gate is coupled to an even-numbered shift register 4, and accordingly, the number of the even-numbered shift registers 4 is equal to the number of the even-numbered gate lines Gate in the plurality of gate lines Gate. In addition, each of the odd-numbered gate lines Gate in the plurality of gate lines Gate is coupled to an odd-numbered shift register 5, and accordingly, the number of the odd-numbered shift registers 5 is equal to the number of the odd-numbered gate lines Gate in the plurality of gate lines Gate. In practical applications, the coupling relationship between the even-numbered shift register 4 and the odd-numbered shift register 5 and the plurality of gate lines Gate can be set according to specific needs, which is not limited here.

[0061] In a specific implementation process, the even-numbered shift register 4 and the odd-numbered shift register 5 can be respectively arranged on two opposite sides of the plurality of gate lines Gate. Figure 6 As shown, the odd-numbered shift register 5 is arranged on the left side of the display area A, and the even-numbered shift register 4 is arranged on the right side of the display area A. In addition, Figure 7 The odd-numbered shift register 5 and the even-numbered shift register 4 are arranged in the manner shown, the odd-numbered shift register 5 is arranged on the right side of the display area A, and the even-numbered shift register 4 is arranged on the left side of the display area A. In practical applications, it can be arranged according to specific needs, and is not limited here.

[0062] In the embodiment of the present invention, Figure 8 Shown Figure 4 The display substrate shown is a structural schematic diagram of one of the Z inversion architectures. Specifically, each of the odd-numbered shift registers 5 is used to control the conduction of the first-type control switch 2 unit coupled to the odd-numbered gate line Gate, and each of the even-numbered shift registers 4 is used to control the cutoff of the second-type control switch 3 coupled to the even-numbered gate line Gate, and the polarities of two adjacent sub-pixels Spx among the multiple sub-pixels Spx are opposite.

[0063] In the specific implementation process, since each of the even-numbered shift registers 4 is coupled to the even-numbered gate line Gate, and each of the odd-numbered shift registers 5 is coupled to the odd-numbered gate line Gate, the even-numbered shift registers 4 and the odd-numbered shift registers 5 are driven independently, and under the drive of multiple cascaded odd-numbered shift registers 5, the first type of control switch 2 coupled to the corresponding odd-numbered gate line Gate can be controlled to be turned on, and under the drive of multiple cascaded even-numbered shift registers 4, the second type of control switch 3 coupled to the corresponding even-numbered gate line Gate can be controlled to be turned off, so that the polarities of two adjacent sub-pixels Spx are opposite, thereby realizing the Z inversion architecture of the display substrate.

[0064] In the embodiment of the present invention, Fig. 9 Shown Figure 4 The display substrate shown in the figure implements one of the structural schematic diagrams of the column architecture. Specifically, each of the even-numbered shift registers 4 is used to control the conduction of the second-type control switch 3 coupled to the even-numbered gate line Gate, and each of the odd-numbered shift registers 5 is used to control the cut-off of the first-type control switch 2 coupled to the odd-numbered gate line Gate. The polarity of each sub-pixel Spx in the same column of sub-pixels Spx among the multiple sub-pixels Spx is the same, and the polarities of the sub-pixels Spx in two adjacent columns are opposite.

[0065] In a specific implementation process, the second type of control switch 3 coupled to the corresponding even-numbered gate line Gate can be controlled to be turned on under the drive of multiple cascaded even-numbered shift registers 4, and the first type of control switch 2 coupled to the corresponding odd-numbered gate line Gate can be controlled to be turned off under the drive of multiple cascaded odd-numbered shift registers 5, so that the polarity of each sub-pixel Spx in the same column of sub-pixels Spx is the same, and the polarity of the sub-pixels Spx in two adjacent columns is opposite, thereby realizing the column architecture of the display substrate.

[0066] In the specific implementation process, combined with Figure 8 and Fig. 9 As shown, by driving the multiple cascaded even-numbered shift registers 4 and the multiple cascaded odd-numbered shift registers 5 separately, flexible switching between the column architecture and the Z-inversion architecture of the display substrate can be achieved, thereby ensuring the performance of the display substrate.

[0067] In the embodiment of the present invention, Fig.10 Shown along Figure 3A schematic diagram of a cross-sectional structure taken along the MM direction is shown in FIG. 1 . Specifically, the display substrate includes a pixel electrode 6 located on the base substrate 1, and a common electrode 7 located between the base substrate 1 and the pixel electrode 6. The two common electrodes 7 corresponding to two adjacent sub-pixels Spx in the same row of sub-pixels Spx are disconnected from each other, and the orthographic projection of the data line Data between the two adjacent sub-pixels Spx on the base substrate 1 does not overlap with the orthographic projection of the two common electrodes 7 on the base substrate 1.

[0068] In the specific implementation process, Fig.10 As shown, the display substrate includes a pixel electrode 6 located on the base substrate 1, and a common electrode 7 located between the base substrate 1 and the pixel electrode 6, the common electrode 7, the data line Data and the pixel electrode 6 are arranged in sequence away from the base substrate 1, wherein the data line Data is made of a source-drain layer, a gate insulating layer 8 is arranged between the data line Data and the common electrode 7, and the gate insulating layer 8 prevents the occurrence of a short circuit between the data line Data and the common electrode 7, and a passivation layer 9 is arranged between the data line Data and the pixel electrode 6, and the passivation layer 9 prevents the occurrence of a short circuit between the data line Data and the pixel electrode 6, thereby ensuring the performance of the display substrate. In addition, the two common electrodes 7 corresponding to two adjacent sub-pixels Spx in the same row of sub-pixels Spx are disconnected, and the orthographic projection of the data line Data between the two adjacent sub-pixels Spx on the base substrate 1 does not overlap with the orthographic projection of the two common electrodes 7 on the base substrate 1, thereby avoiding the generation of capacitance between the data line Data and the common electrode 7 due to overlap, thereby improving the performance of the display substrate.

[0069] In the embodiment of the present invention, Fig.11 Shown along Figure 3 A schematic diagram of a cross-sectional structure in the MM direction, specifically, the common electrode 7 corresponding to the same row of sub-pixels Spx is arranged without interruption in the entire layer, and the orthographic projection of the data line Data between two adjacent sub-pixels Spx in the same row of sub-pixels Spx on the base substrate 1 completely falls within the area of ​​the orthographic projection of the common electrode 7 corresponding to the same row of sub-pixels Spx on the base substrate 1.

[0070] In the specific implementation process, Fig.11As shown, the data line Data, the common electrode 7 and the pixel electrode 6 are arranged away from the base substrate 1 in sequence, a gate insulating layer 8 is arranged between the common electrode 7 and the data line Data, and the gate insulating layer 8 prevents the occurrence of a short circuit between the common electrode 7 and the data line Data, and a passivation layer 9 is arranged between the common electrode 7 and the pixel electrode 6, and the passivation layer 9 prevents the occurrence of a short circuit between the common electrode 7 and the pixel electrode 6. The common electrode 7 corresponding to the sub-pixels Spx in the same row is arranged in an uninterrupted manner throughout the layer, that is, the common electrode 7 corresponding to the sub-pixels Spx in the same row is designed in an entire surface, thereby improving the aperture ratio of the display substrate and improving the display quality of the display substrate. In addition, the orthographic projection of the data line Data between two adjacent sub-pixels Spx in the same row of sub-pixels Spx on the base substrate 1 completely falls within the area of ​​the orthographic projection of the common electrode 7 corresponding to the sub-pixels Spx in the same row on the base substrate 1.

[0071] In the embodiment of the present invention, Fig.12 Shown along Figure 3 A schematic diagram of a cross-sectional structure in the MM direction is shown in FIG. 1 . Specifically, a transparent organic film 10 is provided between the data line Data between two adjacent sub-pixels Spx in the same row of sub-pixels Spx and the common electrode 7. The transparent organic film 10 reduces the overlapping capacitance between the data line Data and the common electrode 7. In practical applications, the transparent organic film 10 of a suitable thickness can be selected according to specific needs, which is not limited here.

[0072] It should be noted that the first type of control switch 2 and the second type of control switch 3 may be thin film transistors (TFT) or metal oxide semiconductor field effect transistors (MOS), which are not limited here. Figures 10-12 As shown, the display substrate may also include other film layers besides the base substrate 1, the common electrode 7, the gate insulating layer 8, the transparent organic layer, the data line Data, the passivation layer 9, and the pixel electrode 6, such as a black matrix (Block Matrix), a cover plate, etc., which may refer to the settings in the prior art and will not be described in detail here. The specific structure of each shift register in the even-numbered shift register 4 and the odd-numbered shift register 5 may refer to the relevant settings in the prior art and will not be limited here.

[0073] Based on the same inventive concept, Fig.13As shown, an embodiment of the present invention further provides a display panel, and the display panel includes any of the display substrates 100 provided in the embodiment of the present invention. The display panel may be a liquid crystal display panel (Liquid Crystal Display, LCD) or an organic light emitting diode display panel (Organic Light Emitting Diode, OLED), which is not limited here. The principle of solving the problem by the display panel is similar to that of the aforementioned display substrate 100, so the implementation of the display panel can refer to the implementation of the aforementioned display substrate 100, and the repeated parts will not be repeated.

[0074] Based on the same inventive concept, Fig.14 As shown, an embodiment of the present invention further provides a display device, which includes the display panel 200 as described above. The principle of solving the problem by the display device is similar to that of the aforementioned display panel 200. Therefore, the implementation of the display device can refer to the implementation of the aforementioned display panel 200, and the repeated parts will not be repeated.

[0075] In the specific implementation process, the display device provided by the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by ordinary technicians in the field, and will not be described in detail here, nor should they be used as limitations of the present invention.

[0076] Based on the same inventive concept, Fig.15 As shown, an embodiment of the present invention further provides a method for driving the display substrate as described above, comprising:

[0077] S101: at a first refresh frequency, controlling the first type of control switch to be turned on and the second type of control switch to be turned off, and alternately loading first data signals with opposite polarities to the plurality of data lines, so that the polarities of two adjacent sub-pixels in the plurality of sub-pixels are opposite;

[0078] S102: At a second refresh frequency greater than the first refresh frequency, control the second type of control switch to be turned on and the first type of control switch to be turned off, and alternately load second data signals with opposite polarities to the multiple data lines, so that the polarity of each sub-pixel in the same column of the multiple sub-pixels is the same, and the polarities of the sub-pixels in two adjacent columns are opposite.

[0079] The execution order between step S101 and step S102 may be to execute step S101 first and then execute step S102, or to execute step S102 first and then execute step S101, which may be specifically set according to actual application conditions.

[0080] In a specific implementation process, at the first refresh frequency, the first type of control switch is controlled to be turned on and the second type of control switch is controlled to be turned off, and the first data signals with opposite polarities are alternately loaded to the plurality of data lines, so that the polarities of two adjacent sub-pixels Spx in the plurality of sub-pixels Spx are opposite, thereby ensuring that the display substrate has a Z-inversion architecture at the first refresh frequency. Since the first refresh frequency is a low refresh frequency, such as 30 Hz, 60 Hz, etc., the display substrate adopts a Z-inversion architecture to avoid the appearance of shaking head lines, thereby improving the display quality of the display substrate at a low refresh frequency.

[0081] In a specific implementation process, at a second refresh frequency greater than the first refresh frequency, the second type of control switch 3 is controlled to be turned on and the first type of control switch 2 is controlled to be turned off, and the second data signals with opposite polarities are alternately loaded to the plurality of data lines Data, so that the polarity of each sub-pixel Spx in the same column of sub-pixels Spx in the plurality of sub-pixels Spx is the same, and the polarities of sub-pixels Spx in two adjacent columns are opposite, thereby ensuring that the display substrate has a column structure at the second refresh frequency. Since the second refresh frequency is a high refresh frequency greater than the first refresh frequency, such as 90Hz, 120Hz, etc., the display substrate adopts a column structure, which avoids the Fine Pitch problem caused by insufficient high-frequency charging and improves the display quality of the display substrate at a high refresh frequency.

[0082] In an embodiment of the present invention, at the first refresh frequency, the method further includes:

[0083] A first scanning signal is loaded onto the odd-numbered gate lines arranged along the first direction among the plurality of gate lines through a plurality of cascaded odd-numbered shift registers, and each sub-pixel is charged under the loading of the first data signal and the first scanning signal.

[0084] In the specific implementation process, at the first refresh frequency, the first scanning signal can be loaded to the odd-numbered gate line Gate arranged along the first direction among the multiple gate lines Gate through multiple cascaded odd-numbered shift registers 5, and each sub-pixel Spx can be charged under the loading of the first data signal and the first scanning signal. The timing control circuit arranged in the non-display area B may output a clock control signal to each of the odd-numbered shift registers 5, thereby controlling each of the odd-numbered gate lines Gate coupled to the corresponding odd-numbered shift registers 5 to be turned on row by row. Accordingly, the corresponding first-type control switch 2 on each of the odd-numbered gate lines Gate is turned on, and the corresponding first scanning signal is loaded to each of the odd-numbered gate lines Gate. At this time, each of the even-numbered shift registers 4 controls the corresponding even-numbered gate lines Gate to output a low voltage. Accordingly, the corresponding second-type control switch 3 on each of the even-numbered gate lines Gate is turned off. Therefore, while ensuring that the display substrate adopts a Z-inversion architecture, it ensures that the pixel voltage written into each odd-numbered row sub-pixel Spx is not interfered, thereby improving the performance of the display substrate.

[0085] In the specific implementation process, when using Figure 4 When the display substrate is as shown, the display substrate is adjusted to Figure 8 In the Z-inversion structure shown in FIG. 1 , the timing control circuit can use the signal of the first data line coupled to the leftmost chip on film (COF) of the display area A as the initial data signal. Figure 8 The Z-inversion architecture shown is switched to Fig. 9 In the column architecture shown, the signal of the second data line coupled to the COF on the leftmost side of the display area A can be used as the initial data signal by the timing control circuit, thereby realizing flexible switching from the Z inversion architecture to the column architecture.

[0086] In an embodiment of the present invention, at the second refresh frequency, the method further includes:

[0087] A second scanning signal is loaded onto the even-numbered gate lines arranged along the first direction among the plurality of gate lines through a plurality of cascaded even-numbered shift registers, and each sub-pixel is charged under the loading of the second data signal and the second scanning signal.

[0088] In the specific implementation process, at the second refresh frequency, a second scanning signal can be loaded to the even-numbered gate lines Gate arranged along the first direction among the multiple gate lines Gate through multiple cascaded even-stage shift registers 4, and each sub-pixel Spx can be charged under the loading of the second data signal and the second scanning signal. The timing control circuit arranged in the non-display area B may output a clock control signal to each of the even-numbered shift registers 4, thereby controlling each of the even-numbered gate lines Gate coupled to the corresponding even-numbered shift registers 4 to be turned on row by row. Accordingly, the corresponding second-type control switch 3 on each of the even-numbered gate lines Gate is turned on, and the corresponding second scanning signal is loaded to each of the even-numbered gate lines Gate. At this time, each of the odd-numbered shift registers 5 controls the corresponding odd-numbered gate lines Gate to output a low voltage. Accordingly, the corresponding first-type control switch 2 on each of the odd-numbered gate lines Gate is turned off, thereby ensuring that the display substrate adopts a column architecture while ensuring that the pixel voltage written into each even-numbered row sub-pixel Spx is not interfered with, thereby improving the performance of the display substrate.

[0089] The embodiment of the present invention provides a display substrate, a driving method thereof, a display panel and a display device, wherein in the display substrate, a sub-pixel Spx is arranged in the minimum area surrounded by a data line Data and a gate line Gate, a first-type control switch 2 coupled to the sub-pixel Spx and a second-type control switch 3 coupled to the sub-pixel Spx are arranged, a data line Data is arranged between two adjacent columns of sub-pixels Spx, and in the same column of sub-pixels Spx, the first-type control switch 2 coupled to each sub-pixel Spx is alternately coupled to two adjacent data lines Data in sequence, and the second-type control switch 3 coupled to each sub-pixel Spx is alternately coupled to two adjacent data lines Data in sequence. In this way, the polarities of two adjacent sub-pixels Spx in the multiple sub-pixels Spx can be opposite by controlling the first-type control switch 2 to be turned on and the second-type control switch 3 to be turned off, that is, the display substrate realizes the Z inversion architecture. The polarity of each sub-pixel Spx in the same column of sub-pixels Spx in the multiple sub-pixels Spx can be the same, and the polarities of two adjacent columns of sub-pixels Spx are opposite, that is, the display substrate realizes the column architecture. In other words, the display substrate is compatible with two pixel architectures including the Z inversion architecture and the column architecture, thereby ensuring the performance of the display substrate.

[0090] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0091] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A display substrate, characterized in that: include: A base substrate, a plurality of sub-pixels arranged in an array on the base substrate, a plurality of data lines extending along a first direction, a plurality of gate lines extending along a second direction intersecting the first direction, a plurality of first-type control switches and a plurality of second-type control switches, wherein one sub-pixel, one first-type control switch coupled to the sub-pixel and one second-type control switch coupled to the sub-pixel are arranged in a minimum area surrounded by the data lines and the gate lines; Among the plurality of sub-pixels, the colors of the sub-pixels in the same column are the same, and the colors of the sub-pixels in two adjacent columns are different; one data line is arranged between the sub-pixels in two adjacent columns, and in the sub-pixels in the same column, the first-type control switch coupled to each sub-pixel is alternately coupled to the two adjacent data lines in sequence, and the second-type control switch coupled to each sub-pixel is coupled to the same data line among the two adjacent data lines; Among them, two gate lines are arranged between two adjacent rows of sub-pixels in the multiple sub-pixels, and the gate of the first type of control switch coupled to each row of sub-pixels in the multiple sub-pixels is coupled to the odd-numbered gate lines arranged along the first direction in sequence among the multiple gate lines; the gate of the second type of control switch coupled to each row of sub-pixels in the multiple sub-pixels is coupled to the even-numbered gate lines arranged along the first direction in sequence among the multiple gate lines.

2. The display substrate according to claim 1, wherein: The display substrate also includes a display area and a non-display area surrounding the display area, the non-display area includes a plurality of cascaded even-numbered shift registers and a plurality of cascaded odd-numbered shift registers, each of the even-numbered shift registers is coupled to the even-numbered gate lines, and each of the odd-numbered shift registers is coupled to the odd-numbered gate lines.

3. The display substrate according to claim 2, wherein: Each of the odd-numbered shift registers is used to control the conduction of the first type of control switch unit coupled to the odd-numbered gate lines, and each of the even-numbered shift registers is used to control the cutoff of the second type of control switch coupled to the even-numbered gate lines, and the polarities of two adjacent sub-pixels in the multiple sub-pixels are opposite.

4. The display substrate according to claim 2, wherein: Each of the even-numbered shift registers is used to control the conduction of the second-type control switch coupled to the even-numbered gate lines, and each of the odd-numbered shift registers is used to control the cutoff of the first-type control switch coupled to the odd-numbered gate lines. The polarity of each sub-pixel in the same column of the multiple sub-pixels is the same, and the polarities of the sub-pixels in two adjacent columns are opposite.

5. The display substrate according to claim 1, wherein: The display substrate includes a pixel electrode located on the base substrate, and a common electrode located between the base substrate and the pixel electrode. The two common electrodes corresponding to two adjacent sub-pixels in the same row of sub-pixels are disconnected, and the orthographic projection of the data line between the two adjacent sub-pixels on the base substrate does not overlap with the orthographic projection of the two common electrodes on the base substrate.

6. The display substrate according to claim 1, wherein: The common electrodes corresponding to the same row of sub-pixels are arranged in an entire layer without interruption, and the orthographic projection of the data line between two adjacent sub-pixels in the same row of sub-pixels on the base substrate completely falls within the area of ​​the orthographic projection of the common electrodes corresponding to the same row of sub-pixels on the base substrate.

7. The display substrate according to claim 6, wherein: A transparent organic film is arranged between the data line between two adjacent sub-pixels in the same row of sub-pixels and the common electrode.

8. A display panel, characterized in that: include: The display substrate according to any one of claims 1 to 7.

9. A display device, characterized in that: include: The display panel as claimed in claim 8.

10. A method for driving a display substrate according to any one of claims 1 to 7, characterized in that: include: At a first refresh frequency, the first type of control switch is controlled to be turned on and the second type of control switch is controlled to be turned off, and first data signals with opposite polarities are alternately loaded to the plurality of data lines, so that the polarities of two adjacent sub-pixels in the plurality of sub-pixels are opposite; At a second refresh frequency greater than the first refresh frequency, the second type of control switch is controlled to be turned on and the first type of control switch is controlled to be turned off, and second data signals with opposite polarities are alternately loaded to the multiple data lines, so that the polarity of each sub-pixel in the same column of the multiple sub-pixels is the same, and the polarities of the sub-pixels in two adjacent columns are opposite.

11. The driving method according to claim 10, characterized in that: At the first refresh frequency, the method further includes: A first scanning signal is loaded onto the odd-numbered gate lines arranged along the first direction among the plurality of gate lines through a plurality of cascaded odd-numbered shift registers, and each sub-pixel is charged under the loading of the first data signal and the first scanning signal.

12. The driving method according to claim 10, characterized in that: At the second refresh frequency, the method further includes: A second scanning signal is loaded onto even-numbered gate lines arranged along the first direction among the plurality of gate lines through a plurality of cascaded even-numbered shift registers, and each sub-pixel is charged under the loading of the second data signal and the second scanning signal.

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