Spread Spectrum Clock Generation System

Abstract

The present invention provides a spread spectrum clock generation system, wherein a digital frequency detection unit receives a reference signal and a feedback signal, compares the reference signal with the feedback signal, and outputs a frequency difference signal. A digital loop filter unit signal is connected to the digital frequency detection unit, which outputs a clock control signal according to the frequency difference signal. A digital spread spectrum control unit receives a reference signal to output a spread spectrum signal, and a digital-to-analog conversion unit converts the clock control signal into a first control signal and converts the spread spectrum signal into a second control signal. An analog control oscillation unit receives the first control signal and the second control signal to output a spread spectrum clock signal. This reduces costs and increases system controllability.

Description

Technical Field

[0001] The present invention relates to a clock generation system, and in particular to a spread spectrum clock generation system. Background Art

[0002] The development of technology has led to the prevalence of digital electronic devices. In order to improve the performance of digital electronic devices, the speed of information processing must also increase. Generally speaking, digital electronic devices have clock circuits to provide clock signals. However, when the clock speed increases, electromagnetic interference (EMI) will become more serious. Therefore, how to reduce electromagnetic interference has become one of the problems that academics and professionals need to solve.

[0003] Therefore, some industry insiders have proposed a spread spectrum clock generation circuit to reduce electromagnetic interference. The existing spread spectrum clock generation circuit includes a phase-locked loop formed by a phase detector, a charge pump, a low-pass loop filter and a voltage-controlled oscillator. The phase detector drives the charge pump after comparing the phase difference between the reference clock signal and the feedback clock signal. The signal output by the charge pump is filtered by the low-pass loop filter and combined with the triangular wave to drive the voltage-controlled oscillator to output the spread spectrum clock signal. However, the cost of the low-pass loop filter is relatively high, and the analog circuit is not easy to control, so there is still room for improvement.

[0004] In view of this, how to effectively improve the configuration of the spread spectrum clock generation circuit to make it have the advantages of low cost and easy control has become the goal of relevant industry players. Summary of the invention

[0005] The present invention provides a spread spectrum clock generation system, which can effectively reduce costs through internal configuration and achieve the purpose of easy regulation.

[0006] According to one embodiment of the present invention, a spread spectrum clock generation system is provided, which includes a digital frequency detection unit, a digital loop filter unit, a digital spread spectrum control unit, a digital-to-analog conversion unit, and an analog control oscillation unit. The digital frequency detection unit receives a reference signal and a feedback signal, and the digital frequency detection unit compares the magnitude of the reference signal and the feedback signal, and outputs a frequency difference signal. The digital loop filter unit is signal-connected to the digital frequency detection unit, and the digital loop filter unit outputs a clock control signal according to the frequency difference signal. The digital spread spectrum control unit receives the reference signal to output a spread spectrum signal, the digital-to-analog conversion unit is signal-connected to the digital loop filter unit and the digital spread spectrum control unit, and the digital-to-analog conversion unit converts the clock control signal into a first control signal, and converts the spread spectrum signal into a second control signal. The analog control oscillation unit receives the first control signal and the second control signal to output a spread spectrum clock signal.

[0007] Thereby, the digital loop filter unit can reduce the cost, and the digital spread spectrum control unit can have the advantage of easy regulation.

[0008] According to the aforementioned embodiments of the spread spectrum clock generation system, the digital frequency detection unit may include a frequency lock determiner, which determines whether a frequency lock state is reached according to the frequency difference signal to output a frequency lock signal.

[0009] According to the aforementioned multiple embodiments of the spread spectrum clock generation system, the digital frequency detection unit further includes a first counter, a second counter, a count controller and a frequency comparator. The first counter receives a reference signal and calculates a first pulse number of the reference signal within a count cycle; the second counter receives a feedback signal and calculates a second pulse number of the feedback signal within the count cycle. The count controller receives a frequency lock signal to adjust the count cycle, the frequency comparator signal connects the first counter and the second counter, and the frequency comparator compares the first pulse number and the second pulse number to output a frequency difference signal.

[0010] According to the aforementioned multiple embodiments of the spread spectrum clock generation system, the digital loop filter unit includes a control code selector, a decoder, an integrator and a control selector. The control code selector includes multiple control curves, and the control code selector selects a control curve according to the frequency difference signal to output a coarse adjustment signal. The decoder receives the frequency difference signal and outputs a fine adjustment code after decoding. The integrator receives the clock control signal and the fine adjustment code to output a fine adjustment signal. The control selector receives the coarse adjustment signal and the fine adjustment signal, and the control selector receives a selection instruction to select one of the coarse adjustment signal and the fine adjustment signal as the clock control signal.

[0011] According to the aforementioned multiple embodiments of the spread spectrum clock generation system, the digital-to-analog conversion unit includes a first voltage converter, a voltage-to-current converter, and a second voltage converter. The first voltage converter receives the clock control signal to output a first voltage signal, the voltage-to-current converter receives the first voltage signal to output a first control signal, and the second voltage converter receives the spread spectrum signal to output a second control signal.

[0012] According to multiple embodiments of the aforementioned spread spectrum clock generation system, the digital-to-analog conversion unit further includes a voltage control module, the voltage control module includes a first resistor, a second resistor and a third resistor, the first resistor includes a first end connected to a reference voltage, the second resistor includes a first end connected to a second end of the first resistor, the second resistor includes a second end grounded, the third resistor includes a first end connected to the first voltage converter and the second voltage converter, and the third resistor includes a second end connected to the first end of the second resistor.

[0013] According to the aforementioned multiple embodiments of the spread spectrum clock generation system, the digital spread spectrum control unit includes a spread spectrum divider and a spread spectrum counter. The spread spectrum divider receives a reference signal to output a divided signal. The spread spectrum counter signal is connected to the spread spectrum divider. The spread spectrum counter receives the divided signal to output the spread spectrum signal.

[0014] According to another embodiment of the present invention, a spread spectrum clock generation system is provided, which includes a digital frequency detection unit, a digital loop filter unit, a digital spread spectrum control unit, a digital-to-analog conversion unit, and an analog control oscillation unit. The digital frequency detection unit receives a reference signal and a feedback signal. After comparing the magnitude of the reference signal and the feedback signal, the digital frequency detection unit outputs a frequency difference signal. The digital loop filter unit is connected to the digital frequency detection unit by signal. The digital loop filter unit outputs a clock control signal according to the frequency difference signal. The digital loop filter unit includes an integrator and a control selector. The integrator receives the clock control signal and adjusts the clock control signal according to the frequency difference signal, and then outputs a fine-tuning signal. The control selector receives a selection instruction to select the output fine-tuning signal as the clock control signal. The digital spread spectrum control unit receives the reference signal to output a spread spectrum signal. The digital-to-analog conversion unit is connected to the digital loop filter unit and the digital spread spectrum control unit by signal. The digital-to-analog conversion unit converts the clock control signal into a first control signal, and converts the spread spectrum signal into a second control signal. The analog controlled oscillation unit receives the first control signal and the second control signal to output a spread spectrum clock signal.

[0015] According to the aforementioned multiple embodiments of the spread spectrum clock generation system, the digital frequency detection unit includes a frequency lock determiner, which determines whether a frequency lock state is reached according to the frequency difference signal to output a frequency lock signal.

[0016] According to the aforementioned multiple embodiments of the spread spectrum clock generation system, the frequency lock judge includes a frequency lock counting element, which accumulates a count value. The frequency difference signal includes an up-counting pulse and a down-counting pulse. When the frequency lock judge receives the up-counting pulse and the down-counting pulse at the same time and triggers the frequency lock counting element, if the up-counting pulse and the down-counting pulse are continuously received at the same time, the count value is accumulated, and when the count value reaches a threshold value, the frequency lock judge outputs a frequency lock signal.

[0017] According to the aforementioned multiple embodiments of the spread spectrum clock generation system, the digital frequency detection unit further includes a first counter, a second counter, a count controller and a frequency comparator. The first counter receives a reference signal and calculates a first pulse number of the reference signal within a count cycle; the second counter receives a feedback signal and calculates a second pulse number of the feedback signal within the count cycle. The count controller receives a frequency lock signal to adjust the count cycle, the frequency comparator signal connects the first counter and the second counter, and the frequency comparator compares the first pulse number and the second pulse number to output a frequency difference signal.

[0018] According to the aforementioned multiple embodiments of the spread spectrum clock generation system, the digital-to-analog conversion unit includes a first voltage converter, a voltage-to-current converter, a second voltage converter and a voltage control module, the first voltage converter receives the clock control signal to output a first voltage signal, the voltage-to-current converter receives the first voltage signal to output a first control signal, and the second voltage converter receives the spread spectrum signal to output a second control signal. The voltage control module includes a first resistor, a second resistor and a third resistor, the first resistor includes a first end connected to a reference voltage, the second resistor includes a first end connected to a second end of the first resistor, the second resistor includes a second end grounded, the third resistor includes a first end connected to the first voltage converter and the second voltage converter, and the third resistor includes a second end connected to the first end of the second resistor.

[0019] According to the aforementioned multiple embodiments of the spread spectrum clock generation system, the digital spread spectrum control unit includes a spread spectrum divider and a spread spectrum counter. The spread spectrum divider receives a reference signal to output a divided signal. The spread spectrum counter signal is connected to the spread spectrum divider. The spread spectrum counter receives the divided signal to output the spread spectrum signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A system block diagram of a spread spectrum clock generation system according to an embodiment of the present invention is shown;

[0021] Figure 2 Show Figure 1 A detailed block diagram of a digital frequency detection unit of a spread spectrum clock generation system according to an embodiment;

[0022] Figure 3 Show Figure 1 A schematic diagram of a determination process flow of a frequency lock determiner of a spread spectrum clock generation system according to an embodiment;

[0023] Figure 4 Show Figure 1 A detailed block diagram of a digital loop filter unit of a spread spectrum clock generation system according to an embodiment;

[0024] Figure 5 Show Figure 1 A detailed block diagram of a digital spread spectrum control unit of a spread spectrum clock generation system of an embodiment;

[0025] Figure 6 Show Figure 1 A schematic diagram of a triangular wave generated by a digital spread spectrum control unit of a spread spectrum clock generation system of an embodiment;

[0026] Figure 7 Show Figure 1 A detailed block diagram of a digital-to-analog conversion unit and an analog controlled oscillation unit of a spread spectrum clock generation system according to an embodiment; and

[0027] Figure 8 Show Figure 1 A detailed block diagram of a voltage control module of a spread spectrum clock generation system according to an embodiment.

[0028] Description of reference numerals:

[0029] 10: Spread spectrum clock generation system

[0030] 100: Digital frequency detection unit

[0031] 110: First counter

[0032] 120: Second counter

[0033] 130: Counting controller

[0034] 140: Frequency comparator

[0035] 150: Frequency lock judgement

[0036] 151: Frequency-locked counting element

[0037] 200: Digital loop filter unit

[0038] 210: Control code selector

[0039] 220: Decoder

[0040] 230: Control selector

[0041] 240: Switch

[0042] 250: Integrator

[0043] 251: Adding element

[0044] 252: Delay element

[0045] 300: Digital spread spectrum control unit

[0046] 310: Spread spectrum divider

[0047] 320: Spread spectrum counter

[0048] 400: Digital to analog conversion unit

[0049] 410: First voltage converter

[0050] 420: Second voltage converter

[0051] 430: Voltage to Current Converter

[0052] 440: Voltage regulation module

[0053] 500: Analog Controlled Oscillation Unit

[0054] 600: Output frequency division unit

[0055] 700: Feedback frequency division unit

[0056] A,D,U: Situation

[0057] Ct: Cycle time

[0058] CCLK: Clock control signal

[0059] CONS: Select Instructions

[0060] CTS: Coarse Tuning Signal

[0061] DOWNS: Down count pulses

[0062] Fd: Deviation value

[0063] FBCLK: feedback signal

[0064] FTC: Fine-tuning code

[0065] FTS: Fine Tuning Signal

[0066] GD:Ground

[0067] LS: frequency locking signal

[0068] OCS1: First control signal

[0069] OCS2: Second control signal

[0070] R1: First resistor

[0071] R2: Second resistor

[0072] R3: The third resistor

[0073] REFCLK: reference signal

[0074] SS: Spread Spectrum Signal

[0075] SSCLK: Spread spectrum clock signal

[0076] ST0,ST1,ST2,ST3,ST4: Stage

[0077] ST5, ST6, ST7, ST8, ST9: Stage

[0078] UPS: Counting pulses

[0079] VDD: reference voltage DETAILED DESCRIPTION

[0080] The embodiments of the present invention will be described below with reference to the accompanying drawings. For the purpose of clarity, many practical details will be described together in the following description. However, the reader should understand that these practical details should not be used to limit the present invention. That is, in some embodiments of the present invention, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and elements will be shown in a simple schematic manner in the drawings; and repeated elements may be represented by the same number or similar number.

[0081] In addition, herein, when a certain element (or mechanism or module, etc.) is "connected", "set" or "coupled" to another element, it may refer to that the element is directly connected, directly set or directly coupled to another element, or it may refer to that a certain element is indirectly connected, indirectly set or indirectly coupled to another element, that is, there are other elements between the element and the other element. When it is clearly stated that a certain element is "directly connected", "directly set" or "directly coupled" to another element, it means that there are no other elements between the element and the other element. The terms first, second, third, etc. are only used to describe different elements or components, and there is no restriction on the elements / components themselves. Therefore, the first element / component may also be renamed as the second element / component. Moreover, the combination of elements / components / mechanisms / modules herein is not a generally known, conventional or existing combination in this field, and it cannot be determined whether the combination relationship is easy to be easily completed by a technician in the technical field based on whether the elements / components / mechanisms / modules themselves are existing.

[0082] See also Figure 1 , Figure 2 and Figure 3 ,in Figure 1 FIG. 1 is a system block diagram of a spread spectrum clock generation system 10 according to an embodiment of the present invention. Figure 2 Show Figure 1 The detailed block diagram of the digital frequency detection unit 100 of the spread spectrum clock generation system 10 of the embodiment is shown in FIG. Figure 3 Show Figure 1Schematic diagram of the determination process of the frequency lock determiner 150 of the spread spectrum clock generation system 10 of the embodiment. The spread spectrum clock generation system 10 comprises a digital frequency detection unit 100, a digital loop filter unit 200, a digital spread spectrum control unit 300, a digital-to-analog conversion unit 400 and an analog controlled oscillation unit 500.

[0083] The digital frequency detection unit 100 receives a reference signal REFCLK and a feedback signal FBCLK. After comparing the reference signal REFCLK with the feedback signal FBCLK, the digital frequency detection unit 100 outputs a frequency difference signal. The digital loop filter unit 200 is connected to the digital frequency detection unit 100. The digital loop filter unit 200 outputs a clock control signal CCLK (indicated at Figure 4 The digital spread spectrum control unit 300 receives the reference signal REFCLK to output a spread spectrum signal SS (indicated by Figure 5 ), the digital-to-analog conversion unit 400 is signal-connected to the digital loop filter unit 200 and the digital spread spectrum control unit 300, and the digital-to-analog conversion unit 400 converts the clock control signal CCLK into a first control signal OCS1 (indicated at Figure 7 ), and converts the spread spectrum signal SS into a second control signal OCS2 (indicated at Figure 7 The analog controlled oscillator unit 500 receives the first control signal OCS1 and the second control signal OCS2 to output a spread spectrum clock signal SSCLK.

[0084] Thus, the digital loop filter unit 200 can reduce the cost, and the digital spread spectrum control unit 300 can have the advantage of easy regulation. The details of the spread spectrum clock generation system 10 will be described in detail later.

[0085] The reference signal REFCLK may be generated by a quartz oscillator, for example but not limited to, and the spread spectrum clock generation system 10 may further include an output frequency dividing unit 600 and a feedback frequency dividing unit 700, and both the output frequency dividing unit 600 and the feedback frequency dividing unit 700 are signal-connected to the analog control oscillation unit 500. The spread spectrum clock signal SSCLK may be used after passing through the output frequency dividing unit 600, and the spread spectrum clock signal SSCLK may also be divided by the feedback frequency dividing unit 700 to form a feedback signal FBCLK to enter the digital frequency detection unit 100. The frequency difference signal includes an up-counting pulse UPS and a down-counting pulse DOWNS. The digital frequency detection unit 100 may compare the reference signal REFCLK and the feedback signal FBCLK, and select to output at least one of the up-counting pulse UPS and the down-counting pulse DOWNS. When the reference signal REFCLK is greater than the feedback signal FBCLK, the digital frequency detection unit 100 outputs an up-counting pulse UPS; conversely, when the reference signal REFCLK is less than the feedback signal FBCLK, the digital frequency detection unit 100 outputs a down-counting pulse DOWNS, and if the reference signal REFCLK is approximately equal to the feedback signal FBCLK, the digital frequency detection unit 100 simultaneously outputs an up-counting pulse UPS and a down-counting pulse DOWNS. In other embodiments, the spread spectrum clock generation system may not include a feedback frequency dividing unit, in which case the feedback signal is equal to the spread spectrum clock signal; similarly, the spread spectrum clock generation system may not include an output frequency dividing unit, so that the spread spectrum clock signal is directly used, but the present invention is not limited thereto.

[0086] The digital frequency detection unit 100 may include a frequency lock determiner 150, which determines whether a frequency lock state is reached according to the frequency difference signal to output a frequency lock signal LS. More specifically, the frequency lock determiner 150 includes a frequency lock counting element 151, which accumulates a count value, wherein when the frequency lock determiner 150 receives an up-counting pulse UPS and a down-counting pulse DOWNS at the same time and triggers the frequency lock counting element 151, if the up-counting pulse UPS and the down-counting pulse DOWNS are continuously received at the same time, the count value is accumulated, and when the count value reaches a threshold value, the frequency lock determiner 150 outputs the frequency lock signal LS.

[0087] Specifically, Figure 3 As shown, the frequency lock determiner 150 can enter different stages ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7, ST8, and ST9 according to the up pulse UPS and the down pulse DOWNS it receives. Initially, the frequency lock determiner 150 is ready in stage ST0.

[0088] In stage ST0, if both the up-counting pulse UPS and the down-counting pulse DOWNS are received at the same time (represented by case A), then the process enters stage ST9, and the frequency-locking counting element 151 is triggered and started. In stage ST9, if case A is encountered continuously, the frequency-locking counting element 151 will continuously accumulate the count value, and when the threshold is reached, it is determined to be in the frequency-locking state. On the contrary, in stage ST9 and when the count value does not reach the threshold, if the frequency-locking judge 150 only receives the up-counting pulse UPS (represented by case U), it means that the frequency lock is not reached, and the process enters stage ST4, the count value is reset to zero, and the frequency-locking counting element 151 is turned off and waits to be triggered and started again. Similarly, in stage ST9 and when the count value does not reach the threshold, if the frequency-locking judge 150 only receives the down-counting pulse DOWNS (represented by case D), it means that the frequency lock is not reached, and the process enters stage ST3, the count value is reset to zero, and the frequency-locking counting element 151 is turned off and waits to be triggered and started again. In addition, when the situation U is encountered in the stage ST0, the stage ST1 is entered, and when the situation D is encountered in the stage ST0, the stage ST2 is entered.

[0089] When encountering situation A in stage ST1, the process enters stage ST9; otherwise, if encountering situation D, the process enters stage ST3, and if encountering situations other than situations A and D, the process remains in stage ST1. When encountering situation A in stage ST3, the process enters stage ST9; otherwise, if encountering situation D, the process enters stage ST5, and if encountering situation U, the process enters stage ST4, and if encountering situations other than situations A, D, and U, the process remains in stage ST3. When encountering situation A in stage ST5, the process enters stage ST9; otherwise, if encountering situation D, the process enters stage ST6, and if encountering situation U, the process enters stage ST4, and if encountering situations other than situations A, D, and U, the process remains in stage ST5. When encountering situation A in stage ST6, the process enters stage ST9; otherwise, if encountering situation D, the process returns to stage ST0, and if encountering situation U, the process enters stage ST4, and if encountering situations other than situations A, D, and U, the process remains in stage ST6.

[0090] If the situation A is encountered in stage ST2, the process enters stage ST9; otherwise, if the situation U is encountered, the process enters stage ST4, and if the situation other than A and U is encountered, the process remains in stage ST2. If the situation A is encountered in stage ST4, the process enters stage ST9; otherwise, if the situation U is encountered, the process enters stage ST8, and if the situation D is encountered, the process enters stage ST3, and if the situation other than A, D, and U is encountered, the process remains in stage ST4. If the situation A is encountered in stage ST8, the process enters stage ST9; otherwise, if the situation U is encountered, the process enters stage ST7, and if the situation D is encountered, the process enters stage ST3, and if the situation other than A, D, and U is encountered, the process remains in stage ST8. If the situation A is encountered in stage ST7, the process enters stage ST9; otherwise, if the situation U is encountered, the process returns to stage ST0, and if the situation D is encountered, the process enters stage ST3, and if the situation other than A, D, and U is encountered, the process remains in stage ST7.

[0091] Thus, the frequency lock determiner 150 determines whether to enter one of the stages ST0-ST9 according to the up-count pulse UPS and the down-count pulse DOWNS, and determines whether to trigger the frequency lock counting element 151 to accumulate the count value. When the count value is equal to the threshold, it is determined that the frequency lock state is reached. In the frequency lock state, the feedback signal FBCLK is already very close to or equal to the reference signal REFCLK.

[0092] like Figure 2 As shown, the digital frequency detection unit 100 may further include a first counter 110, a second counter 120, a count controller 130 and a frequency comparator 140. The first counter 110 receives the reference signal REFCLK and counts a first pulse number of the reference signal REFCLK within a counting cycle; the second counter 120 receives the feedback signal FBCLK and counts a second pulse number of the feedback signal FBCLK within the counting cycle. The count controller 130 receives the frequency lock signal LS to adjust the counting cycle, and the frequency comparator 140 is signal-connected to the first counter 110 and the second counter 120. The frequency comparator 140 compares the first pulse number and the second pulse number to output a frequency difference signal.

[0093] exist Figure 1 and Figure 2In the embodiment of the present invention, the counting cycle is variable. When the frequency lock state is not reached, the counting cycle given by the counting controller 130 may be, for example, T1. The first counter 110 counts the first pulse number in T1, and the second counter 120 counts the second pulse number in T1. The frequency comparator 140 then compares the first pulse number with the second pulse number. If the first pulse number is greater than the second pulse number, it means that the reference signal REFCLK is greater than the feedback signal FBCLK, and the frequency comparator 140 outputs an up-counting pulse UPS; conversely, if the first pulse number is less than the second pulse number, it means that the reference signal REFCLK is less than the feedback signal FBCLK, and the frequency comparator 140 outputs a down-counting pulse DOWNS.

[0094] When the frequency lock determiner 150 determines that the frequency lock state is reached, the count controller 130 receives the frequency lock signal LS and sets a count period, such as T2, which is greater than T1. Thus, before the frequency lock state is reached, the count period is shorter and faster, which can speed up the frequency lock speed; and after the frequency lock state is reached, the count period is longer and slower, which can increase the stability of the spread spectrum clock generation system 10.

[0095] See also Figure 4 ,in Figure 4 Show Figure 1 Detailed block diagram of the digital loop filter unit 200 of the spread spectrum clock generation system 10 of the embodiment. The digital loop filter unit 200 includes an integrator 250 and a control selector 230. The integrator 250 receives the clock control signal CCLK and adjusts the clock control signal CCLK according to the frequency difference signal to output a fine-tuning signal FTS. The control selector 230 receives a selection instruction CONS to select the output fine-tuning signal FTS as the clock control signal CCLK.

[0096] More specifically, in addition to the integrator 250 and the control selector 230, the digital loop filter unit 200 may further include a control code selector 210 and a decoder 220. The control code selector 210 includes a plurality of control curves, and the control code selector 210 selects a control curve according to the frequency difference signal to output a coarse tuning signal CTS. The decoder 220 receives the frequency difference signal, and outputs a fine tuning code FTC after decoding. The integrator 250 receives the clock control signal CCLK and the fine tuning code FTC to output the fine tuning signal FTS. The control selector 230 receives the coarse tuning signal CTS and the fine tuning signal FTS, and the control selector 230 receives the selection instruction CONS to select and output one of the coarse tuning signal CTS and the fine tuning signal FTS as the clock control signal CCLK. The digital loop filter unit 200 may further include a switch 240, and the switch 240 is opened and closed by the selection instruction CONS to turn on or off the integrator 250.

[0097] The control curves may be, for example, 8, one of which may be, for example, 1 MHz to 2 MHz, and another of which may be, for example, 1.5 MHz to 2.5 MHz, but the present invention is not limited thereto. The digital loop filter unit 200 may find a suitable control curve by binary search, and before a suitable control curve is found, the switch 240 is disconnected, so the integrator 250 is not activated (i.e., the integrator 250 is in an open-loop mode), and at this time, the selection instruction CONS controls the control selector 230 to output a coarse adjustment signal CTS corresponding to the selected control curve. On the contrary, when a suitable control curve is found, the selection instruction CONS switches the state of the switch 240 to activate the integrator 250 (i.e., the integrator 250 is in a closed-loop mode).

[0098] The integrator 250 includes an adding element 251 and a delay element 252. The clock control signal CCLK enters the delay element 252 and then enters the adding element 251. At the same time, the fine-tuning code FTC output by the decoder 220 also enters the adding element 251 to fine-tune the value of the clock control signal CCLK recorded at this time and generate a fine-tuning signal FTS. The selection instruction CONS controls the control selector 230 to output the fine-tuning signal FTS. If the decoder 220 only receives the up-counting pulse UPS, the output fine-tuning code FTC is 1; if the decoder 220 only receives the down-counting pulse DOWNS, the output fine-tuning code FTC is -1; if the decoder 220 receives both the up-counting pulse UPS and the down-counting pulse DOWNS, the output fine-tuning code FTC is 0. In this way, the current output clock control signal CCLK can be fine-tuned to reduce the oscillation of the spread spectrum clock generation system 10.

[0099] See also Figure 5 and Figure 6 ,in Figure 5 Show Figure 1 The detailed block diagram of the digital spread spectrum control unit 300 of the spread spectrum clock generation system 10 of the embodiment is as follows. Figure 6 Show Figure 1 Schematic diagram of a triangular wave generated by a digital spread spectrum control unit 300 of the spread spectrum clock generation system 10 of the embodiment. The digital spread spectrum control unit 300 includes a spread spectrum divider 310 and a spread spectrum counter 320. The spread spectrum divider 310 receives a reference signal REFCLK to output a divided signal. The spread spectrum counter 320 is connected to the spread spectrum divider 310. The spread spectrum counter 320 receives the divided signal to output a spread spectrum signal SS. In other words, Figure 6As shown, the spread spectrum divider 310 and the spread spectrum counter 320 can be adjusted by the user to set the required setting values, and the reference signal REFCLK can be processed by the spread spectrum divider 310 to scale the cycle time Ct (cycle time), and then after being processed by the spread spectrum counter 320, the deviation value Fd (deviation) can be scaled, and finally a triangle wave waveform that meets the requirements can be generated.

[0100] See also Figure 7 ,in Figure 7 Show Figure 1 Detailed block diagram of the digital-to-analog conversion unit 400 and the analog controlled oscillation unit 500 of the spread spectrum clock generation system 10 of the embodiment. The digital-to-analog conversion unit 400 includes a first voltage converter 410, a voltage-to-current converter 430, and a second voltage converter 420. The first voltage converter 410 receives the clock control signal CCLK to output a first voltage signal, the voltage-to-current converter 430 receives the first voltage signal to output a first control signal OCS1, and the second voltage converter 420 receives the spread spectrum signal SS to output a second control signal OCS2.

[0101] Specifically, the clock control signal CCLK and the spread spectrum signal SS are both in the form of digital signals, and the two may have the same or different bit lengths. In one embodiment, the bit length of the clock control signal may be greater than the bit length of the spread spectrum signal, and more subtle control may be performed. The first voltage converter 410 is used to convert the clock control signal CCLK from a digital signal form to an analog voltage form, so that a first voltage signal can be generated, and then the analog voltage form can be converted into an analog current form through the voltage-to-current converter 430, which is the first control signal OCS1. Similarly, the second voltage converter 420 converts the spread spectrum signal SS from a digital signal form to an analog voltage form, which is the second control signal OCS2.

[0102] Before the frequency lock state is reached, the second voltage converter 420 is not activated, and only the first voltage converter 410 and the voltage-to-current converter 430 are activated, so the analog control oscillation unit 500 is only driven by the first control signal OCS1. On the contrary, if the frequency lock state is reached, the second voltage converter 420 starts to operate, and the analog control oscillation unit 500 is driven by the first control signal OCS1 and the second control signal OCS2 at the same time, and can generate the spread spectrum clock signal SSCLK.

[0103] See also Figure 8 ,in Figure 8 Show Figure 1Detailed block diagram of the voltage control module 440 of the spread spectrum clock generation system 10 of the embodiment. The digital-to-analog conversion unit 400 further includes a voltage control module 440, the voltage control module 440 includes a first resistor R1, a second resistor R2 and a third resistor R3, the first resistor R1 includes a first end connected to a reference voltage VDD, the second resistor R2 includes a first end connected to a second end of the first resistor R1, the second resistor R2 includes a second end grounded GD, the third resistor R3 includes a first end connected to the first voltage converter 410 and the second voltage converter 420, and the third resistor R3 includes a second end connected to the first end of the second resistor R2.

[0104] In detail, the first voltage converter 410 and the second voltage converter 420 may have an R2R DAC structure, and the first voltage converter 410 and the second voltage converter 420 are respectively electrically connected to the voltage control module 440. Thus, the resistance values ​​of the first resistor R1, the second resistor R2 and the third resistor R3 may be adjusted according to the characteristics of different analog control oscillation units 500. For example, the analog control oscillation unit 500 may be operated at 1V to 2V. Then, by adjusting the resistance value, the digital signal, for example, 000 corresponds to 0V, and 111 corresponds to 2V, so that the adjustment is more linear.

[0105] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the concept and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A spread spectrum clock generation system, characterized in that: Include: A digital frequency detection unit receives a reference signal and a feedback signal, and outputs a frequency difference signal after comparing the reference signal with the feedback signal; a digital loop filter unit, signal-connected to the digital frequency detection unit, the digital loop filter unit outputting a clock control signal according to the frequency difference signal; a digital spread spectrum control unit, receiving the reference signal to output a spread spectrum signal; a digital-to-analog conversion unit, signal-connected to the digital loop filter unit and the digital spread spectrum control unit, the digital-to-analog conversion unit converts the clock control signal into a first control signal, and converts the spread spectrum signal into a second control signal; and An analog controlled oscillator unit receives the first control signal and the second control signal to output a spread spectrum clock signal; the spread spectrum clock signal is the feedback signal or the spread spectrum clock signal is divided by a feedback divider unit to form a feedback signal.

2. The spread spectrum clock generation system as claimed in claim 1, wherein: The digital frequency detection unit comprises: A frequency lock determiner determines whether a frequency lock state is reached according to the frequency difference signal to output a frequency lock signal.

3. The spread spectrum clock generation system as claimed in claim 2, wherein: The digital frequency detection unit also includes: a first counter, receiving the reference signal and counting a first pulse number of the reference signal within a counting cycle; a second counter, receiving the feedback signal and counting a second pulse number of the feedback signal within the counting period; a counting controller, receiving the frequency locking signal to adjust the counting period; and A frequency comparator is signal-connected to the first counter and the second counter. The frequency comparator compares the first pulse number with the second pulse number to output the frequency difference signal.

4. The spread spectrum clock generation system as claimed in claim 1, wherein: The digital loop filter unit comprises: a control code selector including a plurality of control curves, wherein the control code selector selects one of the control curves according to the frequency difference signal to output a coarse adjustment signal; a decoder, receiving the frequency difference signal and outputting a fine-tuning code after decoding; an integrator, receiving the clock control signal and the fine-tuning code to output a fine-tuning signal; as well as A control selector receives the coarse control signal and the fine control signal. The control selector receives a selection instruction to select and output one of the coarse control signal and the fine control signal as the clock control signal.

5. The spread spectrum clock generation system as claimed in claim 1, wherein: The digital-to-analog conversion unit comprises: A first voltage converter receives the clock control signal to output a first voltage signal; a voltage-to-current converter, receiving the first voltage signal to output the first control signal; as well as A second voltage converter receives the spread spectrum signal to output the second control signal.

6. The spread spectrum clock generation system as claimed in claim 5, wherein: The digital-to-analog conversion unit further includes a voltage control module, which includes: A first resistor including a first end connected to a reference voltage; A second resistor, comprising a first end connected to a second end of the first resistor, a second end of the second resistor being grounded; and A third resistor includes a first end connected to the first voltage converter and the second voltage converter, and the third resistor includes a second end connected to the first end of the second resistor.

7. The spread spectrum clock generation system as claimed in claim 1, wherein: The digital spread spectrum control unit comprises: a spread spectrum frequency divider, receiving the reference signal to output a frequency-divided signal; and A spread spectrum counter is signal-connected to the spread spectrum divider. The spread spectrum counter receives the divided frequency signal to output the spread spectrum signal.

8. A spread spectrum clock generation system, characterized in that: Include: A digital frequency detection unit receives a reference signal and a feedback signal, and outputs a frequency difference signal after comparing the reference signal with the feedback signal; A digital loop filter unit is signal-connected to the digital frequency detection unit. The digital loop filter unit outputs a clock control signal according to the frequency difference signal. The digital loop filter unit includes: an integrator, receiving the clock control signal, adjusting the clock control signal according to the frequency difference signal, and outputting a fine-tuning signal; and A control selector receives a selection instruction to select and output the fine-tuning signal as the clock control signal; a digital spread spectrum control unit, receiving the reference signal to output a spread spectrum signal; a digital-to-analog conversion unit, signal-connected to the digital loop filter unit and the digital spread spectrum control unit, the digital-to-analog conversion unit converts the clock control signal into a first control signal, and converts the spread spectrum signal into a second control signal; and An analog controlled oscillator unit receives the first control signal and the second control signal to output a spread spectrum clock signal; the spread spectrum clock signal is the feedback signal or the spread spectrum clock signal is divided by a feedback divider unit to form a feedback signal.

9. The spread spectrum clock generation system as claimed in claim 8, wherein: The digital frequency detection unit comprises: A frequency lock determiner determines whether a frequency lock state is reached according to the frequency difference signal to output a frequency lock signal.

10. The spread spectrum clock generation system as claimed in claim 9, wherein: The frequency lock judgement device comprises: a frequency-locked counting element for accumulating a count value; The frequency difference signal includes an up-counting pulse and a down-counting pulse. When the frequency lock determiner receives the up-counting pulse and the down-counting pulse at the same time and triggers the frequency lock counting element, if the up-counting pulse and the down-counting pulse are continuously received at the same time, the count value will be accumulated, and when the count value reaches a threshold value, the frequency lock determiner outputs the frequency lock signal.

11. The spread spectrum clock generation system as claimed in claim 9, wherein: The digital frequency detection unit also includes: a first counter, receiving the reference signal and counting a first pulse number of the reference signal within a counting cycle; a second counter, receiving the feedback signal and counting a second pulse number of the feedback signal within the counting period; a counting controller, receiving the frequency locking signal to adjust the counting period; and A frequency comparator is signal-connected to the first counter and the second counter. The frequency comparator compares the first pulse number with the second pulse number to output the frequency difference signal.

12. The spread spectrum clock generation system as claimed in claim 8, wherein: The digital-to-analog conversion unit comprises: A first voltage converter receives the clock control signal to output a first voltage signal; a voltage-to-current converter, receiving the first voltage signal to output the first control signal; a second voltage converter, receiving the spread spectrum signal to output the second control signal; and A voltage control module, comprising: A first resistor including a first end connected to a reference voltage; A second resistor including a first end connected to a second end of the first resistor, and a second end of the second resistor being grounded; and A third resistor includes a first end connected to the first voltage converter and the second voltage converter, and the third resistor includes a second end connected to the first end of the second resistor.

13. The spread spectrum clock generation system as claimed in claim 8, wherein: The digital spread spectrum control unit comprises: a spread spectrum frequency divider, receiving the reference signal to output a frequency-divided signal; and A spread spectrum counter is signal-connected to the spread spectrum divider. The spread spectrum counter receives the divided frequency signal to output the spread spectrum signal.

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