Vertical CMOS structure and preparation method

Abstract

The present invention provides a vertical CMOS structure and a preparation method thereof, wherein a vertical CMOS structure having a first conductive type transistor, an isolation layer and a second conductive type transistor stacked on each other is formed in the vertical direction, so as to improve the device density per unit area; wherein the isolation layer is formed by removing a sacrificial layer, and an inclined ring etching method is adopted, and a common drain conductive layer is formed by filling and removing silicon-containing organic matter, so as to prepare a high-quality device structure.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit manufacturing and relates to a vertical CMOS structure and a preparation method. Background Art

[0002] Transistor is a solid semiconductor device with multiple functions such as detection, rectification, amplification, switching, voltage regulation, signal modulation, etc. As a variable current switch, transistor can control the output current based on the input voltage. Unlike ordinary mechanical switches (such as relays and switches), transistors use electrical signals to control their own opening and closing, so the switching speed is very fast.

[0003] Integrated circuit devices use transistors to perform many different functions, and these transistors can take many different forms. With the development of technology and people's pursuit of miniaturized, multifunctional devices, the size of integrated circuit devices continues to shrink, but limited by the limitations of the manufacturing process, the physical size of integrated circuit devices is close to reaching the limit, the size of transistors is shrinking slowly, and it is difficult to have space for miniaturization in the horizontal direction.

[0004] The International Electron Microelectronics Research Center (IEMC) believes that complementary field effect transistors (CFETs) and vertical field effect transistors (VFETs) will be the development trend of the next and next generation of integrated circuit devices after the all-around gate field effect transistor (GAA).

[0005] Therefore, it is necessary to provide a vertical CMOS structure and a preparation method to improve the device density per unit area. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a vertical CMOS structure and a preparation method thereof, so as to solve the problem in the prior art that it is difficult to increase the device density per unit area in the horizontal direction.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a vertical CMOS structure, comprising the following steps:

[0008] providing a substrate;

[0009] forming a first conductive type transistor on the substrate, wherein the first conductive type transistor comprises a first source region, a first channel region and a first drain region stacked in sequence from bottom to top;

[0010] forming an isolation layer on the first conductive type transistor;

[0011] forming a second conductive type transistor on the isolation layer, wherein the second conductive type transistor includes a second drain region, a second channel region and a second source region stacked in sequence from bottom to top;

[0012] forming an annular groove exposing the first source region;

[0013] forming a dielectric layer covering the bottom and sidewalls of the annular groove;

[0014] forming a first gate conductive layer in the annular groove;

[0015] In the annular groove, a tilted annular etching method is used to remove a portion of the dielectric layer to expose the first drain region, the isolation layer and the second drain region, and to form a common drain conductive layer;

[0016] A second gate conductive layer is formed in the annular groove.

[0017] Optionally, the step of forming the isolation layer on the first conductive type transistor includes:

[0018] forming a first protective layer, a sacrificial layer and a second protective layer stacked in sequence on the first drain region;

[0019] Etching a portion of the second protective layer and the sacrificial layer to form an opening exposing the first protective layer;

[0020] Using wet etching to remove a portion of the sacrificial layer from the opening to form a groove connected to the opening;

[0021] The trench is filled to form the isolation layer.

[0022] Optionally, the range of the selective etching ratio of the first protective layer to the sacrificial layer includes 1:200 to 1:400; the range of the selective etching ratio of the second protective layer to the sacrificial layer includes 1:200 to 1:400; the first protective layer includes a Si layer prepared by the EPI method, the sacrificial layer includes a SiGe layer prepared by the EPI method, the second protective layer includes a Si layer prepared by the EPI method, and the etching solution of the wet etching includes hydrochloric acid; the isolation layer includes a SiO2 layer prepared by the ALD method.

[0023] Optionally, the step of forming the common drain conductive layer by using an angled ring etching method includes:

[0024] forming an electrode dielectric layer filling the annular groove;

[0025] Etching the electrode dielectric layer and the dielectric layer to form an inclined annular groove, wherein the inclined annular groove exposes the first drain region, the isolation layer and the second drain region;

[0026] Filling the inclined annular groove with silicon-containing organic matter;

[0027] removing a portion of the electrode dielectric layer and the silicon-containing organic matter to expose the first drain region, the isolation layer and the second drain region;

[0028] The common drain conductive layer is formed.

[0029] Optionally, the silicon-containing organic matter includes hydrogen silsesquioxane resin, and the method for removing the hydrogen silsesquioxane resin includes an ashing method.

[0030] Optionally, after removing the silicon-containing organic matter and before forming the common drain conductive layer, the method further includes forming a first transition metal layer in the first drain region and a second transition metal layer in the second drain region; the first transition metal layer formed covers 20% to 80% of the first drain region, and the second transition metal layer covers 20% to 80% of the second drain region.

[0031] Optionally, in the vertical direction, an angle θ is formed between the first gate conductive layer and the common drain conductive layer, and the second gate conductive layer is located within the angle θ.

[0032] Optionally, the method for forming the first conductive type transistor includes an EPI method; the method for forming the second conductive type transistor includes an EPI method; the first conductive type transistor includes an N-type transistor or a P-type transistor; the second conductive type transistor includes an N-type transistor or a P-type transistor.

[0033] Optionally, the method further includes the step of repeatedly forming one or a combination of the first conductive type transistor and the second conductive type transistor above the second conductive type transistor; and the step of forming a second source conductive layer by using a CMP method.

[0034] The present invention also provides a vertical CMOS structure, the vertical CMOS structure comprising:

[0035] substrate;

[0036] A first conductive type transistor, located on the substrate, comprising a first source region, a first channel region and a first drain region stacked in sequence from bottom to top;

[0037] An isolation layer, located on the first conductive type transistor;

[0038] A second conductive type transistor, located on the isolation layer, comprising a second drain region, a second channel region and a second source region stacked in sequence from bottom to top;

[0039] an annular groove, located on the first source region and located at the periphery of the first conductive type transistor, the isolation layer and the second conductive type transistor;

[0040] a dielectric layer, the dielectric layer covering the bottom and sidewalls of the annular groove and exposing the first drain region, the isolation layer and the second drain region;

[0041] A first gate conductive layer, a common drain conductive layer and a second gate conductive layer are located in the annular groove.

[0042] Optionally, the lower surface of the isolation layer further includes a first protective layer, and the upper surface of the isolation layer further includes a second protective layer; the first protective layer includes a Si layer, the second protective layer includes a Si layer, and the isolation layer includes a SiO2 layer.

[0043] Optionally, the surface of the first drain region further includes a first transition metal layer, and the surface of the second drain region further includes a second transition metal layer; the first transition metal layer covers 20% to 80% of the first drain region, and the second transition metal layer covers 20% to 80% of the second drain region.

[0044] Optionally, an angle θ is formed between the first gate conductive layer and the common drain conductive layer, and the second gate conductive layer is located within the angle θ.

[0045] Optionally, the first conductive type transistor includes an N-type transistor or a P-type transistor; and the second conductive type transistor includes an N-type transistor or a P-type transistor.

[0046] Optionally, the second conductivity type transistor further includes one or a combination of the first conductivity type transistor and the second conductivity type transistor.

[0047] As described above, the vertical CMOS structure and preparation method of the present invention form a vertical CMOS structure having a first conductive type transistor, an isolation layer and a second conductive type transistor stacked in the vertical direction to increase the device density per unit area; wherein the isolation layer is formed by removing the sacrificial layer, and an angled ring etching method is adopted, and a common drain conductive layer is formed by filling and removing silicon-containing organic matter to prepare a high-quality device structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a schematic diagram of the process flow of preparing a vertical CMOS structure in an embodiment.

[0049] Figure 2 to Figure 24 Shown is a schematic diagram of the structure presented in each step of preparing a vertical CMOS structure in an embodiment.

[0050] Component number description

[0051] 100 Base

[0052] 101 Bottom Silicon

[0053] 102 buried oxygen layer

[0054] 103 Top Silicon

[0055] 200 First conductivity type transistor

[0056] 201 First Source Area

[0057] 202 First channel region

[0058] 203 First Drain Region

[0059] 300 Sacrificial Layer

[0060] 401 First protection layer

[0061] 402 Second protection layer

[0062] 500 Open

[0063] 600 Grooves

[0064] 700 Isolation Layer

[0065] 800 Second conductivity type transistor

[0066] 801 Second Drain Area

[0067] 802 Second channel region

[0068] 803 Second Source Area

[0069] 900 Dielectric layer

[0070] 110 Annular groove

[0071] 120 Dielectric layer

[0072] 121 SiO2 layer

[0073] 122 HfO2 layer

[0074] 131 first gate conductive layer

[0075] 132 common drain conductive layer

[0076] 133 second gate conductive layer

[0077] 134 second source conductive layer

[0078] 141 electrode first dielectric layer

[0079] 142 electrode second dielectric layer

[0080] 143 electrode third dielectric layer

[0081] 144 electrode fourth dielectric layer

[0082] 150 DARC layer

[0083] 160 PR layer

[0084] 170 inclined annular groove

[0085] 180 Silicon-containing organic matter

[0086] 191 First transition metal layer

[0087] 192 Second transition metal layer DETAILED DESCRIPTION

[0088] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0089] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0090] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0091] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0092] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0093] See also Figure 1 This embodiment provides a method for preparing a vertical CMOS structure, which forms a vertical CMOS structure having a first conductive type transistor, an isolation layer and a second conductive type transistor stacked on each other in the vertical direction, so as to improve the device density per unit area. Figure 2 to Figure 24 The schematic diagram of the structure presented in each step when preparing the vertical CMOS structure is illustrated.

[0094] For details, see Figure 2 First, a substrate 100 is provided. In this embodiment, the substrate 100 is an SOI substrate, that is, it includes a bottom silicon 101, a buried oxide layer 102 and a top silicon 103, but the selection of the substrate 100 is not limited thereto, and other selections can be made according to specific needs.

[0095] See also Figure 2 A first conductive type transistor 200 is formed on a substrate 100 , wherein the first conductive type transistor 200 includes a first source region 201 , a first channel region 202 , and a first drain region 203 stacked in sequence from bottom to top.

[0096] As an example, a method for forming the first conductive type transistor 200 includes an EPI method; the first conductive type transistor 200 includes an N-type transistor or a P-type transistor.

[0097] Specifically, in this embodiment, the first conductive type transistor 200 is an N-type transistor, but is not limited thereto, and may also be designed as a P-type transistor, which is not excessively limited here. In the first conductive type transistor 200, the material of the first source region 201 and the first drain region 203 is SiC, the material of the first channel region 202 is Si, and the doping of the first conductive type transistor 200 may be performed during the EPI growth process. The selection of the material of the first conductive type transistor 200 is not limited thereto, and may be selected as required.

[0098] See also Figures 4 to 8 , an isolation layer 700 is formed on the first conductive type transistor 200 .

[0099] As an example, the step of forming the isolation layer 700 on the first conductive type transistor 200 includes:

[0100] A first protective layer 401, a sacrificial layer 300 and a second protective layer 402 are sequentially stacked on the first drain region 203. Figure 4 ;

[0101] Part of the second protection layer 402 and the sacrificial layer 300 are etched to form an opening 500 exposing the first protection layer 401. Figure 5 ;

[0102] By wet etching, a portion of the sacrificial layer 300 is removed from the opening 500 to form a groove 600 connected to the opening 500. Figure 6 ;

[0103] Fill the trench 600 to form the isolation layer 700. Figure 7 .

[0104] As an example, the range of the selective etching ratio of the first protective layer 401 to the sacrificial layer 300 includes 1:200 to 1:400; the range of the selective etching ratio of the second protective layer 402 to the sacrificial layer 300 includes 1:200 to 1:400; the first protective layer 401 includes a Si layer prepared by the EPI method, the sacrificial layer 300 includes a SiGe layer prepared by the EPI method, the second protective layer 402 includes a Si layer prepared by the EPI method, and the etching solution of the wet etching includes hydrochloric acid; the isolation layer 700 includes a SiO2 layer prepared by the ALD method.

[0105] Specifically, when the wet etching is performed to remove part of the sacrificial layer 300 from the opening 500, the amount of the sacrificial layer 300 that needs to be etched away can be controlled by controlling the acid soaking time of the etching solution, so that part of the sacrificial layer 300 can be retained as a support to facilitate subsequent process operations.

[0106] For example, see Figure 8 When forming the isolation layer 700, the step of removing the remaining sacrificial layer 300 and the isolation layer 700 beyond the second protective layer 402 by etching to expose the buried oxide layer 102 may be included, so as to facilitate the subsequent formation of a dielectric layer on the surface of the buried oxide layer 102 to be used as a support and isolation layer.

[0107] See also Fig. 9 , a second conductive type transistor 800 is formed on the isolation layer 700, and the second conductive type transistor 800 includes a second drain region 801, a second channel region 802 and a second source region 803 stacked in sequence from bottom to top.

[0108] As an example, a method of forming the second conductive type transistor 800 includes an EPI method; the second conductive type transistor 800 includes an N-type transistor or a P-type transistor.

[0109] Specifically, in this embodiment, since the first conductive type transistor 200 is an N-type transistor, in order to form the vertical CMOS structure, the second conductive type transistor 800 is a P-type transistor, but it is not limited to this. The second conductive type transistor 800 can also be selected as an N-type transistor according to the type of the first conductive type transistor 200, and there is no excessive restriction here. In the second conductive type transistor 800, the material of the second source region 801 and the second drain region 803 is SiGe, the material of the second channel region 802 is Si, and the doping of the second conductive type transistor 800 can be performed during the EPI growth process. The selection of the material of the second conductive type transistor 800 is not limited to this, and can be selected according to needs.

[0110] For example, see Fig. 9 , further comprising the step of forming a dielectric layer 900 on the exposed buried oxide layer 102, wherein the material of the dielectric layer 900 includes TEOS, but is not limited thereto.

[0111] See also Fig.10 , forming an annular groove 110 exposing the first source region 201.

[0112] Specifically, the cross-sectional morphology of the annular groove 110 may include any polygon such as a circular ring, a square, or a triangle, which is not excessively limited here. The step of forming the annular groove 110 may include the step of etching a portion of the dielectric layer 900 to expand the opening area of ​​the annular groove 110 within a limited volume, so as to facilitate the preparation of the vertical CMOS structure with a high integration level and a high device density.

[0113] See also Fig.11 , forming a dielectric layer 120 covering the bottom and sidewalls of the annular groove 110 .

[0114] As an example, the dielectric layer 120 includes an oxide layer and a high-K dielectric layer, wherein the oxide layer includes a SiO2 layer 121 formed by an ALD method, and the high-K dielectric layer includes a HfO2 layer formed by an ALD method, so as to improve the anti-leakage performance and stability of the device. The choice of the material of the dielectric layer 120 is not limited to this, wherein the function of the dielectric layer 120 includes being used as a gate dielectric layer.

[0115] See also Fig.12 , a first gate conductive layer 131 is formed in the annular groove 110 .

[0116] Specifically, the method for forming the first gate conductive layer 131 may include a PVD method. After the first gate conductive layer 131 is formed, a local etching step may be performed to facilitate subsequent electrical lead-out, wherein the material of the first gate conductive layer 131 may be selected from metal materials, but the material and preparation method of the first gate conductive layer 131 are not limited thereto.

[0117] See also Figure 13 to Figure 17 In the annular groove 110 , a tilted annular etching method is used to remove a portion of the dielectric layer 120 to expose the first drain region 203 , the isolation layer 700 and the second drain region 801 , and to form a common drain conductive layer 132 .

[0118] As an example, the steps of forming the common drain conductive layer 132 by using the angled ring etching method include:

[0119] forming an electrode dielectric layer filling the annular groove 110;

[0120] Etching the electrode dielectric layer and the dielectric layer 120 to form an inclined annular groove 170, wherein the inclined annular groove 170 exposes the first drain region 203, the isolation layer 700 and the second drain region 801;

[0121] Filling the inclined annular groove 170 with a silicon-containing organic substance 180;

[0122] Removing part of the electrode dielectric layer and the silicon-containing organic material 180 to expose the first drain region 203, the isolation layer 700 and the second drain region 801;

[0123] The common drain conductive layer 132 is formed.

[0124] For details, see Fig.13 , first deposit the first electrode dielectric layer 141 to fill the annular groove 110. Then, form the DARC layer 150 and the PR layer 160, and pattern the DARC layer 150 by exposure and development to form a pre-etched window, wherein the etching angle can be controlled by controlling the position of the opening of the mask to form the inclined annular groove 170, see Fig.14 . See Fig.15 After forming the inclined annular groove 170, the inclined annular groove 170 is filled with a silicon-containing organic material 180 to cover and protect the exposed first drain region 203, the isolation layer 700 and the second drain region 801. Fig.16 and Fig.17 , remove part of the electrode first dielectric layer 141 and the silicon-containing organic material 180, and form the common drain conductive layer 132. The material of the electrode first dielectric layer 141 can be TEOS, and the material of the common drain conductive layer 132 can be metal, but it is not limited thereto.

[0125] As an example, the silicon-containing organic matter 180 includes hydrogen silsesquioxane resin, and the method of removing the hydrogen silsesquioxane resin includes an ashing method.

[0126] For details, see Fig.15 , firstly, an etching method is used to remove part of the electrode first dielectric layer 141 and the silicon-containing organic material 180. At this time, the remaining silicon-containing organic material 180 can protect the first drain region 203, the isolation layer 700 and the second drain region 801; see Fig.16 Then, the residual silicon-containing organic substance 180 located outside the first drain region 203, the isolation layer 700 and the second drain region 801 can be removed by an ashing method to expose the first drain region 203, the isolation layer 700 and the second drain region 801, thereby reducing damage and improving the stability of the device.

[0127] As an example, after removing the silicon-containing organic matter 180 and before forming the common drain conductive layer 132, the method also includes the steps of forming a first transition metal layer 191 in the first drain region 203 and forming a second transition metal layer 192 in the second drain region 801; the formed first transition metal layer 191 covers 20% to 80% of the first drain region 203, and the second transition metal layer 192 covers 20% to 80% of the second drain region 801.

[0128] Specifically, the material of the first transition metal layer 191 and the second transition metal layer 192 includes metal silicide; since the first drain region 203, the first protective layer 401, the second protective layer 402 and the second drain region 801 are formed by the EPI method, and the isolation layer 700 is formed by the ALD method, metal silicide, namely the first transition metal layer 191 and the second transition metal layer 192, can be formed only on the surface of the exposed first drain region 203 and the second drain region 801 to reduce resistance. In order to further improve the stability of the device, it is preferred that when forming the inclined annular groove 170, by controlling the etching tilt angle, the bottom boundary of the inclined annular groove 170 is located at 20% to 80% of the drain region, such as Fig.14 , thereby forming the first transition metal layer 191 covering 20% ​​to 80% of the first drain region 203, and the second transition metal layer 192 covering 20% ​​to 80% of the second drain region 801, so as to further improve the stability of the device, such as Fig.17 .

[0129] See also Fig.18After forming the first transition metal layer 191 and the second transition metal layer 192, the step of depositing the electrode second dielectric layer 142 is also included to further improve the stability of the device, wherein the material of the electrode second dielectric layer 142 includes TEOS, but is not limited thereto. After forming the common drain conductive layer 132, the step of etching the common drain conductive layer 132 is also included to facilitate subsequent electrical extraction.

[0130] It should be noted that Figures 2 to 18 and Fig.23 All of them are shown as schematic diagrams of the vertical CMOS structure formed in the X direction. For ease of understanding, Figure 19 to Figure 22 The structure diagram of the vertical CMOS structure formed in the Y direction is also shown. Fig.24 Also shown is a schematic diagram of a top view of the vertical CMOS structure.

[0131] See also Fig. 20 , a second gate conductive layer 133 is formed in the annular groove 110 .

[0132] Specifically, before forming the second gate conductive layer 133, a step of depositing an electrode third dielectric layer 143 is included to cover the common drain conductive layer 132. The material of the electrode third dielectric layer 143 can be TEOS, but is not limited thereto. After forming the second gate conductive layer 133, a step of etching the second gate conductive layer 133 is included to facilitate subsequent electrical extraction. Fig.21 After forming the second gate conductive layer 133 , the method further includes depositing an electrode fourth dielectric layer 144 to cover the second gate conductive layer 133 . The material of the electrode fourth dielectric layer 144 may be TEOS, but is not limited thereto.

[0133] As an example, the method further includes repeatedly forming one or a combination of the first conductivity type transistor 200 and the second conductivity type transistor 800 above the second conductivity type transistor 800 .

[0134] Specifically, by repeatedly forming the first conductive type transistor 200 and the second conductive type transistor 800 above the second conductive type transistor 800, a plurality of vertically stacked CMOS structures can be formed above the second conductive type transistor 800 to improve device integration and expand the scope of application. As needed, the step of repeatedly forming the first conductive type transistor 200 or the second conductive type transistor 800 above the second conductive type transistor 800 may also be included, and no excessive restrictions are made here.

[0135] For example, see Fig. 22, and also includes the steps of using a CMP method to expose the second source region 803 and form a second source conductive layer 134, but the preparation method is not limited thereto.

[0136] As an example, in the vertical direction, an angle θ is formed between the first gate conductive layer 131 and the common drain conductive layer 132 , and the second gate conductive layer 133 is located within the angle θ.

[0137] For details, see Fig. 22 , which is a schematic diagram showing a structure of forming the vertical CMOS structure in the Y direction, see Fig.23 , which is a schematic diagram showing a structure of forming the vertical CMOS structure from the X direction, and referring to Fig.24 , which is a schematic diagram of a top view of the vertical CMOS structure formed in the Z-axis direction. In order to facilitate electrical extraction, in this embodiment, the first gate conductive layer 131, the common drain conductive layer 132 and the second gate conductive layer 133 are preferably arranged vertically in pairs, but the present invention is not limited thereto.

[0138] See also Figure 21 to Figure 24 This embodiment further provides a vertical CMOS structure, wherein the method for forming the vertical CMOS structure may refer to the above-mentioned preparation method, but is not limited thereto and will not be described in detail here.

[0139] Specifically, the vertical CMOS structure includes a substrate 100 , a first conductive type transistor 200 , an isolation layer 700 , a second conductive type transistor 800 , an annular groove, a dielectric layer 120 , a first gate conductive layer 131 , a common drain conductive layer 132 and a second gate conductive layer 133 . Among them, the first conductive type transistor 200 is located on the substrate 100, including a first source region 201, a first channel region 202 and a first drain region 203 stacked in sequence from bottom to top; the isolation layer 700 is located on the first conductive type transistor 200; the second conductive type transistor 800 is located on the isolation layer 700, including a second drain region 801, a second channel region 802 and a second source region 803 stacked in sequence from bottom to top; the annular groove is located on the first source region 201, and is located at the periphery of the first conductive type transistor 200, the isolation layer 700 and the second conductive type transistor 800; the dielectric layer 120 covers the bottom and sidewalls of the annular groove, and exposes the first drain region 201, the isolation layer 700 and the second drain region 801; the first gate conductive layer 131, the common drain conductive layer 132 and the second gate conductive layer 133 are located in the annular groove.

[0140] As an example, the lower surface of the isolation layer 700 also includes a first protective layer 401, and the upper surface of the isolation layer 700 also includes a second protective layer 402; the first protective layer includes a Si layer, the second protective layer includes a Si layer, and the isolation layer includes a SiO2 layer.

[0141] As an example, the surface of the first drain region 203 also includes a first transition metal layer 191, and the surface of the second drain region 801 also includes a second transition metal layer 192; the first transition metal layer 191 covers 20% to 80% of the first drain region 203, and the second transition metal layer 192 covers 20% to 80% of the second drain region 801.

[0142] As an example, in the vertical direction, there is an angle θ between the first gate conductive layer 131 and the common drain conductive layer 132, and the second gate conductive layer 133 is located in the angle θ. Preferably, the first gate conductive layer 131, the common drain conductive layer 132 and the second gate conductive layer 133 are arranged vertically in pairs.

[0143] As an example, the first conductive type transistor 200 includes an N-type transistor or a P-type transistor; the second conductive type transistor 800 includes an N-type transistor or a P-type transistor.

[0144] As an example, the second conductive type transistor 800 further includes one or a combination of the first conductive type transistor 200 and the second conductive type transistor 800 to increase device integration density. If necessary, the combination of the first conductive type transistor 200 and the second conductive type transistor 800 may be repeatedly formed above the second conductive type transistor 800, or the first conductive type transistor 200 or the second conductive type transistor 800 may be repeatedly formed only above the second conductive type transistor 800, and no excessive limitation is made here.

[0145] In summary, the vertical CMOS structure and preparation method of the present invention form a vertical CMOS structure having a first conductive type transistor, an isolation layer and a second conductive type transistor stacked in the vertical direction to increase the device density per unit area; wherein the isolation layer is formed by removing the sacrificial layer, and an angled ring etching method is adopted, and a common drain conductive layer is formed by filling and removing silicon-containing organic matter to prepare a high-quality device structure.

[0146] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a vertical CMOS structure, characterized in that: The following steps are involved: providing a substrate; forming a first conductive type transistor on the substrate, wherein the first conductive type transistor comprises a first source region, a first channel region and a first drain region stacked in sequence from bottom to top; forming an isolation layer on the first conductive type transistor; forming a second conductive type transistor on the isolation layer, wherein the second conductive type transistor includes a second drain region, a second channel region and a second source region stacked in sequence from bottom to top; forming an annular groove exposing the first source region; forming a dielectric layer covering the bottom and sidewalls of the annular groove; forming a first gate conductive layer in the annular groove; In the annular groove, a tilted annular etching method is used to remove a portion of the dielectric layer to expose the first drain region, the isolation layer and the second drain region, and to form a common drain conductive layer; forming a second gate conductive layer in the annular groove; The steps of forming the common drain conductive layer by using the angled ring etching method include: forming an electrode dielectric layer filling the annular groove; Etching the electrode dielectric layer and the dielectric layer to form an inclined annular groove, wherein the inclined annular groove exposes the first drain region, the isolation layer and the second drain region; Filling the inclined annular groove with silicon-containing organic matter; removing a portion of the electrode dielectric layer and the silicon-containing organic matter to expose the first drain region, the isolation layer and the second drain region; The common drain conductive layer is formed.

2. The method for preparing a vertical CMOS structure according to claim 1, characterized in that: The step of forming the isolation layer on the first conductive type transistor comprises: forming a first protective layer, a sacrificial layer and a second protective layer stacked in sequence on the first drain region; Etching a portion of the second protective layer and the sacrificial layer to form an opening exposing the first protective layer; Using wet etching to remove a portion of the sacrificial layer from the opening to form a groove connected to the opening; The trench is filled to form the isolation layer.

3. The method for preparing a vertical CMOS structure according to claim 2, characterized in that: The selective etching ratio of the first protective layer to the sacrificial layer ranges from 1:200 to 1:400; the selective etching ratio of the second protective layer to the sacrificial layer ranges from 1:200 to 1:400; the first protective layer includes a Si layer prepared by the EPI method, the sacrificial layer includes a SiGe layer prepared by the EPI method, the second protective layer includes a Si layer prepared by the EPI method, and the etching solution for wet etching includes hydrochloric acid; the isolation layer includes a SiO2 layer prepared by the ALD method.

4. The method for preparing a vertical CMOS structure according to claim 1, characterized in that: The silicon-containing organic matter includes hydrogen silsesquioxane resin, and the method for removing the hydrogen silsesquioxane resin includes an ashing method.

5. The method for preparing a vertical CMOS structure according to claim 1, characterized in that: After removing the silicon-containing organic matter and before forming the common drain conductive layer, the method also includes the steps of forming a first transition metal layer in the first drain region and forming a second transition metal layer in the second drain region; the first transition metal layer formed covers 20% to 80% of the first drain region, and the second transition metal layer covers 20% to 80% of the second drain region.

6. The method for preparing a vertical CMOS structure according to claim 1, characterized in that: In the vertical direction, an angle θ is formed between the first gate conductive layer and the common drain conductive layer, and the second gate conductive layer is located within the angle θ.

7. The method for preparing a vertical CMOS structure according to claim 1, characterized in that: The method for forming the first conductive type transistor includes the EPI method; the method for forming the second conductive type transistor includes the EPI method; the first conductive type transistor includes an N-type transistor or a P-type transistor; the second conductive type transistor includes an N-type transistor or a P-type transistor.

8. The method for preparing a vertical CMOS structure according to claim 1, characterized in that: The method further includes the step of repeatedly forming one or a combination of the first conductive type transistor and the second conductive type transistor above the second conductive type transistor; and the step of forming a second source conductive layer by using a CMP method.

9. A vertical CMOS structure, characterized in that: The vertical CMOS structure comprises: substrate; A first conductive type transistor, located on the substrate, comprising a first source region, a first channel region and a first drain region stacked in sequence from bottom to top; An isolation layer, located on the first conductive type transistor; A second conductive type transistor, located on the isolation layer, comprising a second drain region, a second channel region and a second source region stacked in sequence from bottom to top; an annular groove, located on the first source region and located at the periphery of the first conductive type transistor, the isolation layer and the second conductive type transistor; A first gate conductive layer, a common drain conductive layer and a second gate conductive layer located in the annular groove; The steps of forming the first gate conductive layer and the common drain conductive layer include: forming a dielectric layer covering the bottom and sidewalls of the annular groove; forming the first gate conductive layer in the annular groove; In the annular groove, a tilted annular etching method is used to remove a portion of the dielectric layer to expose the first drain region, the isolation layer and the second drain region, and to form a common drain conductive layer; Furthermore, the step of forming the common drain conductive layer by using an angled ring etching method includes: forming an electrode dielectric layer filling the annular groove; Etching the electrode dielectric layer and the dielectric layer to form an inclined annular groove, wherein the inclined annular groove exposes the first drain region, the isolation layer and the second drain region; Filling the inclined annular groove with silicon-containing organic matter; removing a portion of the electrode dielectric layer and the silicon-containing organic matter to expose the first drain region, the isolation layer and the second drain region; The common drain conductive layer is formed.

10. The vertical CMOS structure according to claim 9, characterized in that: The lower surface of the isolation layer further includes a first protective layer, and the upper surface of the isolation layer further includes a second protective layer; the first protective layer includes a Si layer, the second protective layer includes a Si layer, and the isolation layer includes a SiO2 layer.

11. The vertical CMOS structure according to claim 9, characterized in that: The surface of the first drain region also includes a first transition metal layer, and the surface of the second drain region also includes a second transition metal layer; the first transition metal layer covers 20% to 80% of the first drain region, and the second transition metal layer covers 20% to 80% of the second drain region.

12. The vertical CMOS structure according to claim 9, characterized in that: In the vertical direction, an angle θ is formed between the first gate conductive layer and the common drain conductive layer, and the second gate conductive layer is located within the angle θ.

13. The vertical CMOS structure according to claim 9, characterized in that: The first conductive type transistor includes an N-type transistor or a P-type transistor; the second conductive type transistor includes an N-type transistor or a P-type transistor.

14. The vertical CMOS structure according to claim 9, characterized in that: The second conductive type transistor also includes one or a combination of the first conductive type transistor and the second conductive type transistor.

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