Magnetic Recording Array

Abstract

The magnetic recording array (200) of this embodiment comprises a plurality of spin elements (100) and a common transistor (STr) connected to adjacent first and second spin elements, wherein the plurality of spin elements respectively comprise wiring (20) and a stack (10) comprising a first ferromagnetic layer (1) stacked on the wiring, wherein the common transistor comprises a first gate (G1), a second gate (G2), a first region (A1), a second region (A2) and a third region (A3), wherein when viewed from above in the stacking direction of the stack, the first region is sandwiched between the first gate and the second gate, the second region and the first region sandwich the first gate, the third region and the first region sandwich the second gate, one of the second region and the third region is connected to the first spin element, and the other is connected to the second spin element.

Description

Technical Field

[0001] The invention relates to a magnetic recording array. Background Art

[0002] Next-generation nonvolatile memories that replace flash memory, which has reached its limit in terms of miniaturization, are attracting much attention. Examples of next-generation nonvolatile memories include MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistance Random Access Memory), and PCRAM (Phase Change Random Access Memory).

[0003] MRAM is a storage element using a magnetoresistive element. The resistance of the magnetoresistive element changes according to the relative angle between the magnetization directions of two magnetic films. MRAM records the resistance of the magnetoresistive element as data.

[0004] Among spin elements utilizing magnetoresistance changes, spin-orbit torque type magnetoresistance effect elements utilizing spin-orbit torque (SOT) (e.g., Patent Document 1) or domain wall movement type magnetic recording elements utilizing the movement of magnetic domain walls (e.g., Patent Document 2) have attracted much attention.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent document 1: Japanese Patent Application Publication No. 2017-216286.

[0008] Patent document 2: Japanese Patent No. 5441005. Summary of the invention

[0009] Problems to be solved by the invention

[0010] In a 3-terminal spin element, the current path when writing data is different from the current path when reading data. These spin elements require multiple transistors to control the read current and the write current separately. In other words, in order to operate one spin element, it is necessary to ensure an area equivalent to multiple transistors.

[0011] The present invention is proposed in view of the above-mentioned problems, and an object of the present invention is to provide a magnetic recording array capable of improving integration.

[0012] Technical solutions to the problem

[0013] (1) A first method provides a magnetic recording array, which has a plurality of spin elements and a common transistor connected to adjacent first and second spin elements, wherein the plurality of spin elements respectively have wiring and a stacked body including a first ferromagnetic layer stacked on the wiring, and the common transistor has a first gate, a second gate, a first region, a second region and a third region. When viewed from the stacking direction of the stacked body, the first region is sandwiched by the first gate and the second gate, the second region and the first region sandwich the first gate, the third region and the first region sandwich the second gate, and one of the second region and the third region is connected to the first spin element, and the other is connected to the second spin element.

[0014] (2) The magnetic recording array of the above aspect may include a plurality of the common transistors, and may further include a first wiring connected across the first regions of the plurality of the common transistors.

[0015] (3) The magnetic recording array of the above aspect may further include a first wiring control transistor connected to the first wiring.

[0016] (4) The magnetic recording array of the above aspect may include a plurality of the first wirings, and adjacent first wirings may be connected via a short-circuit transistor.

[0017] (5) The magnetic recording array of the above aspect may further include a second wiring connected across the stacked body of the plurality of spin elements.

[0018] (6) The magnetic recording array of the above aspect may further include a second wiring control transistor connected to the second wiring.

[0019] (7) The magnetic recording array of the above aspect may further include a first gate wiring connected to the first gate and a second gate wiring connected to the second gate.

[0020] (8) In the magnetic recording array of the above aspect, the first gate wiring and the second gate wiring may be at different heights.

[0021] (9) In the magnetic recording array of the above-mentioned method, it may also be that the common transistor has a first common transistor, a second common transistor and a third common transistor, the first spin element is connected to the first common transistor and the second region of the second common transistor, and the second spin element is connected to the second common transistor and the third region of the third common transistor.

[0022] (10) In the magnetic recording array of the above-mentioned method, it may be that at least one of the multiple spin elements is a first reference element whose wiring resistance is higher than that of other spin elements, and at least one of the multiple spin elements is a second reference element whose wiring resistance is lower than that of other spin elements.

[0023] (11) In the magnetic recording array of the above aspect, the wiring width of the wiring of the first reference element may be narrower than the wiring width of other spin elements, and the wiring width of the wiring of the second reference element may be wider than the wiring width of other spin elements.

[0024] (12) In the magnetic recording array of the above-mentioned manner, the stack may also have the first ferromagnetic layer, the non-magnetic layer and the second ferromagnetic layer from the side close to the wiring, and the wiring is any one of a metal, an alloy, an intermetallic compound, a metal boride, a metal carbide, a metal silicide, and a metal phosphide having the function of generating a spin current through the spin Hall effect when an electric current flows.

[0025] (13) In the magnetic recording array of the above aspect, the stacked body may include a nonmagnetic layer and the first ferromagnetic layer from a side close to the wiring, and the wiring may be a ferromagnetic layer that can have a magnetic domain wall inside.

[0026] Effects of the Invention

[0027] The magnetic recording array of the above-described method has excellent integration properties. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a circuit diagram of the magnetic recording array of the first embodiment.

[0029] Figure 2 It is a cross-sectional view of the magnetic recording array according to the first embodiment.

[0030] Figure 3 It is a top view of the magnetic recording array of the first embodiment.

[0031] Figure 4 It is a cross-sectional view of the spin element according to the first embodiment.

[0032] Figure 5 It is a circuit diagram of the magnetic recording array of the second embodiment.

[0033] Figure 6 It is a circuit diagram of a magnetic recording array according to a third embodiment.

[0034] Figure 7 It is a cross-sectional view of a spin element according to a fourth embodiment.

[0035] Figure 8It is a cross-sectional view of the spin element according to the fifth embodiment. DETAILED DESCRIPTION

[0036] Hereinafter, the present embodiment will be described in detail with reference to the accompanying drawings as appropriate. In order to make the features easier to understand, the accompanying drawings used in the following description sometimes enlarge the portions that become features, and the dimensional ratios of the various components are sometimes different from the actual ones. The materials, dimensions, etc. illustrated in the following description are examples, and the present invention is not limited thereto, and can be appropriately changed and implemented within the scope of achieving the effects of the present invention.

[0037] First, define the direction. Figure 2 ) is set as the x-direction, and the direction orthogonal to the x-direction is set as the y-direction. The x-direction is, for example, the row direction in which the spin elements are arranged in the magnetic recording array described later. The y-direction is, for example, the column direction in which the spin elements are arranged in the magnetic recording array described later. The z-direction is a direction orthogonal to the x-direction and the y-direction. The z-direction is an example of a stacking direction. In the following, the +z direction is sometimes expressed as "up" and the -z direction is expressed as "down". Up and down are not necessarily consistent with the direction in which gravity is applied.

[0038] (First Embodiment)

[0039] Figure 1 2 is a circuit diagram of the magnetic recording array 200 according to the first embodiment. The magnetic recording array 200 includes an integrated area IA and a peripheral area PA.

[0040] The integrated region IA is a region where a plurality of magnetoresistance effect elements 100 are integrated. The magnetoresistance effect element 100 is an example of a spin element. The integrated region IA, for example, includes a plurality of magnetoresistance effect elements 100, a plurality of shared transistors STr, a plurality of first wirings L1, a plurality of second wirings L2, a plurality of first gate wirings GL1, and a plurality of second gate wirings GL2. If the integration within the integrated region IA is improved, the recording density of the magnetic recording array 200 is improved.

[0041] The magnetoresistance effect elements 100 are arranged in a matrix, for example. The common transistor STr is, for example, between magnetoresistance effect elements 100 adjacent to each other in the x direction. The common transistor STr is a component that combines two transistors Tr. The common transistor STr is, for example, connected to each of two magnetoresistance effect elements 100 adjacent to each other in the x direction. Sometimes, a magnetoresistance effect element 100 connected to the common transistor STr is referred to as a first magnetoresistance effect element, and the other magnetoresistance effect element 100 is referred to as a second magnetoresistance effect element. The first magnetoresistance effect element is an example of a first spin element, and the second magnetoresistance effect element is an example of a second spin element.

[0042] The first wiring L1 is connected to the wiring 20 described later of the magnetoresistance effect element 100 via the transistor Tr, for example. The first wiring L1 extends in the y direction, for example, and is arranged in the x direction. The first wiring L1 is connected to each of the magnetoresistance effect elements 100 in the same column, for example.

[0043] The second wiring L2 is connected to, for example, a stacked body 10 described later of the magnetoresistance effect element 100. A switching element (for example, a transistor) may be provided between the stacked body 10 and the second wiring L2. The second wiring L2 extends, for example, in the y direction and is arranged in the x direction. The second wiring L2 is connected to, for example, each of the magnetoresistance effect elements 100 in the same column.

[0044] The first gate wiring GL1 is connected to a first gate G1 of the common transistor STr, which will be described later. The first gate wiring GL1 extends in the x direction, for example, and is arranged in the y direction. The first gate wiring GL1 is connected to the common transistor STr in the same row, for example.

[0045] The second gate wiring GL2 is connected to a second gate G2 of the common transistor STr, which will be described later. The second gate wiring GL2 extends in the x direction, for example, and is arranged in the y direction. The second gate wiring GL2 is connected to the common transistor STr in the same row, for example.

[0046] The peripheral area PA is an area where a control element for controlling the operation of the magnetoresistance effect element 100 in the integrated area IA is installed. The peripheral area PA is, for example, located outside the integrated area IA. The peripheral area PA has, for example, a plurality of first wiring control transistors Tr3, a plurality of second wiring control transistors Tr4, a plurality of first gate transistors GTr1, and a plurality of second gate transistors GTr2.

[0047] The first wiring control transistor Tr3 is connected to each of the first wirings L1. The first wiring control transistor Tr3 is connected to, for example, an end of the first wiring L1. The first wiring control transistor Tr3 controls the current flowing in the first wiring L1. By controlling the first wiring control transistor Tr3 and the transistor Tr, the writing of data into the magnetoresistive effect element 100 can be controlled.

[0048] The second wiring control transistor Tr4 is connected to the second wiring L2. The second wiring control transistor Tr4 is connected to the end of the second wiring L2, for example. The second wiring control transistor Tr4 controls the current flowing in the second wiring L2. By controlling the second wiring control transistor Tr4 and the transistor Tr, the reading of data from the magnetoresistive effect element 100 can be controlled.

[0049] The first gate transistor GTr1 is connected to each of the first gate wirings GL1. The first gate transistor GTr1 is connected to an end of the first gate wiring GL1. The first gate transistor GTr1 controls the current flowing through the first gate wiring GL1, and controls the on / off of one transistor Tr in the common transistor STr.

[0050] The second gate transistor GTr2 is connected to each of the second gate wirings GL2. The second gate transistor GTr2 is connected to an end of the second gate wiring GL2. The second gate transistor GTr2 controls the current flowing through the second gate wiring GL2, and controls the on / off of one transistor Tr in the common transistor STr.

[0051] The first wiring control transistor Tr3, the second wiring control transistor Tr4, the first gate transistor GTr1 and the second gate transistor GTr2 are, for example, field effect transistors. The first wiring control transistor Tr3, the second wiring control transistor Tr4, the first gate transistor GTr1 and the second gate transistor GTr2 may be replaced by other switching elements. The switching element may be, for example, an element utilizing the phase change of the crystal layer such as a bidirectional threshold switch (OTS: Ovonic Threshold Switch), an element utilizing the change of the band structure such as a metal insulator transition (MIT) switch, an element utilizing the breakdown voltage such as a Zener diode and an avalanche diode, or an element whose conductivity changes with the change of the atomic position.

[0052] Figure 2 It is a cross-sectional view of the magnetic recording array 200 according to the first embodiment. Figure 2 is an xz cross section passing through the center of the magnetoresistive effect element 100 in the y direction. Figure 2 In FIG. 1 , for the sake of explanation, the first gate wiring GL1 and the second gate wiring GL2 at different positions in the y direction are indicated by dotted lines. Figure 3 This is a plan view of the magnetic recording array 200 according to the first embodiment as viewed from the z direction. Figure 3 Only the conductive portion is extracted for illustration.

[0053] The magnetoresistance effect element 100 and the common transistor STr are located on the substrate Sub. The magnetoresistance effect element 100 and the common transistor STr are connected by a via wiring V1. The magnetoresistance effect element 100 and the common transistor STr are located at different positions in the z direction and are located in different layers.

[0054] The magnetoresistance effect element 100, the common transistor STr, and the via wiring V1 are covered by an insulating layer In. The insulating layer In is an insulating layer for insulating between wirings or between elements of the multilayer wiring. The insulating layer In is made of, for example, silicon oxide (SiO x ), Silicon Nitride (SiNx ), silicon carbide (SiC), chromium nitride, silicon carbonitride (SiCN), silicon oxynitride (SiON), aluminum oxide (Al2O3), zirconium oxide (ZrO x )wait.

[0055] The common transistor STr is, for example, a field effect transistor and includes a first gate G1, a second gate G2, a gate insulating film GI, a first region A1, a second region A2, and a third region A3.

[0056] The first region A1, the second region A2, and the third region A3 are source regions or drain regions of the transistor. The first region A1, the second region A2, and the third region A3 are formed on a substrate Sub. The substrate Sub is, for example, a semiconductor substrate. When viewed from the z direction, the first region A1 is sandwiched between the first gate G1 and the second gate G2. When viewed from the z direction, the second region A2 and the first region A1 sandwich the first gate G1. When viewed from the z direction, the third region A3 and the first region A1 sandwich the second gate G2.

[0057] The first gate G1 controls the flow of charges between the first region A1 and the second region A2. The second gate G2 controls the flow of charges between the second region A2 and the third region A3. The first region A1, the second region A2, and the first gate G1 function as a transistor Tr, and the first region A1, the third region A3, and the second gate G2 function as a transistor Tr.

[0058] The first region A1 is in contact with, for example, the first wiring L1. The first wiring L1 is connected, for example, over the first regions A1 of the plurality of common transistors STr adjacent to each other in the y direction.

[0059] The second region A2 and the third region A3 are connected via the magnetoresistance effect element 100 and the via wiring V1. The second region A2 and the third region A3 are connected to different magnetoresistance effect elements 100. For example, the second region A2 is connected to the first magnetoresistance effect element 100A via the via wiring V1, and the third region A3 is connected to the second magnetoresistance effect element 100B via the via wiring V1.

[0060] The first gate G1 is connected to the first gate wiring GL1. The second gate G2 is connected to the second gate wiring GL2. The first gate wiring GL1 and the second gate wiring GL2 are at different heights in the z direction, for example. If the first gate wiring GL1 and the second gate wiring GL2 have different heights in the z direction, the wiring connection becomes easier, and the integration of the integration area IA is improved.

[0061] In the common transistors STr adjacent to each other in the x direction, the arrangement order of the components constituting the common transistors STr is reversed. For example, the three common transistors arranged in the x direction among the common transistors STr are called the first common transistor STr1, the second common transistor STr2, and the third common transistor STr3. The first common transistor STr1 is arranged in the order of the third region A3, the second gate G2, the first region A1, the first gate G1, and the second region A2 in the x direction, whereas the second common transistor STr2 is arranged in the order of the second region A2, the first gate G1, the first region A1, the second gate G2, and the third region A3 in the x direction.

[0062] The first common transistor STr1 and the second common transistor STr2 are connected to, for example, the first magnetoresistance effect element 100A. The second common transistor STr2 and the third common transistor STr3 are connected to, for example, the second magnetoresistance effect element 100B.

[0063] The first magnetoresistance effect element 100A is connected to the second region A2 of the first common transistor STr1 and the second common transistor STr2, respectively. That is, writing of data to the first magnetoresistance effect element 100A is controlled by the first gate G1 of the first common transistor STr1 and the second common transistor STr2.

[0064] The second magnetoresistance effect element 100B is connected to the third region A3 of the second common transistor STr2 and the third common transistor STr3, respectively. That is, writing of data to the second magnetoresistance effect element 100B is controlled by the second gate G2 of the second common transistor STr2 and the third common transistor STr3.

[0065] In the magnetoresistance effect element 100 , elements for which writing is controlled by the first gate G1 (for example, the first magnetoresistance effect element 100A) and elements for which writing is controlled by the second gate G2 (for example, the second magnetoresistance effect element 100B) are alternately arranged in the x direction.

[0066] Figure 4 2 is a cross-sectional view of the magnetoresistance effect element 100 according to the first embodiment. Figure 4 The cross section of the magnetoresistive effect element 100 is obtained by cutting the magnetoresistive effect element 100 along an xz plane passing through the center of the width of the wiring 20 in the y direction.

[0067] The magnetoresistance effect element 100 includes, for example, a stack 10, a wiring 20, and conductive portions 31 and 32. The resistance value in the z direction of the stack 10 changes due to the injection of spins from the wiring 20 into the stack 10. The magnetoresistance effect element 100 is a spin element using spin-orbit torque (SOT), and is sometimes called a spin-orbit torque type magnetoresistance effect element, a spin injection type magnetoresistance effect element, or a spin current magnetoresistance effect element. In addition, the wiring 20 is sometimes called a spin-orbit torque wiring.

[0068] The laminate 10 is laminated on the wiring 20. Another layer may be provided between the laminate 10 and the wiring 20. The laminate 10 is sandwiched between the wiring 20 and the electrode E in the z direction. The laminate 10 is a columnar body. When the laminate 10 is viewed from the z direction, the shape is, for example, circular, elliptical, or quadrilateral.

[0069] The laminate 10 includes a first ferromagnetic layer 1, a second ferromagnetic layer 2, and a non-magnetic layer 3. The first ferromagnetic layer 1 is connected to, for example, a wiring 20 and is laminated on the wiring 20. Spins are injected from the wiring 20 into the first ferromagnetic layer 1. The magnetization of the first ferromagnetic layer 1 receives a spin-orbit torque (SOT) by the injected spins, and the orientation direction changes. The second ferromagnetic layer 2 is located in the z direction of the first ferromagnetic layer 1. The first ferromagnetic layer 1 and the second ferromagnetic layer 2 sandwich the non-magnetic layer 3 in the z direction.

[0070] The first ferromagnetic layer 1 and the second ferromagnetic layer 2 each have magnetization. When a predetermined external force is applied, the magnetization of the second ferromagnetic layer 2 is less likely to change its orientation direction than the magnetization of the first ferromagnetic layer 1. The first ferromagnetic layer 1 is sometimes called a magnetization free layer, and the second ferromagnetic layer 2 is sometimes called a magnetization fixed layer or a magnetization reference layer. The resistance of the laminate 10 changes depending on the relative angle of the magnetization of the first ferromagnetic layer 1 and the second ferromagnetic layer 2 sandwiching the nonmagnetic layer 3.

[0071] The first ferromagnetic layer 1 and the second ferromagnetic layer 2 include a ferromagnetic material. The ferromagnetic material is, for example, a metal selected from the group consisting of Cr, Mn, Co, Fe, and Ni, an alloy containing one or more of these metals, an alloy containing these metals and at least one element of B, C, and N, etc. The ferromagnetic material is, for example, Co-Fe, Co-Fe-B, Ni-Fe, Co-Ho alloy, Sm-Fe alloy, Fe-Pt alloy, Co-Pt alloy, and CoCrPt alloy.

[0072] The first ferromagnetic layer 1 and the second ferromagnetic layer 2 may also include a Whistler alloy. The Whistler alloy includes an intermetallic compound having a chemical composition of XYZ or X2YZ. X is a transition metal element or a noble metal element of the Co, Fe, Ni, or Cu group in the periodic table, Y is a transition metal of the Mn, V, Cr, or Ti group or an element type of X, and Z is a typical element of the III group to the V group. The Whistler alloy is, for example, Co2FeSi, Co2FeGe, Co2FeGa, Co2MnSi, Co2Mn 1－a Fe a Al b Si 1－b 、Co2FeGe 1－c Ga c Whistler alloys have high spin polarization.

[0073] The stacked body 10 may also have an antiferromagnetic layer on the surface of the second ferromagnetic layer 2 opposite to the non-magnetic layer 3 via an isolation layer. The second ferromagnetic layer 2, the isolation layer, and the antiferromagnetic layer are a synthetic antiferromagnetic structure (SAF structure). The synthetic antiferromagnetic structure is composed of two magnetic layers sandwiching a non-magnetic layer. Since the second ferromagnetic layer 2 and the antiferromagnetic layer are antiferromagnetically coupled, the coercive force of the second ferromagnetic layer 2 becomes larger than that without the antiferromagnetic layer. The antiferromagnetic layer is, for example, IrMn, PtMn, etc. The isolation layer, for example, contains at least one selected from the group consisting of Ru, Ir, and Rh.

[0074] The laminate 10 may include layers other than the first ferromagnetic layer 1, the second ferromagnetic layer 2, and the nonmagnetic layer 3. For example, an underlayer may be included between the wiring 20 and the laminate 10. The underlayer improves the crystallinity of each layer constituting the laminate 10.

[0075] The wiring 20 is in contact with, for example, one surface of the stacked body 10. The wiring 20 is a write wiring for writing data to the magnetoresistive element 100. The wiring 20 extends in the x direction. At least a portion of the wiring 20 sandwiches the first ferromagnetic layer 1 with the nonmagnetic layer 3 in the z direction.

[0076] The wiring 20 generates a spin current through the spin Hall effect when the current I flows, and injects the spin into the first ferromagnetic layer 1. The wiring 20, for example, imparts a spin-orbit torque (SOT) of an amount capable of reversing the magnetization of the first ferromagnetic layer 1 to the magnetization of the first ferromagnetic layer 1. The spin Hall effect is a phenomenon in which a spin current is induced in a direction orthogonal to the direction of flow of the current based on the spin-orbit interaction when a current is passed. The spin Hall effect is common to the conventional Hall effect in that the moving (mobile) charge (electron) bends the direction of movement (movement). In the conventional Hall effect, the direction of movement of a charged particle moving in a magnetic field is bent due to the Lorentz force. In contrast, in the spin Hall effect, even if there is no magnetic field, the direction of movement of the spin is bent by the amount of electron movement (the amount of current flow).

[0077] For example, when a current flows through the wiring 20, a first spin oriented in one direction and a second spin oriented in a direction opposite to the first spin are bent by the spin Hall effect in directions orthogonal to the direction in which the current I flows. For example, the first spin oriented in the -y direction is bent in the +z direction, and the second spin oriented in the +y direction is bent in the -z direction.

[0078] In a non-magnetic body (a material that is not a ferromagnetic body), the number of electrons of the first spin generated by the spin Hall effect is equal to the number of electrons of the second spin. That is, the number of electrons of the first spin facing the +z direction is equal to the number of electrons of the second spin facing the -z direction. The first spin and the second spin flow in the direction that eliminates the segregation of the spins. In the movement of the first spin and the second spin in the z direction, the flow of charges cancels each other, so the current is zero. The spin flow without current is particularly called pure spin flow.

[0079] If the electron current of the first spin is represented by J ↑ , the electron current of the second spin is represented by J ↓ , and the spin current is represented by J S , then according to J S =J ↑ -J ↓ Definition. Spin current J S The first spin is generated in the z direction. The first spin is injected from the wiring 20 into the first ferromagnetic layer 1 .

[0080] The wiring 20 includes any one of a metal, an alloy, an intermetallic compound, a metal boride, a metal carbide, a metal silicide, and a metal phosphide having a function of generating a spin current by a spin Hall effect when a current I flows.

[0081] The wiring 20 contains, for example, a non-magnetic heavy metal as a main element. The main element is the element with the highest proportion among the elements constituting the wiring 20. The wiring 20 contains, for example, a heavy metal having a specific gravity greater than yttrium (Y). The non-magnetic heavy metal has a large atomic number of 39 or greater and has d electrons or f electrons in the outermost layer, so it generates a strong spin-orbit interaction. The spin Hall effect is generated by the spin-orbit interaction, and spins are easily segregated in the wiring 20, and spin current J is easily generated. S The wiring 20 includes, for example, any one selected from the group consisting of Au, Hf, Mo, Pt, W, and Ta.

[0082] Wiring 20 may also include a magnetic metal. The magnetic metal is a ferromagnetic metal or an antiferromagnetic metal. The trace amount of magnetic metal contained in the non-magnetic body is a scattering factor of the spin. The trace amount is, for example, less than 3% of the total molar ratio of the elements constituting wiring 20. If the spin is scattered by the magnetic metal, the spin-orbit interaction is enhanced, and the generation efficiency of the spin flow relative to the current is improved.

[0083] Wiring 20 may also include topological insulators. Topological insulators are materials that are insulators or high-resistance materials inside, but have a spin-polarized metallic state on their surface. Topological insulators generate internal magnetic fields through spin-orbit interactions. Even if there is no external magnetic field, topological insulators exhibit new topological phases through the effect of spin-orbit interactions. Topological insulators can efficiently generate pure spin currents through strong spin-orbit interactions and the destruction of edge inversion symmetry.

[0084] Topological insulators are, for example, SnTe, Bi 1.5 Sb 0.5 Te 1.7 Se 1.3 、TlBiSe2、Bi2Te3、Bi 1－x Sb x 、(Bi 1－ x Sb x )2Te3, etc. Topological insulators can efficiently generate spin currents.

[0085] When viewed from the z direction, the conductive portion 31 and the conductive portion 32 sandwich the laminate 10 in the x direction. The conductive portions 31 and 32 are connected to the via wiring V1, for example. The conductive portions 31 and 32 are made of a material with excellent conductivity. For example, the conductive portions 31 and 32 include any one selected from the group consisting of Ag, Cu, Co, Al, and Au.

[0086] Next, a method for manufacturing the integrated region IA of the magnetic recording array 200 is described. The integrated region IA is formed by a stacking process of each layer and a processing process of processing a portion of each layer into a predetermined shape. The stacking of each layer can be performed using a sputtering method, a chemical vapor growth (CVD) method, an electron beam evaporation method (EB evaporation method), an atomic laser deposition method, etc. The processing of each layer can be performed using a photolithography method, etc.

[0087] First, impurities are doped at predetermined positions of the substrate Sub to form a first region A1 , a second region A2 , and a third region A3 .

[0088] Next, an insulating layer of a certain thickness is formed on the substrate Sub. For example, an opening is formed in the insulating layer by anisotropic etching. When viewed from the z direction, the opening is formed between the first area A1 and the third area A3. The opening does not penetrate the substrate Sub, and an insulating film is left at the bottom. The insulating film left at the bottom becomes the gate insulating film GI. The opening is filled with a conductor to become the second gate G2.

[0089] Next, a conductive layer is stacked on the insulating layer, and the conductive layer is processed to form the second gate wiring GL2. The second gate wiring GL2 connects the second gates G2 arranged in the x direction.

[0090] Next, an insulating layer covering the second gate wiring GL2 is stacked. For example, an opening is formed in the insulating layer by anisotropic etching. When viewed from the z direction, the opening is formed between the first area A1 and the second area A2. The opening does not penetrate the substrate Sub, and an insulating film is left at the bottom. The insulating film left at the bottom becomes the gate insulating film GI. The opening is filled with a conductor to become the first gate G1.

[0091] Next, a conductive layer is stacked on the insulating layer, and the conductive layer is processed to form the first gate wiring GL1. The first gate wiring GL1 connects the first gates G1 arranged in the x direction.

[0092] Next, an insulating layer covering the second gate wiring GL2 is stacked. For example, an opening is formed in the insulating layer by anisotropic etching. When viewed from the z direction, the opening is formed at a position overlapping the second area A2 and the third area A3. The opening reaches the surface of the substrate Sub. The opening is filled with a conductor to form a through-hole wiring V1.

[0093] Next, after overlapping the insulating layer covering the through-hole wiring V1, the conductive parts 31 and 32 are formed at the positions overlapping the through-hole wiring V1. For example, a material harder than the through-hole wiring V1 is used for the conductive parts 31 and 32. Chemical mechanical polishing (CMP) is performed on the surfaces of the insulating layer and the conductive parts 31 and 32. By using a hard material for the conductive parts 31 and 32, the flatness of the surface is improved.

[0094] Next, a wiring layer, a ferromagnetic layer, a non-magnetic layer, and a ferromagnetic layer are sequentially stacked on the surfaces of the insulating layer and the conductive parts 31 and 32. Next, the wiring layer is processed into a predetermined shape. The wiring layer is processed into a predetermined shape to form a wiring 20. Next, the stacked body formed on the wiring layer is processed into a predetermined shape to form a stacked body 10, thereby obtaining a magnetoresistive effect element 100. Through the above steps, the integrated area IA of the magnetic recording array 200 can be manufactured.

[0095] Next, the operation of the magnetic recording array 200 according to the first embodiment will be described. The operation of the magnetic recording array 200 includes a writing operation to the magnetoresistive effect element 100 and a reading operation.

[0096] First, a description will be given of a write operation to an arbitrary magnetoresistance effect element 100. The description will be given by taking as an example a case where data is written to the first magnetoresistance effect element 100A as an arbitrary magnetoresistance effect element 100.

[0097] First, the first gate transistor GTr1 connected to the first magnetoresistance effect element 100A is turned on. When the first gate transistor GTr1 is turned on, the first gate G1 connected to the first gate wiring GL1 is opened. Then, the first region A1 and the second region A2 of the common transistor STr are electrically connected.

[0098] Next, the first wiring control transistor Tr3 connected to the first wiring L1 is turned on, and the first wiring control transistor Tr3 is connected to the first common transistor STr1 and the second common transistor STr2. Since the two adjacent first wirings L1 are electrically connected across the first magnetoresistance effect element 100A, the write current flows through the wiring 20. On the other hand, since the second gate G2 is not open, the write current does not flow to the second magnetoresistance effect element 100B.

[0099] When a write current flows through the wiring 20, a spin Hall effect occurs, and spins are injected into the first ferromagnetic layer 1. The spins injected into the first ferromagnetic layer 1 apply a spin-orbit torque (SOT) to the magnetization of the first ferromagnetic layer 1, thereby changing the orientation direction of the magnetization of the first ferromagnetic layer 1. If the direction of the current flow is reversed, the orientation direction of the spins injected into the first ferromagnetic layer 1 is reversed, and therefore, the orientation direction of the magnetization can be freely controlled.

[0100] The resistance value in the stacking direction of the stack 10 becomes smaller when the magnetization of the first ferromagnetic layer 1 and the magnetization of the second ferromagnetic layer 2 are parallel, and becomes larger when the magnetization of the first ferromagnetic layer 1 and the magnetization of the second ferromagnetic layer 2 are antiparallel. Data is recorded in the magnetoresistive element 100 as the resistance value in the stacking direction of the stack 10.

[0101] Next, first, a description will be given of an operation of reading data from an arbitrary magnetoresistance effect element 100. The description will be given by taking as an example a case where data is read from the first magnetoresistance effect element 100A as an arbitrary magnetoresistance effect element 100.

[0102] When reading data, the first gate transistor GTr1 connected to the first magnetoresistance effect element 100A is turned on. When the first gate transistor GTr1 is turned on, the first gate G1 connected to the first gate wiring GL1 is opened. Furthermore, the first region A1 and the second region A2 of the common transistor STr are electrically connected.

[0103] Next, the second wiring control transistor Tr4 connected to the second wiring L2 is turned on, and the second wiring control transistor Tr4 is connected to the first magnetoresistance effect element 100A. In addition, the first wiring control transistor Tr3 connected to the first wiring L1 is turned on, and the first wiring L1 is connected to the first common transistor STr1 or the second common transistor STr2. Since the first wiring L1 and the second wiring L2 are electrically connected, the read current flows along the stacking direction of the stack 10. On the other hand, since the second gate G2 is not open, the read current does not flow to the second magnetoresistance effect element 100B.

[0104] If the resistance value of the stacked body 10 in the stacking direction changes according to Ohm's law, the output voltage changes. Therefore, for example, by reading the voltage in the stacked direction of the stacked body 10, data recorded in the first magnetoresistive effect element 100A can be read.

[0105] The magnetic recording array 200 of the first embodiment can improve the integration of the integrated area IA. Since the first area A1 of the shared transistor STr, which functions as the two transistors Tr, also serves as the source region or drain region of the two transistors, the required area is smaller than that of the case where the two transistors Tr are arranged. Therefore, the distance between the magnetoresistance effect elements 100 adjacent to each other in the x direction can be shortened, and the integration of the integrated area IA is improved.

[0106] Although one example of the first embodiment has been described above, the present invention is not limited to this example.

[0107] (Second Embodiment)

[0108] Figure 5 1 is a circuit diagram of a magnetic recording array 201 of the second embodiment. The magnetic recording array 201 of the second embodiment is different from the magnetic recording array 200 of the first embodiment in that a part of the magnetoresistive effect element 100 in the integrated area IA1 is the first reference element 101 and the second reference element 102. In the second embodiment, the description of the same structure as the first embodiment is omitted.

[0109] The first reference element 101 and the second reference element 102 exist in a row, for example. The first reference element 101 and the second reference element 102 are connected to one first wiring L1, for example, one by one. The number of the first reference element 101 and the second reference element 102 is not limited to this case. The first reference element 101 and the second reference element 102 exist at least one by one in the magnetic recording array 201.

[0110] The first reference element 101 has the same structure as the magnetoresistance effect element 100 except that the resistance of the wiring 20 is higher than that of the magnetoresistance effect element 100. The resistance of the wiring 20 of the first reference element 101 is, for example, 105% or more of the resistance of the wiring 20 of the magnetoresistance effect element 100, or may be 110% or more.

[0111] The difference in resistance between the first reference element 101 and the magnetoresistive element 100 can be freely designed by changing the width, thickness, and constituent material of the wiring 20. For example, the width of the wiring 20 of the first reference element 101 is narrower than the width of the wiring 20 of the magnetoresistive element 100. The width of the wiring 20 of the first reference element 101 is, for example, 95% or less of the width of the wiring 20 of the magnetoresistive element 100, or may be 90% or less.

[0112] The second reference element 102 has the same structure as the magnetoresistance effect element 100 except that the resistance of the wiring 20 is lower than that of the magnetoresistance effect element 100. The resistance of the wiring 20 of the second reference element 102 is, for example, 95% or less of the resistance of the wiring 20 of the magnetoresistance effect element 100, or may be 90% or less.

[0113] The difference in resistance between the second reference element 102 and the magnetoresistive element 100 can be freely designed by changing the width, thickness, and constituent material of the wiring 20. For example, the width of the wiring 20 of the second reference element 102 is wider than the width of the wiring 20 of the magnetoresistive element 100. The width of the wiring 20 of the second reference element 102 is, for example, 105% or more of the width of the wiring 20 of the magnetoresistive element 100, and may be 110% or more.

[0114] The first reference element 101 and the second reference element 102 are used to confirm whether writing to the magnetoresistive effect element 100 is performed appropriately.

[0115] For example, when a write operation is performed on the magnetoresistance effect element 100, the same write operation is performed on the first reference element 101 and the second reference element 102 paired with the magnetoresistance effect element 100. The first reference element 101 and the second reference element 102 paired with the magnetoresistance effect element 100 are, for example, the first reference element 101 and the second reference element 102 connected to the first wiring L1 in the same manner as the magnetoresistance effect element 100. The voltage applied to each wiring of the first reference element 101 and the second reference element 102 is set to be the same as that of the magnetoresistance effect element 100. The same load as that of the magnetoresistance effect element 100 is applied to the first reference element 101 and the second reference element, and the same data is written.

[0116] Next, the resistance values ​​of the magnetoresistance effect element 100, the first reference element 101, and the second reference element 102 are compared. The resistance value is, for example, the resistance between the electrode E and the conductive portion 32. Each resistance value is obtained by applying a read current. When operating properly, the resistance of the first reference element 101 is higher than the resistance of the magnetoresistance effect element 100. In addition, the resistance of the second reference element 102 is lower than the resistance of the magnetoresistance effect element 100.

[0117] When the resistance of magnetoresistance effect element 100 is not between the resistance of first reference element 101 and the resistance of second reference element 102 , it can be determined that a failure has occurred in magnetoresistance effect element 100 .

[0118] As one way of failure of the magnetoresistance effect element 100, there is degradation or breakage of the wiring 20 between the stack 10 and the conductive parts 31 and 32. If the wiring 20 degrades or breaks, the proper write operation cannot be performed. For example, in the case where the wiring 20 between the stack 10 and the conductive part 31 degrades or breaks, the write operation cannot be performed, but the read operation can be performed. The reason is that the write current flowing between the conductive part 31 and the conductive part 32 does not flow normally, but the read current between the stack 10 and the conductive part 32 flows normally. In this case, the data is read without noticing that the data has not been written, and the risk of erroneous reading of the data increases. If the resistance of the magnetoresistance effect element 100 is compared with the resistance of the first reference element 101 and the second reference element 102, the failure mode can be properly detected.

[0119] The magnetic recording array 201 of the second embodiment has excellent integration properties similar to the magnetic recording array 200 of the first embodiment.

[0120] In the magnetic recording array 201 of the second embodiment, by comparing the resistances of the first reference element 101 and the second reference element 102 with the resistance of the magnetoresistive element 100 , the presence or absence of a failure in the magnetoresistive element 100 can be evaluated in real time.

[0121] Furthermore, since first reference element 101 and second reference element 102 are in the same temperature environment as magnetoresistance effect element 100, it is possible to suppress the reference point variation that becomes the threshold value of data recording due to temperature change. Furthermore, since first reference element 101 and second reference element 102 are given the same load as magnetoresistance effect element 100, it is possible to suppress the reference point variation that becomes the threshold value of data recording due to degradation.

[0122] (Third Embodiment)

[0123] Figure 6This is a circuit diagram of a magnetic recording array 202 of the third embodiment. The point at which adjacent first wirings L1 are connected via short-circuit transistors Tr5 in the magnetic recording array 202 of the third embodiment is different from that in the magnetic recording array 200 of the first embodiment. In the third embodiment, description of the same structure as the first embodiment is omitted.

[0124] The short-circuit transistor Tr5 belongs to the peripheral area PA1. The short-circuit transistor Tr5 does not affect the integration of the integration area IA.

[0125] The short-circuit transistor Tr5 connects the second ends of the adjacent first wirings L1 to each other. The second end is the end on the opposite side of the end of the first wiring L1 connected to the first wiring control transistor Tr3. The short-circuit transistor Tr5 is turned off (OFF) when writing data and turned on (ON) when reading data. If the short-circuit transistor Tr5 is turned on, the adjacent first wiring L1 is short-circuited.

[0126] If the adjacent first wiring L1 is short-circuited, the read current is branched from the stacked body 10 to both ends of the wiring 20. By obtaining the resistance value of the magnetoresistive effect element 100 based on the two branched read currents, data can be read with higher accuracy.

[0127] In addition, the magnetic recording array 202 of the third embodiment has excellent integration properties similar to the magnetic recording array 200 of the first embodiment.

[0128] (Fourth Embodiment)

[0129] Figure 7 2 is a cross-sectional view of a magnetization rotation element 110 according to the fourth embodiment. Figure 7 This is a cross section of the magnetization rotation element 110 cut along an xz plane passing through the center of the width of the wiring 20 in the y direction. The magnetization rotation element 110 of the fourth embodiment is different from the magnetoresistance effect element 100 of the first embodiment in that it does not have a nonmagnetic layer 3 and a second ferromagnetic layer 2. The other structures are the same as those of the magnetoresistance effect element 100 of the first embodiment, and the description thereof is omitted.

[0130] The magnetization rotation element 110 is an example of a spin element. The magnetization rotation element 110, for example, evaluates light incident on the first ferromagnetic layer 1 and reflected by the first ferromagnetic layer 1. If the orientation direction of magnetization changes due to the magneto-optical Kerr effect, the deflection state of the reflected light changes. The magnetization rotation element 110 can be used as a different optical element such as an image display device that utilizes the deflection state of light.

[0131] Furthermore, the magnetization rotation element 110 can also be used alone as an anisotropic magnetic sensor, an optical element utilizing the magnetic Faraday effect, or the like.

[0132] The magnetization rotation element 110 of the fourth embodiment can obtain the same effect as the magnetoresistance effect element 100 of the first embodiment by removing only the nonmagnetic layer 3 and the second ferromagnetic layer 2. The magnetoresistance effect element 100 of the second and third embodiments may be replaced with the magnetization rotation element 110.

[0133] (Fifth Embodiment)

[0134] Figure 8 2 is a cross-sectional view of a magnetoresistance effect element 120 according to the fifth embodiment. Figure 8 The cross section of the magnetoresistance effect element 120 is cut by the xz plane passing through the center of the width of the wiring 40 in the y direction. The magnetoresistance effect element 120 is different from the magnetoresistance effect element 100 in that the stacked body 11 is composed of the non-magnetic layer 5 and the first ferromagnetic layer 4 from the side close to the wiring 40. The same reference numerals are used for the same structures as those of the magnetoresistance effect element 100, and the description thereof is omitted.

[0135] The magnetoresistance effect element 120 includes a stack 11, a wiring 40, and conductive parts 31 and 32. The stack 11 is composed of a non-magnetic layer 5 and a first ferromagnetic layer 4 from the side close to the wiring 40. The magnetoresistance effect element 120 is an element whose resistance value changes due to the movement of the magnetic domain wall DW, and is sometimes called a magnetic domain wall movement element or a magnetic domain wall movement type magnetoresistance effect element. The magnetoresistance effect element 120 is an example of a spin element.

[0136] The wiring 40 is a magnetic layer. The wiring 40 includes a ferromagnetic material. The magnetic material constituting the wiring 40 can be a metal selected from the group consisting of Cr, Mn, Co, Fe, and Ni, an alloy containing one or more of these metals, an alloy containing these metals and at least one element of B, C, and N, etc. Specifically, Co-Fe, Co-Fe-B, and Ni-Fe can be used.

[0137] The wiring 40 is a layer capable of magnetically recording information by changing the internal magnetic state. The wiring 40 has a first magnetic region 41 and a second magnetic region 42 inside. The magnetization of the first magnetic region 41 and the magnetization of the second magnetic region 42 are oriented in opposite directions, for example. The boundary between the first magnetic region 41 and the second magnetic region 42 is a magnetic domain wall DW. The wiring 40 can have a magnetic domain wall DW inside.

[0138] The magnetoresistive element 120 can record data in multiple values ​​or continuously according to the position of the magnetic domain wall DW of the wiring 40. When a read current is applied, the data recorded in the wiring 40 is read as a change in resistance of the magnetoresistive element 120.

[0139] The magnetic domain wall DW moves by passing a write current along the x direction of the wiring 40 or applying an external magnetic field. For example, if a write current (e.g., a current pulse) is applied to the +x direction of the wiring 40, electrons flow in the -x direction opposite to the current, and thus the magnetic domain wall DW moves in the -x direction. When a current flows from the first magnetic region 41 toward the second magnetic region 42, the spin-polarized electrons in the second magnetic region 42 reverse the magnetization of the first magnetic region 41. Due to the magnetization reversal of the first magnetic region 41, the magnetic domain wall DW moves in the -x direction.

[0140] The first ferromagnetic layer 4 and the nonmagnetic layer 5 are respectively the same as the first ferromagnetic layer 1 and the nonmagnetic layer 3 of the first embodiment.

[0141] The magnetoresistance effect element 120 of the fifth embodiment can also obtain the same effects as the magnetoresistance effect element 100 of the first embodiment. In addition, the magnetoresistance effect element 100 of the second embodiment and the third embodiment can be replaced with the magnetoresistance effect element 120.

[0142] The magnetic recording arrays of the first to fifth embodiments can be applied to neuromorphic devices. Neuromorphic devices are components that imitate the human brain through neural networks. Neuromorphic devices artificially imitate the relationship between neurons and synapses in the human brain.

[0143] Neuromorphic devices, for example, have chips arranged in layers (neurons in the brain) and transmission units (synapses in the brain) that connect them. Neuromorphic devices learn through transmission units (synapses) to improve the correct answer rate of problems. Learning discovers knowledge that may be used in the future from information and weights the data input to the neuromorphic device.

[0144] Each synapse performs a product-sum operation mathematically. The magnetic recording array of the first embodiment to the fifth embodiment can perform a product-sum operation by arranging the magnetoresistive effect elements or the magnetization rotation elements in an array. For example, if a current is passed through the read path of the magnetoresistive effect element, the product of the input current and the resistance of the magnetoresistive effect element is output and a product operation is performed. If a plurality of magnetoresistive effect elements are connected by a common wiring, the product operation is performed by adding the common wiring and performing a sum operation. Therefore, the magnetic recording array of the first embodiment to the third embodiment can be applied to a neuromorphic device as a product-sum operator.

[0145] Explanation of symbols

[0146] 1.4 The first ferromagnetic layer

[0147] 2 Second ferromagnetic layer

[0148] 3.5 Non-magnetic layer

[0149] 4First ferromagnetic layer

[0150] 10, 11 laminate

[0151] 20, 40 wiring

[0152] 100 Magnetoresistance effect element

[0153] 100A first magnetoresistance effect element

[0154] 100B first magnetoresistance effect element

[0155] 101 first reference element

[0156] 102 second reference element

[0157] 200, 201, 202 magnetic recording array

[0158] A1 First Area

[0159] A2 Second Area

[0160] A3 Third Area

[0161] DW domain wall

[0162] G1 first gate

[0163] G2 second gate

[0164] GL1 first gate wiring

[0165] GL2 second gate wiring

[0166] L1 first wiring

[0167] L2 second wiring

[0168] STr common transistor

[0169] STr1 first common transistor

[0170] STr2 second common transistor

[0171] STr3 The third common transistor

[0172] Tr3 first wiring control transistor

[0173] Tr4 Second wiring control transistor

[0174] Tr5 short circuit transistor

Claims

1. A magnetic recording array, characterized in that: A device comprising three or more spin elements and a common transistor connected to a first spin element and a second spin element adjacent to each other, The three or more spin elements each include wiring and a stacked body including a first ferromagnetic layer stacked on the wiring. The common transistor has a first gate, a second gate, a first region, a second region and a third region, When looking down from the stacking direction of the stacked body, The first region is sandwiched by the first gate and the second gate, The second region and the first region sandwich the first gate. The third region and the first region sandwich the second gate. One of the second region and the third region is connected to the first spin element, and the other is connected to the second spin element. At least one of the three or more spin elements is a first reference element, and the resistance of the wiring of the first reference element is higher than the resistance of the wiring of the other spin elements. At least one of the three or more spin elements is a second reference element, and the resistance of the wiring of the second reference element is lower than the resistance of the wiring of the other spin elements.

2. The magnetic recording array according to claim 1, wherein: having a plurality of said shared transistors, Also having one or more first wirings, The first wiring is connected to each of the first regions of two or more common transistors selected from the plurality of common transistors. The first region of any one of the common transistors is connected to any one of the one or more first wirings.

3. The magnetic recording array according to claim 2, wherein: A first wiring control transistor connected to the first wiring is further provided.

4. The magnetic recording array according to claim 2 or 3, wherein: having a plurality of said first wirings, The adjacent first wirings are connected via a short-circuit transistor.

5. The magnetic recording array according to any one of claims 1 to 3, wherein: Also having one or more second wirings, The second wiring is connected to each of the stacked bodies of two or more spin elements selected from the three or more spin elements, The stacked body of any one of the three or more spin elements is connected to any one of the one or more second wirings.

6. The magnetic recording array according to claim 5, wherein: A second wiring control transistor connected to the second wiring is further provided.

7. The magnetic recording array according to any one of claims 1 to 3, wherein: The device further includes a first gate wiring connected to the first gate and a second gate wiring connected to the second gate.

8. The magnetic recording array according to claim 7, wherein: The first gate wiring and the second gate wiring are at different heights.

9. The magnetic recording array according to any one of claims 1 to 3, wherein: The common transistor includes a first common transistor, a second common transistor and a third common transistor, The first spin element is connected to the first common transistor and the second region of the second common transistor, The second spin element is connected to the second common transistor and the third region of the third common transistor.

10. The magnetic recording array according to any one of claims 1 to 3, wherein: The wiring width of the wiring of the first reference element is narrower than the wiring width of other spin elements, The wiring width of the wiring of the second reference element is wider than the wiring width of other spin elements.

11. The magnetic recording array according to any one of claims 1 to 3, wherein: The laminate includes the first ferromagnetic layer, a nonmagnetic layer, and a second ferromagnetic layer from the side close to the wiring. The wiring is any one of a metal, an alloy, an intermetallic compound, a metal boride, a metal carbide, a metal silicide, and a metal phosphide having a function of generating a spin current by a spin Hall effect when a current flows.

12. The magnetic recording array according to any one of claims 1 to 3, wherein: The laminated body includes a non-magnetic layer and the first ferromagnetic layer from a side close to the wiring, The wiring is a ferromagnetic layer that can have a magnetic domain wall inside.

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