Gate Parasitic Capacitance Modeling Method
By extracting and adjusting the parameters of the gate capacitance and establishing a detailed capacitance model, the accuracy and predictability of device gate parasitic capacitance modeling in integrated circuit design are solved, and higher modeling accuracy and coverage capabilities are achieved.
Patent Information
- Application Number
- CN202110913952.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-08-10
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2041-08-10
AI Technical Summary
In integrated circuit design, it is difficult for the prior art to accurately model the gate parasitic capacitance of a device, and the predictability and accuracy of the model are limited by the mutual influence of device size selection and parameters, resulting in inconsistent modeling results.
By extracting the capacitance component, capacitance change, capacitance change slope and offset at the lowest point of the gate capacitance, use the formula cgmin = cgmin(S,P)*EXP(C3*L/W) and cgmin(S,P) = C0(x) + C1*S + C2*P, combined with the minimum RMS method and global optimization method, adjust the values of C0 and C3 to establish a detailed capacitance model.
An accurate and reliable gate parasitic capacitance modeling method is provided, which improves the accuracy and coverage of device modeling and ensures the effectiveness of the model under different sizes and parameters.
Smart Images
Figure CN113642277B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit design, and in particular to a gate parasitic capacitance modeling method. Background Art
[0002] The success of integrated circuit design relies on accurate modeling of devices. Combining device measurement results with physical characteristics to provide a model that covers global dimensions and can be predicted has always been a difficult problem that the industry has been working hard to overcome. Since the device designer's choice of device size cannot be predicted at the beginning of modeling, and modeling engineers cannot use infinite measurement and design costs for modeling, the predictability and accuracy of the model often become a difficult problem that needs to be weighed. At the same time, due to the mutual influence of many parameters, modeling engineers are often prone to extracting different model results under the premise of the same methodology. Summary of the invention
[0003] The technical problem to be solved by the present invention is to provide an accurate gate parasitic capacitance modeling method.
[0004] In order to solve the above problems, the present invention provides a gate parasitic capacitance modeling method, comprising the following steps: extracting the capacitance component of the lowest point of the gate capacitance according to the gate area and perimeter; extracting the capacitance change; extracting the capacitance change slope; extracting the offset; and feedback verification.
[0005] Optionally, the method for extracting the capacitance component at the lowest point of the capacitance is further: the capacitance component cgmin at the lowest point of the capacitance is obtained by the formula
[0006] cgmin=cgmin(S,P)*EXP(C3*L / W)
[0007] cgmin(S,P)=C0(x)+C1*S+C2*P
[0008] cgmin(S,P) is an expression based on the gate perimeter P and the gate area S, C0(x) is an expression about x, C1 is the area coefficient, C2 is the perimeter coefficient, and C3 is the aspect ratio correction coefficient.
[0009] At the beginning of modeling, the default C3 coefficient is 0, by solving the following equation:
[0010]
[0011]
[0012] By iterating the minimum RMS method, the initial values of C1 and C2 are assigned.
[0013] The formula here is based on the above formula:
[0014] cgmin(S,P)=C0(x)+C1*S+C2*P
[0015] According to the extraction results, extract the C0 and C3 values.
[0016] Since the L / W of a device with a large aspect ratio tends to 0, a device with a large aspect ratio can be used to extract C0.
[0017] After determining the value of C0, C3 is extracted using a global optimization method, thereby completing the extraction of the capacitance component at the lowest point of the capacitance.
[0018] The above technical solution combines the physical characteristics of gate parasitic capacitance with mathematical formulas to establish a detailed extraction process and provide a reliable device modeling method and model. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Attached Figure 1 Shown is a schematic diagram of the implementation steps of a specific embodiment of the present invention.
[0020] Attached Figure 2 The figure shows the variation trend of the capacitance of the variable capacitor with the voltage according to a specific embodiment of the present invention.
[0021] Attached Figure 3 Shown is a schematic structural diagram of a channel parasitic capacitor according to a specific embodiment of the present invention.
[0022] Attached Figure 4 Shown is a comparison of characterization results before and after cgmin correction according to a specific embodiment of the present invention. DETAILED DESCRIPTION
[0023] The specific implementation of the gate parasitic capacitance modeling method provided by the present invention is described in detail below with reference to the accompanying drawings.
[0024] Attached Figure 1 The figure is a schematic diagram of the implementation steps of this specific embodiment, including: step S10, extracting the capacitance component of the lowest point of the gate capacitance according to the gate area and the perimeter; step S11, extracting the capacitance change; step S12, extracting the capacitance change slope; step S13, extracting the offset; step S14, feedback verification.
[0025] Attached Figure 2 The figure shows the variation trend of the capacitance of the variable capacitor with voltage. The lower capacitance is due to the increase in the thickness of the depletion layer after the channel inversion, which causes the capacitance to decrease.
[0026] The gate capacitance formula can be roughly expressed as C = Cdep*Cox / (Cdep+Cox)
[0027] Due to the complex relationship between the depletion layer capacitance and voltage in the above equation, more complex effects are used in many models to correct the errors between the models and the effects. At present, the industry uses the mathematical representation method of the hyperbolic tangent function to simplify this complex modeling:
[0028] C=cgmin+dcg*(1+tanh((v(nds,ng)-dvgs) / vgnorm))
[0029] In the above formula, cgmin is the capacitance component at the lowest point of the capacitor, dcg is the capacitance change, v(nds,ng) represents the voltage at both ends of the capacitor, dvgs is the offset, and vgnorm is the capacitance change slope.
[0030] As attached Figure 3 The figure shows the schematic diagram of the structure of the channel parasitic capacitance, with the gate oxide layer on the top and the channel below. The distribution of the depletion layer in the channel is greatly affected by the size of the gate oxide layer area, but the gate capacitance is also affected by the gate edge capacitance, which comes from the capacitance effect of the gate edge perimeter and the surrounding medium. In order to cover this physical property in modeling, cgmin is usually characterized based on the gate area S = W*L and the perimeter P = 2*(W+L). However, there is a big difference between the distributed capacitance on the channel side and the distributed capacitance in the active area of the device.
[0031] Since the model needs to cover the performance characterization of devices of all sizes, the overall capacitance model can be expressed as a function of the device gate width W and the device channel length L. This method improves the global extraction accuracy when the variable capacitor CV model is established.
[0032] The cgmin in the above formula is given by the formula
[0033] cgmin=cgmin(S,P)*EXP(C3*L / W)
[0034] cgmin(S,P)=C0(x)+C1*S+C2*P
[0035] cgmin(S, P) is an expression based on the perimeter P and the area S, C0(x) is an expression about x, C1 is the area coefficient, C2 is the perimeter coefficient, and C3 is the aspect ratio correction coefficient.
[0036] At the beginning of modeling, the default C3 coefficient is 0, by solving the following equation:
[0037]
[0038] The initial values of C1 and C2 are assigned through the iteration of the minimum RMS method.
[0039] The formula here is based on the above formula:
[0040] cgmin(S,P)=C0(x)+C1*S+C2*P
[0041] At the same time, the method of extracting the partial differential solution results that establish an obvious direct relationship between the area S, the perimeter P, etc., and the width and length of the device should belong to the same mathematical method and be included in the scope of patent protection.
[0042] According to the extraction results, extract the C0 and C3 values.
[0043] Since the L / W of a device with a large aspect ratio tends to 0, a device with a large aspect ratio can be used to extract C0
[0044] After determining the C0 value, C3 is extracted using a global optimization method to complete the device characterization. Figure 4 Shown is the comparison of characterization results before and after cgmin correction.
[0045] According to different parameters, dcg, dvg, and vgnorm are all applicable to the above-mentioned representation and extraction forms, which will not be described in detail here.
[0046] The results obtained by the above formula are verified with the actual capacitance test results, and the extracted parameter values are adjusted according to the verification results to make the model more accurate. The way to extract the parameter values is to import the test data into the modeling and parameter extraction software, such as MBP, and then manually or automatically match them to extract the parameters.
[0047] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A gate parasitic capacitance modeling method, characterized in that: The steps include: Extract the capacitance component of the lowest point of the gate capacitance based on the gate area and perimeter, including: The capacitance component cgmin at the lowest point of capacitance is given by the formula cgmin=cgmin(S,P)*EXP(C3*L / W) cgmin(S,P)=C0(x)+C1*S+C2*P cgmin(S,P) is an expression based on the gate perimeter P and the gate area S, C0(x) is an expression about x, C1 is the area coefficient, C2 is the perimeter coefficient, C3 is the aspect ratio correction coefficient, At the beginning of modeling, the default C3 coefficient is 0, by solving the following equation: By iterating the minimum RMS method, the initial values of C1 and C2 are assigned. The formula here is based on the above formula: cgmin(S,P)=C0(x)+C1*S+C2*P According to the extraction value results, extract the C0 and C3 values; Extract capacitance change; Extract the capacitance change slope; Extract offset; Feedback verification.