Electrostatic discharge protection circuit and chip with electrostatic discharge protection circuit

Abstract

An electrostatic discharge protection circuit and a chip having the electrostatic discharge protection circuit, the electrostatic discharge protection circuit comprising an RC module (101), an alarm module (102) and a discharge module (103); when the input voltage of the RC module (101) increases, its output voltage increases; the alarm module (102) receives the input voltage of the RC module (101) and the output voltage of the RC module (101); when the input voltage of the RC module (101) increases, the alarm voltage of the alarm module (102) increases, and when the alarm voltage is greater than or equal to the output voltage of the RC module (101), an electrostatic alarm signal is output; the discharge module (103) receives the input voltage of the RC module (101) and the output voltage of the RC module (101); when the input voltage of the RC module (101) increases, the discharge voltage of the discharge module (103) increases, and when the discharge voltage is greater than or equal to the output voltage of the RC module (101), electrostatic discharge is performed, and the alarm voltage is greater than the discharge voltage. The protection circuit can discharge static electricity based on advance knowledge, thereby improving the stability of chip operation and improving user experience.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic technology, and in particular to an electrostatic discharge protection circuit and a chip having the electrostatic discharge protection circuit. Background Art

[0002] Electrostatic discharge (ESD) events of varying degrees will occur during the production, testing, transportation, and use of chips. When an electrostatic discharge event occurs, a large amount of charge will instantly flow into the chip from the outside to the inside. If the chip encounters an electrostatic discharge event or an impact from external electrostatic coupling during operation, the chip system will enter an abnormal state (such as abnormal reset, runaway, or deadlock), affecting the normal operation of the chip. Whether the chip can withstand electrostatic discharge events is an important test standard for chip electromagnetic compatibility (EMC) testing.

[0003] By packaging the chip, some static electricity can be prevented from being directly released to the internal circuit of the chip, but the pins of the chip exposed to the outside (such as power pins, clock pins, communication pins, etc.) will still be exposed to the static environment. In order to prevent static electricity from being released to the internal circuit of the chip through these pins, an electrostatic discharge protection circuit can be set in the chip, and the static electricity can be discharged through the electrostatic discharge protection circuit to avoid damaging the internal circuit of the chip. For example, an electrostatic discharge protection circuit can be set at the input and output pads (IO PAD) of the chip, and the electrostatic discharge protection circuit can guide the static electricity to be released in the input and output power rings that can pass larger currents when discharging static electricity.

[0004] Although equipping the chip with an electrostatic discharge protection circuit can prevent damage to the chip's internal circuits when an electrostatic discharge event occurs, it is impossible to know in advance whether the electrostatic discharge protection circuit will perform electrostatic discharge, so it is impossible to control the chip to take any software or hardware preventive measures for the electrostatic discharge protection circuit. If such preventive measures are lacking, on the one hand, electrostatic discharge in a complex electromagnetic environment may cause the device in the chip to be broken down, resulting in abnormal chip current, or completely damaging the chip, etc., causing irreversible hardware damage to the chip. On the other hand, during the electrostatic discharge process of the electrostatic discharge protection circuit, the voltage of each node on the discharge path will change instantly, and the chip may therefore have a series of operational errors (such as abnormal reset, program deadlock, etc.). Although these operational errors are non-physical damage that can be restored by external intervention such as power off or reset, they may still cause greater errors in the chip at the system level, thereby reducing the stability of the chip's operation and damaging the user experience. Summary of the invention

[0005] In view of this, one of the technical problems solved by the embodiments of the present application is to provide an electrostatic discharge protection circuit and a chip having the electrostatic discharge protection circuit to overcome some or all of the problems in the prior art.

[0006] The embodiment of the present application provides an electrostatic discharge protection circuit, which includes an RC module, an alarm module and a discharge module;

[0007] When the input voltage of the RC module increases, its output voltage increases;

[0008] The alarm module receives the input voltage of the RC module and the output voltage of the RC module. When the input voltage of the RC module increases, the alarm voltage of the alarm module increases, and when the alarm voltage is greater than or equal to the output voltage of the RC module, the static electricity alarm signal is output;

[0009] The discharge module receives the input voltage of the RC module and the output voltage of the RC module. When the input voltage of the RC module increases, the discharge voltage of the discharge module increases. When the discharge voltage is greater than or equal to the output voltage of the RC module, static discharge is performed, and the alarm voltage is greater than the discharge voltage.

[0010] An embodiment of the present application provides a chip with an electrostatic discharge protection circuit. The chip with an electrostatic discharge protection circuit includes the electrostatic discharge protection circuit provided by the embodiment of the present application.

[0011] In the electrostatic discharge protection circuit provided in the embodiment of the present application, when an electrostatic discharge event occurs, the input voltage of the RC module will rise sharply due to the instantaneous electrostatic high voltage shock. At this time, the output voltage of the RC module, the alarm voltage of the alarm module, and the discharge voltage of the discharge module all increase. Since the alarm voltage is greater than the discharge voltage, the moment when the alarm voltage is greater than the output voltage of the RC module is earlier than the moment when the discharge voltage is greater than the output voltage of the RC module, ensuring that the alarm module outputs an electrostatic alarm signal first to warn that electrostatic discharge is about to be performed, and then the discharge module performs electrostatic discharge. Therefore, the electrostatic discharge protection circuit provided in the embodiment of the present application can output an electrostatic alarm signal before electrostatic discharge to warn that an electrostatic discharge event is about to occur, so that the chip can take software or hardware preventive measures or post-event remedial measures for the electrostatic discharge event, reducing the probability of irrecoverable hardware damage or operation errors in the chip during electrostatic discharge, thereby improving the stability of the chip operation and improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Hereinafter, some specific embodiments of the present application will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings:

[0013] Figure 1 A schematic circuit structure diagram of an electrostatic discharge protection circuit provided in an embodiment of the present application;

[0014] Figure 2 A schematic circuit structure diagram of an electrostatic discharge protection circuit provided in an embodiment of the present application;

[0015] Figure 3 A schematic diagram of voltage variation over time provided in an embodiment of the present application;

[0016] Figure 4 A schematic circuit structure diagram of an electrostatic discharge protection circuit provided in an embodiment of the present application;

[0017] Figure 5 A schematic circuit structure diagram of an electrostatic discharge protection circuit provided in an embodiment of the present application;

[0018] Figure 6 A schematic circuit structure diagram of an electrostatic discharge protection circuit provided in an embodiment of the present application;

[0019] Figure 7 A schematic circuit structure diagram of an electrostatic discharge protection circuit provided in an embodiment of the present application;

[0020] Figure 8 A schematic circuit structure diagram of a pulse extension alarm module provided in an embodiment of the present application;

[0021] Fig. 9 A schematic circuit structure diagram of a pulse extension alarm module provided in an embodiment of the present application;

[0022] Fig.10 A schematic circuit structure diagram of an electrostatic discharge protection circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The implementation of any technical solution of the embodiments of the present application does not necessarily require achieving all of the above advantages at the same time.

[0024] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the embodiments of the present application should fall within the scope of protection of the embodiments of the present application.

[0025] The uncontrolled transfer of static charge from one object to another is generally referred to as an electrostatic discharge event. When an electrostatic discharge event occurs, a large amount of charge will instantly flow into the chip from the outside to the inside. If the chip encounters an electrostatic discharge event or an impact of external electrostatic coupling during operation, the chip system will enter an abnormal state, affecting the normal operation of the chip.

[0026] In order to prevent static electricity from being released into the internal circuit of the chip through these pins, an electrostatic discharge protection circuit (such as an RC clamp electrostatic discharge protection circuit, or a transient suppression diode electrostatic discharge protection circuit, etc.) can be set in the chip, and static electricity can be discharged through the electrostatic discharge protection circuit to avoid damaging the internal circuit of the chip. Among them, in order to protect the devices in different voltage domains in the chip, corresponding electrostatic discharge protection circuits can be set for the input and output interfaces of each voltage domain.

[0027] Specifically, Figure 1 As shown, the electrostatic discharge protection circuit includes: a resistor R0, a capacitor C0, an inverter P0 and an N-type transistor N0, wherein one end of the resistor R0 is connected to the electrostatic discharge terminal V0, the other end of the resistor R0 is connected to one end of the capacitor C0, the other end of the capacitor C0 is grounded, the connection between the resistor R0 and the capacitor C0 is connected to the first input terminal of the inverter P0, the second input terminal of the inverter P0 is connected to the electrostatic discharge terminal V0, the inverter P0 has a ground terminal, the drain of the N-type transistor N0 is connected to the electrostatic discharge terminal V0, the gate of the N-type transistor N0 is connected to the output terminal of the inverter P0, and the source of the N-type transistor N0 is grounded. Among them, the electrostatic discharge terminal V0 can be connected to the pins or components in the chip that are prone to electrostatic discharge events. For example, the electrostatic discharge terminal V0 can be connected to the chip input interface or the chip output interface, and the ground terminal of the electrostatic discharge protection circuit can be connected to the ground terminal of the power ring in the chip that allows large current to pass through; for another example, the electrostatic discharge terminal V0 can be connected to the power pin of the input and output pad (IOPAD), and the ground terminal of the electrostatic discharge protection circuit can also be connected to the ground pin of the input and output pad, and when an electrostatic discharge event occurs in the input and output pad, the static electricity is guided to be released in the input and output power ring that can pass a large current. For another example, the electrostatic discharge terminal V0 can be connected to the power terminal of the power ring in the chip, and the ground terminal of the electrostatic discharge protection circuit can be connected to the ground terminal of the power ring in the chip.

[0028] exist Figure 1In the electrostatic discharge protection circuit shown, the connection point of the resistor R0 and the capacitor C0 is connected to the first input terminal of the inverter P0, and the voltage at the connection point of the resistor R0 and the capacitor C0 is the same as the voltage of the first input terminal of the inverter P0. The second input terminal of the inverter P0 is connected to the electrostatic discharge terminal V0 of the electrostatic discharge protection circuit, and the voltage of the second input terminal of the inverter P0 is the same as the voltage of the electrostatic discharge terminal V0 of the electrostatic discharge protection circuit. The breakover voltage of the inverter P0 is proportional to the voltage of the second input terminal of the inverter P0. When the voltage of the first input terminal of the inverter P0 is the same as the voltage of the second input terminal of the inverter P0, the breakover voltage of the inverter P0 is less than the voltage of the first input terminal of the inverter P0, the output terminal of the inverter P0 is connected to the ground terminal of the inverter P0, and the output terminal of the inverter P0 outputs a low voltage. When the breakover voltage of the inverter P0 is greater than or equal to the voltage of the first input terminal of the inverter P0 , the output terminal of the inverter P0 is connected to the second input terminal of the inverter P0 , and the output terminal of the inverter P0 outputs a high voltage.

[0029] When the chip is operating normally (i.e., when the pins or devices in the chip that are connected to the electrostatic discharge terminal V0 do not have an electrostatic discharge event), the voltage at the connection point between the resistor R0 and the capacitor C0 is the same as the voltage of the electrostatic discharge terminal V0, the voltage of the first input terminal of the inverter P0 is the same as the voltage of the second input terminal of the inverter P0, the breakover voltage of the inverter P0 is less than the voltage of the first input terminal of the inverter P0, the output terminal of the inverter P0 is connected to the ground terminal of the inverter P0, the output terminal of the inverter P0 outputs a low voltage, the gate of the N-type transistor N0 receives the low voltage, the drain of the N-type transistor N0 and the source of the N-type transistor N0 are cut off, the electrostatic discharge terminal V0 is disconnected from the ground, and the electrostatic discharge terminal V0 is prevented from being grounded when the chip is operating normally.

[0030] When an electrostatic discharge event occurs in a pin or device in the chip that is connected to the electrostatic discharge terminal V0, the voltage of the electrostatic discharge terminal V0 rises, and the turning voltage of the inverter P0 and the voltage at the connection point of the resistor R0 and the capacitor C0 also rise accordingly, wherein the turning voltage of the inverter P0 rises faster than the voltage at the connection point of the resistor R0 and the capacitor C0. When the turning voltage of the inverter P0 is greater than or equal to the voltage at the connection point of the resistor R0 and the capacitor C0 (that is, the turning voltage of the inverter P0 is greater than or equal to the voltage at the first input terminal of the inverter P0), the output terminal of the inverter P0 is connected to the second input terminal of the inverter P0, and the output terminal of the inverter P0 outputs a high voltage. The gate of the N-type transistor N0 receives the high voltage signal, and the drain of the N-type transistor N0 is connected to the source of the N-type transistor N0, so that the electrostatic discharge terminal V0 is connected to the ground, and the static electricity at the electrostatic discharge terminal V0 is introduced into the ground.

[0031] Although the chip can be equipped with the above-mentioned electrostatic discharge protection circuit to avoid damage to the internal circuit of the chip when an electrostatic discharge event occurs, it is impossible to know in advance whether the electrostatic discharge protection circuit will perform electrostatic discharge, and it is impossible to control the chip to take any software or hardware preventive measures for the electrostatic discharge protection circuit. If such preventive measures are lacking, on the one hand, electrostatic discharge in a complex electromagnetic environment may cause the device in the chip to be broken down, resulting in abnormal chip current, or completely damaging the chip, etc., causing irreversible hardware damage to the chip. On the other hand, during the electrostatic discharge process of the electrostatic discharge protection circuit, the voltage of each node on the discharge path will change instantly, and the chip may therefore have a series of operating errors (such as abnormal reset, program deadlock, etc.). Although these operating errors are non-physical damage that can be restored by external intervention such as power off or reset, they may still cause greater errors in the chip at the system level, thereby reducing the stability of the chip and damaging the user experience.

[0032] In view of this, the embodiments of the present application provide an electrostatic discharge protection circuit and a chip having the electrostatic discharge protection circuit to overcome the technical defect in the prior art that it is impossible to know in advance whether the electrostatic discharge protection circuit is going to perform electrostatic discharge.

[0033] In the electrostatic discharge protection circuit provided in the embodiment of the present application, when an electrostatic discharge event occurs, the input voltage of the RC module will rise sharply due to the instantaneous electrostatic high voltage shock. At this time, the output voltage of the RC module, the alarm voltage of the alarm module, and the discharge voltage of the discharge module all increase. Since the alarm voltage is greater than the discharge voltage, the moment when the alarm voltage is greater than the output voltage of the RC module is earlier than the moment when the discharge voltage is greater than the output voltage of the RC module, ensuring that the alarm module outputs an electrostatic alarm signal first to warn that electrostatic discharge is about to be performed, and then the discharge module performs electrostatic discharge. Therefore, the electrostatic discharge protection circuit provided in the embodiment of the present application can output an electrostatic alarm signal before electrostatic discharge to warn that an electrostatic discharge event is about to occur, so that the chip can take software or hardware preventive measures or post-event remedial measures for the electrostatic discharge event, reducing the probability of irrecoverable hardware damage or operation errors in the chip during electrostatic discharge, thereby improving the stability of the chip operation and improving the user experience.

[0034] The specific implementation of the embodiment of the present application is further explained below in conjunction with the accompanying drawings of the embodiment of the present application.

[0035] Embodiment 1

[0036] Figure 2 A schematic circuit structure diagram of an electrostatic discharge protection circuit provided in an embodiment of the present application, Figure 4 A schematic circuit structure diagram of an electrostatic discharge protection circuit provided in an embodiment of the present application, such as Figure 2 as well as Figure 4 As shown, in the electrostatic discharge protection circuit provided in the first embodiment of the present application, the electrostatic discharge protection circuit includes: an RC module 101, an alarm module 102 and a discharge module 103. Among them, when the input voltage of the RC module 101 increases, its output voltage increases.

[0037] The alarm module 102 receives the input voltage of the RC module 101 and the output voltage of the RC module 101. When the input voltage of the RC module 101 increases, the alarm voltage of the alarm module 102 increases, and when the alarm voltage is greater than or equal to the output voltage of the RC module 101, the electrostatic alarm signal is output.

[0038] The discharge module 103 receives the input voltage of the RC module 101 and the output voltage of the RC module 101. When the input voltage of the RC module 101 increases, the discharge voltage of the discharge module 103 increases, and when the discharge voltage is greater than or equal to the output voltage of the RC module 101, static electricity is discharged, and the alarm voltage is greater than the discharge voltage.

[0039] Exemplarily, the static electricity alarm signal output by the alarm module 102 is a signal output by the alarm module 102 that flips from a low voltage to a high voltage. The input end of the RC module 101 can be connected to a device in the chip where an electrostatic discharge event may occur, for example, Figure 5 As shown, the input end of the RC module 101 can be connected to the power pin VDDIO PAD 110 of the input and output pad (IO PAD). For another example, Figure 6 As shown, the ground of the electrostatic discharge protection circuit can be connected to the ground VSSIOPAD 120 of the input and output pad (IO PAD).

[0040] The increase of the input voltage of the RC module 101 will cause an electrostatic discharge event to occur at the input end of the RC module 101, such as an electrostatic discharge event of the human body model (HBM), and the input voltage of the RC module 101 will increase instantly. In addition, when the input voltage of the RC module 101 increases, the output voltage of the RC module 101, the alarm voltage of the alarm module 102, and the discharge voltage of the discharge module 103 all increase.

[0041] In the electrostatic discharge protection circuit provided by the embodiment of the present application, when an electrostatic discharge event occurs, the input voltage of the RC module will rise sharply due to the instantaneous electrostatic high voltage shock. At this time, the output voltage of the RC module, the alarm voltage of the alarm module, and the discharge voltage of the discharge module all increase. Since the alarm voltage is greater than the discharge voltage, the moment when the alarm voltage is greater than or equal to the output voltage of the RC module is earlier than the moment when the discharge voltage is greater than the output voltage of the RC module, ensuring that the alarm module outputs an electrostatic alarm signal first to warn that electrostatic discharge is about to be performed, and then the discharge module performs electrostatic discharge. Therefore, the electrostatic discharge protection circuit provided by the embodiment of the present application can output an electrostatic alarm signal to warn that an electrostatic discharge event is about to occur before electrostatic discharge, so that the chip can take software or hardware preventive measures or post-event remedial measures for the electrostatic discharge event, reducing the probability of irrecoverable hardware damage or operation errors in the chip during electrostatic discharge, thereby improving the stability of the chip operation and improving the user experience.

[0042] Embodiment 2

[0043] On the basis of Example 1, in the electrostatic discharge protection circuit provided in Example 2 of the present application, the initial value of the alarm voltage of the alarm module and the initial value of the discharge voltage of the discharge module are both smaller than the initial value of the output voltage of the RC module, and the growth rate of the alarm voltage of the alarm module and the growth rate of the discharge voltage of the discharge module are both greater than the growth rate of the output voltage of the RC module.

[0044] Exemplarily, the initial value of the output voltage of the RC module is the value of the output voltage of the RC module when no electrostatic discharge event occurs at the input end of the RC module (i.e., the chip where the electrostatic discharge protection circuit is located is in a normal operating state). Similarly, the initial value of the alarm voltage of the alarm module can be understood as the value of the alarm voltage of the alarm module when no electrostatic discharge event occurs at the input end of the RC module, and the initial value of the discharge voltage of the discharge module can be understood as the value of the discharge voltage of the discharge module when no electrostatic discharge event occurs at the input end of the RC module.

[0045] For example, Figure 3 A schematic diagram of voltage variation over time provided in an embodiment of the present application, such as Figure 3As shown, time t0 is the time when an electrostatic discharge event occurs at the input end of the RC module. Before time t0, the chip where the electrostatic discharge protection circuit is located is in normal operation, and the initial value of the output voltage Vc of the RC module is the same as the input voltage VDD of the RC module. Before time t0, the alarm voltage Vth_inv_det of the alarm module and the discharge voltage Vth_inv_clamp of the discharge module are both lower than the output voltage Vc of the RC module, and the discharge voltage Vth_inv_clamp of the discharge module is lower than the alarm voltage Vth_inv_de of the alarm module. Before time t0, the alarm module will not output an electrostatic alarm signal and the discharge module will not perform electrostatic discharge.

[0046] At time t0, an electrostatic discharge event occurs at the input end of the RC module, and the input voltage VDD of the RC module begins to rise sharply. At this time, the output voltage VC of the RC module, the alarm voltage Vth_inv_det of the alarm module, and the discharge voltage Vth_inv_clamp of the discharge module all begin to rise. The growth rates of the alarm voltage Vth_inv_det of the alarm module and the discharge voltage Vth_inv_clamp of the discharge module are greater than the growth rate of the output voltage VC of the RC module.

[0047] Since the alarm voltage Vth_inv_det of the alarm module is always greater than the discharge voltage Vth_inv_clamp of the discharge module, the alarm voltage Vth_inv_det of the alarm module increases to the same as the output voltage VC of the RC module at time t1, and the alarm module outputs an electrostatic alarm signal at time t1. At time t2 after time t1, the discharge voltage Vth_inv_clamp of the discharge module also increases to the same as the output voltage VC of the RC module, and the discharge module performs electrostatic discharge at time t1.

[0048] For example, in one embodiment of the present application, Figure 4As shown, the RC module 101 may include a first resistor 211 and a first capacitor 221 connected in series, and the connection point between the first resistor 211 and the first capacitor 221 is the output voltage terminal of the RC module 101. The alarm module 102 may include a first inverter 212. The first input terminal of the first inverter 212 receives the input voltage of the RC module 101, and the second input terminal of the first inverter 212 receives the output voltage of the RC module 101. When the alarm voltage is greater than the output voltage of the RC module 101, the first input terminal of the first inverter 212 is connected to the output terminal of the first inverter 212, and the electrostatic alarm signal is output. The discharge module may include a second inverter 213 and a first switch unit 223. The first input terminal of the second inverter 213 receives the input voltage of the RC module 101, and the second input terminal of the second inverter 213 receives the output voltage of the RC module 101. When the alarm voltage is greater than or equal to the output voltage of the RC module, the output terminal of the second inverter 213 is connected to the first input terminal of the first switch unit 223. The first input end of the first switch unit 223 is connected to the output end of the second inverter 213 . When the output voltage of the second inverter 213 is greater than the first switch voltage, the first switch unit 223 is turned on to achieve static discharge.

[0049] The warning voltage may be a breakover voltage of the first inverter 212 , and the discharge voltage may be a breakover voltage of the second inverter 213 .

[0050] It should be noted that the turn-on voltage of the inverter is proportional to the power supply voltage of the inverter, and the turn-on voltage of the inverter is less than the power supply voltage of the inverter. When the turn-on voltage of the inverter is less than the voltage of the input inverter, the output terminal of the inverter is connected to the ground terminal of the inverter, and the output terminal of the inverter outputs a low voltage. When the turn-on voltage of the inverter is greater than or equal to the voltage of the input inverter, the output terminal of the inverter is connected to the power supply terminal voltage of the inverter, and the output terminal of the inverter outputs a high voltage, i.e., the power supply voltage. In an embodiment of the present application, the first inverter 212 receives the power supply voltage, i.e., the input voltage of the RC module 101, through the first input terminal, and the first inverter 212 receives the input voltage, i.e., the output voltage of the RC module 101, through the second input terminal; the second inverter 213 receives the power supply voltage, i.e., the input voltage of the RC module 101, through the first input terminal, and the second inverter 213 receives the input voltage, i.e., the output voltage of the RC module 101, through the second input terminal.

[0051] When the first inverter 212 is composed of an NMOS transistor and a PMOS transistor, the turn-on voltage Vth_inv_det of the first inverter 212 can be calculated according to Determine, wherein VDD is the power supply voltage of the first inverter 212, that is, the input voltage of the RC module 101, Vthp is the on-voltage of the PMOS tube in the first inverter 212, Vthn is the on-voltage of the NMOS tube in the first inverter 212, βp is the transconductance parameter of the PMOS tube in the first inverter 212, and βn is the transconductance parameter of the NMOS tube in the first inverter 212. The transconductance parameter βn of the NMOS tube can be adjusted by adjusting the width-to-length ratio of the NMOS tube, and the transconductance parameter βp of the PMOS tube can be adjusted by adjusting the width-to-length ratio of the PMOS tube. The on-voltage Vthn of the NMOS tube and the transconductance parameter βn of the NMOS tube can be adjusted by adjusting the preparation process of the NMOS tube, and the on-voltage Vthp of the PMOS tube and the transconductance parameter βp of the PMOS tube can be adjusted by adjusting the preparation process of the PMOS tube. By adjusting the on-voltage Vthn of the NMOS tube, the transconductance parameter βn of the NMOS tube, the on-voltage Vthp of the PMOS tube and the transconductance parameter βp of the PMOS tube in the first inverter 212, the ratio of the turning voltage Vth_inv_det of the first inverter 212, i.e., the alarm voltage, to the input voltage of the RC module 101 can be adjusted. At the same time, the ratio of the increase rate of the alarm voltage to the increase rate of the input voltage of the RC module 101 can also be adjusted.

[0052] Similarly, when the second inverter 213 is composed of an NMOS tube and a PMOS tube, by adjusting the on-voltage Vthn1 of the NMOS tube in the second inverter 212, the transconductance parameter βn1 of the NMOS tube, the on-voltage Vthp1 of the PMOS tube, and the transconductance parameter βp1 of the PMOS tube, the ratio of the turning voltage Vth_inv_clamp (i.e., the discharge voltage) of the second inverter 213 to the input voltage of the RC module 101 can be adjusted, and the ratio of the increase rate of the discharge voltage to the increase rate of the input voltage of the RC module 101 can also be adjusted.

[0053] Since the initial value of the alarm voltage can be understood as the value of the alarm voltage when no electrostatic discharge event occurs at the input end of the RC module 101, and the initial value of the discharge voltage can be understood as the value of the discharge voltage when no electrostatic discharge event occurs at the input end of the RC module 101. The output voltage of the RC module 101 is equal to the voltage on the first capacitor 221. When no electrostatic discharge event occurs at the input end of the RC module 101, the voltage on the first capacitor 221 is equal to the input voltage of the RC module 101, that is, the initial value of the output voltage of the RC module 101 is the input voltage of the RC module 101, therefore, according to the above method, the ratio of the alarm voltage to the input voltage of the RC module 101 and the ratio of the discharge voltage to the input voltage of the RC module 101 are adjusted so that the alarm voltage and the discharge voltage are both less than the input voltage of the RC module 101, which can ensure that the initial value of the alarm voltage and the initial value of the discharge voltage are both less than the initial value of the output voltage of the RC module.

[0054] In addition, since the output voltage of the RC module 101 is equal to the voltage on the first capacitor 221 in the RC module, the voltage on the first capacitor 221 cannot change suddenly, and the increase rate of the voltage on the first capacitor 221 is less than the increase rate of the input voltage of the RC module 101, so that the output voltage of the RC module 101 is less than the increase rate of the input voltage of the RC module 101. By adjusting the ratio of the increase rate of the alarm voltage to the increase rate of the input voltage of the RC module 101 and the ratio of the increase rate of the discharge voltage to the increase rate of the input voltage of the RC module 101, the increase rate of the alarm voltage and the increase rate of the discharge voltage can be made greater than the increase rate of the input voltage of the RC module 101, thereby ensuring that the increase rate of the alarm voltage and the increase rate of the discharge voltage are greater than the increase rate of the output voltage of the RC module.

[0055] By making the initial value of the alarm voltage of the alarm module and the initial value of the discharge voltage of the discharge module smaller than the initial value of the output voltage of the RC module, the electrostatic discharge protection circuit can be made such that the alarm module will not output an electrostatic alarm signal in the initial state, and the discharge module will not discharge electrostatic electricity, ensuring that the electrostatic discharge protection circuit will not affect the normal operation of other components in the chip. The increase rate of the alarm voltage of the alarm module is greater than the increase rate of the output voltage of the RC module, which can increase the alarm voltage of the alarm module to a value greater than the output voltage of the RC module over time, so that the output alarm module outputs an electrostatic alarm signal; similarly, the increase rate of the discharge voltage of the discharge module is greater than the increase rate of the output voltage of the RC module, which can increase the discharge voltage of the discharge module to a value greater than the output voltage of the RC module over time, so that the discharge module discharges electrostatic electricity.

[0056] Embodiment 3

[0057] Based on the first embodiment, Figure 4As shown, in the electrostatic discharge protection circuit provided in the third embodiment of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102 and a discharge module 103. Among them, the RC module 101 includes a first resistor 211 and a first capacitor 221 connected in series, one end of the first capacitor 221 is grounded, the other end of the first capacitor 221 is connected to the first resistor 211, the other end of the first resistor 211 is the input voltage end of the RC module 101, and the connection point between the first resistor 211 and the first capacitor 221 is the output voltage end of the RC module 101.

[0058] Specifically, the first resistor 211 may also be a plurality of resistors connected in series or in parallel, and the embodiments of the present application are not limited thereto. Figure 4 The first resistor 211 is taken as an example for demonstration. The first capacitor 221 may also be a plurality of capacitors connected in series or in parallel, which is not limited in the embodiments of the present application. Figure 4 In the figure, the first capacitor 221 is taken as an example for demonstration.

[0059] The first resistor 211 and the first capacitor 221 connected in series form an RC circuit structure. When the voltage input from the input voltage end of the RC module 101 increases, the voltage on the first capacitor 221 also increases. By adjusting the resistance value of the first resistor 211 and the capacitance value of the first capacitor 221, the charging time constant of the RC circuit structure can be adjusted. Since the charging time constant of the RC circuit structure is positively correlated with the increase rate of the voltage on the first capacitor 221, by adjusting the resistance value of the first resistor 211 and the capacitance value of the first capacitor 221, the increase rate of the voltage on the first capacitor 221, that is, the increase rate of the voltage output from the output voltage end of the RC module 101, can be adjusted.

[0060] The discharge module 103 performs electrostatic discharge when the discharge voltage is greater than or equal to the output voltage of the RC module 101. If the increase rate of the input voltage of the RC module 101 and the increase rate of the discharge voltage are both unchanged, by slowing down the increase rate of the voltage outputted by the output voltage terminal of the RC module 101, the moment when the discharge voltage is greater than or equal to the output voltage of the RC module 101 can be advanced, that is, the moment when the discharge module 103 performs electrostatic discharge in advance; by accelerating the increase rate of the voltage outputted by the output voltage terminal of the RC module 101, the moment when the discharge voltage is greater than or equal to the output voltage of the RC module 101 can be delayed, that is, the moment when the discharge module 103 performs electrostatic discharge in advance is delayed.

[0061] The alarm module 102 outputs an electrostatic alarm signal when the alarm voltage is greater than or equal to the output voltage of the RC module 101. If the increase rate of the input voltage of the RC module 101 and the increase rate of the alarm voltage remain unchanged, by slowing down the increase rate of the voltage output by the output voltage terminal of the RC module 101, the moment when the alarm voltage is greater than or equal to the output voltage of the RC module 101 can be advanced, that is, the moment when the alarm module 102 outputs the electrostatic alarm signal; by accelerating the increase rate of the voltage output by the output voltage terminal of the RC module 101, the moment when the alarm voltage is greater than or equal to the output voltage of the RC module 101 can be delayed, that is, the moment when the alarm module 102 outputs the electrostatic alarm signal.

[0062] In summary, by adjusting the resistance value of the first resistor 211 and the capacitance value of the first capacitor 221, the time when the discharge module 103 performs electrostatic discharge and the time when the alarm module 102 outputs the electrostatic alarm signal can be adjusted under the premise that the increase rate of the input voltage of the RC module 101, the increase rate of the discharge voltage and the increase rate of the alarm voltage remain unchanged.

[0063] Preferably, the resistance value of the first resistor 211 may be 1 mΩ, and the capacitance value of the first capacitor 221 may be 1 pF.

[0064] Embodiment 4

[0065] Based on the first embodiment, Figure 4 As shown, in the electrostatic discharge protection circuit provided in the fourth embodiment of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102 and a discharge module 103. Among them, the alarm module 102 includes a first inverter 212. The first inverter 212 is used to receive the input voltage of the RC module 101 through the first input terminal, and receive the output voltage of the RC module 101 through the second input terminal of the first inverter 212. When the alarm voltage is greater than the output voltage of the RC module 101, the first input terminal of the first inverter 212 is connected to the output terminal of the first inverter 212, and an electrostatic alarm signal is output.

[0066] Specifically, when the first input terminal of the first inverter 212 is connected to the output terminal of the first inverter 212 , the output terminal of the first inverter 212 can output the input voltage of the RC module 101 , so that the static electricity alarm signal is a high voltage.

[0067] The first inverter 212 may be a complementary metal oxide semiconductor (CMOS) circuit, or may be composed of at least two field effect transistors, or may be composed of a plurality of logic gate circuits, etc. The embodiments of the present application do not impose any specific restrictions on the specific implementation of the first inverter 212.

[0068] The alarm voltage may be a breakover voltage of the second inverter 213. It should be noted that the breakover voltage of the inverter is proportional to the power supply voltage of the inverter, and the breakover voltage of the inverter is less than the power supply voltage of the inverter. When the breakover voltage of the inverter is less than the input voltage of the inverter, the output terminal of the inverter is grounded, and the output terminal of the inverter outputs a low voltage. When the breakover voltage of the inverter is greater than or equal to the voltage of the input inverter, the output terminal of the inverter is connected to the power supply terminal voltage of the inverter, and the output terminal of the inverter outputs a high voltage, i.e., the power supply voltage. In this embodiment, the first inverter 212 receives the power supply voltage, i.e., the input voltage of the RC module 101, through the first input terminal, and the first inverter 212 receives the input voltage, i.e., the output voltage of the RC module 101, through the second input terminal.

[0069] For example, when the first inverter 212 is composed of an NMOS transistor and a PMOS transistor, the warning voltage may be a breakover voltage Vth_inv_det of the first inverter 212. The breakover voltage Vth_inv_det of the first inverter 212 may be calculated based on Determine, wherein VDD is the power supply voltage of the first inverter 212, that is, the input voltage of the RC module 101, Vthp is the on-voltage of the PMOS tube in the first inverter 212, Vthn is the on-voltage of the NMOS tube in the first inverter 212, βp is the transconductance parameter of the PMOS tube in the first inverter 212, and βn is the transconductance parameter of the NMOS tube in the first inverter 212. The transconductance parameter βn of the NMOS tube can be adjusted by adjusting the width-to-length ratio of the NMOS tube, and the transconductance parameter βp of the PMOS tube can be adjusted by adjusting the width-to-length ratio of the PMOS tube. The on-voltage Vthn of the NMOS tube and the transconductance parameter βn of the NMOS tube can be adjusted by adjusting the preparation process of the NMOS tube, and the on-voltage Vthp of the PMOS tube and the transconductance parameter βp of the PMOS tube can be adjusted by adjusting the preparation process of the PMOS tube. By adjusting the on-voltage Vthn of the NMOS tube, the transconductance parameter βn of the NMOS tube, the on-voltage Vthp of the PMOS tube and the transconductance parameter βp of the PMOS tube in the first inverter 212, the ratio of the turning voltage Vth_inv_det of the first inverter 212, i.e., the alarm voltage, to the input voltage of the RC module 101 can be adjusted. At the same time, the ratio of the increase rate of the alarm voltage to the increase rate of the input voltage of the RC module 101 can also be adjusted.

[0070] Optionally, in an embodiment of the present application, when the alarm voltage of the first inverter 212 is less than the output voltage of the RC module 101 , the ground terminal of the first inverter 212 is conductively connected to the output terminal of the first inverter 212 .

[0071] Specifically, since the alarm voltage is less than the output voltage of the RC module 101, it can be understood that the electrostatic discharge event has ended. When the alarm voltage of the first inverter 212 is less than the output voltage of the RC module 101, the ground terminal of the first inverter 212 is connected to the output terminal of the first inverter 212, and the output voltage of the output terminal of the first inverter 212 is 0. When the output voltage of the output terminal of the first inverter 212 is 0, it can be considered that the output terminal of the first inverter 212 has not outputted an electrostatic alarm signal, so that no alarm is given after the electrostatic discharge event ends, thereby avoiding the chip from performing unnecessary processing operations after the electrostatic discharge event has ended, thereby saving the processing resources of the chip.

[0072] Embodiment 5

[0073] Based on the first embodiment, Figure 4 As shown, in the electrostatic discharge protection circuit provided in the fifth embodiment of the present application, the electrostatic discharge protection circuit includes an RC module 101 , an alarm module 102 and a discharge module 103 . The discharge module includes a second inverter 213 and a first switch unit 223 .

[0074] The first input end of the second inverter 213 receives the input voltage of the RC module 101, and the second input end of the second inverter 213 receives the output voltage of the RC module 101. When the alarm voltage is greater than or equal to the output voltage of the RC module, the output end of the second inverter 213 is connected to the first input end of the first switch unit 223.

[0075] The first input end of the first switch unit 223 is connected to the output end of the second inverter 213 . When the output voltage of the second inverter 213 is greater than the first switch voltage, the first switch unit 223 is turned on to achieve static discharge.

[0076] Specifically, the second input end of the first switch unit 223 is connected to the input end of the RC module 101, and the output end of the first switch unit 223 is grounded. When the output voltage of the second inverter 213 is greater than the first switch voltage, the second input end of the first switch unit 223 is connected to the output end of the first switch unit 223, and the static electricity at the input end of the RC module 101 is guided to the ground to achieve static electricity discharge.

[0077] The discharge voltage may be the breakover voltage of the second inverter 213. It should be noted that the breakover voltage of the inverter is proportional to the power supply voltage of the inverter, and the breakover voltage of the inverter is less than the power supply voltage of the inverter. When the breakover voltage of the inverter is less than the input voltage of the inverter, the output terminal of the inverter is grounded, and the output terminal of the inverter outputs a low voltage. When the breakover voltage of the inverter is greater than or equal to the voltage of the input inverter, the output terminal of the inverter is connected to the power supply terminal voltage of the inverter, and the output terminal of the inverter outputs a high voltage, i.e., the power supply voltage. In this embodiment, the second inverter 213 receives the power supply voltage, i.e., the input voltage of the RC module 101, through the first input terminal, and the second inverter 213 receives the input voltage, i.e., the output voltage of the RC module 101, through the second input terminal.

[0078] For example, when the second inverter 213 is composed of an NMOS transistor and a PMOS transistor, the breakover voltage Vth_inv_clamp of the second inverter 213 can be calculated according to Determine, wherein VDD is the power supply voltage of the second inverter 213, i.e., the input voltage of the RC module 101, Vthp1 is the on-voltage of the PMOS tube in the second inverter 213, Vthn1 is the on-voltage of the NMOS tube in the second inverter 213, βp1 is the transconductance parameter of the PMOS tube in the second inverter 213, and βn1 is the transconductance parameter of the NMOS tube in the second inverter 213. The transconductance parameter βn1 of the NMOS tube can be adjusted by adjusting the width-to-length ratio of the NMOS tube, and the transconductance parameter βp1 of the PMOS tube can be adjusted by adjusting the width-to-length ratio of the PMOS tube. The on-voltage Vthn1 of the NMOS tube and the transconductance parameter βn1 of the NMOS tube can be adjusted by adjusting the preparation process of the NMOS tube, and the on-voltage Vthp1 of the PMOS tube and the transconductance parameter βp1 of the PMOS tube can be adjusted by adjusting the preparation process of the PMOS tube. By adjusting the on-voltage Vthn1 of the NMOS tube in the second inverter 213, the transconductance parameter βn1 of the NMOS tube, the on-voltage Vthn1 of the PMOS tube, and the transconductance parameter βp1 of the PMOS tube, the breaking voltage Vth_inv_clamp of the second inverter 213, i.e., the ratio of the discharge voltage to the input voltage of the RC module 101, can be adjusted. At the same time, the ratio of the increase rate of the alarm voltage to the increase rate of the input voltage of the RC module 101 can also be adjusted.

[0079] The first switch unit 223 may be composed of one or more transistors. When the first switch unit 223 includes multiple transistors, the multiple transistors can respectively perform corresponding switching actions when the output voltage of the second inverter 213 is greater than the first switch voltage, so that the first switch unit 223 is turned on. The embodiment of the present application does not specifically limit the composition of the first switch unit 223. Figure 4In the example, the first switch unit 223 includes a single N-type transistor, wherein the gate of the N-type transistor receives the output voltage of the second inverter 213, the drain of the N-type transistor is connected to the input end of the RC module 101, and the source of the N-type transistor is grounded. When the voltage at the gate of the N-type transistor is greater than the first switch voltage, the drain of the N-type transistor is turned on with the source of the N-type transistor, and the static electricity at the input end of the RC module 101 is guided to the ground through the N-type transistor to achieve static electricity discharge.

[0080] Embodiment 6

[0081] Based on any one of the first to fifth embodiments, Figure 7 A schematic circuit structure diagram of an electrostatic discharge protection circuit provided in an embodiment of the present application, such as Figure 7 As shown, in the electrostatic discharge protection circuit provided in the sixth embodiment of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102 and a discharge module 103. Among them, the electrostatic discharge protection circuit also includes a pulse extension alarm module 104, and the pulse extension alarm module 104 delays the electrostatic alarm signal and outputs a delayed electrostatic alarm signal whose duration is greater than the duration of the electrostatic alarm signal.

[0082] Specifically, the duration of an electrostatic discharge event is often short (for example, an electrostatic discharge event gradually disappears after lasting for about 100nS). When an alarm signal occurs, the chip may take hardware preventive measures very quickly, but the software processing speed may not be able to respond to the alarm signal in time. By delaying the electrostatic alarm signal through the pulse extension alarm module 104 and outputting a delayed electrostatic alarm signal with a duration greater than the electrostatic alarm signal, the circuit module for processing electrostatic discharge events in the microcontroller unit MCU or the chip where the electrostatic discharge protection circuit is located can respond to the delayed electrostatic alarm signal with a duration greater than the electrostatic alarm signal when the alarm signal is not responded to in time, such as performing subsequent error correction, thereby improving the stability of the chip operation and the user experience.

[0083] Embodiment 7

[0084] Based on Example 6, Figure 8 A schematic circuit structure diagram of a pulse extension alarm module provided in an embodiment of the present application, such as Figure 7 as well as Figure 8 As shown, in the electrostatic discharge protection circuit provided in Embodiment 7 of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, a discharge module 103 and a pulse extension alarm module 104, wherein the pulse extension alarm module 104 includes a second switch unit 114, a third switch unit 124, a second capacitor 134, and a third inverter 144.

[0085] The second switch unit 114 is turned on when the first input terminal of the second switch unit 114 receives the static electricity alarm signal, and is turned off when the first input terminal of the second switch unit 114 does not receive the static electricity alarm signal.

[0086] The third switch unit 124 is disconnected when the first input terminal of the third switch unit 124 receives the static electricity alarm signal, and is turned on when the first input terminal of the third switch unit 124 does not receive the static electricity alarm signal.

[0087] The second capacitor 134 is used for charging when the second switch unit 114 is turned off and the third switch unit 134 is turned on, and discharging when the second switch unit 114 is turned on and the third switch unit 134 is turned off.

[0088] The first input terminal of the third inverter 144 receives the voltage of the second capacitor 134 , and outputs a delayed electrostatic alarm signal when the voltage of the second capacitor 134 is less than the pulse extension voltage.

[0089] Specifically, the first input end of the second switch unit 114 is connected to the output end of the alarm module 102, the second input end of the second switch unit 114 is connected to the first end of the second capacitor 134, and the output end of the second switch unit 114 is grounded. The first input end of the third switch unit 124 is connected to the output end of the alarm module 102, the second input end of the third switch unit 124 receives the input voltage of the RC module 101, the output end of the third switch unit 124 is connected to the first end of the second capacitor 134, and the second end of the second capacitor 134 is grounded. The second input end of the third inverter 144 receives the input voltage of the RC module 101, and the third inverter 144 has a ground end.

[0090] When the output end of the alarm module 102 outputs an electrostatic alarm signal, the first input end of the second switch unit 114 receives the electrostatic alarm signal output from the output end of the alarm module 102, the second input end of the second switch unit 114 is connected to the output end of the second switch unit 114, and the first end of the second capacitor 134 is grounded. At the same time, the first input end of the third switch unit 124 receives the electrostatic alarm signal output from the output end of the alarm module 102, the second input end of the third switch unit 124 is disconnected from the output end of the third switch unit 124, the output end of the third switch unit 124 does not output any voltage to the first end of the second capacitor 134, the first end of the second capacitor 134 is discharged, so that the voltage of the second capacitor 134 is in a state less than the pulse expansion voltage, the first input end of the third inverter 144 receives the voltage of the second capacitor 134, and outputs a delayed electrostatic alarm signal through the output end of the third inverter 144.

[0091] When the output end of the alarm module 102 does not output the electrostatic alarm signal, the first input end of the second switch unit 114 does not receive the electrostatic alarm signal output by the output end of the alarm module 102, the second input end of the second switch unit 114 is disconnected from the output end of the second switch unit 114, so that the first end of the second capacitor 134 is disconnected from the ground, and at the same time, when the first input end of the third switch unit 124 does not receive the electrostatic alarm signal output by the output end of the alarm module 102, the second input end of the third switch unit 124 is connected to the output end of the third switch unit 124, and the input voltage of the RC module 101 is output to the first end of the second capacitor 134 through the output end of the third switch unit 124, and the second capacitor 134 is charged to increase the voltage of the second capacitor 134. The first input terminal of the third inverter 144 receives the voltage of the second capacitor 134. When the voltage of the second capacitor 134 does not increase to a value greater than or equal to the pulse extension voltage, the third inverter 144 still outputs a delayed electrostatic alarm signal. When the voltage of the second capacitor 134 increases to a value greater than or equal to the pulse extension voltage, the third inverter 144 stops outputting the delayed electrostatic alarm signal. The time length from the moment when the output terminal of the alarm module 102 does not output the electrostatic alarm signal to the moment when the voltage of the second capacitor 134 increases to a value greater than or equal to the pulse extension voltage can be understood as the time difference between the duration of the delayed electrostatic alarm signal and the duration of the electrostatic alarm signal.

[0092] It should be noted that the time when the third inverter 144 outputs the delayed static electricity alarm signal is later than the time when the alarm module 102 outputs the static electricity alarm signal, but the time difference between the two times is very short and can be ignored.

[0093] The second switch unit 114 may be composed of one or more transistors. When the second switch unit 114 includes multiple transistors, the multiple transistors may respectively perform corresponding switching actions to turn on the second switch unit 114 when the first input terminal of the second switch unit 114 receives the electrostatic alarm signal, and may also respectively perform corresponding switching actions to turn off the second switch unit 114 when the first input terminal of the second switch unit 114 does not receive the electrostatic alarm signal. The embodiment of the present application does not specifically limit the composition of the second switch unit 114.

[0094] The third switch unit 124 may be composed of one or more transistors. When the third switch unit 124 includes multiple transistors, the multiple transistors may respectively perform corresponding switching actions to turn on the third switch unit 124 when the first input terminal of the third switch unit 124 receives the electrostatic alarm signal, and may also respectively perform corresponding switching actions to turn off the third switch unit 124 when the first input terminal of the third switch unit 124 does not receive the electrostatic alarm signal. The embodiment of the present application does not specifically limit the composition of the third switch unit 124. The second capacitor 134 may also include multiple capacitors connected in series or in parallel, and the embodiment of the present application does not limit this.

[0095] The third inverter 144 may be a complementary metal oxide semiconductor circuit, or may be composed of at least two field effect transistors, or may be composed of a plurality of logic gate circuits, etc. The embodiments of the present application do not impose any specific limitation on the specific implementation method of the third inverter 144.

[0096] Among them, the pulse extension voltage can be the breakover voltage of the third inverter 144. It should be noted that the breakover voltage of the inverter is proportional to the power supply voltage of the inverter, and the breakover voltage of the inverter is less than the power supply voltage of the inverter. When the breakover voltage of the inverter is less than the input voltage of the inverter, the output end of the inverter is grounded, and the output end of the inverter outputs a low voltage. When the breakover voltage of the inverter is greater than or equal to the voltage of the input inverter, the output end of the inverter is connected to the power supply terminal voltage of the inverter, and the output end of the inverter outputs a high voltage, that is, the power supply voltage. In this embodiment, the third inverter 144 receives the power supply voltage, that is, the input voltage of the RC module 101, through the second input terminal, and the third inverter 144 receives the input voltage, that is, the voltage of the second capacitor 134, through the first input terminal.

[0097] Exemplarily, when the third inverter 144 is composed of an NMOS transistor and a PMOS transistor, the pulse extension voltage may be a turn-on voltage Vth_inv_pulse of the third inverter 144. The turn-on voltage Vth_inv_pulse of the third inverter 144 may be based on Determine, wherein VDD is the power supply voltage of the third inverter 144, i.e., the input voltage of the RC module 101, vthp2 is the on-voltage of the PMOS tube in the third inverter 144, Vthn2 is the on-voltage of the NMOS tube in the third inverter 144, βp2 is the transconductance parameter of the PMOS tube in the third inverter 144, and βn2 is the transconductance parameter of the NMOS tube in the third inverter 144. The transconductance parameter βn2 of the NMOS tube can be adjusted by adjusting the width-to-length ratio of the NMOS tube, and the transconductance parameter βp2 of the PMOS tube can be adjusted by adjusting the width-to-length ratio of the PMOS tube. The on-voltage Vthn2 of the NMOS tube and the transconductance parameter βn2 of the NMOS tube can be adjusted by adjusting the preparation process of the NMOS tube, and the on-voltage Vthp2 of the PMOS tube and the transconductance parameter βp2 of the PMOS tube can be adjusted by adjusting the preparation process of the PMOS tube. By adjusting the on-voltage Vthn2 of the NMOS tube, the transconductance parameter βn2 of the NMOS tube, the on-voltage Vthp2 of the PMOS tube and the transconductance parameter βp2 of the PMOS tube in the third inverter 144, the ratio of the turning voltage Vth_inv_pulse of the third inverter 144, i.e., the pulse extension voltage to the input voltage of the RC module 101, can be adjusted. At the same time, the ratio of the increase rate of the pulse extension voltage to the increase rate of the input voltage of the RC module 101 can also be adjusted.

[0098] It should be noted that, since when the voltage of the second capacitor 134 is charged to be greater than or equal to the pulse extension voltage (i.e., when the voltage of the second capacitor 134 increases to be greater than or equal to the pulse extension voltage), the voltage input to the first input terminal of the third inverter 144 is greater than or equal to the pulse extension voltage, the third inverter 144 stops outputting the delayed electrostatic alarm signal, and thus the duration of the delayed electrostatic alarm signal can be adjusted by adjusting the charging speed of the voltage of the second capacitor 134. Among them, by adjusting the resistance value between the first input terminal of the third switch unit 124 and the output terminal of the third switch unit 124 and the capacitance value of the second capacitor 134, the RC time constant between the third switch unit 124 and the second capacitor 134 can be adjusted, thereby adjusting the charging speed of the second capacitor 134.

[0099] Embodiment 8

[0100] On the basis of Example 7, Figure 7 as well as Figure 8As shown, in the electrostatic discharge protection circuit provided in the eighth embodiment of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, a discharge module 103 and a pulse extension alarm module 104, wherein the pulse extension alarm module 104 includes a second switch unit 114, a third switch unit 124, a second capacitor 134, and a third inverter 144. The second input terminal of the third inverter 114 is connected to the input voltage terminal of the RC module 101, and when the voltage of the second capacitor 134 is less than the pulse extension voltage, the second input terminal of the third inverter 144 is connected to the output terminal of the third inverter 144.

[0101] Among them, the second input end of the third inverter 144 receives the input voltage of the RC module 101. When the voltage of the second capacitor 134 received at the first input end of the third inverter 144 is less than the pulse expansion voltage, the second input end of the third inverter 144 and the output end of the third inverter 144 are connected, and the output end of the third inverter 144 outputs the input voltage signal of the RC module 101, so that the delayed electrostatic alarm signal is a high voltage, ensuring that the voltage value of the delayed electrostatic alarm signal can meet the requirements.

[0102] Furthermore, when the voltage of the second capacitor 134 received at the first input terminal of the third inverter 144 is greater than or equal to the pulse expansion voltage, the ground terminal of the third inverter 144 and the output terminal of the third inverter 144 are connected, the delayed electrostatic alarm signal is a high voltage, and the output terminal of the third inverter 144 stops outputting the delayed electrostatic alarm signal.

[0103] Embodiment 9

[0104] On the basis of Example 8, Figure 7 as well as Figure 8 As shown, in the electrostatic discharge protection circuit provided in Embodiment 9 of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, a discharge module 103 and a pulse extension alarm module 104, wherein the pulse extension alarm module 104 includes a second switch unit 114, a third switch unit 124, a second capacitor 134, and a third inverter 144.

[0105] The third switch unit 124 includes a P-type transistor, a gate of the P-type transistor receives the electrostatic alarm signal, a drain of the P-type transistor receives the input voltage of the RC module 11, a source of the P-type transistor is connected to the second capacitor 134, and the P-type transistor is turned on when the electrostatic alarm signal is greater than or equal to the first switch threshold.

[0106] Since the process of setting transistors in the chip is relatively mature and the cost is low, the third switch unit 144 includes a P-type transistor, which can enable the third switch unit 144 to be turned on when the electrostatic alarm signal is greater than or equal to the first switch threshold at a low manufacturing cost.

[0107] Embodiment 10

[0108] On the basis of Example 8, Figure 7 as well as Fig. 9 As shown, in the electrostatic discharge protection circuit provided in the tenth embodiment of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, a discharge module 103 and a pulse extension alarm module 104, wherein the pulse extension alarm module 104 includes a second switch unit 114, a third switch unit 124, a second capacitor 134, and a third inverter 144.

[0109] The third switch unit 124 includes n P-type transistors, n≥2, where n is a natural number, the gates of the n P-type transistors receive the electrostatic alarm signal, the drain of the first-stage P-type transistor among the n P-type transistors receives the input voltage of the RC module 11, the source of the previous-stage P-type transistor among the n P-type transistors is connected to the drain of the adjacent subsequent-stage P-type transistor, the source of the nth-stage P-type transistor among the n P-type transistors is connected to the second capacitor 134, and the n P-type transistors are turned on when the electrostatic alarm signal is greater than or equal to the first switching threshold.

[0110] By including n P-type transistors in the third switch unit 144, where n≥2, compared with the case where the third switch unit 144 includes only one transistor, the third switch unit 144 can be turned on when the electrostatic alarm signal is greater than or equal to the first switch threshold, while increasing the resistance of the third switch unit 144 and extending the charging time of the second capacitor 134, thereby extending the duration of the delayed electrostatic alarm signal. Compared with a solution of extending the duration of the delayed electrostatic alarm signal by adjusting the structure of the second capacitor 134 or setting a resistor in the third switch unit 144, this solution has a lower cost.

[0111] Embodiment 11

[0112] Fig.10 A schematic circuit structure diagram of an electrostatic discharge protection circuit provided in an embodiment of the present application, such as Fig.10 As shown, based on the first embodiment, in the electrostatic discharge protection circuit provided in the eleventh embodiment of the present application, the electrostatic discharge protection circuit further includes a processing module 200.

[0113] The processing module 200 receives the electrostatic warning signal, and executes at least one of an electrostatic discharge prevention method and an electrostatic discharge remediation method in response to the electrostatic warning signal.

[0114] The electrostatic discharge prevention method includes pausing the program currently executed by the processing module 200 .

[0115] The electrostatic discharge remediation method includes resending the data sent by the processing module 200 within the electrostatic discharge time interval after the electrostatic alarm signal ends. The electrostatic discharge time interval is the time interval between the moment when the processing module 200 receives the electrostatic alarm signal and the moment when the processing module 200 stops receiving the electrostatic alarm signal.

[0116] Specifically, the processing module 200 may be a micro controller unit (MCU), or may be a circuit module in a chip where an electrostatic discharge protection circuit is located and used for processing electrostatic discharge events.

[0117] In the electrostatic discharge protection circuit provided in the embodiment of the present application, the processing module 200 receives an electrostatic alarm signal, and executes at least one of an electrostatic discharge prevention method and an electrostatic discharge remediation method in response to the electrostatic alarm signal. The electrostatic discharge prevention method includes pausing the program currently executed by the processing module 200. By executing the electrostatic discharge prevention method, it is possible to avoid errors in the program currently executed by the processing module 200 due to the occurrence of an electrostatic discharge event. The data sent by the processing module 200 during the electrostatic discharge time interval may be erroneous due to the influence of the electrostatic discharge event. By resending this part of the data after the electrostatic alarm signal ends, the module receiving the data sent by the processing module 200 can obtain the data sent by the processing module 200 without errors.

[0118] Embodiment 12

[0119] On the basis of any one of embodiments 1 to 11, a chip with an electrostatic discharge protection circuit is provided as embodiment 12 of the present application. The chip includes the electrostatic discharge protection circuit provided by any one of embodiments 1 to 12.

[0120] The chip provided in the embodiment of the present application includes an electrostatic discharge protection circuit. In the electrostatic discharge protection circuit, when an electrostatic discharge event occurs, the input voltage of the RC module will rise sharply due to the instantaneous electrostatic high voltage shock. At this time, the output voltage of the RC module, the alarm voltage of the alarm module, and the discharge voltage of the discharge module all increase. Since the alarm voltage is greater than the discharge voltage, the moment when the alarm voltage is greater than or equal to the output voltage of the RC module is earlier than the moment when the discharge voltage is greater than or equal to the output voltage of the RC module, ensuring that the alarm module outputs an electrostatic alarm signal first to warn that electrostatic discharge is about to be performed, and then the discharge module performs electrostatic discharge. Therefore, the electrostatic discharge protection circuit provided in the embodiment of the present application can output an electrostatic alarm signal to warn that an electrostatic discharge event is about to occur before electrostatic discharge, so that the chip can take software or hardware preventive measures or post-event remedial measures for the electrostatic discharge event, reducing the probability of irrecoverable hardware damage or operation errors in the chip during electrostatic discharge, thereby improving the stability of the chip operation and improving the user experience.

[0121] For the convenience of description, the above device is described in terms of functions and is described separately in various units. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple hardware.

[0122] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0123] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0124] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. An electrostatic discharge protection circuit, characterized in that: The electrostatic discharge protection circuit includes an RC module, an alarm module and a discharge module; When the input voltage of the RC module increases, the output voltage thereof increases; The alarm module receives the input voltage of the RC module and the output voltage of the RC module, and when the input voltage of the RC module increases, the alarm voltage of the alarm module increases, and when the alarm voltage is greater than or equal to the output voltage of the RC module, outputs a static electricity alarm signal; The discharge module receives the input voltage of the RC module and the output voltage of the RC module. When the input voltage of the RC module increases, the discharge voltage of the discharge module increases, and when the discharge voltage is greater than or equal to the output voltage of the RC module, electrostatic discharge is performed, and the alarm voltage is greater than the discharge voltage.

2. The electrostatic discharge protection circuit according to claim 1, characterized in that: An initial value of the alarm voltage of the alarm module and an initial value of the discharge voltage of the discharge module are both smaller than an initial value of the output voltage of the RC module, and an increase rate of the alarm voltage of the alarm module and an increase rate of the discharge voltage of the discharge module are both greater than an increase rate of the output voltage of the RC module.

3. The electrostatic discharge protection circuit according to claim 1, characterized in that: The RC module includes a first resistor and a first capacitor connected in series, one end of the first capacitor is grounded, the other end of the first capacitor is connected to the first resistor, the other end of the first resistor is the input voltage end of the RC module, and the connection point between the first resistor and the first capacitor is the output voltage end of the RC module.

4. The electrostatic discharge protection circuit according to claim 1, characterized in that: The alarm module includes a first inverter; The first input end of the first inverter receives the input voltage of the RC module, and the second input end of the first inverter receives the output voltage of the RC module. When the alarm voltage is greater than or equal to the output voltage of the RC module, the second input end of the first inverter is connected to the output end of the first inverter to output the electrostatic alarm signal.

5. The electrostatic discharge protection circuit according to claim 4, characterized in that: When the alarm voltage of the first inverter is less than the output voltage of the RC module, the ground terminal of the first inverter is conductively connected to the output terminal of the first inverter.

6. The electrostatic discharge protection circuit according to claim 1, characterized in that: The discharge module includes a second inverter and a first switch unit; The first input terminal of the second inverter receives the input voltage of the RC module, and the second input terminal receives the output voltage of the RC module. When the alarm voltage is greater than or equal to the output voltage of the RC module, the first input terminal of the second inverter is connected to the output terminal of the second inverter; The first input end of the first switch unit is connected to the output end of the second inverter. When the output voltage of the second inverter is greater than the first switch voltage, the first switch unit is turned on to achieve static discharge.

7. The electrostatic discharge protection circuit according to any one of claims 1 to 6, characterized in that: The electrostatic discharge protection circuit further includes a pulse extension alarm module, which delays the electrostatic alarm signal and outputs a delayed electrostatic alarm signal having a duration greater than that of the electrostatic alarm signal.

8. The electrostatic discharge protection circuit according to claim 7, characterized in that: The pulse extension alarm module includes a second switch unit, a third switch unit, a second capacitor, and a third inverter; The second switch unit is turned on when the first input end of the second switch unit receives the static electricity alarm signal, and is turned off when the first input end of the second switch unit does not receive the static electricity alarm signal; The third switch unit is disconnected when the first input end of the third switch unit receives the static electricity alarm signal, and is turned on when the first input end of the third switch unit does not receive the static electricity alarm signal; The second capacitor is charged when the second switch unit is turned off and the third switch unit is turned on, and is discharged when the second switch unit is turned on and the third switch unit is turned off; The first input terminal of the third inverter receives the voltage of the second capacitor, and outputs the delayed electrostatic alarm signal when the voltage of the second capacitor is less than the pulse expansion voltage.

9. The electrostatic discharge protection circuit according to claim 8, characterized in that: The second input terminal of the third inverter is connected to the input voltage terminal of the RC module. When the voltage of the second capacitor is less than the pulse extension voltage, the second input terminal of the second inverter is connected to the output terminal of the second inverter.

10. The electrostatic discharge protection circuit according to claim 9, characterized in that: When the voltage of the second capacitor of the third inverter is greater than or equal to the pulse extension voltage, the ground terminal of the third inverter is conductively connected to the output terminal of the third inverter.

11. The electrostatic discharge protection circuit according to claim 8, characterized in that: The third switch unit includes n P-type transistors, n≥2; The gates of the n P-type transistors receive the electrostatic alarm signal, the drain of the first-stage P-type transistor among the n P-type transistors receives the input voltage of the RC module, the source of the previous-stage P-type transistor among the n P-type transistors is connected to the drain of the adjacent subsequent-stage P-type transistor, the source of the nth-stage P-type transistor among the n P-type transistors is connected to the second capacitor, and the n P-type transistors are turned on when the electrostatic alarm signal is greater than or equal to the first switching threshold.

12. The electrostatic discharge protection circuit according to claim 8, characterized in that: The third switch unit includes a P-type transistor; The gate of the P-type transistor receives the electrostatic alarm signal, the drain of the P-type transistor receives the input voltage of the RC module, the source of the P-type transistor is connected to the second capacitor, and the P-type transistor is turned on when the electrostatic alarm signal is greater than or equal to a first switching threshold.

13. The electrostatic discharge protection circuit according to claim 1, characterized in that: The electrostatic discharge protection circuit also includes a processing module: The processing module receives the electrostatic warning signal, and executes at least one of an electrostatic discharge prevention method and an electrostatic discharge remediation method in response to the electrostatic warning signal; The electrostatic discharge prevention method includes pausing a program currently executed by the processing module; The electrostatic discharge remediation method includes resending the data sent by the processing module within the electrostatic discharge time interval after the alarm module stops outputting the electrostatic alarm signal, and the electrostatic discharge time interval is the time interval between the moment when the processing module receives the electrostatic alarm signal and the moment when the processing module stops receiving the electrostatic alarm signal.

14. A chip with an electrostatic discharge protection circuit, characterized in that: The invention comprises an electrostatic discharge protection circuit as claimed in any one of claims 1 to 13.

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