Switching circuit for addressable test chip and high-density addressable test chip

Abstract

The switch circuit for addressable test chip provided by the present invention includes several devices to be tested and several switches, and can select a designated device to be tested to connect to the test path by controlling the on-off state of the switches; two adjacent devices to be tested share an excitation switch and a sensing switch located at the same end of one of the devices to be tested; an intermediate switch is connected between the device to be tested and the sensing switch shared by the device to be tested and the adjacent device to be tested. The switch circuit of the present invention can, when measuring the selected device, have only one end of the sensing end connected to the selected device to be tested turned on while the other end is turned off, thereby solving the winding resistance error introduced by the shared switch and optimizing the accuracy of the shared circuit in small resistance measurement applications. The high-density addressable test chip also provided by the present invention has corresponding advantages due to the switch circuit for addressable test chip of the present invention.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor design and production, and in particular relates to a switch circuit for an addressable test chip and a corresponding high-density addressable test chip. Background Art

[0002] As the design scale of integrated circuits continues to expand, the density of electronic devices on a single chip is increasing, while the feature size of electronic devices is decreasing. At the same time, the integrated circuit process flow contains many complex process steps, each of which may have specific process manufacturing deviations, which ultimately leads to a reduction in the yield of integrated circuit chips. In the context of manufacturability design, in order to improve the yield of integrated circuit chips and shorten the yield maturity cycle, the industry generally uses a test method based on specially designed test chips to test test chips to obtain the data necessary for manufacturing process and design yield improvement.

[0003] The addressable test chip uses a decoder and a switch selection circuit to achieve the purpose of sharing pads for multiple test structures. Based on the requirements of advanced processes, in order to improve the area density of addressable test chips and ensure measurement accuracy as much as possible, the current better practice is to use a shared switch circuit for adjacent devices under test (DUT) to increase density. This method will introduce errors due to the shared switch circuit and the winding resistance related to the switch circuit cannot be ignored. If the resistance of the device under test is thousands of times the winding resistance of the switch circuit, the error introduced by the switch circuit can be ignored; however, if the resistance of the device under test is of the same order of magnitude as or smaller than the winding resistance of the switch circuit, the error introduced by the switch circuit cannot be ignored. This defect limits the application scenarios of addressable test chips with high-density shared switch circuits. Therefore, it is currently necessary to study a switch circuit for an addressable test chip and a corresponding high-density addressable chip that can break through the application limitations caused by the error introduced by the switch circuit and improve the test accuracy, so as to further promote the in-depth development and wide application of semiconductor design and production technology. Summary of the invention

[0004] The present invention is to solve all or part of the problems of the above-mentioned prior art. On one hand, it provides a switch circuit for an addressable test chip, which is suitable for device testing and does not affect the accuracy due to the winding resistance generated by the shared switch. Another aspect of the present invention provides a high-density addressable test chip having the switch circuit for the addressable test chip of the present invention, which can perform fast testing and has good measurement accuracy.

[0005] On one hand, the present invention provides a switch circuit for an addressable test chip, comprising a plurality of devices under test and a plurality of switches, which can select a designated device under test to connect to a test path by controlling the on-off state of the switches; two switches are respectively arranged at both ends of the device under test, and the two switches connected to the same end of the device under test are: an excitation switch for connecting an excitation pad, and an induction switch for connecting an induction pad; two adjacent devices under test share one excitation switch and one induction switch, and the two shared switches are located at the same end of the device under test; an intermediate switch is connected between the device under test and the induction switch shared by the device under test and the adjacent device under test.

[0006] The excitation switch and the induction switch connected to the same end of the device under test are controlled by the same control signal and are turned on or off at the same time.

[0007] For two adjacent devices under test, the middle switch connected to one of the devices under test is set as the first switch; the middle switch connected to the other device under test is set as the second switch; the first switches are connected to the same first control signal; the second switches are connected to the same second control signal; the first control signal and the second control signal are complementary signals, which are used to control the on-off state of the switches.

[0008] The second switch is connected to the same control signal output terminal as the first switch after passing through an inverter, so that the first control signal and the second control signal are outputted using the same control signal output terminal.

[0009] The switch is a PMOS tube, an NMOS tube or a transmission gate.

[0010] Another aspect of the present invention provides a high-density addressable test chip, comprising an array of devices to be tested, a switch circuit, an addressing circuit, a counter and a plurality of pads; the switch circuit is implemented by the switch circuit for the addressable test chip described in the first aspect of the present invention; the array of devices to be tested is formed by a plurality of devices to be tested, and the specified devices to be tested are selected to be connected to the test path through the on-off state of the switch in the switch circuit; the output end of the addressing circuit is connected to the control end of the switch circuit, and is used to generate a control signal according to an address signal and then provide it to the switch circuit, thereby controlling the on-off of the switch in the switch circuit; the plurality of pads include a power access pad, a clock signal pad, a reset signal pad and a plurality of test signal pads; the power access pad is used to supply power to the counter, the addressing circuit and the switch circuit; the test signal pads include an excitation pad and an induction pad; the input end of the counter is connected to the clock signal pad and the reset signal pad, and the output end of the counter is connected to the input end of the addressing circuit; the counter is used to provide an address signal to the addressing circuit, and directly provide the control signal to the switch circuit.

[0011] There are more than two DUT arrays, and the control signal is transmitted to the switch circuit connected to the DUT array through the same addressing circuit, so as to simultaneously select the DUTs in different DUT arrays to connect the test paths for parallel testing.

[0012] The device under test array is connected to the test signal pad via the switch circuit connected thereto; different device under test arrays are connected to different test signal pads.

[0013] The addressing circuit is implemented by a two-stage decoder, including a row decoder and a column decoder; the row decoder is used to select a device under test array from a plurality of device under test arrays; the column decoder is used to select a device under test from the device under test array.

[0014] At least two empty address bits are provided in each of the DUT arrays for background leakage current detection, address verification and continuous addressing within the DUT array; the empty address bits refer to the address bits that are provided with switches and the address bits selected by the switch circuits do not have corresponding DUTs placed therein.

[0015] The plurality of pads also include an output signal pad, which is connected to the Q end of the positive edge trigger at the first position in the queue of the counter, and is used for least significant bit address verification.

[0016] The power access pads are provided with at least two pairs, one pair of which is used to independently power the counter, and the other pair is used to power the remaining circuits except the counter. The remaining circuits include the switch circuit and the addressing circuit. Powering the counter separately is more conducive to ensuring the stability of the counter operation and the accuracy of the control signal.

[0017] The counter is an asynchronous counter, including a plurality of positive edge triggers and a plurality of buffers; the number of the positive edge triggers matches the number of address bits required by the addressing circuit; the Qn terminal of each of the positive edge triggers is connected to the D terminal of the positive edge trigger through the buffer; the reset terminal of each of the positive edge triggers is connected to the reset signal pad for low-level reset; the Q terminal of the positive edge trigger is the output terminal, the Q terminal of each of the positive edge triggers is connected to the addressing circuit, and each of the positive edge triggers outputs a one-bit address; the plurality of positive edge triggers are arranged in a continuous queue, the input terminal of the positive edge trigger at the head of the queue is connected to the clock signal pad, and the input terminals of the remaining positive edge triggers are connected to the Qn terminal of the positive edge trigger located one position before it in the queue; the Q terminal and / or Qn terminal of the positive edge trigger at the head of the queue are also connected to the switch circuit for providing a control signal for the intermediate switch.

[0018] The Q and Qn terminals of the positive edge trigger at the first position in the queue are also connected to the switch circuit for providing a control signal for the intermediate switch, specifically: the Qn terminal of the positive edge trigger at the first position in the queue is also connected to the first switch in the switch circuit for providing the first control signal, and the Q terminal of the positive edge trigger at the first position in the queue is also connected to the second switch in the switch circuit for providing the second control signal.

[0019] Compared with the prior art, the main beneficial effects of the present invention are:

[0020] 1. The switch circuit for the addressable test chip of the present invention not only adopts the Kelvin connection of two excitation ports and two sensing ports to accurately measure the electrical characteristics of the selected device under test, but also introduces a set of switch circuits at the sensing port by setting the intermediate switch between the device under test and the sensing switch shared by the device under test and the adjacent device under test. When measuring the selected device, only one end of the sensing end connected to the selected device is turned on, and the other end is turned off. The winding resistance error introduced by the shared switch is solved, the accuracy of the shared circuit in the small resistance measurement application is optimized, and a limitation of the current application scenario of the addressable test chip is broken through.

[0021] 2. The high-density addressable test chip of the present invention has corresponding advantages because it has the switch circuit for the addressable test chip of the present invention, and the number of devices to be tested in parallel can be increased by increasing the number of test signal pads, thereby enabling rapid testing. In small resistance measurements, high test accuracy and high test speed can be achieved simultaneously, further improving the company's test work efficiency and providing more accurate data for subsequent process and design optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the working principle of the shared switch circuit affected by the winding resistance in the first embodiment of the present invention.

[0023] Figure 2 Schematic diagram of error analysis affected by winding resistance in Embodiment 1 of the present invention.

[0024] Figure 3 This is a schematic diagram of a switch circuit according to a second embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram of the working principle of the high-density addressable test chip according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0026] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings. In the drawings, parts with the same structure or function are marked with the same reference numerals, and for the sake of clarity, not all parts shown are marked with the corresponding reference numerals in all drawings when necessary.

[0027] Embodiment 1

[0028] like Figure 1 As shown in Figure 1, two adjacent DUTs share switching circuits to improve density. Figure 1Among them, ForcePin1 and ForcePin12 are excitation pads, which are used to form an excitation circuit path and measure the path current at ForcePin1 and ForcePin2. SensePin1 and SensePin2 are induction pads, which are used to form an induction circuit path and measure the voltage at both ends of the device under test at SensePin1 and SensePin2. There are four switches at both ends of each device under test (DUT1, DUT2, DUT3, DUT4, DUT5 for example), which are respectively marked as Q1, Q2, Q3, and Q4 and connected to the excitation pad ForcePin1, the induction pad SensePin1, the excitation pad ForcePin2, and the induction pad SensePin2. The device under test is selected only when the four sets of switches at both ends of the device under test are turned on. When each device under test is selected for measurement through control signals COL1, COL2, COL3, COL4, COL5, and COL6, the corresponding switch control signal state examples are shown in Table 1 below.

[0029] Table 1. Control signal status table

[0030] Selected DUT COL1 COL2 COL3 COL4 COL5 COL6 DUT1 1 1 0 0 0 0 DUT2 0 1 1 0 0 0 DUT3 0 0 1 1 0 0 DUT4 0 0 0 1 1 0 DUT5 0 0 0 0 1 1

[0031] Figure 1 Although the shared switch circuit in the 4-pin Kelvin measurement method can be used to improve the measurement accuracy, there is winding resistance in the wiring from the switch to the device under test. Figure 1 As shown in the figure, the measurement situation is analyzed by taking DUT3 as an example. Figure 2 As shown, since switches Q1 and Q2 are shared switches with the device under test DUT2, the corresponding winding resistors R12 and R22 are also introduced into the measurement path; since switches Q3 and Q4 are shared switches with the device under test DUT4, the winding resistors R32 and R42 are also introduced into the measurement path. Without considering the measurement error, the true resistance value of the device under test DUT3 can be obtained by the following formula: Due to the existence of winding resistance, the actual resistance value of the device under test DUT3 should be derived and calculated using the following formula.

[0032]

[0033]

[0034]

[0035]

[0036] From the above analysis, it can be seen that the actual measured value is larger than the true value due to the introduction of the winding resistance of the shared switch circuit. If the resistance of the device under test is thousands of times greater than the winding resistance of the switch circuit, the error introduced by the switch circuit can be ignored; however, if the resistance of the device under test is of the same order of magnitude as or smaller than the winding resistance of the switch circuit, the error introduced by the switch circuit cannot be ignored, which has a great impact on the accuracy of the measurement results.

[0037] Embodiment 2

[0038] In order to solve the problem that the shared switch circuit in the first embodiment generates errors due to the introduced winding resistance, the second embodiment is provided as follows: Figure 3 The switch circuit for the addressable test chip shown includes several devices under test and several switches, which can select the specified device under test to connect the test path by controlling the on-off state of the switch. In this embodiment, several devices under test are taken as DUT1, DUT2, DUT3, DUT4, and DUT5. In actual application, the number of devices under test is set accordingly according to the actual circuit design and test requirements and is not limited. Several switches in this embodiment all use PMOS tubes, and in some implementations, switches use NMOS tubes or transmission gates and other switches, which can be implemented without limitation. Four switches are set at both ends of each device under test, denoted as Q1, Q2, Q3, and Q4, wherein switches Q1 and Q2 are respectively connected to one end of the device under test, and switches Q3 and Q4 are respectively connected to the other end of the device under test; the device under test is connected to the excitation pads ForcePin1 and ForcePin2 through switches Q1 and Q3 as excitation switches, respectively, for forming an excitation circuit path; the device under test is connected to the sensing pads SensePin1 and SensePin2 through switches Q2 and Q4 as sensing switches, respectively, for forming a sensing circuit path. Switches Q1 and Q2 are connected to the same control signal, and switches Q3 and Q4 are connected to the same control signal. The control signal controls the two switches connected to the same end of the device under test to be turned on or off at the same time.

[0039] Two switches are shared between adjacent devices under test, that is, switches Q1 and Q2 are shared between two adjacent devices under test, or switches Q3 and Q4 are shared; Figure 3 As shown in the figure, the switch Q1 and switch Q2 connected to one end of DUT2 are shared with the adjacent DUT3 on one side, and the switch Q3 and switch Q4 connected to the other end of DUT2 are shared with the adjacent DUT1 on the other side. In this embodiment, an intermediate switch is connected between the device under test and the inductive switch shared by it and the adjacent device under test; for two adjacent devices under test, the intermediate switch connected to one of the devices under test is set as the first switch; and the intermediate switch connected to the other device under test is set as the second switch. Figure 3As shown, two adjacent devices under test DUT2 and DUT3 share the sensing switch Q2, and two adjacent devices under test DUT3 and DUT4 share the sensing switch Q4; a first switch denoted as Q21 is connected between DUT3 and switch Q2, and a second switch denoted as Q22 is connected between DUT2 and switch Q2; a first switch denoted as Q41 is connected between DUT3 and switch Q4, and a second switch denoted as Q42 is connected between DUT4 and switch Q4.

[0040] In this embodiment, a group of switch circuits are introduced at the SensePin (sensing pad) end, and the control signals of the first switch and the second switch in the group of switch circuits are respectively the complementary first control signal and the second control signal, which are respectively recorded as / CON and CON. The Drain (drain) ends of the first switch and the second switch are simultaneously connected to the Source (source) end of the original SensePin switch circuit, the Source end of the first switch is connected to a device under test of the original shared SensePin switch circuit, and the Source end of the second switch is connected to another device under test of the original shared SensePin switch circuit. In this embodiment, all the first switches (example switches Q21 and Q41) are connected to the same control signal / CON, and all the second switches (example switches Q22 and Q42) are connected to the same control signal CON. In this embodiment, the second switch is connected to the same control signal output end with the first switch through an inverter, so that the first control signal / CON and the second control signal CON are output using the same control signal output end. Compared with the shared circuit design affected by the winding resistance, the switch circuit of this embodiment only needs to add an additional control signal after adding switches Q21, Q22, Q41 and Q42. When each device under test of the addressable test chip switch circuit of this embodiment is selected for measurement through control signals COL1, COL2, COL3, COL4, COL5, COL6, CON and / CON, the corresponding switch control signal state is shown in Table 2 below. When measuring the selected device under test, only one end of the SensePin terminal connected to the selected device under test is turned on while the other end is turned off. In addition, since CON and / CON are complementary control signals, only the state of CON is listed in Table 2.

[0041] Table 2. Control signal status table

[0042] Selected DUT COL1 COL2 COL3 COL4 COL5 COL6 CON DUT1 1 1 0 0 0 0 0 DUT2 0 1 1 0 0 0 1 DUT3 0 0 1 1 0 0 0 DUT4 0 0 0 1 1 0 1 DUT5 0 0 0 0 1 1 0

[0043] For example, the device under test DUT3 is selected for measurement. Since Q22 is turned off, is infinite because Q42 is off. is infinite, so the measured resistance value can be obtained by the following formula:

[0044]

[0045] From the above analysis, it can be seen that the switch circuit for addressable test chip in this embodiment solves the winding resistance error introduced by the shared switch, which is beneficial to significantly improve the measurement accuracy of the test chip using the switch circuit.

[0046] Embodiment 3

[0047] This embodiment provides an example of a high-density addressable chip. Figure 4 As shown, it includes an array of devices to be tested, a switch circuit, an addressing circuit, a counter and several pads. The switch circuit example adopts the switch circuit of the addressable test chip of the second embodiment to realize. The array of devices to be tested is formed by several devices to be tested, and the specified device to be tested is selected to connect the test path through the on-off of the switch in the switch circuit. The output end of the addressing circuit is connected to the control end of the switch circuit, which is used to generate a control signal according to the address signal and then provide it to the switch circuit, thereby controlling the on-off of the switch in the switch circuit. Several pads include power access pads, clock signal pads, reset signal pads and several test signal pads; the power access pads are used to supply power to the counter, the addressing circuit and the switch circuit; the test signal pads include excitation pads and induction pads. The input end of the counter is connected to the clock signal pad and the reset signal pad, and the output end of the counter is connected to the input end of the addressing circuit. The counter is used to provide an address signal to the addressing circuit and directly provide a control signal to the switch in the switch circuit.

[0048] In this embodiment, the counter of the example adopts an asynchronous counter, including several positive edge triggers and several buffers, and the number of positive edge triggers matches the number of address bits required by the addressing circuit. The Qn terminal of each positive edge trigger is connected to the D terminal through the buffer; the reset terminal of each positive edge trigger is connected to the reset signal pad for low level reset; the Q terminal of each positive edge trigger is an output terminal, connected to the addressing circuit, and each positive edge trigger outputs a bit address; several positive edge triggers are in a continuous queue, the input terminal of the positive edge trigger at the head of the queue is connected to the clock signal pad, and the input terminals of the remaining positive edge triggers are connected to the Qn terminal of the positive edge trigger at the previous position in the queue. The Qn terminal of the positive edge trigger at the head of the queue is also connected to the first switch in the switch circuit for outputting the first control signal / CON; the Q terminal of the positive edge trigger at the head of the queue is also connected to the second switch in the switch circuit for outputting the second control signal CON. The Q end of the first positive edge trigger is connected to provide a second control signal CON, and the second switches Q22 and Q42 are connected to CON (ie, the second control signal); and the Qn end can provide a first control signal / CON, and the first switches Q21 and Q41 are connected to / CON.

[0049] Reference to the working principles of switching circuits, addressing circuits and counters Figure 4 As shown, the address signals ADDR0~ADDRn generated by the counter are transmitted to the addressing circuit, and then the addressing circuit generates 2 n Bit control signal COL1~COL2 n , to control the on / off state of the switch in the switch circuit. Among them, the address signal ( Figure 4 The address signal ADDR0 outputted from the Q terminal is not shown in the figure), and is also used as the first control signal / CON of the first switch and the second control signal CON of the second switch in the switch circuit for controlling the shared SensePin terminal. In some embodiments, the address signal ADDR0 outputted from the Q terminal of the positive edge trigger at the head of the queue can also be used as the control signal for controlling the shared SensePin terminal in the switch circuit. It only needs to be directly connected to the second switch, but it needs to pass through an inverter before being connected to the first switch. The high-density addressable test chip shares the switch while avoiding the influence of the winding resistance on the measurement accuracy. The measurement accuracy of the test chip is higher, so that the high-density addressable test chip can be applied to the application scenario of small resistance measurement.

[0050] In some embodiments, there are multiple arrays of device under test for example, and a control signal is transmitted to the switch circuit connected to these device under test arrays through the same addressing circuit to simultaneously select the devices under test in each device under test array for connection and parallel testing. The number of device under test arrays can be set according to the actual circuit design and specific application requirements, and can be one, two or more. The number of devices under test in each device under test array can be the same or different, and is not limited. Each device under test array is connected to its own test signal pad through a switch circuit, and the number of parallel tests can be increased by increasing the number of test signal pads according to the specific application scenario. In a better practice of this embodiment, the addressing circuit is implemented by a two-stage decoder, and the addressing circuit includes a row decoder and a column decoder; the row decoder is used to select a device under test array from a number of device under test arrays, and the column decoder is used to select a device under test from the device under test array.

[0051] In this embodiment, at least two empty address bits are set in each array of devices under test, which are used for background leakage current detection, address verification and continuous addressing in the array of devices under test; the empty address bits refer to the address bits with switches, and the corresponding devices under test are not placed in the address bits selected by the switch circuit. In some specific implementations, empty address bits are not set, and they are set accordingly according to specific circuit design and application requirements, and are not limited.

[0052] In this embodiment, the plurality of pads also include an output signal pad, which is connected to the Q end of the positive edge trigger at the first position in the queue of the counter, for least significant bit address verification. The corresponding setting is made according to the specific circuit design and application requirements, and in some implementations, there is no corresponding setting for least significant bit address verification, which is not limited.

[0053] In this embodiment, at least two pairs of power access pads are provided, one pair of which is used to independently power the counter, and the other pair is used to power the remaining circuits (addressing circuit, switch circuit) except the counter. In the example of this embodiment, powering the counter separately is more conducive to ensuring the stability of the counter. In some implementations, there are other designs for power supply combined with specific circuit designs and electrical components, which are not limited.

[0054] Some commonly used English nouns or letters used in the present invention for the sake of clarity are only used for exemplary references rather than restrictive interpretations or specific usages, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters. It should also be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0055] The structure and working principle of the present invention are described in this article using specific examples, and the description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. For ordinary technicians in this technical field, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A switch circuit for an addressable test chip, characterized in that: It includes a plurality of devices under test and a plurality of switches, and can select a designated device under test to connect to a test path by controlling the on and off states of the switches; Two switches are respectively provided at two ends of the device under test, and the two switches connected to the same end of the device under test are: an excitation switch for connecting to an excitation pad, and a sensing switch for connecting to a sensing pad; Two adjacent devices under test share one excitation switch and one induction switch, and the two shared switches are located at the same end of the device under test; An intermediate switch is connected between the device under test and the sensing switch shared by the device under test and an adjacent device under test; for two adjacent devices under test, the device under test is selected to be connected to the sensing switch by controlling the on / off state of the intermediate switch.

2. The switch circuit for an addressable test chip according to claim 1, characterized in that: The excitation switch and the induction switch connected to the same end of the device under test are controlled by the same control signal and are turned on or off at the same time.

3. The switch circuit for an addressable test chip according to claim 1, characterized in that: For two adjacent devices under test, the middle switch connected to one of the devices under test is set as the first switch; the middle switch connected to the other device under test is set as the second switch; the first switches are connected to the same first control signal; the second switches are connected to the same second control signal; the first control signal and the second control signal are complementary signals, which are used to control the on-off state of the switches.

4. The switch circuit for an addressable test chip according to claim 3, characterized in that: The second switch is connected to the same control signal output terminal as the first switch after passing through an inverter, so that the first control signal and the second control signal are outputted using the same control signal output terminal.

5. The switch circuit for an addressable test chip according to any one of claims 1 to 4, characterized in that: The switch is a PMOS tube, an NMOS tube or a transmission gate.

6. High-density addressable test chip, characterized in that: It comprises a device array under test, a switch circuit, an addressing circuit, a counter and a plurality of pads; the switch circuit is implemented by the switch circuit for the addressable test chip according to any one of claims 1 to 5; The DUT array is formed by a plurality of DUTs, and the DUT is selected to be connected to the test path through the on-off state of the switch in the switch circuit; The output end of the addressing circuit is connected to the control end of the switch circuit, and is used to generate a control signal according to the address signal and then provide it to the switch circuit, thereby controlling the on and off of the switch in the switch circuit; The plurality of pads include a power supply access pad, a clock signal pad, a reset signal pad and a plurality of test signal pads; The power access pad is used to supply power to the counter, the addressing circuit and the switching circuit; the test signal pad includes an excitation pad and an induction pad; the input end of the counter is connected to the clock signal pad and the reset signal pad, and the output end of the counter is connected to the input end of the addressing circuit; the counter is used to provide an address signal to the addressing circuit, and directly provide the control signal to the switching circuit.

7. The high-density addressable test chip according to claim 6, characterized in that: There are more than two DUT arrays, and the control signal is transmitted to the switch circuit connected to the DUT array through the same addressing circuit, so as to simultaneously select the DUTs in different DUT arrays to connect the test paths for parallel testing.

8. The high-density addressable test chip according to claim 7, characterized in that: The device under test array is connected to the test signal pad via the switch circuit connected thereto; different device under test arrays are connected to different test signal pads.

9. The high-density addressable test chip according to claim 7, characterized in that: The addressing circuit is implemented by a two-stage decoder, including a row decoder and a column decoder; the row decoder is used to select a device under test array from a plurality of device under test arrays; the column decoder is used to select a device under test from the device under test array.

10. The high-density addressable test chip according to claim 6, characterized in that: At least two empty address bits are provided in each of the DUT arrays for background leakage current detection, address verification and continuous addressing within the DUT array; the empty address bits refer to the address bits that are provided with switches and the address bits selected by the switch circuits do not have corresponding DUTs placed therein.

11. The high-density addressable test chip according to claim 6, characterized in that: The plurality of pads also include an output signal pad, which is connected to the Q end of the positive edge trigger at the first position in the queue of the counter, and is used for least significant bit address verification.

12. The high-density addressable test chip according to claim 6, characterized in that: At least two pairs of power access pads are provided, one pair of which is used to independently supply power to the counter, and the other pair is used to supply power to the remaining circuits except the counter.

13. The high-density addressable test chip according to any one of claims 6 to 12, characterized in that: The counter is an asynchronous counter, comprising a plurality of positive edge triggers and a plurality of buffers; The number of the positive edge triggers matches the number of address bits required by the addressing circuit; the Qn terminal of each positive edge trigger is connected to the D terminal of the positive edge trigger through the buffer; The reset terminal of each positive edge trigger is connected to the reset signal pad for low level reset; The Q end of the positive edge trigger is an output end, the Q end of each edge trigger is connected to the addressing circuit, and each positive edge trigger outputs a one-bit address; The several positive edge triggers are arranged in a continuous queue, the input end of the positive edge trigger at the first position in the queue is connected to the clock signal pad, and the input ends of the remaining positive edge triggers are connected to the Qn end of the positive edge trigger located at the previous position in the queue; the Q end and / or Qn end of the positive edge trigger at the first position in the queue is also connected to the switching circuit for providing a control signal for the intermediate switch.

14. The high-density addressable test chip according to claim 13, characterized in that: The Q and Qn terminals of the positive edge trigger at the first position in the queue are also connected to the switch circuit for providing a control signal for the intermediate switch, specifically: the Qn terminal of the positive edge trigger at the first position in the queue is also connected to the first switch in the switch circuit for providing a first control signal, and the Q terminal of the positive edge trigger at the first position in the queue is also connected to the second switch in the switch circuit for providing a second control signal.

Images