A Reconfigurable Nonlinear Logic Gate Circuit Based on Memristive Cells

Abstract

The present invention proposes a reconfigurable non-linear logic gate circuit based on memristive cells, and its structure includes a first template parameter setting circuit, a second template parameter setting circuit, a third bias quantity parameter setting circuit, a first summing circuit, an absolute value circuit, a second summing circuit, an integrating circuit, and a comparison circuit; wherein, the output end of the first template parameter setting circuit is connected to the first input end of the first summing circuit, the output end of the second template parameter setting circuit is connected to the second input end of the first summing circuit, the output end of the first summing circuit is connected to the input end of the absolute value circuit, the output end of the third bias quantity parameter setting circuit is connected to the input end of the second summing circuit, the output ends of the second summing circuit and the absolute value circuit are jointly connected to the input end of the integrating circuit and one end of the load memristor Mr, the output end of the integrating circuit is connected to the input end of the comparison circuit, and the other end of the load memristor Mr is grounded.

Description

Technical Field

[0001] The present invention relates to a reconfigurable non - linear logic gate circuit based on memristive cells, belonging to the technical field related to memristors. Background Art

[0002] The emergence of memristors brings hope for solving problems such as the impending failure of Moore's Law. The characteristics of memristors, such as non - volatility and nanoscale size, give them great advantages in storage technology, neural networks, etc.

[0003] Traditional cell units are composed of multiple operational amplifiers, which greatly increases the integration area of the circuit, and the constructed circuit can only implement a specific logic function. With the emergence of memristor nanodevices, using memristors in combination with traditional MOS transistors to realize reconfigurable logic circuits has become an important research direction in the development of current microelectronics technology.

[0004] In the prior art, the reconfigurable logic gate circuit uses operational amplifiers and fixed resistors, which not only has a large integration area, but also inevitably encounters time delay. Moreover, the method for realizing the reconfigurable function is relatively complex, that is, the adjustment of parameter values is relatively complex. Summary of the Invention

[0005] The present invention proposes a reconfigurable non - linear logic gate circuit based on memristive cells, aiming to solve the problem that the circuit constructed in the prior art can only implement a specific logic function.

[0006] The technical solution of the present invention: A reconfigurable non - linear logic gate circuit based on memristive cells, whose structure includes a first template parameter setting circuit, a second template parameter setting circuit, a third bias parameter setting circuit, a first summing circuit, an absolute - value circuit, a second summing circuit, an integrating circuit, and a comparing circuit; wherein, the output end of the first template parameter setting circuit is connected to the first input end of the first summing circuit, the output end of the second template parameter setting circuit is connected to the second input end of the first summing circuit, the output end of the first summing circuit is connected to the input end of the absolute - value circuit, the output end of the third bias parameter setting circuit is connected to the input end of the second summing circuit, the output ends of the second summing circuit and the absolute - value circuit are commonly connected to the input end of the integrating circuit and one end of the load memristor Mr, the output end of the integrating circuit is connected to the input end of the comparing circuit, and the other end of the load memristor Mr is grounded.

[0007] Further, the input end of the first template parameter setting circuit is connected to the No. 1 signal input terminal and the No. 2 signal input terminal. The No. 1 signal input terminal and the No. 2 signal input terminal are connected in parallel. A first switch W1 is connected in series on the No. 1 signal input terminal, and a second switch W2 is connected in series on the No. 2 signal input terminal. The input end of the second template parameter setting circuit is connected to the No. 3 signal input terminal and the No. 4 signal input terminal. The No. 3 signal input terminal and the No. 4 signal input terminal are connected in parallel. A third switch W3 is connected in series on the No. 3 signal input terminal, and a fourth switch W4 is connected in series on the No. 4 signal input terminal. The input end of the third bias amount parameter setting circuit is connected to the No. 5 signal input terminal and the No. 6 signal input terminal. The No. 5 signal input terminal and the No. 6 signal input terminal are connected in parallel. A fifth switch W5 is connected in series on the No. 5 signal input terminal, and a sixth switch W6 is connected in series on the No. 6 signal input terminal.

[0008] Further, the first template parameter setting circuit includes a first memristor M1, a second memristor M2, a third memristor M3, a fourth memristor M4, a fifth memristor M5, a first NMOS transistor U1, a second NMOS transistor U2, and a third NMOS transistor U3. The first memristor M1, the second memristor M2, the third memristor M3, the fourth memristor M4, and the fifth memristor M5 form a first memristive bridge. The first NMOS transistor U1, the second NMOS transistor U2, and the third NMOS transistor U3 form a first differential amplifier. The first memristive bridge and the first differential amplifier together form a first memristive bridge synaptic circuit. Among them, the first memristor M1 and the second memristor M2 are connected in series in reverse. The third memristor M3 and the fourth memristor M4 are connected in series in reverse. The positive and negative ends of the fifth memristor M5 are respectively connected to the two gates of the first differential amplifier. The first memristor M1 and the third memristor M3 are connected in series in the same direction. The second memristor M2 and the fourth memristor M4 are connected in series in the same direction. The connection point between the first memristor M1 and the third memristor M3 leads out the signal input end of the first memristive bridge synaptic circuit. The connection point between the second memristor M2 and the fourth memristor M4 is grounded. The signal input end of the first memristive bridge synaptic circuit is the input end of the first template parameter setting circuit.

[0009] Further, the second template parameter setting circuit includes a sixth memristor M6, a seventh memristor M7, an eighth memristor M8, a ninth memristor M9, a tenth memristor M10, a fourth NMOS transistor U4, a fifth NMOS transistor U5, and a sixth NMOS transistor U6; the sixth memristor M6, the seventh memristor M7, the eighth memristor M8, the ninth memristor M9, and the tenth memristor M10 form a second memristor bridge; the fourth NMOS transistor U4, the fifth NMOS transistor U5, and the sixth NMOS transistor U6 form a second differential amplifier; the second memristor bridge and the second differential amplifier together form a second memristor bridge synaptic circuit; wherein, the sixth memristor M6 and the seventh memristor M7 are connected in series in anti-phase, the eighth memristor M8 and the ninth memristor M9 are connected in series in anti-phase, the positive and negative terminals of the tenth memristor M10 are respectively connected to the two gates of the second differential amplifier, the sixth memristor M6 and the eighth memristor M8 are connected in series in the same direction, the seventh memristor M7 and the ninth memristor M9 are connected in series in the same direction, the connection between the sixth memristor M6 and the eighth memristor M8 leads out the signal input terminal of the second memristor bridge synaptic circuit, and the connection between the seventh memristor M7 and the ninth memristor M9 is grounded; the signal input terminal of the second memristor bridge synaptic circuit is the input terminal of the second template parameter setting circuit.

[0010] Further, the third bias amount parameter setting circuit includes an eleventh memristor M11, a twelfth memristor M12, a thirteenth memristor M13, a fourteenth memristor M14, a fifteenth memristor M15, a seventh NMOS transistor U7, an eighth NMOS transistor U8, and a ninth NMOS transistor U9; the eleventh memristor M11, the twelfth memristor M12, the thirteenth memristor M13, the fourteenth memristor M14, and the fifteenth memristor M15 form a third memristor bridge; the seventh NMOS transistor U7, the eighth NMOS transistor U8, and the ninth NMOS transistor U9 form a third differential amplifier; the third memristor bridge and the third differential amplifier together form a third memristor bridge synaptic circuit; wherein, the eleventh memristor M11 and the twelfth memristor M12 are connected in series in anti-phase, the thirteenth memristor M13 and the fourteenth memristor M14 are connected in series in anti-phase, the positive and negative terminals of the fifteenth memristor M15 are respectively connected to the two gates of the third differential amplifier, the eleventh memristor M11 and the thirteenth memristor M13 are connected in series in the same direction, the twelfth memristor M12 and the fourteenth memristor M14 are connected in series in the same direction, the connection between the eleventh memristor M11 and the thirteenth memristor M13 leads out the signal input terminal of the third memristor bridge synaptic circuit, and the connection between the twelfth memristor M12 and the fourteenth memristor M14 is grounded; the signal input terminal of the third memristor bridge synaptic circuit is the input terminal of the third bias amount parameter setting circuit.

[0011] Further, the initial resistance values of the first memristor M1 and the fourth memristor M4 are equal, the initial resistance values of the second memristor M2, the third memristor M3, and the fifth memristor M5 are equal, and the initial resistance values of the first memristor M1 and the fourth memristor M4 are greater than the initial resistance values of the second memristor M2, the third memristor M3, and the fifth memristor M5.

[0012] Further, the initial resistance values of the sixth memristor M6 and the ninth memristor M9 are equal, the initial resistance values of the seventh memristor M7, the eighth memristor M8, and the tenth memristor M10 are equal, and the initial resistance values of the sixth memristor M6 and the ninth memristor M9 are greater than the initial resistance values of the seventh memristor M7, the eighth memristor M8, and the tenth memristor M10.

[0013] Further, the initial resistance values of the eleventh memristor M11 and the fourteenth memristor M14 are equal, the initial resistance values of the twelfth memristor M12, the thirteenth memristor M13, and the fifteenth memristor M15 are equal, and the initial resistance values of the eleventh memristor M11 and the fourteenth memristor M14 are greater than the initial resistance values of the twelfth memristor M12, the thirteenth memristor M13, and the fifteenth memristor M15.

[0014] Further, the first summing circuit includes a tenth PMOS transistor U10, an eleventh PMOS transistor U11, a twelfth PMOS transistor U12, and a thirteenth PMOS transistor U13; wherein, the sources of the twelfth PMOS transistor U12 and the thirteenth PMOS transistor U13 are respectively and correspondingly connected to the drains of the tenth PMOS transistor U10 and the eleventh PMOS transistor U11; the sources of the tenth PMOS transistor U10 and the eleventh PMOS transistor U11 are connected to the power supply VDD; the gates of the tenth PMOS transistor U10 and the eleventh PMOS transistor U11 are interconnected; and the gates of the twelfth PMOS transistor U12 and the thirteenth PMOS transistor U13 are interconnected.

[0015] Further, the second summing circuit includes a fourteenth PMOS transistor U14, a fifteenth PMOS transistor U15, a sixteenth PMOS transistor U16, and a seventeenth PMOS transistor U17; wherein, the drains of the fourteenth PMOS transistor U14 and the fifteenth PMOS transistor U15 are respectively and correspondingly connected to the sources of the sixteenth PMOS transistor U16 and the seventeenth PMOS transistor U17; the sources of the fourteenth PMOS transistor U14 and the fifteenth PMOS transistor U15 are connected to the power supply VDD; the gates of the fourteenth PMOS transistor U14 and the fifteenth PMOS transistor U15 are interconnected; and the gates of the sixteenth PMOS transistor U16 and the seventeenth PMOS transistor U17 are interconnected.

[0016] Further, the absolute value circuit includes a first operational amplifier J1, a second operational amplifier J2, a first diode D1, a second diode D2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. Among them, the positive electrode of the first operational amplifier J1 is connected to the ground, and the negative electrode of the first operational amplifier J1 is connected to the negative electrode of the first diode D1, the first resistor R1, and the second resistor R2. The positive electrode of the first diode D1 is connected to the negative electrode of the second diode D2 and the output terminal of the first operational amplifier J1. The positive electrode of the second diode D2 is connected to the second resistor R2 and the third resistor R3. The third resistor R3 is connected to the negative electrode of the second operational amplifier J2, the fourth resistor R4, and the fifth resistor R5. The fourth resistor R4 is connected to the output terminal of the second operational amplifier J2. The positive electrode of the second operational amplifier J2 is connected to the ground. The first resistor R1 is connected to the fifth resistor R5.

[0017] Further, the integration circuit includes an eighteenth NMOS transistor U18, a nineteenth NMOS transistor U19, and a capacitor C1. Among them, the source electrode of the eighteenth NMOS transistor U18 is connected to the drain electrode of the nineteenth NMOS transistor U19. The drain electrode of the eighteenth NMOS transistor U18 is connected to the source electrode of the nineteenth NMOS transistor U19. The drain electrode of the eighteenth NMOS transistor U18 is connected to the capacitor C1. The capacitor C1 is connected to the power supply VSS. The gate electrodes of the eighteenth NMOS transistor U18 and the nineteenth NMOS transistor U19 are connected to the power supply VDD.

[0018] Further, the comparison circuit includes a twentieth PMOS transistor U20, a twenty-first PMOS transistor U21, a sixth resistor Ri1, a seventh resistor Ri2, an eighth resistor Ri3, a triode Q1, and a ninth resistor Rt. Among them, the source electrodes of the twentieth PMOS transistor U20 and the twenty-first PMOS transistor U21 are connected. One end of the eighth resistor Ri3 is connected to the source electrode of the twenty-first PMOS transistor U21, and the other end of the eighth resistor Ri3 is connected to the power supply VDD1. The gate electrode of the twentieth PMOS transistor U20 is connected to the ground. The drain electrode of the twentieth PMOS transistor U20 is connected to the sixth resistor Ri1. The drain electrode of the twenty-first PMOS transistor U21 is connected to the seventh resistor Ri2 and the base electrode of the triode Q1. The sixth resistor Ri1 and the seventh resistor Ri2 are connected in series and then grounded. The emitter electrode of the triode Q1 is connected to the ground. The collector electrode of the triode Q1 is connected to the ninth resistor Rt. The ninth resistor Rt is connected to the power supply Vt.

[0019] Further, a method for performing logic function reconstruction by using the reconfigurable non-linear logic gate circuit based on memristive cells as claimed in claim 3, characterized in that the method comprises the following steps:

[0020] 1) Set a reference voltage in the comparison circuit;

[0021] 2) Use the first template parameter setting circuit to set the first template parameter b1 as the weight of the first template parameter;

[0022] 3) Use the second template parameter setting circuit to set the second template parameter b2 as the weight of the second template parameter;

[0023] 4) Use the third bias parameter setting circuit to set the bias parameter as the bias parameter c;

[0024] 5) Input the second signal V2, the fourth signal V4, and the sixth signal V6 into the first template parameter setting circuit, the second template parameter setting circuit, and the third bias parameter setting circuit respectively; Set the second signal V2 and the fourth signal V4 to high level or low level according to the needs of the implemented logic function;

[0025] 6) The second signal V2, the fourth signal V4, and the sixth signal V6 respectively form voltage drops on the fifth memristor M5, the tenth memristor M10, and the fifteenth memristor M15. The sum of the products of the voltage drops on the fifth memristor M5 and the tenth memristor M10 and the first template parameter b1 and the second template parameter b2 is sent to the absolute value circuit to obtain the absolute value and then output. The bias parameter c is multiplied by the voltage drop on the fifteenth memristor M15. The output of the absolute value circuit is then converged and added to the product of the bias parameter c and the voltage drop on the fifteenth memristor M15, and then integrated by the integration circuit to form an integrated output voltage. The integrated output voltage obtained by integrating the integration circuit is compared with the reference voltage set in the comparison circuit; If the integrated output voltage obtained by integrating the integration circuit is less than the reference voltage, the output terminal voltage Vout of the entire memristor cell-based reconfigurable non-linear logic gate circuit is defined as low level, and the corresponding output terminal logic is "0"; If the output voltage obtained by integrating the integration circuit is greater than the reference voltage, the output terminal voltage Vout of the entire memristor cell-based reconfigurable non-linear logic gate circuit is defined as high level, and the corresponding output terminal logic is "1".

[0026] Further, the sixth signal V6 is set to 1v, and the reference voltage set in the comparison circuit is set to 0v; Then the condition for the output terminal voltage of the entire memristor cell-based reconfigurable non-linear logic gate circuit to be high level is shown as follows:

[0027] |b1V2 + b2V4| + c > 0;

[0028] The condition for the output terminal voltage of the entire memristor cell-based reconfigurable non-linear logic gate circuit to be low level is shown as follows:

[0029] |b1V2 + b2V4| + c < 0;

[0030] The second signal V2 and the fourth signal V4 are respectively used as the input voltages of the first template parameter setting circuit and the second template parameter setting circuit. When the input voltage is defined as 1V, it corresponds to the logic "1"; when the input voltage is -1V, it corresponds to the logic "0".

[0031] At this time, the conditions for implementing the exclusive - OR circuit are: the conditions for implementing the exclusive - OR logic are: |b1 - b2|+c>0, |b1 + b2|+c<0; the conditions for implementing the equivalence logic are: |b1 - b2|+c<0, |b1 + b2|+c>0.

[0032] Furthermore, the first template parameter setting circuit implements the first template parameter b1, the second template parameter setting circuit implements the second template parameter b2, and the third bias parameter setting circuit implements the bias parameter c. The first template parameter b1, the second template parameter b2, and the third bias parameter c all include two parts: magnitude and direction.

[0033] For the setting of the first template parameter b1, it specifically includes: in the first template parameter setting circuit, a pulse signal is input to the first template parameter setting circuit from the signal input terminal of the first template parameter setting circuit. By controlling the length of the input pulse signal, the current direction and the resistance value of the fifth memristor M5 are changed. When the input pulse signal ends, if the current flowing through the fifth memristor M5 is positive, then the first template parameter b1 is positive; if the current flowing through the fifth memristor M5 is negative, then the first template parameter b1 is negative. At this time, the resistance value of the fifth memristor M5 is the magnitude of the first template parameter b1.

[0034] For the setting of the second template parameter b2, it specifically includes: in the second template parameter setting circuit, a pulse signal is input to the second template parameter setting circuit from the signal input terminal of the second template parameter setting circuit. By controlling the length of the input pulse signal, the current direction and the resistance value of the tenth memristor M10 are changed. When the input pulse signal ends, if the current flowing through the tenth memristor M10 is positive, then the second template parameter b2 is positive; if the current flowing through the tenth memristor M10 is negative, then the second template parameter b2 is negative. At this time, the resistance value of the tenth memristor M10 is the magnitude of the second template parameter b2.

[0035] For the setting of the offset parameter c, it specifically includes: in the third offset parameter setting circuit, a pulse signal is input into the third offset parameter setting circuit from the signal input terminal of the third offset parameter setting circuit. By controlling the length of the input pulse signal, the current direction flowing through the fifteenth memristor M15 and the resistance value of the fifteenth memristor M15 are changed. When the input pulse signal ends, if the current flowing through the fifteenth memristor M15 is positive, the offset parameter c is positive; if the current flowing through the fifteenth memristor M15 is negative, the offset parameter c is negative. At this time, the resistance value of the fifteenth memristor M15 is the magnitude of the offset parameter c.

[0036] A reconfigurable non - linear logic gate circuit based on memristive cells according to the present invention has the following advantages compared with the existing cell unit for realizing reconfigurable logic gate technology:

[0037] 1) Few circuit elements are selected. The present invention only uses two operational amplifiers and multiple nano - devices, greatly reducing the integration area of the circuit and having a small size;

[0038] 2) The logic function can be changed only by changing the duration of the input pulse, without changing any device and its parameter values inside the internal circuit, realizing the reconfiguration of the logic circuit, and the operation is simple and easy to implement;

[0039] 3) A single cell can be used to implement a non - linear logic circuit. Description of the Drawings

[0040] Fig. Figure 1 is the overall structure block diagram of the reconfigurable non - linear logic gate circuit based on memristive cells.

[0041] Fig. Figure 2 is the complete circuit diagram of a specific application embodiment of the reconfigurable non - linear logic gate based on memristive cells.

[0042] Fig. Figure 3 is the waveform diagram of the memristance change corresponding to each parameter value.

[0043] Fig. Figure 4 is the waveform diagram of the memristor current change.

[0044] Fig. Figure 5 is the schematic diagram of the input - output waveform of the exclusive - OR gate in the embodiment.

[0045] Fig. Figure 6 is the schematic diagram of the input - output waveform of the equivalence gate in the embodiment. Detailed Embodiments

[0046] A reconfigurable non-linear logic gate circuit based on memristive cells, the structure of which includes a first template parameter setting circuit, a second template parameter setting circuit, a third bias parameter setting circuit, a first summing circuit, an absolute value circuit, a second summing circuit, an integration circuit, and a comparison circuit; wherein, the output terminal of the first template parameter setting circuit is connected to the first input terminal of the first summing circuit, the output terminal of the second template parameter setting circuit is connected to the second input terminal of the first summing circuit, the output terminal of the first summing circuit is connected to the input terminal of the absolute value circuit, the output terminal of the third bias parameter setting circuit is connected to the input terminal of the second summing circuit, the output terminals of the second summing circuit and the absolute value circuit are commonly connected to the input terminal of the integration circuit and one end of the load memristor Mr, the output terminal of the integration circuit is connected to the input terminal of the comparison circuit, and the other end of the load memristor Mr is grounded.

[0047] Refer to the appendix Figure 2 , the input terminal of the first template parameter setting circuit is connected to the No. 1 signal input terminal and the No. 2 signal input terminal, the No. 1 signal input terminal and the No. 2 signal input terminal are in parallel, a first switch W1 is connected in series on the No. 1 signal input terminal, and a second switch W2 is connected in series on the No. 2 signal input terminal; the input terminal of the second template parameter setting circuit is connected to the No. 3 signal input terminal and the No. 4 signal input terminal, the No. 3 signal input terminal and the No. 4 signal input terminal are in parallel, a third switch W3 is connected in series on the No. 3 signal input terminal, and a fourth switch W4 is connected in series on the No. 4 signal input terminal; the input terminal of the third bias parameter setting circuit is connected to the No. 5 signal input terminal and the No. 6 signal input terminal, the No. 5 signal input terminal and the No. 6 signal input terminal are in parallel, a fifth switch W5 is connected in series on the No. 5 signal input terminal, and a sixth switch W6 is connected in series on the No. 6 signal input terminal.

[0048] The first template parameter setting circuit, the second template parameter setting circuit, and the third bias parameter setting circuit are all the same parameter setting circuits. Each parameter setting circuit includes five memristors and three MOS transistors. The five memristors form a memristor bridge, and the three MOS transistors form a differential amplifier; the five memristors and the three MOS transistors together form a memristor bridge synaptic circuit, and the signal input terminal of the memristor bridge synaptic circuit is connected to the memristor bridge.

[0049] The first summing circuit and the second summing circuit are both the same summing circuits. Each summing circuit is implemented by a current source circuit composed of four MOS transistors.

[0050] Refer to the appendix Figure 2, the first template parameter setting circuit includes a first memristor M1, a second memristor M2, a third memristor M3, a fourth memristor M4, a fifth memristor M5, a first NMOS transistor U1, a second NMOS transistor U2, and a third NMOS transistor U3; the first memristor M1, the second memristor M2, the third memristor M3, the fourth memristor M4, and the fifth memristor M5 form a first memristive bridge; the first NMOS transistor U1, the second NMOS transistor U2, and the third NMOS transistor U3 form a first differential amplifier; the first memristive bridge and the first differential amplifier together form a first memristive bridge synaptic circuit; wherein, the first memristor M1 and the second memristor M2 are connected in series in reverse, the third memristor M3 and the fourth memristor M4 are connected in series in reverse, the positive and negative terminals of the fifth memristor M5 are respectively connected to the two gates of the first differential amplifier, the first memristor M1 and the third memristor M3 are connected in series in the same direction, the second memristor M2 and the fourth memristor M4 are connected in series in the same direction, the connection between the first memristor M1 and the third memristor M3 leads to the signal input terminal of the first memristive bridge synaptic circuit, and the connection between the second memristor M2 and the fourth memristor M4 is grounded; the signal input terminal of the first memristive bridge synaptic circuit is the input terminal of the first template parameter setting circuit.

[0051] See the appendix Figure 2 , the second template parameter setting circuit includes a sixth memristor M6, a seventh memristor M7, an eighth memristor M8, a ninth memristor M9, a tenth memristor M10, a fourth NMOS transistor U4, a fifth NMOS transistor U5, and a sixth NMOS transistor U6; the sixth memristor M6, the seventh memristor M7, the eighth memristor M8, the ninth memristor M9, and the tenth memristor M10 form a second memristive bridge; the fourth NMOS transistor U4, the fifth NMOS transistor U5, and the sixth NMOS transistor U6 form a second differential amplifier; the second memristive bridge and the second differential amplifier together form a second memristive bridge synaptic circuit; wherein, the sixth memristor M6 and the seventh memristor M7 are connected in series in reverse, the eighth memristor M8 and the ninth memristor M9 are connected in series in reverse, the positive and negative terminals of the tenth memristor M10 are respectively connected to the two gates of the second differential amplifier, the sixth memristor M6 and the eighth memristor M8 are connected in series in the same direction, the seventh memristor M7 and the ninth memristor M9 are connected in series in the same direction, the connection between the sixth memristor M6 and the eighth memristor M8 leads to the signal input terminal of the second memristive bridge synaptic circuit, and the connection between the seventh memristor M7 and the ninth memristor M9 is grounded; the signal input terminal of the second memristive bridge synaptic circuit is the input terminal of the second template parameter setting circuit.

[0052] See the appendix Figure 2, the third bias parameter setting circuit includes an eleventh memristor M11, a twelfth memristor M12, a thirteenth memristor M13, a fourteenth memristor M14, a fifteenth memristor M15, a seventh NMOS transistor U7, an eighth NMOS transistor U8, and a ninth NMOS transistor U9; the eleventh memristor M11, the twelfth memristor M12, the thirteenth memristor M13, the fourteenth memristor M14, and the fifteenth memristor M15 form a third memristive bridge; the seventh NMOS transistor U7, the eighth NMOS transistor U8, and the ninth NMOS transistor U9 form a third differential amplifier; the third memristive bridge and the third differential amplifier together form a third memristive bridge synaptic circuit; wherein, the eleventh memristor M11 and the twelfth memristor M12 are connected in series in antiphase, the thirteenth memristor M13 and the fourteenth memristor M14 are connected in series in antiphase, the positive and negative terminals of the fifteenth memristor M15 are respectively connected to the two gates of the third differential amplifier, the eleventh memristor M11 and the thirteenth memristor M13 are connected in series in the same direction, the twelfth memristor M12 and the fourteenth memristor M14 are connected in series in the same direction, the connection point of the eleventh memristor M11 and the thirteenth memristor M13 leads out the signal input terminal of the third memristive bridge synaptic circuit, and the connection point of the twelfth memristor M12 and the fourteenth memristor M14 is grounded; the signal input terminal of the third memristive bridge synaptic circuit is the input terminal of the third bias parameter setting circuit.

[0053] The initial resistance values of the first memristor M1 and the fourth memristor M4 are equal, the initial resistance values of the second memristor M2, the third memristor M3, and the fifth memristor M5 are equal, and the initial resistance values of the first memristor M1 and the fourth memristor M4 are greater than the initial resistance values of the second memristor M2, the third memristor M3, and the fifth memristor M5; the initial resistance values of the first memristor M1 and the fourth memristor M4 are preferably 15 kΩ, and the initial resistance values of the second memristor M2, the third memristor M3, and the fifth memristor M5 are preferably 1 kΩ.

[0054] The initial resistance values of the sixth memristor M6 and the ninth memristor M9 are equal, the initial resistance values of the seventh memristor M7, the eighth memristor M8, and the tenth memristor M10 are equal, and the initial resistance values of the sixth memristor M6 and the ninth memristor M9 are greater than the initial resistance values of the seventh memristor M7, the eighth memristor M8, and the tenth memristor M10; the initial resistance values of the sixth memristor M6 and the ninth memristor M9 are preferably 15 kΩ, and the initial resistance values of the seventh memristor M7, the eighth memristor M8, and the tenth memristor M10 are preferably 1 kΩ.

[0055] The initial resistance values of the eleventh memristor M11 and the fourteenth memristor M14 are equal, and the initial resistance values of the twelfth memristor M12, the thirteenth memristor M13, and the fifteenth memristor M15 are equal. The initial resistance values of the eleventh memristor M11 and the fourteenth memristor M14 are greater than those of the twelfth memristor M12, the thirteenth memristor M13, and the fifteenth memristor M15. The initial resistance values of the eleventh memristor M11 and the fourteenth memristor M14 are preferably 15 kΩ, and the initial resistance values of the twelfth memristor M12, the thirteenth memristor M13, and the fifteenth memristor M15 are preferably 1 kΩ.

[0056] See the attached Figure 2 , the first summing circuit includes the tenth PMOS transistor U10, the eleventh PMOS transistor U11, the twelfth PMOS transistor U12, and the thirteenth PMOS transistor U13. Among them, the sources of the twelfth PMOS transistor U12 and the thirteenth PMOS transistor U13 are respectively connected to the drains of the tenth PMOS transistor U10 and the eleventh PMOS transistor U11 in correspondence; the sources of the tenth PMOS transistor U10 and the eleventh PMOS transistor U11 are connected to the power supply VDD; the gates of the tenth PMOS transistor U10 and the eleventh PMOS transistor U11 are interconnected; the gates of the twelfth PMOS transistor U12 and the thirteenth PMOS transistor U13 are interconnected.

[0057] See the attached Figure 2 , the second summing circuit includes the fourteenth PMOS transistor U14, the fifteenth PMOS transistor U15, the sixteenth PMOS transistor U16, and the seventeenth PMOS transistor U17. Among them, the drains of the fourteenth PMOS transistor U14 and the fifteenth PMOS transistor U15 are respectively connected to the sources of the sixteenth PMOS transistor U16 and the seventeenth PMOS transistor U17 in correspondence; the sources of the fourteenth PMOS transistor U14 and the fifteenth PMOS transistor U15 are connected to the power supply VDD; the gates of the fourteenth PMOS transistor U14 and the fifteenth PMOS transistor U15 are interconnected; the gates of the sixteenth PMOS transistor U16 and the seventeenth PMOS transistor U17 are interconnected.

[0058] The absolute value circuit includes a first operational amplifier J1, a second operational amplifier J2, a first diode D1, a second diode D2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. Among them, the positive electrode of the first operational amplifier J1 is connected to the ground, and the negative electrode of the first operational amplifier J1 is connected to the negative electrode of the first diode D1, the first resistor R1, and the second resistor R2. The positive electrode of the first diode D1 is connected to the negative electrode of the second diode D2 and the output terminal of the first operational amplifier J1. The positive electrode of the second diode D2 is connected to the second resistor R2 and the third resistor R3. The third resistor R3 is connected to the negative electrode of the second operational amplifier J2, the fourth resistor R4, and the fifth resistor R5. The fourth resistor R4 is connected to the output terminal of the second operational amplifier J2. The positive electrode of the second operational amplifier J2 is connected to the ground. The first resistor R1 is connected to the fifth resistor R5.

[0059] The integration circuit includes an eighteenth NMOS transistor U18, a nineteenth NMOS transistor U19, and a capacitor C1. Among them, the source electrode of the eighteenth NMOS transistor U18 is connected to the drain electrode of the nineteenth NMOS transistor U19. The drain electrode of the eighteenth NMOS transistor U18 is connected to the source electrode of the nineteenth NMOS transistor U19. The drain electrode of the eighteenth NMOS transistor U18 is connected to the capacitor C1. The capacitor C1 is connected to the power supply VSS. The gate electrodes of the eighteenth NMOS transistor U18 and the nineteenth NMOS transistor U19 are connected to the power supply VDD.

[0060] The comparison circuit includes a twentieth PMOS transistor U20, a twenty-first PMOS transistor U21, a sixth resistor Ri1, a seventh resistor Ri2, an eighth resistor Ri3, a triode Q1, and a ninth resistor Rt. Among them, the source electrodes of the twentieth PMOS transistor U20 and the twenty-first PMOS transistor U21 are connected. One end of the eighth resistor Ri3 is connected to the source electrode of the twenty-first PMOS transistor U21, and the other end of the eighth resistor Ri3 is connected to the power supply VDD1. The gate electrode of the twentieth PMOS transistor U20 is connected to the ground. The drain electrode of the twentieth PMOS transistor U20 is connected to the sixth resistor Ri1. The drain electrode of the twenty-first PMOS transistor U21 is connected to the seventh resistor Ri2 and the base electrode of the triode Q1. The sixth resistor Ri1 and the seventh resistor Ri2 are connected in series and then grounded. The emitter electrode of the triode Q1 is connected to the ground. The collector electrode of the triode Q1 is connected to the ninth resistor Rt. The ninth resistor Rt is connected to the power supply Vt.

[0061] The described reconfigurable non - linear logic gate circuit based on memristive cells further includes a tenth resistor Ro1, an eleventh resistor Ro2, and a twelfth resistor Ro3. One end of the tenth resistor Ro1 is connected to the drain of the thirteenth PMOS transistor U13, and the other end of the tenth resistor Ro1 is connected to the first resistor R1. One end of the eleventh resistor Ro2 is connected to the output terminal of the second operational amplifier J2, and the other end of the eleventh resistor Ro2 is connected to the twelfth resistor Ro3. One end of the twelfth resistor Ro3 is connected to the drain of the seventeenth PMOS transistor U17, and the other end of the twelfth resistor Ro3 is connected to the load memristor Mr.

[0062] A method for logical function reconfiguration using a reconfigurable non - linear logic gate circuit based on memristive cells, the method comprising the following steps:

[0063] 1) Set a reference voltage in the comparison circuit;

[0064] 2) Use the first template parameter setting circuit to set the first template parameter b1 as the weight of the first template parameter;

[0065] 3) Use the second template parameter setting circuit to set the second template parameter b2 as the weight of the second template parameter;

[0066] 4) Use the third bias parameter setting circuit to set the third bias parameter as the bias parameter c;

[0067] 5) Input the second signal V2, the fourth signal V4, and the sixth signal V6 into the first template parameter setting circuit, the second template parameter setting circuit, and the third bias parameter setting circuit respectively; set the second signal V2 and the fourth signal V4 to high level or low level according to the requirements of the implemented logical function; the high level is preferably 1, and the low level is preferably - 1; the sixth signal V6 is preferably set to 1; the second signal V2, the fourth signal V4, and the sixth signal V6 are preferably input from the 2 - signal input terminal, the 4 - signal input terminal, and the 6 - signal input terminal respectively;

[0068] 6) The second signal V2, the fourth signal V4, and the sixth signal V6 respectively form voltage drops across the fifth memristor M5, the tenth memristor M10, and the fifteenth memristor M15. The sum of the products of the voltage drops across the fifth memristor M5 and the tenth memristor M10 and the first template parameter b1 and the second template parameter b2 respectively is sent to an absolute value circuit to obtain the absolute value and then output. The bias parameter c is multiplied by the voltage drop across the fifteenth memristor M15. The output of the absolute value circuit is then converged and added to the product of the bias parameter c and the voltage drop across the fifteenth memristor M15 and then integrated by an integration circuit to form an integrated output voltage. The integrated output voltage obtained by integrating through the integration circuit is compared with the reference voltage set in the comparison circuit; if the integrated output voltage obtained by integrating through the integration circuit is less than the reference voltage, the output terminal voltage Vout of the entire memristor cell-based reconfigurable non-linear logic gate circuit is defined as a low level, and the corresponding output terminal logic is "0"; if the output voltage obtained by integrating through the integration circuit is greater than the reference voltage, the output terminal voltage Vout of the entire memristor cell-based reconfigurable non-linear logic gate circuit is defined as a high level, and the corresponding output terminal logic is "1".

[0069] The sixth signal V6 is set to 1 v, and the reference voltage set in the comparison circuit is set to 0 v; then the condition for the output terminal voltage of the entire memristor cell-based reconfigurable non-linear logic gate circuit to be at a high level is shown by the following formula:

[0070] |b1V2 + b2V4| + c > 0;

[0071] The condition for the output terminal voltage of the entire memristor cell-based reconfigurable non-linear logic gate circuit to be at a low level is shown by the following formula:

[0072] |b1V2 + b2V4| + c < 0;

[0073] The second signal V2 and the fourth signal V4 respectively serve as the input voltages of the first template parameter setting circuit and the second template parameter setting circuit. When the input voltage is defined as 1 v, the corresponding logic is "1"; when the input voltage is -1 v, the corresponding logic is "0".

[0074] At this time, the conditions for implementing an exclusive OR circuit are: the conditions for implementing an exclusive OR logic are: |b1 - b2| + c > 0, |b1 + b2| + c < 0; the conditions for implementing an exclusive NOR logic are: |b1 - b2| + c < 0, |b1 + b2| + c > 0.

[0075] The first template parameter setting circuit implements the first template parameter b1, the second template parameter setting circuit implements the second template parameter b2, the third bias parameter setting circuit implements the bias parameter c. The first template parameter b1, the second template parameter b2, and the bias parameter c all include two parts: magnitude and direction.

[0076] For the setting of the first template parameter b1, it specifically includes: in the first template parameter setting circuit, close the first switch W1 and open the second switch W2; at this time, input a pulse signal into the first template parameter setting circuit from the No. 1 signal input terminal, and change the current direction and the resistance value of the fifth memristor M5 by controlling the length of the input pulse signal time; when the input pulse signal ends, if the current flowing through the fifth memristor M5 is positive, then the first template parameter b1 is positive, if the current flowing through the fifth memristor M5 is negative, then the first template parameter b1 is negative, and at this time the resistance value of the fifth memristor M5 is the magnitude of the first template parameter b1;

[0077] For the setting of the second template parameter b2, it specifically includes: in the second template parameter setting circuit, close the first switch W3 and open the second switch W4; at this time, input a pulse signal into the second template parameter setting circuit from the No. 3 signal input terminal, and change the current direction and the resistance value of the tenth memristor M10 by controlling the length of the input pulse signal time; when the input pulse signal ends, if the current flowing through the tenth memristor M10 is positive, then the second template parameter b2 is positive, if the current flowing through the tenth memristor M10 is negative, then the second template parameter b2 is negative, and at this time the resistance value of the tenth memristor M10 is the magnitude of the second template parameter b2;

[0078] For the setting of the bias parameter c, it specifically includes: in the third bias parameter setting circuit, close the first switch W5 and open the second switch W6; at this time, input a pulse signal into the third bias parameter setting circuit from the No. 5 signal input terminal, and change the current direction and the resistance value of the fifteenth memristor M15 by controlling the length of the input pulse signal time; when the input pulse signal ends, if the current flowing through the fifteenth memristor M15 is positive, then the bias parameter c is positive, if the current flowing through the fifteenth memristor M15 is negative, then the bias parameter c is negative, and at this time the resistance value of the fifteenth memristor M15 is the magnitude of the bias parameter c.

[0079] When the present invention is in use, only the first template parameter setting circuit, the second template parameter setting circuit, and the third bias parameter setting circuit are needed to set the first template parameter, the second template parameter, and the bias parameter according to needs, so that a certain conditional relationship is satisfied among the first template parameter, the second template parameter, and the bias parameter, and the exclusive - OR logic function or the equivalence logic function can be realized. When it is necessary to switch between the exclusive - OR logic function and the equivalence logic function, only the specific settings of the first template parameter, the second template parameter, and the bias parameter need to be changed, and only by changing the duration of the input pulse signals of the first template parameter setting circuit, the second template parameter setting circuit, and the third bias parameter setting circuit respectively can the logic function be changed, without changing any devices and their parameter values in the internal circuit, realizing the reconfigurability of the logic circuit, and the operation is simple and easy to implement.

[0080] Embodiment 1

[0081] A method for realizing a reconfigurable non - linear logic function in a cellular neural network by using a reconfigurable non - linear logic gate circuit based on memristive cells, the method comprising:

[0082] Step (1): In the cellular neural network, using the input signal, bias parameter, template parameter, and state variable, the following state equation can be obtained:

[0083]

[0084] The output equation is:

[0085] f(V x ) = 0.5[|V x + 1| - |V x - 1|];

[0086] In the above equations, V2 and V4 are respectively defined as the input voltages of the first template parameter setting circuit and the second template parameter setting circuit, a, b1, b2 are template parameters, V x is the system state variable of the cellular neural network, c is the bias parameter, and f(Vx) is the output signal of the logic gate circuit;

[0087] Step (2): Assume a = 2, and the state equation dVx / dt in step (1) is 0. At this time, the state equation in step (1) is a steady - state equation. If it is necessary to make the logic gate output a high level, that is, f(Vx)>0, and if it is necessary to make the logic gate output a low level, that is, f(Vx)<0, then substitute the critical value f(Vx) = 0 into the equation in step (1), and the inputs are the two input variables V2 and V4. Finally, the equation of the system state variable Vx is obtained as:

[0088] V x = b1V2 + b2V4 + c;

[0089] Step (3): Since the equation in step (2) can only implement a finite number of linear functions, in order to obtain the non-linear relationship between the input and the template parameters b1 and b2, the equation in step (2) is replaced with the following equation, and finally the equation of the state variable Vx is obtained as:

[0090] Vx = |b1V2 + b2V4| + c;

[0091] Step (4): If the logic gate is to output a high level, that is, f(Vx)>0, then the system state variable Vx>0. Then the condition for the logic gate to output a high-level signal is: |b1V2 + b2V4| + c > 0;

[0092] If the logic gate is to output a low level, that is, f(Vx)<0, then the system state variable Vx<0. Then the condition for the logic gate to output a high-level signal is: |b1V2 + b2V4| + c < 0;

[0093] Step (5): When the cell implements an exclusive-OR circuit, the parameter values b1, b2, and c need to simultaneously satisfy the following conditions: When the input signals are all high levels (1, 1), substituting V2 = 1v and V4 = 1v into step (4), the condition for the logic gate to output a low level is: |b1 + b2| + c < 0;

[0094] When the input signal is (0, 1), substituting V2 = -1v and V4 = 1v into step (3), the condition for the logic gate to output a high level is: |-b1 + b2| + c > 0;

[0095] When the input signal is (1, 0), substituting V2 = 1v and V4 = -1v into step (3), the condition for the logic gate to output a high level is: |b1 - b2| + c > 0;

[0096] When the input signals are all low levels (0, 0), substituting V2 = -1v and V4 = -1v into step (3), the condition for the logic gate to output a low level is: |-b1 - b2| + c < 0;

[0097] In summary:

[0098] The value range of each parameter for implementing the exclusive-OR logic is: |b1 - b2| + c > 0, |b1 + b2| + c < 0;

[0099] The value range of each parameter for implementing the equivalence logic is: |b1 - b2| + c < 0, |b1 + b2| + c > 0.

[0100] As Figure 2 shown, in this embodiment, a reconfigurable non-linear logic gate implementation circuit based on memristive cells is designed. By setting different parameter values, the exclusive-OR and equivalence circuits can be implemented.

[0101] The logic states in the logic gate circuit are voltage values. Among them, it is defined that the input voltage of 1V corresponds to logic "1", and the input voltage of -1V corresponds to logic "0"; the output voltage of 0V corresponds to logic "0", and the output voltage of 5V corresponds to logic "1".

[0102] According to the above analysis of the implementation conditions of the logic gate, the parameter values b1, b2, and c are set to implement the exclusive OR logic and the equivalence logic functions. The specific parameter value settings are shown in Table 1 below:

[0103] Table 1 Parameter Values

[0104]

[0105] The specific parameter value settings are as follows:

[0106] The setting of each parameter is realized by the memristive bridge synapse circuit. The first template parameter setting circuit realizes b1, the second template parameter setting circuit realizes b2, and the third bias parameter setting circuit realizes c; setting the parameter value means setting the weight, including two parts: the magnitude and the direction of the weight value. In the circuit Figure 2 it is shown as: when switches W1, W3, and W5 are closed and switches W2, W4, and W6 are open:

[0107] (1) For the setting of the direction, in the memristive bridge synapse circuit, if a positive signal is input, the currents flowing through the middle fifth memristor M5, tenth memristor M10, and fifteenth memristor M15 are positive, then the weight is positive; if a negative signal is input, the currents flowing through the middle fifth memristor M5, tenth memristor M10, and fifteenth memristor M15 are negative, then the weight is negative;

[0108] (2) For the setting of the magnitude, in the memristive bridge synapse circuit, the resistance value of the middle memristor represents the magnitude of the weight. When the input voltage is greater than the threshold voltage of the middle memristor, its resistance value can be changed.

[0109] In the first template parameter setting circuit, the initial resistance values of the first memristor M1 and fourth memristor M4 are set to 15 kΩ, and the initial resistance values of the second memristor M2, third memristor M3, and fifth memristor M5 are set to 1 kΩ. The input signal is a pulse signal with a voltage amplitude of 3V, a pulse width of 20 ms, and a period of 100 ms; the change curve of the resistance value, that is, the change curve of the weight, is as Figure 3 shown. It can be seen from the figure that the change range of the resistance value of the fifth memristor is (1k, 13k); the direction of the weight can be determined by the direction of the current flowing through the fifth memristor; as Figure 4It can be seen that at the beginning, since the initial resistance values of the first memristor M1 and the fourth memristor M4 are at the maximum, and the initial resistance values of the second memristor M2 and the third memristor M3 are at the minimum, according to Ohm's law, at this time, the signal path is the second memristor M2, the third memristor M3, and the fifth memristor M5. The current flowing through the fifth memristor M5 is negative, so the voltage difference VAB between the fifth memristor M5 is negative, indicating that the weight of the first memristive bridge synaptic circuit at this time is negative; as the resistance values of the first memristor M1 and the fourth memristor M4 gradually decrease, finally the voltage difference VAB between the fifth memristor M5 will be greater than 0. At this time, the current direction flowing through the fifth memristor M5 is positive, indicating that the weight is positive (the same applies to the setting of the second template parameter and the third bias parameter); so according to Figure 3 , Figure 4 The corresponding positive and negative weights, when the parameter value is 1, an input pulse signal lasting for 1.1 s can obtain 13 kΩ, that is, a positive weight; when the parameter value is -1, an input pulse signal lasting for 0.9 s can obtain 13 kΩ, that is, a negative weight.

[0110] Figure 2 In Figure 2 , in addition to the setting of each parameter value, another key step in the circuit implementation is that in order to obtain a non-linear correlation between the input and each parameter value, an absolute value module is added to implement the absolute value of the sum of the template parameters b1 and b2. Figure 2 In , it is shown as the output values of the first template parameter setting circuit and the second template parameter setting circuit, which are sent as inputs to the first summing circuit. The output value of the first summing circuit is sent as an input to the absolute value circuit, and then |b1 + b2| can be obtained.

[0111] For example, the circuit implements the exclusive OR logic. Figure 2When the second input signal V2 is at a low level and the fourth input signal V4 is at a low level, the sum of the voltage drops across the fifth memristor M5 and the tenth memristor M10 multiplied by the template parameters b1 and b2 is sent to the absolute value circuit for output. After converging and adding it to the product of the bias parameter c and the voltage drop across the fifteenth memristor M15, the integrated output voltage is less than the reference voltage 0V of the comparison circuit, and the output terminal Vout outputs a low voltage 0v, which is the low level "0"; when the second input signal V2 is at a low level and the fourth input signal V4 is at a high level, the sum of the voltage drops across the fifth memristor M5 and M10 multiplied by the template parameters b1 and b2 is sent to the absolute value circuit for output. After converging and adding it to the product of the bias parameter c and the voltage drop across the fifteenth memristor M15, the integrated output voltage is greater than the reference voltage 0v of the comparison circuit, and the output terminal Vout outputs a high voltage 5v, which is the high level "1"; when the input terminal V2 is at a high level and the input terminal V4 is at a low level, the sum of the voltage drops across the fifth memristor M5 and the tenth memristor M10 multiplied by the template parameters b1 and b2 is sent to the absolute value circuit for output. After converging and adding it to the product of the bias parameter c and the voltage drop across the fifteenth memristor M15, the integrated output voltage is greater than the reference voltage 0v of the comparison circuit, and the output terminal Vout outputs a high voltage 5v, which is the high level "1"; when the second input signal V2 is at a high level and the fourth input signal V4 is at a high level, the sum of the voltage drops across the fifth memristor M5 and the tenth memristor M10 multiplied by the template parameters b1 and b2 is sent to the absolute value circuit for output. After converging and adding it to the product of the bias parameter c and the voltage drop across the fifteenth memristor M15, the integrated output voltage is less than the reference voltage 0V of the comparison circuit, and the output terminal Vout outputs a low voltage 0v, which is the low level "0".

[0112] The output results of the exclusive - or circuit are as follows Figure 5 As shown, when the input voltage is (-1v, -1v), the output voltage is the low voltage 0v; when the input voltage is (-1v, 1v), the output voltage is the high voltage 5v; when the input voltage is (1v, -1v), the output voltage is the high voltage 5v; when the input voltage is (1v, 1v), the output voltage is the low voltage 0v;

[0113] To further prove the correctness of the circuit in realizing the reconfigurable non - linear logic function, the present invention changes the values of each parameter to verify the function of the circuit in realizing the exclusive - nor logic: As can be seen from Table 1, only by changing the value of the template parameter b1 in the above - mentioned exclusive - or circuit from 1 to -1, that is, adjusting the first template parameter setting circuit, the output result of the exclusive - nor logic gate circuit is as Figure 6 shown. It can be seen from the figure that due to the limited switching speed, time delay will inevitably be encountered. When the input signals are both at a high level, the output level has a delay of 0.01s. In subsequent experiments, it can be further studied, but the impact on the result correctness is negligible.

Claims

1. A reconfigurable non - linear logic gate circuit based on memristive cells, characterized in that It includes a first template parameter setting circuit, a second template parameter setting circuit, a third bias quantity parameter setting circuit, a first summing circuit, an absolute value circuit, a second summing circuit, an integrating circuit, and a comparing circuit. Among them, the output terminal of the first template parameter setting circuit is connected to the first input terminal of the first summing circuit, the output terminal of the second template parameter setting circuit is connected to the second input terminal of the first summing circuit, the output terminal of the first summing circuit is connected to the input terminal of the absolute value circuit, the output terminal of the third bias quantity parameter setting circuit is connected to the input terminal of the second summing circuit, the output terminals of the second summing circuit and the absolute value circuit are commonly connected to the input terminal of the integrating circuit and one end of the load memristor Mr, the output terminal of the integrating circuit is connected to the input terminal of the comparing circuit, and the other end of the load memristor Mr is grounded. The input terminal of the first template parameter setting circuit is connected to the No. 1 signal input terminal and the No. 2 signal input terminal. The No. 1 signal input terminal and the No. 2 signal input terminal are in parallel. A first switch W1 is connected in series on the No. 1 signal input terminal, and a second switch W2 is connected in series on the No. 2 signal input terminal. The input terminal of the second template parameter setting circuit is connected to the No. 3 signal input terminal and the No. 4 signal input terminal. The No. 3 signal input terminal and the No. 4 signal input terminal are in parallel. A third switch W3 is connected in series on the No. 3 signal input terminal, and a fourth switch W4 is connected in series on the No. 4 signal input terminal. The input terminal of the third bias quantity parameter setting circuit is connected to the No. 5 signal input terminal and the No. 6 signal input terminal. The No. 5 signal input terminal and the No. 6 signal input terminal are in parallel. A fifth switch W5 is connected in series on the No. 5 signal input terminal, and a sixth switch W6 is connected in series on the No. 6 signal input terminal. The first template parameter setting circuit includes a first memristor M1, a second memristor M2, a third memristor M3, a fourth memristor M4, a fifth memristor M5, a first NMOS transistor U1, a second NMOS transistor U2, and a third NMOS transistor U3. The first memristor M1, the second memristor M2, the third memristor M3, the fourth memristor M4, and the fifth memristor M5 form a first memristive bridge. The first NMOS transistor U1, the second NMOS transistor U2, and the third NMOS transistor U3 form a first differential amplifier. The first memristive bridge and the first differential amplifier together form a first memristive bridge synaptic circuit. Among them, the first memristor M1 and the second memristor M2 are connected in series in reverse, the third memristor M3 and the fourth memristor M4 are connected in series in reverse, the positive and negative ends of the fifth memristor M5 are respectively connected to the two gates of the first differential amplifier, the first memristor M1 and the third memristor M3 are connected in series in the same direction, the second memristor M2 and the fourth memristor M4 are connected in series in the same direction, the connection point of the first memristor M1 and the third memristor M3 leads out the signal input terminal of the first memristive bridge synaptic circuit, and the connection point of the second memristor M2 and the fourth memristor M4 is grounded. The signal input terminal of the first memristive bridge synaptic circuit is the input terminal of the first template parameter setting circuit.

2. The reconfigurable non-linear logic gate circuit based on memristive cells according to claim 1, characterized in that The second template parameter setting circuit includes a sixth memristor M6, a seventh memristor M7, an eighth memristor M8, a ninth memristor M9, a tenth memristor M10, a fourth NMOS transistor U4, a fifth NMOS transistor U5, and a sixth NMOS transistor U6; the sixth memristor M6, the seventh memristor M7, the eighth memristor M8, the ninth memristor M9, and the tenth memristor M10 form a second memristive bridge; the fourth NMOS transistor U4, the fifth NMOS transistor U5, and the sixth NMOS transistor U6 form a second differential amplifier; the second memristive bridge and the second differential amplifier together form a second memristive bridge synaptic circuit; wherein, the sixth memristor M6 and the seventh memristor M7 are connected in series in antiphase, the eighth memristor M8 and the ninth memristor M9 are connected in series in antiphase, the positive and negative terminals of the tenth memristor M10 are respectively connected to the two gates of the second differential amplifier, the sixth memristor M6 and the eighth memristor M8 are connected in series in the same direction, the seventh memristor M7 and the ninth memristor M9 are connected in series in the same direction, the connection between the sixth memristor M6 and the eighth memristor M8 leads to the signal input terminal of the second memristive bridge synaptic circuit, and the connection between the seventh memristor M7 and the ninth memristor M9 is grounded; the signal input terminal of the second memristive bridge synaptic circuit is the input terminal of the second template parameter setting circuit; The third bias parameter setting circuit includes an eleventh memristor M11, a twelfth memristor M12, a thirteenth memristor M13, a fourteenth memristor M14, a fifteenth memristor M15, a seventh NMOS transistor U7, an eighth NMOS transistor U8, and a ninth NMOS transistor U9; the eleventh memristor M11, the twelfth memristor M12, the thirteenth memristor M13, the fourteenth memristor M14, and the fifteenth memristor M15 form a third memristive bridge; the seventh NMOS transistor U7, the eighth NMOS transistor U8, and the ninth NMOS transistor U9 form a third differential amplifier; the third memristive bridge and the third differential amplifier together form a third memristive bridge synaptic circuit; wherein, the eleventh memristor M11 and the twelfth memristor M12 are connected in series in antiphase, the thirteenth memristor M13 and the fourteenth memristor M14 are connected in series in antiphase, the positive and negative terminals of the fifteenth memristor M15 are respectively connected to the two gates of the third differential amplifier, the eleventh memristor M11 and the thirteenth memristor M13 are connected in series in the same direction, the twelfth memristor M12 and the fourteenth memristor M14 are connected in series in the same direction, the connection between the eleventh memristor M11 and the thirteenth memristor M13 leads to the signal input terminal of the third memristive bridge synaptic circuit, and the connection between the twelfth memristor M12 and the fourteenth memristor M14 is grounded; the signal input terminal of the third memristive bridge synaptic circuit is the input terminal of the third bias parameter setting circuit.

3. The reconfigurable non-linear logic gate circuit based on memristive cells according to claim 2, characterized in that The initial resistance values of the first memristor M1 and the fourth memristor M4 are equal, the initial resistance values of the second memristor M2, the third memristor M3, and the fifth memristor M5 are equal, and the initial resistance values of the first memristor M1 and the fourth memristor M4 are greater than the initial resistance values of the second memristor M2, the third memristor M3, and the fifth memristor M5; The initial resistance values of the sixth memristor M6 and the ninth memristor M9 are equal, the initial resistance values of the seventh memristor M7, the eighth memristor M8, and the tenth memristor M10 are equal, and the initial resistance values of the sixth memristor M6 and the ninth memristor M9 are greater than the initial resistance values of the seventh memristor M7, the eighth memristor M8, and the tenth memristor M10; The initial resistance values of the eleventh memristor M11 and the fourteenth memristor M14 are equal, the initial resistance values of the twelfth memristor M12, the thirteenth memristor M13, and the fifteenth memristor M15 are equal, and the initial resistance values of the eleventh memristor M11 and the fourteenth memristor M14 are greater than the initial resistance values of the twelfth memristor M12, the thirteenth memristor M13, and the fifteenth memristor M15.

4. A reconfigurable non-linear logic gate circuit based on memristive cells according to claim 1, characterized in that The first summing circuit includes a tenth PMOS transistor U10, an eleventh PMOS transistor U11, a twelfth PMOS transistor U12, and a thirteenth PMOS transistor U13; wherein, the sources of the twelfth PMOS transistor U12 and the thirteenth PMOS transistor U13 are respectively connected to the drains of the tenth PMOS transistor U10 and the eleventh PMOS transistor U11 correspondingly; the sources of the tenth PMOS transistor U10 and the eleventh PMOS transistor U11 are connected to the power supply VDD; the gates of the tenth PMOS transistor U10 and the eleventh PMOS transistor U11 are interconnected; the gates of the twelfth PMOS transistor U12 and the thirteenth PMOS transistor U13 are interconnected; The second summing circuit includes a fourteenth PMOS transistor U14, a fifteenth PMOS transistor U15, a sixteenth PMOS transistor U16, and a seventeenth PMOS transistor U17; wherein, the drains of the fourteenth PMOS transistor U14 and the fifteenth PMOS transistor U15 are respectively connected to the sources of the sixteenth PMOS transistor U16 and the seventeenth PMOS transistor U17 correspondingly; the sources of the fourteenth PMOS transistor U14 and the fifteenth PMOS transistor U15 are connected to the power supply VDD; the gates of the fourteenth PMOS transistor U14 and the fifteenth PMOS transistor U15 are interconnected; the gates of the sixteenth PMOS transistor U16 and the seventeenth PMOS transistor U17 are interconnected.

5. A reconfigurable non - linear logic gate circuit based on memristive cells according to claim 1, characterized in that The absolute value circuit includes a first operational amplifier J1, a second operational amplifier J2, a first diode D1, a second diode D2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5; wherein, the positive terminal of the first operational amplifier J1 is connected to the ground, the negative terminal of the first operational amplifier J1 is connected to the negative terminal of the first diode D1, the first resistor R1, and the second resistor R2; the positive terminal of the first diode D1 is connected to the negative terminal of the second diode D2 and the output terminal of the first operational amplifier J1; the positive terminal of the second diode D2 is connected to the second resistor R2 and the third resistor R3; the third resistor R3 is connected to the negative terminal of the second operational amplifier J2, the fourth resistor R4, and the fifth resistor R5; the fourth resistor R4 is connected to the output terminal of the second operational amplifier J2; the positive terminal of the second operational amplifier J2 is connected to the ground; the first resistor R1 is connected to the fifth resistor R5.

6. A reconfigurable non-linear logic gate circuit based on memristive cells according to claim 1, characterized in that the The integrating circuit includes the eighteenth NMOS transistor U18, the nineteenth NMOS transistor U19, and the capacitor C1. Among them, the source of the eighteenth NMOS transistor U18 is connected to the drain of the nineteenth NMOS transistor U19; the drain of the eighteenth NMOS transistor U18 is connected to the source of the nineteenth NMOS transistor U19; the drain of the eighteenth NMOS transistor U18 is connected to the capacitor C1; the capacitor C1 is connected to the power supply VSS; the gates of the eighteenth NMOS transistor U18 and the nineteenth NMOS transistor U19 are connected to the power supply VDD. The comparison circuit includes the twentieth PMOS transistor U20, the twenty-first PMOS transistor U21, the sixth resistor Ri1, the seventh resistor Ri2, the eighth resistor Ri3, the triode Q1, and the ninth resistor Rt. Among them, the source of the twentieth PMOS transistor U20 is connected to the source of the twenty-first PMOS transistor U21, one end of the eighth resistor Ri3 is connected to the source of the twenty-first PMOS transistor U21, and the other end of the eighth resistor Ri3 is connected to the power supply VDD1; the gate of the twentieth PMOS transistor U20 is connected to the ground; the drain of the twentieth PMOS transistor U20 is connected to the sixth resistor Ri1; the drain of the twenty-first PMOS transistor U21 is connected to the seventh resistor Ri2 and the base of the triode Q1; the sixth resistor Ri1 and the seventh resistor Ri2 are connected in series and then grounded; the emitter of the triode Q1 is connected to the ground; the collector of the triode Q1 is connected to the ninth resistor Rt; the ninth resistor Rt is connected to the power supply Vt.

7. A method for logical function reconstruction using a reconfigurable non - linear logic gate circuit based on memristive cells as described in claim 2, characterized in that The method includes the following steps: 1) Set a reference voltage in the comparison circuit. 2) Use the first template parameter setting circuit to set the first template parameter b1 as the weight of the first template parameter. 3) Use the second template parameter setting circuit to set the second template parameter b2 as the weight of the second template parameter. 4) Use the third bias parameter setting circuit to set the bias parameter as the bias parameter c. 5) Input the second signal V2, the fourth signal V4, and the sixth signal V6 into the first template parameter setting circuit, the second template parameter setting circuit, and the third bias parameter setting circuit respectively; set the second signal V2 and the fourth signal V4 to high level or low level respectively according to the requirements of the implemented logic function. 6) The second signal V2, the fourth signal V4, and the sixth signal V6 respectively form voltage drops across the fifth memristor M5, the tenth memristor M10, and the fifteenth memristor M15. The sum of the products of the voltage drops across the fifth memristor M5 and the tenth memristor M10 and the first template parameter b1 and the second template parameter b2 is sent to an absolute value circuit to obtain the absolute value and then output. The bias parameter c is multiplied by the voltage drop across the fifteenth memristor M15. The output of the absolute value circuit is converged and added to the product of the bias parameter c and the voltage drop across the fifteenth memristor M15, and then integrated by an integration circuit to form an integrated output voltage. The integrated output voltage obtained by integrating through the integration circuit is compared with the reference voltage set in the comparison circuit. If the integrated output voltage obtained by integrating through the integration circuit is less than the reference voltage, the output terminal voltage Vout of the entire memristor cell-based reconfigurable non-linear logic gate circuit is defined as a low level, and the corresponding output terminal logic is "0"; if the output voltage obtained by integrating through the integration circuit is greater than the reference voltage, the output terminal voltage Vout of the entire memristor cell-based reconfigurable non-linear logic gate circuit is defined as a high level, and the corresponding output terminal logic is "1".

8. A method for performing logic function reconfiguration of a reconfigurable non - linear logic gate circuit based on memristive cells according to claim 7, characterized in that The sixth signal V6 is set to 1V, and the reference voltage set in the comparison circuit is set to 0V. The condition for the output terminal voltage of the entire memristor cell-based reconfigurable non-linear logic gate circuit to be at a high level is shown by the following formula: |b1V2 + b2V4| + c > 0; The condition for the output terminal voltage of the entire memristor cell-based reconfigurable non-linear logic gate circuit to be at a low level is shown by the following formula: |b1V2 + b2V4| + c < 0; The second signal V2 and the fourth signal V4 are respectively used as the input voltages of the first template parameter setting circuit and the second template parameter setting circuit. When the input voltage is defined as 1V, the corresponding logic is "1"; when the input voltage is -1V, the corresponding logic is "0". At this time, the conditions for implementing an exclusive OR circuit are: the conditions for implementing an exclusive OR logic are: |b1 - b2| + c > 0, |b1 + b2| + c < 0; the conditions for implementing an exclusive NOR logic are: |b1 - b2| + c < 0, |b1 + b2| + c > 0.

9. The reconfigurable non-linear logic gate circuit based on memristive cells according to claim 1, characterized in that The first template parameter setting circuit implements the first template parameter b1, the second template parameter setting circuit implements the second template parameter b2, and the third bias parameter setting circuit implements the bias parameter c. The first template parameter b1, the second template parameter b2, and the bias parameter c all include two parts: magnitude and direction. For the setting of the first template parameter b1, specifically, in the first template parameter setting circuit, a pulse signal is input to the first template parameter setting circuit from the signal input terminal of the first template parameter setting circuit. By controlling the length of the input pulse signal, the current direction flowing through the fifth memristor M5 and the resistance value of the fifth memristor M5 are changed. When the input pulse signal ends, if the current flowing through the fifth memristor M5 is positive, the first template parameter b1 is positive; if the current flowing through the fifth memristor M5 is negative, the first template parameter b1 is negative. At this time, the resistance value of the fifth memristor M5 is the magnitude of the first template parameter b1. For the setting of the second template parameter b2, it specifically includes: in the second template parameter setting circuit, a pulse signal is input into the second template parameter setting circuit from the signal input terminal of the second template parameter setting circuit. By controlling the length of the input pulse signal, the current direction through the tenth memristor M10 and the resistance value of the tenth memristor M10 are changed; when the input pulse signal ends, if the current through the tenth memristor M10 is positive, the second template parameter b2 is positive, and if the current through the tenth memristor M10 is negative, the second template parameter b2 is negative. At this time, the resistance value of the tenth memristor M10 is the magnitude of the second template parameter b2. For the setting of the bias parameter c, it specifically includes: in the third bias parameter setting circuit, a pulse signal is input into the third bias parameter setting circuit from the signal input terminal of the third bias parameter setting circuit. By controlling the length of the input pulse signal, the current direction through the fifteenth memristor M15 and the resistance value of the fifteenth memristor M15 are changed; when the input pulse signal ends, if the current through the fifteenth memristor M15 is positive, the bias parameter c is positive, and if the current through the fifteenth memristor M15 is negative, the bias parameter c is negative. At this time, the resistance value of the fifteenth memristor M15 is the magnitude of the bias parameter c.

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