Use the void to partially remove the device's substrate

Abstract

An epitaxial lateral overgrowth (ELO) III-nitride layer is grown on or above an opening area of ​​a growth limit mask deposited on a substrate, wherein the growth of the ELO III-nitride layer and / or the subsequent regrown layer forms one or more voids. A III-nitride device layer is grown on or above the ELO III-nitride layer and / or the regrown layer. Stress is applied to a break point at the substrate, wherein the voids facilitate the application of stress so that a strip of the device consisting of the III-nitride device layer, the ELO III-nitride layer, and the regrown layer is removed from the substrate. The voids relieve stress from the growth limit mask, which helps prevent cracks. Decomposition of the growth limit mask is avoided to prevent compensation of the p-type layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of the following co-pending and commonly assigned applications pursuant to 35 USC § 119(e):

[0003] U.S. Provisional Application Serial No. 62 / 817,757, filed on March 13, 2019 by Takeshi Kamikawa, Masahiro Araki, and Srinivas Gandrothula, entitled SUBSTRATE FOR REMOVAL OF DEVICES USING VOID PORTIONS, attorney docket No. G&C 30794.0722USP1 (UC 2019-412-1);

[0004] This application is incorporated herein by reference.

[0005] This application is related to the following co-pending and co-assigned applications:

[0006] U.S. utility patent application Ser. No. 16 / 608,071, filed on Oct. 24, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, and entitled METHOD OF REMOVING ASUBSTRATE, and attorney docket No. 3G794.0653USWO (UC 2017-621-2), claiming the benefit under 35 U.S.C. § 365(e) of co-pending and commonly assigned PCT International Patent Application Ser. No. PCT / US18 / 31393, filed on May 7, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, and entitled METHOD OF REMOVING ASUBSTRATE, and attorney docket No. 30794.0653WOU1 (UC 2017-621-2). 2017-621-2), which claims the benefit under 35 U.S.C. § 119(e) of co-pending and commonly assigned U.S. Provisional Patent Application No. 62 / 502,205 filed on May 5, 2017 by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, and entitled “METHOD OF REMOVING ASUBSTRATE”, attorney docket number 30794.0653USP1 (UC 2017-621-1);

[0007] U.S. Utility Patent Application No. 16 / 642,298, filed on February 20, 2020 by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, and entitled METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE, and attorney docket number 30794.0659USWO (UC2018-086-2), claims the benefit under 35 U.S.C. § 365(e) of co-pending and commonly assigned PCT International Patent Application No. PCT / US18 / 51375, filed on September 17, 2018 by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, and entitled METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE TECHNIQUE), attorney docket number 30794.0659WOU1 (UC2018-086-2), claiming the benefit under 35 U.S.C. § 119(e) of co-pending and commonly assigned U.S. Provisional Patent Application No. 62 / 559,378, filed on September 15, 2017 by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, and entitled METHOD OF REMOVING A SUBSTRATE WITH ACLEAVING TECHNIQUE, attorney docket number 30794.0659USP1 (UC 2018-086-1);

[0008] PCT International Patent Application No. PCT / US19 / 25187, filed on April 1, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, and entitled METHOD OF FABRICATING NONPOLAR AND SEMIPOLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH, and attorney docket number 30794.0680WOU1 (UC 2018-427-2), claims the benefit under 35 U.S.C. § 119(e) of co-pending and commonly assigned U.S. Provisional Patent Application No. 62 / 650,487, filed on March 30, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, and entitled METHOD OF FABRICATING NONPOLAR AND SEMIPOLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH OFFABRICATING NONPOLAR AND SEMIPOLAR DEVICES USING EPITAXIAL LATERALOVERGROWTH), case number G&C 30794.0680USP1 (UC 2018-427-1);

[0009] PCT International Patent Application No. PCT / US19 / 32936, filed on May 17, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, and entitled METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES, and attorney docket number 30794.0681WOU1 (UC 2018-605-2), claiming the benefit under 35 U.S.C. § 119(e) of co-pending and commonly assigned U.S. Provisional Application Serial No. 62 / 672,913, filed on May 17, 2018, by Takeshi Kamikawa and Srinivas Gandrothula, and entitled METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES, and attorney docket number G&C 30794.0681USP1 (UC 2018-605-2). 2018-605-1);

[0010] PCT International Patent Application No. PCT / US19 / 34686, filed on May 30, 2019 by Srinivas Gandrothula and Takeshi Kamikawa, and entitled METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE, and attorney docket number 30794.0682WOU1 (UC 2018-614-2), claims the benefit under 35 U.S.C. § 119(e) of co-pending and commonly assigned U.S. Provisional Application Serial No. 62 / 677,833, filed on May 30, 2018 by Srinivas Gandrothula and Takeshi Kamikawa, and entitled METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE SUBSTRATE), case number G&C 30794.0682USP1 (UC 2018-614-1);

[0011] PCT International Patent Application No. PCT / US19 / 59086, filed on October 31, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, and entitled METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH, and attorney docket number 30794.0693WOU1 (UC 2019-166-2), claims the benefit under 35 U.S.C. § 119(e) of co-pending and commonly assigned U.S. Provisional Application Serial No. 62 / 753,225, filed on October 31, 2018, by Takeshi Kamikawa and Srinivas Gandrothula, and entitled METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH, and attorney docket number 30794.0693WOU1 (UC 2019-166-2). LATERAL OVERGROWTH)”, case number G&C30794.0693USP1(UC 2019-166-1);

[0012] PCT International Patent Application No. PCT / US20 / 13934, filed on January 16, 2020 by Takeshi Kamikawa, Srinivas Gandrothula, and Masahiro Araki, and entitled METHOD FOR REMOVAL OF DEVICES USING ATRENCH, and attorney docket number 30794.0713WOU1 (UC2019-398-2), claims the benefit under 35 U.S.C. § 119(e) of co-pending and commonly assigned U.S. Provisional Patent Application No. 62 / 793,253, filed on January 16, 2019 by Takeshi Kamikawa, Srinivas Gandrothula, and Masahiro Araki, and entitled METHOD FOR REMOVAL OF DEVICES USING ATRENCH TRENCH)》), the case number is G&C30794.0713USP1(UC 2019-398-1);

[0013] PCT International Patent Application No. PCT / US20 / 20647, filed on March 2, 2020 by Takeshi Kamikawa and Srinivas Gandrothula, and entitled METHOD FOR FLATTENING A SURFACE ON AN EPITAXIAL LATERAL GROWTH LAYER, and attorney docket number 30794.0720WOU1 (UC 2019-409-2), claims the benefit under 35 U.S.C. § 119(e) of co-pending and commonly assigned U.S. Provisional Application Serial No. 62 / 812,453, filed on March 1, 2019 by Takeshi Kamikawa and Srinivas Gandrothula, and entitled METHOD FOR FLATTENING A SURFACE ON AN EPITAXIAL LATERAL GROWTH LAYER, and entitled GROWTH LAYER), case number G&C 30794.0720USP1 (UC 2019-409-1); and

[0014] PCT International Patent Application No. PCT / US20 / 22430, filed on March 12, 2020, by Takeshi Kamikawa, Srinivas Gandrothula, and Masahiro Araki, and entitled METHOD FOR REMOVING A BAR OF ONE OR MORE DEVICES USING SUPPORTING PLATES, and attorney docket number 30794.0724WOU1 (UC 2019-416-2), claims the benefit under 35 U.S.C. § 119(e) of co-pending and commonly assigned U.S. Provisional Application Serial No. 62 / 817,216, filed on March 12, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, and Masahiro Araki, and entitled METHOD FOR REMOVING A BAR OF ONE OR MORE DEVICES USING SUPPORTING PLATES MOREDEVICES USING SUPPORTING PLATES), case number G&C 30794.0724USP1 (UC 2019-416-1);

[0015] The entire contents of these applications are incorporated herein by reference. Background of the Invention 1. Technical Field

[0017] The present invention relates to a substrate for partially removing a device using a void.

[0018] 2. Description of the Prior Art

[0019] Many device manufacturers have used freestanding bulk GaN substrates to produce laser diodes (LDs) and light-emitting diodes (LEDs) for lighting, optical storage, and other purposes. The appeal of GaN substrates is that high-quality III-nitride-based semiconductor layers with low defect density can be easily obtained by homoepitaxial growth on GaN substrates.

[0020] However, GaN substrates typically produced using hydride vapor phase epitaxy (HVPE) are very expensive. Therefore, researchers have investigated removing the III-nitride-based semiconductor layer from the GaN substrate after device fabrication. Such a technique would yield a GaN substrate that can be recycled, which would provide customers with very cheap and high-quality GaN substrates and III-nitride-based devices.

[0021] Therefore, there is a need for a technology for removing a Group III-nitride-based semiconductor layer from a Group III-nitride-based substrate or layer and a heterogeneous substrate having a Group III-nitride-based layer in an easy manner.

[0022] In one previous technique, a GaN layer is exfoliated by a metallic stressor layer under tensile stress. See, for example, Applied Physics Express 6 (2013) 112301 and U.S. Pat. No. 8,450,184, both of which are incorporated herein by reference. Specifically, the technique uses exfoliation in the middle of a GaN layer.

[0023] However, the surface morphology on the peeling plane is rough, and this technique cannot be controlled at the peeling location. In addition, this removal method may damage the semiconductor layer due to excessive bending in the layer being removed, which may cause cleavage in unintended directions. Therefore, it is necessary to reduce any such damage and surface roughness.

[0024] Another conventional technique is to use photoelectrochemical (PEC) etching of a sacrificial layer to remove the device structure from the GaN substrate, but this takes a long time and involves several complex processes. In addition, the yield of these processes has not yet met industry expectations.

[0025] Therefore, there is a need in the art for improved methods of removing a Group III nitride based substrate from a Group III nitride based semiconductor layer. In addition, there is a need to easily manufacture devices in very small sizes. The present invention meets this need. Summary of the invention

[0026] To overcome the limitations of the prior art described above, and to overcome other limitations that will become apparent after reading and understanding this specification, the present invention discloses a method of manufacturing a substrate using a void portion, and a method of removing a substrate from one or more device layers using a void portion. In the present invention, there are two different ways to form voids in an ELO III-nitride layer.

[0027] In a first method for manufacturing a void portion, a growth restriction mask is formed on the surface of a substrate having, for example, a stripe pattern. A III-nitride layer is grown on the substrate by epitaxial lateral overgrowth (ELO) through an opening region in the growth restriction mask. The growth of the ELO III-nitride layer is stopped before the ELO III-nitride layers are bonded to each other and / or before the growth restriction mask is completely covered by the ELO III-nitride layer. The growth restriction mask is removed by etching, wherein any exposed region of the growth restriction mask contributes to etching. After removing the growth restriction mask, a regrown layer is grown on the ELO III-nitride layer, which results in a void region created by etching of the growth restriction mask embedded in the ELO III-nitride layer and the regrown layer. The recessed portion of the non-growth region is buried by the regrown layer, which also flattens the surface of the regrown layer. A III-nitride device layer is then grown on the ELO nitride layer and / or the regrown layer, and a device is manufactured from the III-nitride device layer using an additional process. Dry etching removes portions of: the III-nitride device layer, the regrown layer, the ELO nitride layer, and the substrate to expose the void region. A polymer film, plate, substrate, or other stress-applying material is used to contact the surface of the substrate from the device side, wherein the stress-applying material applies stress to separate the strips of the device from the substrate. Due to the presence of the void region, the stress-applying material can effectively transfer stress to the breaking point at the edge of the opening region. After removing the strip, the n-electrode can be deposited on the back side of the strip. This method is called the "without growth limiting mask" method.

[0028] In the second method of making the void portion, optimizing the growth conditions during the growth of the ELO III-nitride layer can automatically form voids in the ELO III-nitride layer without removing the growth limit mask. For example, the low V / III conditions will produce (11-2-2) facets at the edges of the ELO III-nitride layer, and these facets are inverted cones. After the ELO III-nitride layer is coalesced, the inverted cones produce triangular-shaped voids in the coalesced area. Therefore, this method can easily form voids without the need for an additional process for forming voids. This method is called a "triangular void" method.

[0029] In both methods, cracks caused by stress from the growth limit mask can be avoided because the voids can effectively release stress. In addition, decomposition of the growth limit mask is avoided, which would lead to overdoping of the active region and compensation of the p-type layer.

[0030] The present invention has the following advantages:

[0031] 1. Prevent cracks from occurring in the III-nitride device layer. Due to the difference in thermal expansion coefficients between the growth restriction mask and the III-nitride device layer, cracks may occur when the growth restriction mask is buried.

[0032] In the "without growth limiting mask" method, the growth limiting mask is removed, which eliminates this problem. In addition, the substrate includes a void region, which can effectively release the stress of the Group III nitride semiconductor layer.

[0033] In the "triangular void" approach, the triangular voids effectively relieve stress in the ELO III-nitride layer even when the growth-limiting mask remains, which prevents cracks from occurring. In this case, the void placed directly on the growth-limiting mask can effectively relieve stress because it enables the formation of large voids.

[0034] 2. Reduce the number of holes on the surface of the regrown layer. The presence of holes leads to surface roughness. Using a Mg-doped regrown layer can reduce the number of holes. In addition, the Mg-doped regrown layer can bury the recessed area of ​​the non-grown area, which reduces the growth time of the regrown layer.

[0035] 3. Obtain a smooth surface after coalescing the ELO III-nitride layer. Chemical mechanical polishing (CMP) can smooth the surface after coalescence, thereby promoting a planar surface for the III-nitride device layers and reducing the in-plane distribution of the thickness of each layer.

[0036] 4. Perform device processing using a flat surface substrate. The substrate can be processed as a conventional wafer with the void region fully embedded within the ELO III-nitride layer and the regrown layer.

[0037] 5. The present invention can prevent the compensation of the p-type layer by decomposing the growth restriction mask. Generally, in the ELO method, the growth restriction mask is made of SiO 2 or SiN. However, both silicon (Si) and oxygen (O) atoms are n-type dopants for GaN. Therefore, if SiO 2 Decomposed during the growth of the p-type layer, these atoms compensate for the p-type dopants in the p-type layer of GaN.

[0038] In the "no growth limiting mask" approach, the growth limiting mask is removed, which eliminates this problem.

[0039] In the "triangular gap" approach, even if the growth limit mask remains, the ELO III-nitride layer coalesces (which covers the growth limit mask), and then a p-type layer is grown on the ELO III-nitride layer. This also avoids compensating the p-type layer by decomposing the growth limit mask.

[0040] 6. An etching process is performed to remove the strips of the device from the substrate.

[0041] In the "without growth limiting mask" approach, voids are etched, which facilitates the removal of the strips of the device from the substrate.

[0042] In the "triangular void" method, the void height is high and the etching depth easily reaches the top of the void. When the etching depth reaches the top of the void, the III-nitride device layer on the substrate can be divided into strips. Less etching time and reduced amount of etching material provide advantages for mass production.

[0043] 7. The present invention can use III-nitride substrates or heterogeneous substrates, such as sapphire, SiC, LiAlO 2 , Si, etc., as long as it can grow a III-nitride semiconductor layer through a growth restriction mask. In the case of using a III-nitride substrate, the present invention can obtain a high-quality III-nitride-based semiconductor layer and avoid the substrate bending or bending caused by homoepitaxial growth during epitaxial growth. Therefore, in the case of using a III-nitride substrate, a device with reduced defect density, such as dislocations and stacking faults, can also be easily obtained.

[0044] 8. The present invention can be used to manufacture light emitting diodes (LEDs), laser diodes (LDs), photodetectors (PDs), Schottky barrier diodes (SBDs), metal oxide semiconductor field effect transistors (MOSFETs) or other optoelectronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Referring now to the drawings, wherein like reference numerals designate corresponding parts throughout:

[0046] Figure 1(a) , 1(b) , 1(c), 1(d), 1(e), 1(f), 1(g), 1(h), 1(i), 1(j) and Figure 1(k) are schematic diagrams illustrating a method without a growth limiting mask.

[0047] Figure 2(a) , 2(b) , 2(c), 2(d), 2(e), 2(f) and 2(g) are schematic diagrams and scanning electron microscope (SEM) images illustrating the shapes and sizes of the growth limit mask, the ELO III-nitride layer and the non-growth region.

[0048] Figure 3(a) and 3(b) is a schematic diagram illustrating polishing the surface of a regrown layer prior to growth of a III-nitride device layer.

[0049] Figure 4(a) , 4(b), 4(c), 4(d) and 4(e) are diagrams Figure 1(a) , 1(b) , 1(c), 1(d) and 1(e) are schematic diagrams of alternative examples.

[0050] Figure 5(a) and 5(b) is a SEM image showing cracks that appear after coalescence of the ELO III-nitride layer.

[0051] Figure 6(a) and 6(b) It is a graphic Figure 1(d) and 1(e) Schematic diagram of an alternative example.

[0052] Figure 7 is a SEM image showing the void region formed after the regrown layer is grown.

[0053] Figure 8 is a SEM image illustrating how the void area is eliminated.

[0054] Figure 9(a) , 9(b) , 9(c), 9(d), 9(e) and 9(f) are diagrams Figure 1(d) , 1(e) , 1(f), 1(g) and 1(h) are schematic diagrams of alternative examples.

[0055] Figure 10(a) and 10(b) is a SEM image showing the etching below the void area.

[0056] Figure 11(a) and 11(b) is a schematic diagram illustrating etching beneath the void region.

[0057] Figure 12(a) , 12(b) , 12(c), 12(d) and 12(e) are schematic diagrams illustrating how a strip of devices is removed from a substrate.

[0058] Fig.13 is a schematic diagram illustrating the coating of facets on a device.

[0059] Figure 14(a) , 14(b) and 14(c) are schematic diagrams illustrating how to mount the device on a heat sink.

[0060] Figure 15(a) and 15(b) is a schematic diagram showing how to divide the components mounted on the heat sink.

[0061] Figure 16(a) and 16(b)is a schematic diagram illustrating how devices are screened and tested.

[0062] Fig.17 is a schematic diagram showing how to install the device in the TO-CAN package.

[0063] Fig.18 is a schematic diagram showing how to install the components in the module.

[0064] Figure 19(a),19(b),19(c),19(d),19(e),19(f),19(g),19(h),19(i),19(j), Figure 19(k) , 19(l) , 19(m) and 19(n) are schematic diagrams illustrating a method of using triangular gaps.

[0065] Figure 20(a) and 20(b) are SEM images illustrating non-uniform and uniform ELO Group III nitride layers grown along the opening regions.

[0066] Figure 21(a) , 21(b) 21(c) are SEM images and schematic diagrams illustrating the growth of an ELO III-nitride layer from an initial layer forming an inverted tapered facet.

[0067] Figure 22(a) , 22(b) , 22(c), 22(d), 22(e) and 22(f) are diagrams Figure 19(j) , 19(k) , 19(l), 19(m) and 19(n) are schematic diagrams of alternative examples.

[0068] Fig.23 is a schematic diagram illustrating how an area for forming a device avoids the center of a void area.

[0069] Fig.24 is a schematic diagram illustrating the structure of a polymer film.

[0070] Figure 25(a) and 25(b) is a schematic diagram illustrating a growth restriction mask and its opening area.

[0071] Figure 26(a) , 26(b) , 26(c), 26(d), 26(e), 26(f), 26(g) and 26(h) are schematic diagrams illustrating the use of a growth support layer deposited on a substrate.

[0072] Figure 27(a) , 27(b), 27(c), 27(d), 27(e), 27(f), 27(g) and 27(h) are schematic diagrams illustrating the use of a growth support layer deposited on a substrate.

[0073] Fig.28 is a flow chart illustrating a method of removing a strip of one or more devices from a substrate using a void region. DETAILED DESCRIPTION

[0074] In the following description of the preferred embodiments, reference is made to specific embodiments in which the invention may be practiced. It should be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0075] Method without growth limiting mask

[0076] The following procedure is for a method without a growth limiting mask.

[0077] Figure 1(a) , 1(b) , 1(c), 1(d), 1(e), 1(f), 1(g), 1(h), 1(i), 1(j) and 1(k) are schematic diagrams illustrating a method without a growth limiting mask according to an embodiment of the present invention. These structures include a III-nitride substrate 101, a growth limiting mask 102, an opening region 103, a non-growth region 104, an ELO III-nitride layer 105A, a regrown layer 105B, a III-nitride device layer 106, a void region 107, a ridge structure 108, a current blocking layer 109, a p-type electrode 110, a polymer film 111, a device strip 112, a break point 113 and an etched region 114.

[0078] These process steps and structures will be described in more detail below.

[0079] Step 1: A growth restriction mask 102 is deposited on a substrate 101 , with the remaining surface of the substrate 101 being exposed by stripe opening regions 103 in the growth restriction mask 102 , as shown in FIG. 1( a ) and FIG. 1( b ).

[0080] In addition, the present invention can use various template substrates 101, such as a III-nitride layer on a sapphire substrate 101, a silicon substrate 101 or a SiC substrate 101, and other substrates 101. For example, an ELO III-nitride layer 105A can be directly grown on a sapphire substrate 101 with a growth limiting mask 102. In these cases, the present invention can obtain almost the same results and effects.

[0081] Step 2: Using the growth restriction mask 102, an ELO III-nitride layer 105A is grown on the substrate 101, so that the growth extends in a direction parallel to the stripe opening region 103 of the growth restriction mask 102, and the ELO III-nitride layer 105A does not coalesce. Depending on the growth conditions of the ELO III-nitride layer 105A and the shape and size of the growth restriction mask 102, the non-growth region 104 can take a variety of shapes, such as Figure 2(a) , 2(b) , 2(c), 2(d), 2(e), 2(f) and 2(g), which are schematic diagrams and scanning electron microscope (SEM) images illustrating the shapes and sizes of the growth limit mask, the ELO III nitride layer and the non-growth area.

[0082] Figure 2(a) , 2(b) 2(c), the edge of the ELO III-nitride layer 105A is straight. Figure 2(d) , 2(e) , 2(f) and 2(g), the ELO III-nitride layer 105A has a meandering shape at its edge portion and a portion of the ELO III-nitride layer 105A is coalesced to the adjacent ELO III-nitride layer 105A. However, the ELO III-nitride layer 105A cannot be coalesced. Compared with the left side of FIG. 2(e) and the case shown in FIG. 2(f), the coalescence of the ELO III-nitride layer 105A shown in the right side of FIG. 2(e) and FIG. 2(g) is further advanced. Each of the cases of 2(a), 2(b), 2(c), 2(d), 2(e), 2(f) and 2(g) has at least an exposed region 104 where the growth limiting mask 102 is not covered with the ELO III-nitride layer 105A. Therefore, in the next process, the growth limiting mask 102 can be easily removed by wet etching. The etchant easily dissolves the growth limiting mask 102 through the exposed non-growth region 104.

[0083] As shown in FIG2(b), Wex is the width of the exposed non-growth region 104. Preferably, Wex is less than 6 μm so that the void region 107 can be properly formed by subsequent growth. A wider Wex has the possibility of causing the void region 107 to disappear because epitaxial growth may occur in the region where the growth restriction mask 102 is removed and exposed to the surface of the substrate 101. More preferably, the width of Wex is 3 μm or less.

[0084] Step 3: The substrate 101 having the ELO III-nitride layer 105A is removed from the MOCVD reactor, and then the growth limiting mask 102 is removed by a dry etching or wet etching method using an etchant such as hydrofluoric acid (HF) or buffered HF (BHF).

[0085] Step 4: Grow a regrown layer 105B on the ELO III-nitride layer 105A to form a void region 107 and planarize the surface of the layer 105B.

[0086] Step 5: growing a III-nitride device layer 106 on the regrown layer 105B, as shown in FIG. 1( f ), wherein the III-nitride device layer 106 comprises an island-shaped III-nitride layer, which can be used to manufacture a discrete device.

[0087] Step 5': Polishing the surface of the regrown layer 105B before growing the III-nitride device layer 106. In the present invention, this is an optional step, such as Figure 3(a) and 3(b) As shown, they are variations of FIG1(e). When the surface of the regrown layer 105B is rough as shown in FIG3(a), the surface can be polished by CMP or the like, as shown in FIG3(b). This makes the in-plane distribution of the layer thickness more uniform.

[0088] Step 6: A device is manufactured at a flat surface area of ​​the III-nitride device layer 106 by conventional methods, wherein a ridge structure 108, a current blocking layer 109, a p-electrode 110, a pad electrode, etc. are arranged at predetermined positions on the island-shaped III-nitride device layer 106, as shown in FIG. 1( g).

[0089] Step 7: Etch the III-nitride device layer 106, the regrown layer 105B and the ELO III-nitride layer 105A by a conventional dry etching method, as shown in FIG. 1(h).

[0090] Step 8: Remove the strip 112 of devices from the substrate 101 by:

[0091] Step 8.1: Attach the polymer film 111 to the strip 112 as shown in FIG. 1( i ).

[0092] Step 8.2: Apply pressure to the polymer film 111 and the substrate 101, as shown in FIG1(j).

[0093] Step 8.3: Lowering the temperature of the polymer film 111 and the substrate 101 while applying pressure.

[0094] Step 8.4: Using the thermal coefficient difference between the polymer film 111 and the substrate 101 to remove the strip 112 of the device, as shown in FIG. 1( k ).

[0095] Step 9: Fabricate n-electrodes on the strips 112 of the device.

[0096] Step 10: Breaking the strip 112 into separate devices.

[0097] Step 11: Mount each device on a heat sink.

[0098] Step 12: Coating the Facets of the Laser Diode Device

[0099] Step 13: Divide the Coating Strips.

[0100] Step 14: Screening devices.

[0101] Step 15: Mount the device on or into the package.

[0102] These steps are explained in more detail below.

[0103] There is another option, such as Figure 4(a) , 4(b) , 4(c), 4(d) and 4(e), which are shown in FIG. Figure 1(a) , 1(b) , 1(c), 1(d) and 1(e) are schematic diagrams of alternative examples. The method is almost the same as the above process except for step 3. In this method, by controlling the time of dissolving the growth limit mask 102, a portion of the growth limit mask 102 remains in step 3, as shown in FIG4(d). A short dissolving time can remove only the area below the no-growth area 104.

[0104] Even in this case, the void 107 may be included between the surface of the substrate 101 and the surface of the ELO III-nitride layer 105A. Before step 8, the remaining growth restriction mask 102 may be removed by wet etching with HF or BHF, as shown in FIG4(d). In this case, the void 107 may effectively release the stress from the growth restriction mask 102.

[0105] Depending on the growth conditions and time, the growth of the III-nitride device layer 106 on the ELO III-nitride layer 105A results in deformation of the edge of the void 107. Portions of the edge of the void 107 are shown as 113 in FIG. 4( d ). The remaining growth limit mask 102 avoids deformation of the edge of the void 107. This can improve the yield when removing the strip 112 from the substrate 101 by making the edge shape of the void 107 uniform.

[0106] Step 1: Deposit a growth limiting mask on the substrate

[0107] like Figure 1(a)-1(c) As shown, the c-plane GaN substrate 101 is made of SiO 2 The resulting growth restriction mask 102 is patterned. The growth restriction mask 102 comprises stripes along a <10-10> axis separated by open regions 103, although other axes may also be used.

[0108] The width of the stripes in the growth restriction mask 102 is 30 μm, more preferably 30 μm. The width of the opening region 103 is 2 μm, more preferably 4 μm.

[0109] Furthermore, these techniques can also be used with a GaN template grown as a 2-6 μm GaN underlayer on a foreign substrate 101. Alternatively, the GaN underlayer can be formed on a growth limiting mask 102.

[0110] Step 2: Grow the ELO III-nitride layer on the substrate using a growth-limiting mask

[0111] The ELO III-nitride layer 105A grows in the opening region 103 of the growth limiting mask 102 on the exposed surface of the substrate 101 or template. Preferably, the ELO III-nitride layer 105A does not coalesce on top of the growth limiting mask 102 and remains separated from each other.

[0112] MOCVD is used for the epitaxial growth of the ELO III-nitride layer 105A. Trimethylgallium (TMGa) is used as a III-group element source; ammonia (NH 3 ) is used as a raw material gas for supplying nitrogen; and hydrogen (H 2 ) and nitrogen (N 2 ) is used as a carrier gas for the source of the group III element. It is important to include hydrogen in the carrier gas to obtain a smooth surface of the epitaxial layer. The thickness of the ELO group III nitride layer 105A is about 3 μm and about II. The ELO group III nitride layer 105A may include a GaN or AlGaN layer to obtain a smooth surface.

[0113] Step 3: Remove the substrate from the MOCVD equipment

[0114] The substrate 101 having the ELO III-nitride layer 105A is removed from the MOCVD reactor to remove the growth limiting mask 102. The growth limiting mask 102 is removed by wet etching with HF, BHF or the like.

[0115] This step is important because when the growth limiting mask 102 is not removed, many cracks will appear after the ELO III-nitride layer 105A coalesces, such as Figure 5(a) and 5(b) 5( a ) and 5( b ) show a surface without cracks.

[0116] For example, SiO2 is generally used as the growth restriction mask 102.2 The ELO III-nitride layer 105A has a lower thermal expansion coefficient than the III-nitride layers 105A, 105B, 106. The difference in thermal expansion coefficients causes cracks to appear in the III-nitride layers 105A, 105B, 106. The time when the cracks appear is when the growth limit mask 102 is completely covered by the ELO III-nitride layer 105A. Therefore, the ELO III-nitride layer 105A is stopped before the growth limit mask 102 is completely covered.

[0117] There are two advantages in doing so: one is that it is easy to remove the growth limiting mask 102 by wet etching through the space between the strips 112; the other is that the void region 107 is retained after the regrown layer 105B is grown, which helps to release the internal stress and can reduce the occurrence of cracks.

[0118] Step 4: Grow a regrown layer on the ELO III-nitride layer to form a void region and planarize the surface of the layer

[0119] In this step, a regrown layer 105B is grown on the ELO III-nitride layer 105A to form a void region 107, as shown in Fig. 1(e). An unintentionally doped (UID) layer or a Si-doped layer may be used as the regrown layer 105B.

[0120] In addition, a Mg doped layer or a co-doped layer 301 of Mg and Si may be used as the regrown layer 105B, such as Figure 6(a) and 6(b) , they are shown in the figure respectively Figure 1(d) and 1(e) The growth of the Mg-containing III-nitride layer effectively buries the recessed region at the non-growth region 104 .

[0121] like Figure 7 As shown, which is a SEM image, a void region 107 may be formed after growing the regrown layer 105B.

[0122] However, depending on the growth conditions and the size of the growth limiting mask 102, there is the possibility of eliminating the void region 107, such as Figure 8 When the size of the void region 107 is smaller than a predetermined size, the regrown layer 105B buries the void region 107, as shown in 801. It has been found that the Mg doped layer or the co-doped layer of Mg and Si has the effect of allowing the void region 107 to remain after the regrown layer 105B is grown.

[0123] Step 5: Grow III-nitride device layers on the regrown layer

[0124] As shown in FIG1(f), the substrate 101 after the growth restriction mask 102 is removed is loaded into the chamber of the MOCVD reactor, where MOCVD is used for the epitaxial growth of the III-nitride device layer 106. Trimethylgallium (TMGa), trimethylindium (TMIn) and triethylaluminum (TMAl) are used as the III-group element sources; ammonia (NH 3 ) is used as a raw material gas for supplying nitrogen; and hydrogen (H 2 ) and nitrogen (N 2 ) is used as a carrier gas for the Group III element source. It is important to include hydrogen in the carrier gas to obtain a smooth surface of the epitaxial layer.

[0125] Salt and bis(cyclopentadienyl)magnesium (Cp 2 Mg) is used as n-type and p-type dopants. The pressure setting is typically 50 to 760 Torr. The III-nitride device layer 106 is typically grown in a temperature range of 700 to 1250°C.

[0126] For example, the growth parameters include the following: TMG is 12 sccm, NH 3 8slm, carrier gas 3slm, SiH 4 The growth conditions are 1.0 sccm and the V / III ratio is about 7700. These growth conditions are only an example and can be varied and optimized for each of the above layers.

[0127] Step 5': Polishing the surface of the substrate

[0128] There can also be another optional step, such as Figure 3(a) and 3(b) As shown, they are variations of FIG. 1( e ) in which the surface is polished by CMP or the like. Figure 9(a) , 9(b) , 9(c), 9(d), 9(e) and 9(f) are diagrams Figure 1(d) , 1(e) , 1(f), 1(g) and 1(h) are schematic diagrams of alternative examples. Specifically, Figure 9(a) , 9(b) 9(c) illustrate another variation of 1(d) and 1(e) in which polishing reduces the in-plane distribution of the thickness of each layer.

[0129] Step 6: Fabricate devices on the III-nitride device layer

[0130] The surface after the regrown layer 105B is flat, and a conventional device process such as a dry etching process, a wet etching process, a photolithography process, a deposition process, etc. may be used.

[0131] In one embodiment, the above-described processes may be used to fabricate a ridge structure 108 for a laser diode device, and a p-electrode 110 structure for LEDs and power devices such as SBDs, MOSFETs, photodiodes, etc.

[0132] The ridge process for laser diode devices is described in more detail below. The ridge depth (from the surface to the bottom of the ridge) is in the p-GaN guide layer. The ridge depth is predetermined based on simulation or previous experimental data before performing the dry etch. The present invention can be applied to any device on the regrown layer 105B.

[0133] The p-electrode 110 may be made of one or more of the following materials: Pd, Ni, Ti, Pt, Mo, W, Ag, Au, etc. For example, the p-electrode may include Pd-Ni-Au (having a thickness of 3-30-300 nm). These materials may be deposited by electron beam evaporation, sputtering, thermal evaporation, etc. In addition, the p-electrode 110 is typically deposited on an ITO coating.

[0134] Step 7: Etching the III-nitride device semiconductor layer, the regrown layer, and the ELO III-nitride layer

[0135] The etching of the III-nitride device layer 106, the regrown layer 105B, and the ELO III-nitride layer 105A can be performed by a conventional dry etching method, as shown in FIG. 1( h). The etching depth is at least to the void region 107 exposed by the etching. Preferably, the end point of the etching 901 is below the void region 107, as shown in FIG. Figure 10(a) and 10(b) and Figure 11(a) and 11(b) As shown, the Figure 10(a) and 10(b) is a SEM image showing etching 1001, 1002 below the void region 107. Figure 11(a) and 11(b) 1 is a schematic diagram illustrating etching 1001 below the void region. By doing so, it is easy to remove the strip 112 of the device from the substrate 101 because the stress from the polymer film 111, the plate and the substrate can be effectively applied to the fracture point 113.

[0136] When etching, Figure 1(h) , 10(a) As shown in FIG. 11( a), the etched region 114 may expose the void region 107. Figure 10(b) and 8 As shown, etched region 114 may not expose void region 107. When considering removal of strip 112, it is more preferred that strip 112 have void region 107 on at least one side of strip 112.

[0137] Step 8: Remove the device strips from the substrate

[0138] This step describes the removal of the strip 112, which can be adjusted by several methods. In order to remove the strip 112, stress is applied to the breaking point 113 in the direction indicated by the arrow shown in Figure 1 (k). The material to which the stress is applied can be a polymer film 111, a plate, a substrate, etc. This article describes a method using a polymer tape 111, but the present invention is not limited to this method. In addition, the applied stress can utilize thermal expansion, mechanical force, etc.

[0139] In this step, in order to remove the strips 112, stress is applied to the strips 112 from the polymer film 111, the plate, the substrate, etc. At that moment, the strips 112 are slightly moved by the applied stress. Therefore, as shown in FIG. 1( h), the etching width L needs to be at least 2 μ, more preferably 5 μ. L is defined as the distance between two adjacent strips 112 at the top of the strips 112, as shown in FIG. 1( h).

[0140] From here, use Figure 1(i) , 1(j) and 1(k) explain the process of removing strip 112.

[0141] Step 8.1 includes attaching the polymer film 111 to the strip 112, as shown in Figure 1(i).

[0142] Step 8.2 includes applying pressure to the polymer film 111 and the substrate 101, as shown in FIG1(j). The purpose of applying pressure is to place the polymer film 111 between the strips 112. The polymer film 111 is softer than the strips 112, so the polymer layer 111 can easily surround the strips 112. Preferably, the polymer film 111 is heated to soften it, which makes it easier for the polymer film 111 to cover the strips 112. The force from the polymer film 111 is effectively applied to the breaking point 113.

[0143] Step 8.3 comprises reducing the temperature of the membrane 111 and the substrate 101 while maintaining the applied pressure. It is not necessary to increase the applied pressure during the temperature change.

[0144] Step 8.4 includes removing the strips 112 of the device by taking advantage of the thermal coefficient difference between the polymer film 111 and the substrate 101 .

[0145] As shown in FIG. 1( k ), the polymer film 111 shrinks as the temperature decreases. Therefore, as shown in FIG. 1( j ), the bottom of the polymer film 111 is lower than the top of the strip 112. In this case, the polymer film 111 can apply pressure in the horizontal direction on the side face of the strip 112. Such pressure applied to the side face allows the strip 112 to be effectively removed from the substrate 101 because the pressure is ultimately applied to the breaking point 113 by generating the void region 107. During low temperatures, the polymer film 111 maintains the applied pressure from the top of the film 111 to the strip 112. By doing so, the present invention can utilize the void region 107 to remove the strip 112 from the substrate 101.

[0146] Various methods can be used to reduce the temperature. For example, the substrate 101 and the polymer film 111 can be placed in a liquid N 2 The temperature of the substrate 101 and the membrane 111 can also be controlled using a piezoelectric transducer.

[0147] Furthermore, the plate applying pressure to the polymer film 111 may be cooled to a low temperature before and / or during contact with the polymer film 111. By doing so, the polymer film 111 is cooled and may apply pressure to the strip 112 due to a large thermal expansion coefficient.

[0148] When the temperature is lowered, the substrate 101 and the film 111 may be wetted by atmospheric humidity. In this case, the substrate 101 and the film 111 may be wetted by atmospheric humidity. 2 The temperature is lowered in the atmosphere, which prevents the substrate 101 and the film 111 from getting wet.

[0149] Thereafter, the temperature is raised, for example, to room temperature, and no pressure is applied to the film 111. At that time, the strip 112 has been removed from the substrate 101, and then the polymer film 111 is separated from the substrate 101. When the polymer film 111, especially the polymer film 111 with an adhesive, is used, the device or chip can be removed in a simple and fast manner using the polymer film 111.

[0150] This method of using adhesive film 111 and substrate 101 with ELO III-nitride layer 105A can be repeated multiple times. If some strips 112 remain on substrate 101, repeating the method even for 2-inch, 4-inch or larger sized wafers allows the remaining strips 112 to be completely removed from substrate 101.

[0151] Step 9: Deposition of n-electrode

[0152] After removing the strip 112 from the substrate 101, the strip 112 is attached to the UV dicing tape 111 in an inverted manner as shown in FIG12(a). A metal mask 1201 can be used to place an n-electrode 1202 on the back side of the strip 112 as shown in FIG12(b).

[0153] Typically, the n-electrode 1202 is made of the following materials: Ti, Hf, Cr, Al, Mo, W, Au. For example, the n-electrode can be made of Ti-Al-Pt-Au (thickness is 30-100-30-500 nm), but is not limited to these materials. The deposition of these materials can be performed by electron beam evaporation, sputtering, thermal evaporation, etc.

[0154] In the case of forming n-electrode 1202 on the back side of strip 112 after removing strip 112 from substrate 101, n-electrode 1202 is preferably formed on an area on the back side of strip 112 where n-electrode 1202 remains in good surface condition to obtain low contact resistivity.

[0155] The n-electrode 1202 may also be disposed on the top surface of the strip 112, which is the same surface made for the p-electrode.

[0156] Step 10: Break the Strips into Devices

[0157] After providing the n-electrode 1202, the strip 112 can be segmented into a plurality of devices 1203, as shown in FIG12(c). The segmentation support region helps segment the strip 112 into the devices 1203.

[0158] Step 11: Mount Each Device on a Heat Sink

[0159] After step 8, the separated strips 112 are still on the polymer film 111. In one embodiment, a UV-sensitive dicing tape can be used as the polymer film 111. In this case, the UV-sensitive dicing tape is exposed to ultraviolet (UV) light, which reduces the adhesive strength of the tape, as shown in FIG12( d). This makes it easy to remove the chip from the UV-sensitive dicing tape.

[0160] In this case, a heat sink 1204 made of AlN is prepared. Au-Sn solder 1205 is provided on the heat sink, and the device 1203 removed from the UV-sensitive dicing tape 111 is mounted on the heat sink 1204 at the Au-Sn solder 1205 between the grooves 1206 in the heat sink 1204. At this time, the heat sink 1204 heated to above the melting temperature of the solder 1205 can mount the device 1203. The device 1203 can be mounted in two ways, either with the n-electrode side facing down or with the p-electrode side facing down. FIG. 12( e) shows the device 1203 mounted to the heat sink 1204 with the n-electrode 1202 side facing down and the p-electrode side 110 facing up with the facet 1207 exposed.

[0161] Step 12: Coating the Laser Device Facets

[0162] The next step in the device 1203 processing includes coating the facets 1207. When the laser device is emitting laser light, light in the device that penetrates through the facets of the device to the outside of the device is absorbed by non-radiative recombination centers at the facets, causing the facet temperature to continue to rise. Therefore, the temperature increase may cause catastrophic optical damage (COD) to the facets.

[0163] Facet coating can reduce non-radiative recombination centers. To prevent COD, facets need to be coated with dielectric layers such as AlN, AlON, Al 2 O 3 、SiN、SiON、SiO 2 、ZrO 2 、TiO 2 、 2 O 5 Etc. In general, the coating film is a multilayer structure composed of the above materials. The structure and thickness of the layer are determined by the predetermined reflectivity.

[0164] The strips 112 of the devices 1203 have been separated in step 10 to obtain the cleaved facets 1207. As a result, a method for coating the facets 1207 on a plurality of devices 1203 simultaneously in a simple manner is needed. In the facet 1207 coating process, the devices 1203 are mounted on the heat sink 1204 in a low horizontal position before coating, as shown in FIG. 12( e). Then, as shown in FIG. Fig.13 As shown, the device 1203 is mounted on a coating bar 1301, which may be placed on a spacer plate, and a plurality of coating bars 1301 are stored in a coating support 1302. Note that it is not always necessary to use a spacer plate, and the coating bars 1301 may be used alone.

[0165] By doing so, multiple devices 1203 can be coated simultaneously. In one embodiment, facet 1207 coating is performed at least twice: the first time for the front facet 1207, and the second time for the rear facet 1207. The length of the heat sink 1204 is set almost to the cavity length of the laser diode device 1203, which makes it easy and fast to perform two coatings. Once the coating bar 1301 is set in the coating holder 1302, two facets 1207 can be coated without setting the coating bar 1301 in the coating holder 1302 again. In one embodiment, the first coating is performed on the front facet 1207 that emits the laser, and the second coating is performed on the rear facet 1207 that reflects the laser. The coating holder 1301 is flipped in the holder 1302 where the coating film is deposited before the second coating. This substantially reduces the lead time of the process.

[0166] Step 13: Divide the Coating Strips.

[0167] like Figure 14(a) ,14(b) As shown in Fig. 14(c), the heat sink 1204 is divided at the grooves 1206 formed on the surface of the heat sink 1204, for example, between one or more devices 1203. Fig. 15 further shows how the heat sink 1204 is divided to separate the devices 1203. By doing so, it is easy to separate the devices 1203 after the coating process.

[0168] Step 14: Screening Devices

[0169] This step distinguishes defective and non-defective devices. First, various characteristics of the device are tested under given conditions; such as output power, voltage, current, resistivity, FFP (far field pattern), slope-efficiency, etc. At this time, the chip is already mounted on the heat sink, so it is easy to test these characteristics. As shown in Figure 14 (a), the wire bonds 1401, 1402 to the probe contact the p-electrode 110 and the solder 1205 that has electrical continuity with the n-electrode 1202. Then, non-defective devices 1203 can be selected and screened through aging tests (life tests).

[0170] As shown in Figure 16, preferably, the aging test is performed in a box sealed in a dry air or nitrogen atmosphere. The heating stage maintains the temperature of the device through a heat sink during the screening test, such as 60 degrees, 80 degrees, etc. A photodetector can be used to measure the optical output power, which identifies a non-defective device with a constant output power, or identifies a defective device.

[0171] In particular, in the case of III-nitride laser diode devices, it is well known that when the laser diode oscillates in an atmosphere containing moisture, it deteriorates. This degradation is caused by moisture and siloxane in the air, so it is necessary to seal the III-nitride laser diode device in dry air during the aging test. Therefore, when the III-nitride laser diode is shipped from the device manufacturer, the laser diode is already sealed in a dry air atmosphere by using a TO-CAN package, such as Fig.17 shown.

[0172] Screening or burn-in test

[0173] Generally speaking, screening or aging tests are performed before shipment in order to screen out defective products. For example, screening conditions are performed according to the specifications of laser devices such as high temperature and high power.

[0174] Additionally, burn-in testing is performed with the device mounted on / into a package that is sealed in dry air and / or dry nitrogen prior to screening, such as Figure 16(a) and 16(b) This fact limits the flexibility of packaging and mounting of laser devices.

[0175] In the prior art, if a defective product appears, the defective product is discarded in the entire TO-CAN package, such as Fig.17 As shown, this is a great loss for manufacturing. This makes it difficult to reduce the manufacturing cost of laser diodes. It is necessary to detect defective devices at an early step.

[0176] Advantages of heat sink

[0177] Heat Sink 1204 provides many advantages and benefits:

[0178] The facets 1207 of the device 1203 are coated using a heat sink 1204 on which multiple devices 1203 can be mounted in a low horizontal position, and then the heat sink 1204 is segmented using grooves 1206 after the coating process to separate the device 1203 from the sub-mount, which allows the device 1203 with the sub-mount to be inspected in a screening test in a dry gas or nitrogen atmosphere.

[0179] When the screening test is performed, the device 1203 already has two contacts, namely, the p-electrode 110 on the heat sink 1204 and the solder 1205, or in the case of flip chip bonding, the n-electrode 1202 on the heat sink 1204 and the solder 1205. In addition, when the device 1203 is composed of only a chip and a base, the present invention can use the screening test to select defective products. Therefore, in the case of discarding defective products, the present invention can reduce losses more significantly than the prior art, which is of great value.

[0180] As shown in FIG. 14( c ), in the case of screening high-power laser diode devices, preferably, the heat sink 1204 has two parts of solder 1205 that are arranged to have no electrical continuity. One part of the solder 1205 is connected to the p-electrode 110 through the wire 1403, and the other part of the solder 1205 is connected to the n-electrode 1202. In this way, a probe 1404 for applying a current to the device 1203 can be used, which can avoid direct contact with the p-electrode 110 and the n-electrode 1202, which is crucial in the case of applying a high current for screening high-power laser diodes. The probe 1404 does not directly contact the electrodes 110, 1202, which would damage the contacted parts, especially in the case of applying a high current density.

[0181] Step 15: Mount the device on or into the package

[0182] like Fig.18As shown, device 1801 can be installed in a package. The solder (Au-Sn, Sn-AG-Cu, etc.) or bonding metal arranged at the bottom of the package is bonded to the solder on the heat sink by wires, such as AlN, SiC, etc. The pins of the package are connected to the solder on the heat sink by wires. By doing so, a current from an external power supply can be applied to the device. This is more preferred than the bonding between the package and the heat sink performed by metal bonding such as Au-Au, Au-In, etc. This method requires flatness at the surface of the package and at the back of the heat sink. However, in the absence of solder, the configuration achieves high thermal conductivity and low temperature bonding. These are great advantages of device technology.

[0183] In addition, a phosphor can be provided outside and / or inside the package. By doing so, the module can be used as a light bulb or a headlight.

[0184] As described herein, these processes provide an improved method for obtaining laser diode devices. Furthermore, once the device is removed from the substrate, the substrate can be recycled multiple times. This achieves the goal of environmentally friendly production and low-cost modules. These devices can be used as lighting devices such as light bulbs, data storage devices, optical communication devices such as Li-Fi, etc.

[0185] It is currently difficult to package multiple lasers of different types in one package. However, this method can overcome this problem because it can perform aging tests without packaging. Therefore, in the case of installing different types of devices in one package, it can be easily installed.

[0186] Manufacturing LED devices

[0187] In the case of making LED devices, the same process can be used until step 6. This discussion briefly explains how to make two types of LEDs. Type 1 LEDs have two electrodes (p-electrode and n-electrode) on one side of the chip, while type 2 LEDs have one electrode on the opposite side of the chip.

[0188] First, in the case of a Type 1 LED, p-electrodes and n-electrodes are formed on the top surface of the device in step 6. Then, the strip of devices is removed, and the removed chips are mounted on a package and a heat sink as described in step 8. The backside surface of the chip, the package, and the heat sink are bonded using silver paste.

[0189] Secondly, in the case of type 2 LED, almost the same process is used before step 6, where an ITO electrode is formed on the p-GaN contact layer. In this case, the method of dividing the strips is the same. In addition, it is preferred that the layer bending area is eliminated.

[0190] Method using triangular gap

[0191] The following process is for a method using triangular voids.

[0192] Figure 19(a) , 19(b) ,19(c),19(d),19(e),19(f),19(g),19(h),19(i),19(j), Figure 19(k) , 19(l) , 19(m) and 19(n) are schematic diagrams illustrating a method using triangular gaps, which is similar to a method without a growth limiting mask. However, steps 2 to 4 of the method using triangular gaps are different from those of the method without a growth limiting mask.

[0193] Step 2': Grow the ELO III-nitride layer on the substrate using a growth-limiting mask

[0194] The ELO III-nitride layer 105A is initially grown 1901 on the opening region 103. Preferably, the surface of the initial growth layer is higher than the surface of the growth limit mask 102. When the growth conditions are optimized to achieve a high lateral growth rate, the growth of the ELO III-nitride layer 105A sometimes cannot be performed on the growth limit mask 102 due to the height of the growth limit mask 102. In this case, a uniform ELO III-nitride layer 105A cannot be grown along the opening region 103, as shown in FIG20(a). However, when the height of the initial growth layer is higher than the height of the growth limit mask 102, the uniformity of the ELO III-nitride layer 105A can be grown, as shown in FIG20(b).

[0195] The ELO III-nitride layer 1902 is grown from the initial layer 1901. The low V / III growth conditions accelerate the growth rate in the lateral direction and help form an inverted cone facet. The inverted cone facet is {11-2-2}, such as Figure 21(a) , 21(b) and 21(c). During the growth of the ELO III-nitride layer, the {11-2-2} facets appear, but before coalescence, the {11-2-2} facets are tilted due to the change in growth conditions caused by the proximity of each ELO III-nitride layer 105A. However, the inverted tapered facets help to generate triangular voids 2101 in the ELO III-nitride layer 105A, as shown in FIG. Figure 21(a) and 21(b) shown. Figure 21(a) and 21(b) 1 and 2 are cross-sectional and bird's-eye SEM images of the ELO III-nitride layer 105A after coalescence, respectively. Once the ELO III-nitride layer 105A coalesces in this case, the triangular voids do not disappear even if growth continues.

[0196] MOCVD is used for the epitaxial growth of the ELO III-nitride layer 1902. Trimethylgallium (TMGa) is used as the III-element source; ammonia (NH 3 ) is used as a raw material gas for supplying nitrogen; and hydrogen (H 2 ) and nitrogen (N 2 ) is used as a carrier gas for the source of the group III element. It is important to include hydrogen in the carrier gas to obtain a smooth surface of the epilayers. The thickness of the ELO group III nitride layer 105A is about 1 μm and about 1 μm. In addition, the ELO group III nitride layer 1902 can include GaN or AlGaN, InGaN, InAlGaN layers to obtain a smooth surface.

[0197] The triangular voids 107 can effectively release stress caused by the difference in thermal expansion coefficients between the III-nitride layers 105A, 105B, 106 and the growth limit mask 102. The voids 107 formed by doing so appear directly on the growth limit mask 102 and are surrounded by the growth limit mask 102 and the ELO III-nitride layer 105A, which can effectively release stress from the growth limit mask 102. In addition, since the height of the voids 107 is higher than the voids 107 manufactured without the growth limit mask 102, the triangular voids 107 are more preferable in terms of releasing stress. In an additional advantage, the voids 107 can be formed without interrupting the growth.

[0198] After coalescence, those voids 107 prevent cracks from appearing in the ELO III-nitride layer 105A. In addition, the ELO III-nitride layer 105A substantially covers the growth limit mask 102, which prevents the p-type layer from being compensated due to the decomposition of the growth limit mask 102.

[0199] Step 3: Flatten the surface above the void

[0200] Just after the ELO III-nitride layer 105A coalesces, the above-mentioned recessed portion 1903 of the void 107 has a depth of more than 100 nm. In order to flatten the surface, it is preferred to grow a flat layer 1904 on the ELO III-nitride layer 1902. The thickness of the flat layer 1904 is at least 1 μ, more preferably more than 2 μ, to improve the flatness of the epitaxial layer surface. If the recessed portion 1903 cannot be flattened before the III-nitride device layer 106 is grown, this sometimes leads to fluctuations in the components of In, Al, etc. at or near the recessed portion 1903. The depth of the recessed portion 1903 is preferably at most 50 nm, more preferably less than 30 nm. In order to flatten the surface, a flat layer 1904 is grown. This layer 1904 is an unintentionally doped (UID) layer or a Si-doped layer. In addition, a Mg-doped layer or a layer 301 co-doped with Mg and Si can be used as a III-nitride layer. Mg-doped growth is effective for burying the recessed portion 1903. Furthermore, there is no problem in polishing the surface of the flat layer 1904 to obtain a flatter surface.

[0201] Step 4: Growing III-nitride device layers on the planar layer

[0202] As shown in FIG. 19( g ), the III-nitride device layer 106 is continuously grown on the flat layer 1904. The III-nitride device layer 106 is typically grown at a temperature in the range of 700 to 1250° C. For example, the growth parameters include the following: TMG is 12 sccm, NH 3 8slm, carrier gas 3slm, SiH 4 The growth conditions are 1.0 sccm and the V / III ratio is about 7700. These growth conditions are only an example and can be varied and optimized for each of the above layers.

[0203] After performing step 4, the method performs step 6 as described above and then performs step 7 as described below.

[0204] Step 7: Etching the III-nitride device semiconductor layer, planarization layer, and ELO III-nitride layer

[0205] The etching of the III-nitride device layer 106, the planarization layer 1904, and the ELO III-nitride layer 1902 can be performed by conventional photolithography and dry etching methods, such as Figure 19(i) and 19(j) Photoresist 1905 is patterned to etch the above-mentioned portion of void 107, but other materials may also be used.

[0206] The depth of the etching is at least to the top of the void region 107 exposed by the etching. By doing so, the epitaxial layer can be segmented like strips 112. To facilitate the removal of strips 112, the growth limit mask 102 is removed by wet etching, as shown in Figure 19(k).

[0207] After dissolving the growth limit mask 102, the strip 112 is processed the same as in step 8 above, such as Figure 19(l) , 19(m) , as shown in 19(n).

[0208] Can be used Figure 22(a) , 22(b) , 22(c), 22(d), 22(e) and 22(f) are process removal bars that illustrate Figure 19(j) , 19(k) , 19(l), 19(m) and 19(n) are schematic diagrams of alternatives. In this process, the upper portion of the gap 107 and the upper portion of the opening area 103 are removed by etching. Figure 22(a) and 22(b) As shown, these can be etched by a dry etching process. At this time, if the etching area at the opening area 2201 reaches the growth restriction mask 102, the strip 112 can be separated from the substrate 101. The hook layer 2202 (e.g., SiO 2 The photoresist 1905 is dissolved to allow the hook layer 2202 on the photoresist to be peeled off, as shown in FIG. 22( d ).

[0209] The hook layer 2202 has two purposes. One purpose is to temporarily fix the strip 112 on the growth restriction mask 102 to avoid stripping of the strip 112 during the ultrasonic solvent dissolution of the photoresist. Secondly, using a dielectric material as the hook layer 2202 can passivate the side facets of the strip 112. Depending on the etching conditions, the side facets of the strip 112 are sometimes damaged by dry etching. If the width of the strip 112 is narrow, leakage current is generated at the side facets of the strip due to etching damage, which may affect the characteristics of the device. Materials can be selected to reduce the leakage current of the side facets, for example, SiO 2 、SiON、SiN、Al 2 O 3 、AlON、AlN、ZrO 2 、 2 O 3 etc.

[0210] The strength of the fixation can be varied by varying the thickness of the hook layer 2202. The strength of not removing the strip 112 during ultrasonic or post-processing, etc. can be controlled.

[0211] It can be removed using step 8 mentioned above as shown in Figure 22(e). It can be removed in a different way, as shown in Figure 22(f). This way is to use a support plate 2203 with solder 2204. The use of solder 2204 on the support plate 2203 can be joined to the strip 112. Conventional joining methods can also be used. Typically, the joining process will increase the temperature during the joining process. If Au-Sn solder is used, the joining temperature is about 280°C. After bonding, when the temperature drops to room temperature, the thermal stress from the different thermal expansion coefficients can destroy the hook layer 2202.

[0212] Since the bonding strength at the interface of the ELO III-nitride layer 1902 and the growth limiting mask 102 is not strong, the strip 112 can be easily separated from the substrate 101 for removal. In addition, an ultrasonic process can be used to break the hook layer 2202. In this case, the break point of the hook layer 2202 is marked with an arrow in FIG. 22( f).

[0213] By doing so, the strip 112 can be removed from the substrate 101. Before the packaging process, it can be the same as the process without the growth limiting mask 102.

[0214] Definition of terms

[0215] III-Nitride-Based Substrates

[0216] As long as the III-nitride-based substrate 101 is capable of growing a III-nitride-based semiconductor layer through the growth restriction mask 102, any GaN substrate sliced ​​on the {0001}, {11-22}, {1-100}, {20-21}, {20-2-1}, {10-11}, {10-1-1} plane or other planes and from bulk GaN and AlN crystals can be used.

[0217] Heterogeneous Substrate

[0218] In addition, the present invention can also use a heterogeneous substrate 101 for devices. For example, a GaN template or other III-nitride-based semiconductor layer can be grown on a heterogeneous substrate 101, such as sapphire, Si, GaAs, SiC, etc., for use in the present invention. The GaN template or other III-nitride-based semiconductor layer is typically grown on the heterogeneous substrate 101 to a thickness of about 2-6μ-, and then a growth restriction mask 102 is set on the GaN template or other III-nitride-based semiconductor layer. The growth restriction mask is formed directly on a heterogeneous substrate, such as sapphire, silicon and SiC, as another option. In this case, the initial growth layer or ELO III-nitride layer 105A is grown directly on the heterogeneous substrate with the growth restriction mask. Therefore, the substrate does not have to have a GaN layer.

[0219] Growth restriction mask

[0220] The growth restriction mask 102 includes a dielectric layer such as SiO 2 、SiN、SiON、Al 2 O 3 、AlN、AlON、MgF、ZrO 2 The growth restriction mask 102 may be a laminated structure selected from the above materials. It may also be a multi-stacked layer structure selected from the above materials.

[0221] The growth limiting mask 102 is deposited by sputtering, electron beam evaporation, plasma enhanced chemical vapor deposition (PECVD), ion beam deposition (IBD), etc., but is not limited to these methods.

[0222] The thickness of the growth limiting mask 102 is about 0.05-3.0. The width of the mask 102 is preferably greater than 20 μm, more preferably greater than 40 μm. The length of the opening region 103 is, for example, 200 to 35000 μm, and the width is, for example, 2 to 180 μm.

[0223] In one embodiment, the growth limit mask 102 is made of 1 μm thick SiO 2 The film is constituted in which the length of the opening area 103 is 1200 μm; the width is 15-25 μm; the interval between the opening areas 103 is 55-85 μm; and the width of the mask 102 part is 40-60 μm.

[0224] Direction of the growth restriction mask

[0225] On a c-plane free standing GaN substrate 101, stripe opening regions 103 are periodically arranged at first intervals and second intervals in a first direction parallel to the 11-20 direction (a-axis) of the substrate 101 and in a second direction parallel to the 1-100 direction (m-axis) of the substrate, and extend in the second direction.

[0226] On the m-plane independent GaN substrate 101, the opening areas 103 of the stripes are periodically arranged at first intervals and second intervals in a first direction parallel to the 11-20 direction (a-axis) of the substrate 101 and in a second direction parallel to the 0001 direction (c-axis) of the substrate 101, respectively, and extend in the second direction.

[0227] On the semipolar (20-21) or (20-2-1) GaN substrate 101, the opening regions 103 are arranged in directions parallel to [-1014] and [10-14], respectively.

[0228] Alternatively, a heterogeneous substrate 101 may be used. When a c-plane GaN template is grown on a c-plane sapphire substrate 101, the opening region 103 is in the same direction as the GaN substrate 101 independent of the c-plane; when an m-plane GaN template is grown on an m-plane sapphire substrate 101, the opening region is in the same direction as the GaN substrate 101 independent of the m-plane. By doing so, the m-plane cleavage plane can be used to divide the strips 112 of the device with the c-plane GaN template, and the c-plane cleavage plane can be used to divide the strips 112 of the device with the m-plane GaN template; this is more preferred.

[0229] The width of the opening 103 is typically constant in the second direction, but may vary in the second direction as desired.

[0230] Growth support layer

[0231] A growth support (GS) layer may be used with the substrate 101. The growth support layer may be any semiconductor alloy layer, any dielectric layer, and any insulating layer that supports the growth of a III-nitride layer on top of the growth support layer. Some potential candidates for the growth support layer include AlN, CrN, BN, GaN, ZnO, Ga 2 O 3 etc., but not limited to these materials. The typical thickness of the growth support layer is about 10nm-1000nm. Once the growth support layer is placed on the growth restriction mask 102 area or replaces the dielectric layer, the entire semiconductor substrate 101 can grow a group III nitride layer without the need for growth interruption.

[0232] III-nitride semiconductor layer

[0233] The ELO III-nitride layer 105A and the III-nitride device layer 106 are Figure 1(a)-1(k) , and includes III-nitride based semiconductor layers. These layers may include In, Al and / or B, as well as other impurities such as Mg, Si, Zn, O, C, H, etc.

[0234] The III-nitride device layer 106 generally includes more than two layers, including at least one of an n-type layer, an undoped layer, and a p-type layer. The III-nitride device layer 106 specifically includes a GaN layer, an AlGaN layer, an AlGaInN layer, an InGaN layer, and the like.

[0235] Semiconductor Devices

[0236] Semiconductor devices include, for example, Schottky diodes, light emitting diodes, laser diodes, photodiodes, transistors, etc., but are not limited to these devices. The present invention is particularly useful for micro-LEDs and laser diodes, such as edge-emitting lasers and vertical cavity surface-emitting lasers (VCSELs). The present invention is particularly useful for semiconductor lasers with split facets. In a semiconductor device, a plurality of electrodes according to the type of semiconductor device are arranged at predetermined positions.

[0237] Device forming area

[0238] In the present invention, the region 2301 where the device is formed preferably avoids the center of the gap region 107, such as Fig.23 This region includes a high density of dislocations because the coalescence of the ELO III-nitride layer 105A occurs at the center of the void region 107. More preferably, the device is formed in a region about 5 μm from the center of the void region 107. In the case of a laser diode device, the ridge of the laser structure is preferably located at the region where the device is formed.

[0239] Polymer film

[0240] The polymer film 111 is used to remove the III-nitride device layer 106 , the regrown layer 105B, and the ELO III-nitride layer 105A from the substrate 101 .

[0241] In the present invention, a dicing tape including a commercially available UV-sensitive dicing tape may be used as the polymer film 111. For example, the structure of the polymer film 111 may include Fig.24 The double layer 2410, 2402 or triple layer is shown, but is not limited to these examples. The base film material 2401 has a thickness of about 115 μm, for example, and can be made of polyvinyl chloride (PVC). For example, the adhesive layer 2402 has a thickness of about 40 μm and can be made of an acrylic UV sensitive adhesive.

[0242] When the UV sensitive dicing tape is exposed to UV light, the stickiness of the tape drops dramatically. After the strip 112 is removed from the substrate 101, the UV sensitive dicing tape is exposed to UV light, which makes it easy to remove.

[0243] Heat sink

[0244] The removed strip 112 is transferred to a heat sink 1204, which may be AlN, SiC, Si, Cu, CuW, etc. As shown in FIG12( d ), a solder 1205 for bonding, which may be Au-Sn, Su-Ag-Cu, Ag paste, etc., is provided on the heat sink 1204. Then, the n-electrode 1202 or the p-electrode 110 is bonded to the solder 1205. The device 1203 may also be flip-chip bonded.

[0245] In the case of bonding the LED to the heat sink 1204, the size of the heat sink 1204 is not critical and can be designed as desired.

[0246] In the case where the LD is bonded to the heat sink 1204, it is preferred that the length of the heat sink 1204 is equal to or shorter than the length of the LD used for the facet 1207 coating process, wherein the length of the LD is almost the same as the length of the laser cavity. By doing so, it is easy to coat both facets 1207 of the laser cavity. If the length of the heat sink 1204 is longer than the laser cavity, the heat sink 1204 may prevent uniform coating of the facets 1207.

[0247] Length and width of heat sink

[0248] The length and width of the heat sink plate 1204 makes the process of manufacturing the laser device more efficient. Fig.13 As shown, heat sink 1204 is placed on coating bar 1301 and then stacked with other coating bars 1301 in coating holder 1302 for simultaneous coating of facets 1207 of multiple devices 1203. Thus, a single coating process can coat many devices 1203.

[0249] Heat sink with grooves

[0250] Preferably, the heat sink 1204 has grooves 1206 for dividing the device 1203, as shown in Figure 12 (d). This structure is useful after the facet 1207 coating process, in which the heat sink 1204 is divided into one or more devices 1203, such as a single device 1203 or an array of devices 1203. After dividing the heat sink 1204, the device 1203 can be manufactured into a module, such as a lighting module. The grooves 1206 in the heat sink 1204 guide the division of the device 1203. The grooves 1206 can be formed by a wet etching method and mechanically processed before the device 1203 is installed. For example, if the heat sink 1204 is made of silicon, wet etching can be used to form the grooves 1206. Using the grooves 1206 in this way reduces the lead time of the process.

[0251] Heat sink with solder

[0252] Preferably, the length of solder 1205 is shorter than the length of device 1203 on heat sink 1204, as shown in FIG12(e). This prevents any wrapping of solder 1205 around facet 1207, which may result in degradation of the characteristics of device 1203. In particular, wrapping should be avoided during flip chip mounting.

[0253] like Figure 14(a) and 14(b)As shown, after the coating process, the strip of the heat sink 1204 has a surrounding area, which is the area surrounded by the dotted line. The width W of the surrounding area is about 10-20 μm. The coating film will have coated these areas. It is also difficult to avoid coating the solder 1205 with the coating film. Typically, the coating film is selected from one or more dielectric materials, which is why this area is not conductive. When the lead is bonded to the solder 1205, this is a problem for both conductivity and adhesion. Therefore, it is preferred to place the lead in a position avoiding the surrounding area. At least, the place where the lead is bonded should be about 25 μm away from the edge of the heat sink 1204.

[0254] Alternative Embodiments

[0255] First embodiment

[0256] The III-nitride based semiconductor device and the method for manufacturing the same according to the first embodiment are explained. The process of the device is substantially as described above.

[0257] exist Figure 1(a)-1(b) In the first embodiment shown in , a substrate 101 is first provided, and a growth restriction mask 102 having a plurality of stripe opening regions 103 is formed on the substrate 101 .

[0258] In this embodiment, the substrate 101 is a c-plane substrate composed of a III-nitride semiconductor having a -0.4 degree misalignment orientation toward the m-axis. Figure 25(a) and 25(b) In the embodiment, the width Wo of the opening region 103 and the width Wr of the growth restriction mask 102 are set to 10 μm and 10 μm, respectively. The thickness of the growth restriction mask 102 is 0.22 μm, and the width of the etching region L is 20 μm.

[0259] In this embodiment, the process is as follows Figure 1(a)-1(e) As shown in FIG. 5( b ), the present invention achieves a flat surface without cracks after the regrown layer 105B is grown, including the void region 107 . Figure 1(f) , 1(g) , 1(h), 1(i), 1(j), and 1(k) to remove strip 112.

[0260] Second embodiment

[0261] In the second embodiment, the substrate 101 is a c-plane substrate composed of a III-nitride semiconductor with a -0.2 degree misalignment orientation toward the m-axis. In this embodiment, the width Wo of the opening region 103 and the width Wr of the growth restriction mask 102 are set to 25 μm and 55 μm, respectively. The thickness of the growth restriction mask 102 is about 1.0 μm. The width of the etching region L is 20 μm. By doing so, it is possible to obtain a larger size of the strip 112. In this case, the strip 112 includes a void region 107, which makes it easy to remove.

[0262] Third embodiment

[0263] In the third embodiment, different types of regrown layers 105B may be used. In the first embodiment, an unintentionally doped layer or a Si doped layer is used as the regrown layer 105B. In the third embodiment, a Mg doped layer 601 is used as the regrown layer 105B, such as Figure 6(a) and 6(b) Said, it is Figure 1(d) and 1(e) The regrown layer 105B can effectively bury the recessed area at the non-growth area 104 .

[0264] However, if Figure 8 As shown, depending on the growth conditions and the size of the growth limit mask 102, it is possible to make the void region 107 disappear. In this case, the size of the void region 107 is smaller than the predetermined size, and the regrown layer 105B buries the void region 107. It has been found that when the void region 107 remains after the growth of the regrown layer 105B, the regrown layer 105B as a Mg doped layer or a co-doped Mg and Si layer has this effect. In this regard, it is preferred that the regrown layer 105B contains a Mg dopant.

[0265] Another advantage of using the Mg-doped regrown layer 105B is that it can reduce the number of holes. The presence of holes causes the surface roughness of the layer, which makes it important to reduce the number of holes. In addition, the Mg-doped regrown layer 105B can bury the concave portion at the non-growth area 104, and the growth time of the regrown layer 105B can be reduced.

[0266] Fourth embodiment

[0267] In the fourth embodiment, after the regrown layer 105B is grown, the surface of the regrown layer 105B is polished so as to make the surface level, as shown in FIG. Figure 3(a) and 3(b) As shown in Figure 1(e), they are variations of Figure 1(e). Figure 9(a) , 9(b) , 9(c), 9(d), 9(e) and 9(f), which are Figure 1(d) ,1(e) , 1(e), 1(f), 1(g) and 1(h) in which the Mg doped layer 601 is used as the regrown layer 105B.

[0268] This reduces the in-plane distribution of the thickness of the layer. The fluctuation of the characteristics of the device is also improved, which improves the yield in the mass production process. In addition, in the case of using a Mg-doped layer as the regrown layer 105B, polishing the Mg-doped regrown layer 105B eliminates the need for the ELO III-nitride layer 105A to be a Mg-doped layer. The presence of the Mg-doped layer leads to an increase in the device voltage. Therefore, polishing leads to a decrease in voltage. Using a co-doped layer as the regrown layer 105B also increases the voltage of the device.

[0269] Fifth embodiment

[0270] In the fifth embodiment, before removing the device, the device has a plurality of void regions 107, such as Fig.23 By doing this, a large chip size can be achieved for the device.

[0271] Sixth embodiment

[0272] In the sixth embodiment, the ELO III-nitride layer 105A can be grown by hydride vapor phase epitaxy (HVPE), which can grow a III-nitride layer at a high growth rate. In this case, using HVPE to grow the ELO III-nitride layer 105A makes it possible to reduce the growth time while covering a wider area of ​​the growth limit mask 102 with the ELO III-nitride layer 105A.

[0273] The present invention can use the ELO technology to manufacture other devices, such as AlGaAs laser diodes, etc., and can also be applied to manufacture LED devices.

[0274] Seventh embodiment

[0275] According to Figure 26(a) , 26(b) , 26(c), 26(d), 26(e), 26(f), 26(g) and 26(h) of the seventh embodiment shown in Figures 26(a), 26(c), 26(d), 26(e), 26(f), 26(g) and 26(h) are based on a III-nitride semiconductor device and a method for manufacturing the same using a growth support layer deposited on a substrate.

[0276] This embodiment uses a growth support layer 2601 deposited on the substrate 101. The main advantage of the growth support layer 2601 is that it takes a short time to cover the entire substrate 101 or wafer with the group III nitride layer. For example, due to the use of lateral growth technology, it takes a long time to cover the growth limit mask 102 using a wide growth limit mask 102 (for example, more than 100 μm wide). In this embodiment, since the group III nitride layer can be grown on the growth support layer 2601, the time to cover the growth support layer 2601 with the group III nitride layer is very short. The time is the same and does not depend on the width of the growth support layer 2601. Therefore, there is a great advantage when using a wide growth support layer 2601, which can easily form wide strips 112.

[0277] Two different methods are described to achieve a flat epitaxial layer on a III-nitride base substrate 101 using a growth support layer 2601. In the first method, a dielectric layer 2602 is deposited on the semiconductor substrate 101, followed by the growth support layer 2601. The thickness of the dielectric layer 2602 can be anywhere between 100nm and 1000nm, and the thickness of the growth support layer 2601 can be anywhere between 10nm and 100nm. A typical example of dielectric layer 2602 is SiO 2 , SiN, SiON or a mixture thereof, typical examples of the growth support layer 2601 are AlN, AlON, BN, CrN, ZnO, etc. The dielectric layer 2602 and the growth support layer 2601 are then patterned to have a plurality of stripe openings 103 similar to the stripe openings in the growth restriction mask 102 shown in FIG. 1( b). The etching of the dielectric layer 2602 and the growth support layer 2601 can be performed chemically using a BHF solution and then a suitable solvent for the growth support layer 2601. For example, a heated KOH (potassium hydroxide) solution can be used to dissolve AlN. By doing so, one can obtain a void below the flat epitaxial layer area of ​​the patterned portion.

[0278] In an alternative method, a growth support layer 2601 having a thickness of 10 nm to 1000 nm is deposited on the substrate 101, and then the growth support layer 2601 is patterned to have a plurality of stripe openings 103, such as Figure 27(a) , 27(b) , 27(c), 27(d), 27(e), 27(f), 27(g) and 27(h).

[0279] Afterwards, if step 2 including growing an ELO III-nitride layer 105A on the substrate using a growth restriction mask is performed on the substrate 101 with the growth support layer 2601, steps 3 and 4 can be skipped, and step 5 can be performed directly. This means that after obtaining a flat surface area on the substrate 101 including the growth support layer 2601, one can directly grow the III-nitride device layer 106 on top of the fully covered substrate 101, such as Figure 26(e) and 27(e) shown.

[0280] Compared to the III-nitride layer grown on the opening region 103, the III-nitride layer 106 grown on the growth support layer 2601 is more chemically reactive, which will simplify the process of segmenting the III-nitride device layer 106. After forming the selective mask portion on the area of ​​interest, the substrate 101 can be immersed in a chemical solution (e.g., heated KOH, HF, BHF, etc.) to remove the chemically reactive portion grown on the growth support layer 2601. This method exposes at least the original substrate 101 and leaves the device structure in the form of an easily removable shape, such as Figure 26(h) and 27(h) shown.

[0281] Alternatively, step 7 can be performed as is to obtain Figure 26(h) and 27(h) Of course, a conventional dry etching method may also be used to etch part of the region on the growth support layer 2601 .

[0282] In this embodiment, if Figure 26(a) and 26(b) First, a base substrate 101 is provided, and a growth restriction layer 2602 (eg, a dielectric layer such as SiO 2 A growth support layer 2601 is deposited on top of the substrate (e.g., SiN, etc.). Later, the growth support layer 2601 and the growth restriction layer 2602 combination is patterned to have a plurality of opening regions 103, as shown in FIG. 26( c). Alternatively, a similar method may be followed by replacing the combination with only the growth support layer 2601, as shown in FIG. Figure 27(a) , 27(b) and 27(c).

[0283] The III-nitride ELO layer 105A may be grown using MOCVD or HVPE on these growth support layers 2601. Thereafter, the III-nitride device layer 106 may be grown to realize functional devices such as laser diodes, LEDs, VCSELs, power electronic devices, and the like.

[0284] It is preferred that a portion of the active region (such as the ridge structure 108 or the emission region of the LED) is located on the opening region 103 because the region on the growth support layer 2601 has more dislocations than the region on the opening region 103 .

[0285] After fabricating the III-nitride device layer 106 on the substrate 101 including the growth support layer 2601, the region including the growth support layer 2601 is etched from the top surface of the III-nitride device layer 106 to the surface of the base substrate 101 to separate the individual device units. At least one individual device unit is mechanically removed from the base substrate 101 using the methods of other embodiments.

[0286] In this embodiment, the base substrate 101 is a c-plane substrate composed of a III-nitride based semiconductor having a -0.4 degree mis-cut orientation toward the m-axis. Alternatively, the present invention may be practiced on any substrate 101 independent of the crystal orientation.

[0287] Eighth embodiment

[0288] This embodiment explains the triangular gap method. Here, the method is how to make a triangular gap.

[0289] In this embodiment as shown in FIGS. 19( a ) to 19 ( b ), a substrate 101 is first provided, and a growth restriction mask 102 having a plurality of stripe opening regions 103 is formed on the substrate 101 .

[0290] In this embodiment, the substrate 101 is a c-plane substrate composed of a III-nitride semiconductor with a -0.4 degree misalignment orientation toward the m-axis. In this embodiment as shown in Figure 19 (c), the width Wo of the opening area 103 and the width Wr of the growth restriction mask 102 are set to 5μm and 50μm, respectively. The thickness of the growth restriction mask 102 is 1.0μm, and the width of the etching area L is 15μm. Since the recessed portion 1903 is an agglomerated portion that is adjacent to the ELO III-nitride layer 105A, the portion has many defects. In this method, in order to separate the ELO III-nitride layer 105A and the device layer 106, the region is eliminated by etching. Therefore, the defects in this portion do not affect the characteristics of the device, which is a great advantage.

[0291] The growth conditions of the initial growth layer and the ELO III-nitride layer 105A are explained below. First, as shown in FIG19( c ), the surface of the initial growth layer is raised above the growth limit mask 102 to obtain a uniform shape of the ELO III-nitride layer 105A. Because it is not necessary to have a high lateral growth rate, the initial growth layer has a higher V / III ratio than the ELO III-nitride layer 105A.

[0292] In order to achieve a high lateral growth rate, a low V / III ratio of less than 500 needs to be precisely controlled. However, the appropriate V / III ratio varies depending on the growth temperature. The higher the temperature, the higher the V / III ratio is required. In the temperature range of 850°C to 1250°C, the lateral growth rate can reach more than 20 μm / hour. The growth conditions are optimized to obtain a uniform shape of the ELO III-nitride layer 105A.

[0293] For example, the growth conditions of the ELO III-nitride layer 105A may include the following: TEG=200 slm, NH 3 =0.2slm, growth temperature = 1100℃, carrier gas is N 2 and H 2 The layer is an unintentionally doped (UID) layer. Under this growth condition, the growth time of the ELO III-nitride layer 105A is 1 hour and 30 minutes. After the ELO III-nitride layer 105A grows for 2 hours, the adjacent ELO III-nitride layers 105A coalesce with each other. This can produce a triangular gap 107, as shown in FIG. 19( e) and FIG. Figure 21(a) and 21(b) The flat surface on the substrate 101 including the ELO III-nitride layer 105A and the triangular voids 107 is shown in FIG. Figure 21(a) , 21(b) 21(c). There are no cracks on the surface of the ELO III-nitride layer 105A. This is evidence of stress relaxation due to the presence of the triangular voids 107.

[0294] Later, as shown in Fig. 19(h), the method can manufacture a device on the substrate 101. Then, the area above the gap 107 is eliminated by dry etching, as shown in Fig. 19(j).

[0295] In this embodiment, strip 112 does not contain the center of void region 107. Since there is no center of void region 107, the active area of ​​the device can be freely placed on strip 112.

[0296] As shown in FIG19( k), the growth restriction mask 102 is dissolved by HF to facilitate the removal of the strips 112. The strips 112 are removed from the substrate 101 using the adhesive tape 111 and the aforementioned method, such as Figure 19(l) , 19(m) 19(n). It is also possible to remove the strip 112 using another substrate bonded to the strip 112. This embodiment can also be packaged using the same process, as shown in FIGS. 12(a)-12(f) and Figure 13-18 shown.

[0297] Ninth embodiment

[0298] The process of this embodiment is almost the same as that of the eighth embodiment, except that dry etching is performed to remove a portion of the strip 112. In this embodiment, dry etching is performed to remove two portions of the gap 107 and the portion above the opening region 103, such as Figure 22(a) and 22(b) As shown, the strip 112 does not include the center of the void region 107 and the portion above the opening region 103. Since the strip 112 does not exist in the center of the void region 107 and the portion above the opening region 103, the active region of the device can be freely placed on the strip 112.

[0299] This helps the device have high reliability. After etching, the strip 112 is on the growth limit mask 102. The interface between the bottom surface of the ELO III-nitride layer 105A and the upper surface of the growth limit mask 102 does not have a strong bonding strength. Therefore, in order to fix the strip 112 on the growth limit mask 102, a hook layer 2202 is deposited on the photoresist 1905 as shown in FIG. 22(c). A portion of the hook layer 2202 on the photoresist 1905 is removed by a stripping method as shown in FIG. 22(d). By doing so, the strip 112 directly on the growth limit mask 102 is fixed by the hook layer 2202, which covers the side of the strip 112 and the surface of the growth limit mask 102. This allows the substrate 101 to be further processed without stripping the strip 112 from the substrate 101.

[0300] Then, various methods can be used to remove the strips 112 on the growth limiting mask 102, such as the adhesive tape 111 method as shown in FIG. 22( e), or the support plate 2203 method as shown in FIG. 22( f), wherein the support plate 2203 is Si, Cu, etc., and the support plate 2203 uses solder 2204, such as Au-Sn, Sn-Ag-Cu, etc.

[0301] In the support plate 2203 method, after the support plate 2203 and the substrate 101 are in contact with the strip 112, the bonded substrate 101 is heated to 280-300°C and then cooled to room temperature. At this point, the thermal stress breaks the hook layer 2202 at the fracture point 113, as shown in FIG. 22(f), which allows the strip 112 to be removed from the substrate 101.

[0302] Thereafter, the same process and package are shown in Figures 12(a)-12(f) and can be used Figure 13-18 .

[0303] Process steps

[0304] Fig.281 is a flow chart illustrating a method of removing strips 112 of one or more devices from substrate 101 using void regions 107, wherein: one or more strips 112 composed of group III nitride semiconductor layers 105A, 105B, 106 are formed on substrate 101, and a structure of a device is formed on strips 112; and stress is applied using void regions 107 to remove strips 112 from substrate 101. The steps of the method are described in more detail below.

[0305] Box 2801 represents the step of providing a base substrate 101. In one embodiment, the base substrate 101 is a III-nitride based substrate 101 such as a GaN based substrate 101, or a foreign substrate 101 such as a sapphire substrate 101. This step may also include an optional step of depositing a template layer on or over the substrate 101, wherein the template layer may include a buffer layer or an intermediate layer, such as a GaN bottom layer.

[0306] Box 2802 represents the step of depositing a growth restriction mask 102 on or over the substrate 101. The growth restriction mask 102 is patterned to include a plurality of stripe-shaped opening regions 103.

[0307] Box 2803 represents the step of growing one or more III-nitride layers 105A on or over growth limit mask 102 using epitaxial lateral overgrowth (ELO), followed by one or more III-nitride regrown layers 105B. The growth of ELO III-nitride layer 105A forms one or more void regions 107 on or over substrate 101. This step may include removing any exposed areas of growth limit mask 102 by etching, and then growing regrown layer 105B on ELO III-nitride layer 105A after removing the exposed areas of growth limit mask 102, thereby forming void regions 107. This step may also include optimizing growth conditions during the growth of ELO III-nitride layer 105A to create void regions 107 in ELO III-nitride layer 105A without removing growth limit mask 102. After growing regrown layer 105B, ELO III-nitride layer 105A may be polished or planarized.

[0308] Block 2804 represents the step of growing one or more III-nitride device layers 106 on or over ELO III-nitride layer 105A and III-nitride regrown layer 105B, thereby fabricating strips 112 on substrate 101. Additional device fabrication may be performed before and / or after strips 112 are removed from substrate 101.

[0309] Box 2805 represents the step of etching the ELO III-nitride layer 105A, the regrown layer 105B, and the III-nitride device layer 106 over the void region 107 to at least expose at least a portion of the void region 107 .

[0310] Box 2806 represents the step of removing strips 112 from substrate 101 using void region 107. Preferably, strips 112 do not contain the center of void region 107.

[0311] Box 2807 represents the step of fabricating the strips 112 into a device after removing the strips 112 from the substrate 101 .

[0312] Block 2808 represents the step of segmenting strip 112 into one or more devices.

[0313] Block 2809 represents the step of mounting the device in a package or module.

[0314] Box 2810 represents the resulting product of the method, namely one or more III-nitride based semiconductor devices fabricated according to the method, and substrate 101 that has been removed from the device and is available for recycling and reuse.

[0315] The device may include one or more ELO III-nitride layers 105A grown on or over a growth limiting mask 102 on a substrate 101, wherein the growth of the ELO III-nitride layers 105A is stopped before adjacent ELO III-nitride layers 105A are bonded to each other. The device may also include one or more III-nitride regrown layers 105B and one or more additional III-nitride device layers 106 grown on or over the ELO III-nitride layers 105A and the substrate 101.

[0316] Advantages and Benefits

[0317] The present invention provides many advantages and benefits, including but not limited to the following:

[0318] 1. The void regions can be used to fracture or break the semiconductor layer without using a growth limiting mask.

[0319] 2. When the magnesium-doped layer is agglomerated, the appearance of holes can be avoided.

[0320] 3. A smooth surface can be obtained by chemical mechanical polishing after layer coalescence, which can eliminate the need for a Mg doping layer.

[0321] 4. Laser diode structures can be processed on the flat surface of the layer.

[0322] 5. The risk of edge growth occurring can be eliminated.

[0323] 6. Larger chip sizes can be achieved using HVPE growth.

[0324] Modifications and Replacements

[0325] Various modifications and substitutions may be made without departing from the scope of the invention.

[0326] For example, the present invention can be used with other oriented III-nitride substrates. Specifically, the substrate can be a basal non-polar m-plane {1 0 -1 0} family; and a semi-polar plane family with at least two non-zero h, i or k Miller indices and a non-zero l Miller index, such as a {2 0 -2 -1} plane. (20-2-1) semi-polar substrates are particularly useful because the area of ​​planarized ELO growth is very wide.

[0327] In addition, the present invention can use various heterogeneous substrates, such as a III-nitride layer on a sapphire substrate, a silicon substrate, and a SiC substrate, etc. The ELO III-nitride layer 105A can be grown directly on a sapphire substrate with a growth limiting mask.

[0328] In another example, the present invention is described as being used to manufacture different optoelectronic device structures, such as light emitting diodes (LEDs), laser diodes (LDs), photodiodes (PDs), Schottky barrier diodes (SBDs), or metal oxide semiconductor field effect transistors (MOSFETs). The present invention can also be used to manufacture other optoelectronic devices, such as micro-LEDs, vertical cavity surface emitting lasers (VCSELs), edge emitting laser diodes (EELDs), and solar cells.

[0329] in conclusion

[0330] The above is a description of a preferred embodiment of the present invention. The foregoing description of one or more embodiments of the present invention has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. In view of the above teachings, many modifications may be made. The scope of the present invention is intended to be limited not by this specific embodiment but by the appended claims.

Claims

1. A method of removing a substrate from one or more device layers using a void portion, comprising: growing one or more epitaxially laterally overgrown Group III-nitride layers through open regions in a growth limit mask deposited on or over a substrate, wherein initial growth of the Group III-nitride layer is above the growth limit mask, subsequent growth of the Group III-nitride layer from the initial growth coalesces to produce one or more triangular voids between a surface of the substrate and a surface of the Group III-nitride layer, and the triangular voids appear directly above the growth limit mask and are surrounded by the growth limit mask and the Group III-nitride layer; growing one or more Group III-nitride device layers on or over the Group III-nitride layer; etching the III-nitride layer and the III-nitride device layer above the triangular void to expose at least the triangular void; and Strips comprised of the III-nitride layer and the III-nitride device layer are removed from the substrate at the exposed triangular voids.

2. The method according to claim 1, wherein: The group III nitride layer includes a regrown layer and / or a planarization layer.

3. The method according to claim 2, wherein: The regrown layer and / or the planarization layer includes magnesium (Mg).

4. The method according to claim 2, wherein: The Group III nitride layer is polished after growing the regrown layer.

5. The method according to claim 1, wherein: The strip does not contain the center of the triangular void.

6. The method according to claim 1, wherein: One or more devices are fabricated from the strips.

7. A structure obtained by a method of removing a substrate from one or more device layers using a void portion, comprising: one or more epitaxially laterally overgrown Group III-nitride layers grown through open regions in a growth limit mask deposited on or above the substrate, wherein initial growth of the Group III-nitride layer is above the growth limit mask, subsequent growth of the Group III-nitride layer from the initial growth coalesces to produce one or more triangular voids between a surface of the substrate and a surface of the Group III-nitride layer, and the triangular voids appear directly above the growth limit mask and are surrounded by the growth limit mask and the Group III-nitride layer; one or more Group III-nitride device layers grown on or over the Group III-nitride layer; etching the III-nitride device layer and the III-nitride layer over the void to expose at least the triangular void; and Strips comprised of the III-nitride layer and the III-nitride device layer are removed from the substrate at the exposed triangular voids.

8. A method of removing a substrate from one or more device layers using a void portion, comprising: growing one or more epitaxially laterally overgrown Group III-nitride layers through open regions in a growth limit mask deposited on or over a substrate, wherein an initial growth of the Group III-nitride layer is above the growth limit mask, subsequent growth of the Group III-nitride layer from the initial growth forms one or more triangular voids on or over the substrate, and the triangular voids appear directly above the growth limit mask and are surrounded by the growth limit mask and the Group III-nitride layer; growing one or more Group III-nitride device layers on or over the Group III-nitride layer; etching the III-nitride device layer and the III-nitride layer to expose at least a portion of the triangular void; as well as A strip comprised of the Ill-nitride device layer and the Ill-nitride layer is separated from the substrate at an exposed portion of the triangular void.

9. The method according to claim 8, wherein: The triangular voids relieve stress caused by the growth limiting mask.

10. The method according to claim 8, wherein: The recessed portion in the non-growth region is buried by the regrown layer of the group III nitride layer, which planarizes the surface of the regrown layer.

11. The method according to claim 10, wherein: The regrown layer is doped with magnesium (Mg) to reduce the number of pores at a surface of the regrown layer.

12. The method according to claim 8, wherein: The triangular void is formed by: Growth conditions are optimized during growth of the III-nitride layer to form the triangular voids in the III-nitride layer without removing a growth limiting mask.

13. The method according to claim 12, wherein: The growth conditions form facets at edges of the III-nitride layer, and the facets include an inverted tapered shape.

14. The method according to claim 13, wherein: The inverted tapered shape produces the triangular void having a triangular shape at the coalescence region of the Group III-nitride layer.

15. The method according to claim 8, wherein: Stress is applied to separate the strip from the substrate.

16. The method according to claim 15, wherein: The stress is applied at the triangular gap.

17. The method of claim 8, further comprising smoothing a surface of the Group III-nitride layer.

18. The method according to claim 8, wherein: One or more devices are fabricated from the strips.

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