Method and apparatus for temperature modification and contamination reduction in microelectronic devices

Abstract

The present patent application relates to a method and apparatus for temperature change and contamination reduction in a microelectronic device. Heat is applied to the stack from a bonding head of a thermocompression bonding tool. The stack is substantially enclosed in a skirt carried by the bonding head to reduce heat loss and contamination from the stack, and heat can be added from the skirt.

Description

[0001] Priority claim

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 16 / 895,751, filed on June 8, 2020, “METHODS AND APPARATUS FOR TEMPERATURE MODIFICATION AND REDUCTION OF CONTAMINATION IN BONDING STACKED MICROELECTRONIC DEVICES”. Technical Field

[0003] Embodiments disclosed herein relate to the bonding of stacked microelectronic devices. More particularly, embodiments disclosed herein relate to methods and apparatus for temperature modification and contamination reduction during collective bonding of a stack of microelectronic devices. Background Art

[0004] Over time, leadframe-based microelectronic device packaging has gained a major market share in microelectronic devices that utilize an array of conductive elements protruding from its surface to connect to the terminal pads of another target microelectronic device or other substrate. To a large extent, the increased circuit density, the increased number of lead wires, and the smaller form factor required for the "footprint" of the microelectronic device have stimulated this transition. This configuration is generally referred to as a "flip chip" configuration because the microelectronic device is inverted so that the surface carrying the protruding conductive elements faces downward to the target. Although the flip chip configuration was initially implemented using solder balls or bumps in the so-called C4 (controlled collapse chip connection) structure, the recent requirements for smaller conductive elements and tighter spacing (i.e., the spacing between conductive elements) to accommodate a smaller form factor and an increased number of lead wires have stimulated the use of conductive metal (e.g., copper) columns as conductive elements. In some cases, the column has a solder cap, which is usually isolated from the copper column material by a thin barrier layer (e.g., nickel) material. In either case, bonding between the conductive elements of a microelectronic device and the terminal pads of another microelectronic device is conventionally accomplished by applying heat to the assembly in a reflow oven to melt the solder, or by applying heat in combination with force applied by a thermocompression bonding head to melt the solder, or the absence of solder, to achieve diffusion bonding between the metal pillars and the aligned terminal pads.

[0005] As part of the thermocompression bonding process, dielectric material is inserted in the so-called "bond wire" between adjacent stacked microelectronic devices to electrically insulate laterally adjacent conductive elements of the connected devices and to provide electrical insulation between the stacked microelectronic devices, as well as to provide additional adhesion between the devices. In recent years, it has become more common to stack preformed dielectric films adhered to the microelectronic devices or to dispense dielectric material on the microelectronic devices prior to stacking, rather than dispensing flowable dielectric material on each device during stacking, or using post-stack capillary underfill in the bond wire. Such preformed dielectric or pre-stacked dispensed material films are referred to as non-conductive films (NCFs), as well as wafer-level underfill films (WLUFs). Summary of the invention

[0006] Embodiments of the present disclosure include a thermocompression bonding apparatus including a bonding stage and a bonding head movable in the X, Y, and Z directions. The bonding head includes a bonding tip having a compression surface on its underside, the bonding tip including a primary heating device and a skirt extending downwardly from the bonding head, surrounding the bonding tip and laterally enclosing a bottom-open chamber.

[0007] An embodiment of the present disclosure includes a method comprising: aligning a bonding head of a thermocompression bonding tool with a stack of microelectronic devices; and lowering the bonding head over the stack of microelectronic devices to substantially enclose the stack in a chamber within a skirt extending downwardly from the bonding head, and contacting an uppermost microelectronic device of the stack with a bonding tip of the bonding head within the chamber. Heat is applied from the bonding tip to the stack of microelectronic devices through the uppermost microelectronic device, and heat loss from the bonding tip through the stack of microelectronic devices and from the periphery of the stack is reduced by the skirt.

[0008] An embodiment of the present disclosure includes a method comprising: aligning a bonding head of a thermocompression bonding tool with a stack of microelectronic devices; lowering the bonding head of the thermocompression bonding tool over the stack of microelectronic devices; heating the stack of microelectronic devices with the bonding head; and substantially containing contaminant material degassed from bonding wires between the stacked microelectronic devices within a skirt that is carried by the bonding head and substantially encloses the stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a schematic side partial cross-sectional view of a stack of microelectronic devices in the form of semiconductor die, and Figure 1B yes Figure 1A an enlarged view of a portion showing an open circuit interconnect;

[0010] Figure 2is a schematic side view of a stack of semiconductor dies being thermocompression bonded by conventional techniques and illustrating a heat loss gradient for a large distance downward and outward through the die stack from a bond tip of a bond head;

[0011] Figure 3 is a side view photomicrograph of a thermal compression bonded semiconductor die stack showing a thin sheet of dielectric material at one side of the semiconductor die stack configured as an HBM assembly;

[0012] Figure 4 is a side view of a thermally compression bonded semiconductor die stack on a base semiconductor wafer in a chip-to-wafer (C2W) assembly and showing a thin sheet of dielectric material extruded out of one side of the assembly;

[0013] Figure 5 is a micrograph of a die surface contaminated by outgassing of material from the thermocompression bonding process;

[0014] Figure 6 is a side schematic diagram of adjacent die stacks on a substrate, one die stack being thermocompression bonded and degassing contaminants on an adjacent die stack;

[0015] Fig. 7A is a schematic side view of a semiconductor die thermocompression bonded to a semiconductor wafer by conventional techniques;

[0016] Figure 7B yes Figure 7B a schematic side view of an assembly during thermocompression bonding and depicting heat loss through and from the periphery of the assembly;

[0017] Figure 8 is a finite element analysis heat map in grayscale, which shows Figure 7B Heat losses shown and described relative thereto;

[0018] Fig. 9 is a graphical representation of heat loss in a semiconductor die during a thermocompression bonding operation, showing a lack of sufficient heat gain over time at the corners of the die;

[0019] Fig.10 is a side schematic partial cross-sectional view of a thermocompression bonding tool according to an embodiment of the present disclosure, and Fig. 10A is through Fig.10 A schematic cross-sectional view of section line AA;

[0020] Fig.11 is a schematic partial cross-sectional side view of a thermocompression bonding tool according to another embodiment of the present disclosure, and Fig.11A is through Fig.11 A schematic cross-sectional view of section line AA;

[0021] Fig.12 is a side schematic partial cross-sectional view of another thermocompression bonding tool according to another embodiment of the present disclosure;

[0022] Fig.13 is a side partial cross-sectional view of a thermocompression bonding tool according to yet another embodiment of the present disclosure, Fig.14 Before being placed on a stack of microelectronic devices, looking upward Fig.14 A front view of a bonding head skirt of a thermocompression bonding tool; and

[0023] Fig.15 is a flow chart of a thermocompression bonding process according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Embodiments of the present disclosure relate to methods and apparatus for controlling the temperature, and more particularly the temperature gradient, within a stack of microelectronic devices during collective bonding of the microelectronic devices to each other. A bonding tool for controlled heating of a microelectronic stack at various levels of the device stack, and a temperature control method employing such a bonding tool are disclosed. A bonding tool is also disclosed that is configured to reduce contamination of contaminants of adjacent microelectronic devices by limiting the diffusion of such contaminants during bonding.

[0025] The following description provides specific details, such as size, shape, material composition, location, and orientation, in order to provide a comprehensive description of the embodiments of the present disclosure. However, those skilled in the art will understand and appreciate that the embodiments of the present disclosure may be practiced without adopting these specific details, because the embodiments of the present disclosure may be practiced in conjunction with conventional process behaviors and equipment used in the industry and appropriately modified according to the present disclosure. In addition, the description provided below may not form a complete process flow for thermal compression bonding. Only those process actions and structures necessary to understand the embodiments of the present disclosure are described in detail below.

[0026] The drawings presented herein are for illustrative purposes only and are not meant to be actual views of any particular material, device, structure, apparatus, or system. Changes in the shapes depicted in the drawings may be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes or regions shown, but rather include shape deviations, for example, caused by manufacturing. For example, an area illustrated or described as box-shaped may have roughness and / or nonlinear features, while an area illustrated or described as circular may include some roughness and / or linear features. In addition, the sharp angles between the illustrated surfaces may be rounded, and vice versa. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the area, and do not limit the scope of the present claims. The drawings do not have to be drawn to scale.

[0027] Embodiments can be described according to a process depicted as a flow chart, a flow chart, a structure diagram, or a block diagram. Although a flow chart can describe an operational action as a sequential process, many of these actions can be performed in another order, in parallel, or substantially simultaneously. In addition, the order of the actions can be rearranged. A process can correspond to a method, a thread, a function, a process, a subroutine, a subprogram, other structures, or a combination thereof. In addition, the method disclosed herein can be implemented in hardware, software, or both. If implemented in software, the function can be stored or transmitted as one or more instructions or codes on a computer-readable medium. A computer-readable medium includes a computer storage medium and a communication medium, and the communication medium includes any medium that is convenient for transmitting a computer program from one place to another. In the specification, for convenience, the same or similar reference numerals can be used to identify features and elements shared between the various figures.

[0028] The mutual bonding of the columnar conductive element to the terminal pad of another microelectronic device or substrate is usually achieved by thermally induced mass reflow of the solder cap material or by thermocompression bonding, in which the bonding head applies a normal (i.e., vertical) downward force to the microelectronic device while applying heat by the bonding head. Both techniques are suitable when stacking and bonding only one or a few flip-chip configured microelectronic devices. However, as the demand for increased circuit density continues, the stacking of four, eight, twelve, sixteen or even more flip-chip configured microelectronic devices requires unacceptable increases in temperature or dwell time in large-scale reflow ovens to achieve bonding, thereby straining the thermal budget of the microelectronic device and increasing the possibility of device failure. On the other hand, the effective use of thermocompression bonding may be compromised by the heat loss of the bonding tip through the stack of microelectronic devices and through the bonding platform and the side of the assembly that supports the stack of microelectronic devices, resulting in difficulty in forming solder or diffusion bonds near the periphery of the assembly. The heat loss problem is further exacerbated when thermocompression bonding is used to bond a larger number (e.g., four, eight, twelve, sixteen, etc.) of stacked microelectronic devices. In such cases, due to the heat loss over the greater height of the assembly, the relatively steep temperature gradient from the topmost microelectronic device contacted by the bonding tip of the bonding head to the bottommost microelectronic device or substrate in the stack and from the center of the stack to the lateral periphery of the stack may cause the solder to not fully liquefy or fail to form a strong metal-metal diffusion bond. As a result, open circuit interconnects may remain between the conductive element and the associated terminal pads adjacent to the periphery of this assembly. In addition, heat loss and uneven heating of the stack may cause insufficient and / or uneven solidification of dielectric materials, such as non-conductive films (NCFs) or wafer-level underfill films (WLUFs) in the bonding wires between adjacent devices in the stack, resulting in inconsistent bonding wire thicknesses, gaps in the bonding wires, or both. In addition, although the substrate carrying the stack of microelectronic devices can be thermocompressively bonded using a bonding tool with a heated bonding station, the bonding station temperature cannot be high enough to compensate for the heat loss caused by the stacking of semiconductor devices without risking premature solidification of the NCF or WLUF in the lower bonding wires in the stack.

[0029] Figure 1AA schematic side cross-sectional view of an assembly of a stacked and conventionally thermocompressively bonded microelectronic device in the form of semiconductor die SD is shown, each die SD except for the uppermost die SD in the stack containing a through silicon via (TSV) T, which includes a conductive material isolated from the material of the semiconductor die, extending between the main surfaces of the die, aligned with and respectively connected to a conductive element in the form of a solder-terminated metal pillar on one main surface and a terminal pad on the opposite main surface. Ideally, after thermocompression bonding, the solder S covering each metal pillar MP has melted and cooled, contacting the terminal pad TP to form a secure interconnect bond I, as shown in FIG. Figure 1A However, Figure 1A As shown in the lower right corner of FIG. , even when it is undesirable to use a maximum tool (ie, bonding tip of the bonding head) temperature, heat losses over the lateral extent of the lower microelectronic device and the associated insufficient temperature margin may result in an open interconnect OI. Figure 1B yes Figure 1A 1 and depicts the open interconnect OI in more detail, showing that there is no contact at all to the terminal pad TP by the solder S on the metal pillar MP. The dielectric material D surrounding the interconnect I (e.g., NCF or WLUF) is shown in the bond wire BL between adjacent devices, including Figure 1A and 1B The portion passes through the component after encapsulation.

[0030] Figure 2 Schematically depicts a thermal gradient between a bonding tip BT of a thermocompression bonding head BH and a bonding table BS of a thermocompression bonding tool during a thermocompression bonding operation, wherein heat H and a normal force N are applied by the bonding head BH to a semiconductor die SD on a substrate 1 and SD 2 A stack of microelectronic devices in the form of a semiconductor die W supported on a carrier wafer CW on a bonding station BS of a thermocompression bonding tool. As can be easily seen and understood from the thermal gradient lines G1 to G8, the further the heat propagates longitudinally and laterally through the stack of semiconductor die SD, the greater the heat loss, and thus the greater the probability that mutual bonding of the conductive elements in the stack will not occur. As shown in the figure, in the region of the thermal gradient lines G7 and G8, the lower semiconductor die SD of the stack near the wafer W is moved toward the bottom of the stack. 1 Undue heat loss may occur around the periphery, thus preventing the lower semiconductor die SD 1 The solder S at the periphery of the stack, the metal pillars MP and the strong interconnection between the terminal pads TP. It is again noted that this heat loss phenomenon increases with the increase in the number of microelectronic devices and therefore with the increase in stack height.

[0031] Although bonding tip temperatures of 400°C or even 450°C have been employed, as recognized by the inventors herein, such temperatures may prove insufficient for thermocompression bonding of, for example, eight or more stacked microelectronic devices due to a lack of sufficiently high temperatures at the periphery of lower devices in the stack. Furthermore, the use of high temperatures of the order of magnitude described above may exceed the thermal budget of certain microelectronic devices, such as dynamic random access memory (DRAM) semiconductor dies, and cause damage thereto. Additionally, the application of excessive heat from the bonding head may result in premature solidification of the NCF or WLUF in the bond wire, resulting in the inability of the NCF or WLUF to maintain minimal viscosity spread during thermocompression bonding and provide a thin and uniform bond wire. For example, since conventional Sn / Ag solder has a melting point of about 221°C, or Sn solder has a melting point of about 231°C, and even indium solder requires about 170°C to melt, it is apparent that heat loss through a stack of microelectronic devices quickly becomes a problem, even though the temperature drop of each microelectronic device vertically through the stack is even only 10°C, which drop is exacerbated by the presence of dielectric material (such as NCF or WLUF) in the bond wires, and the further distance heat applied by the bond tips can propagate from the centerline of the stack to the periphery of the stack. Thus, in a stack of eight (8) DRAM semiconductor devices, for example, heat losses along the centerline of the stack from the top to the bottom of the stack may easily exceed 80°C, while heat losses to the sides and particular corners of the stack may be significantly greater.

[0032] The use of this rectangular shaped dielectric material, sized to coincide with the outer boundaries of the microelectronic devices in the stack, in conjunction with thermocompression bonding techniques, has resulted in yield issues as well as bond head contamination issues because the peripheral extension (i.e., protrusion) of the sheet of dielectric film material beyond the sides of the devices, and to a maximum extent along the midpoint of the sides, in response to the normal forces and heat applied by the bond head. Specifically, as the thickness of the film decreases until the aligned conductive elements of adjacent devices come into contact, and before the dielectric film is fully cured to the final bond line thickness between the devices, the heat and forces applied by the bond head cause "expulsion" (i.e., extrusion) of the peripheral portions of the dielectric film. Additionally, the inventors herein have observed that, in many cases, the size of the peripheral portions of the dielectric film, including the sheet, increases gradually from the upper film layer to the lower film layer in the stack. As a result, thin flakes of dielectric material may also protrude upward and contaminate the bond head, but even if this does not occur, the presence of the flakes may compromise the formation and integrity of the epoxy molding compound (EMC) on the sides of the microelectronic device stack, cause flammability issues due to exposed dielectric films, cause problems with package moisture absorption, or even extend between adjacent stacks of microelectronic devices formed on a base substrate (e.g., a base wafer), which may cause the aforementioned EMC problems as well as cause warping of the base wafer. Such flakes result in non-linear device stack sides and other anomalies that affect the thickness and continuity of the EMC, causing damage when adjacent microelectronic devices are separated by a dicing saw along a path that does not completely fill the EMC in the path of the saw blade. Although stacks of microelectronic devices are currently typically separated by a considerable distance, such as about 600 μm, this distance continues to shrink as circuit density increases, allowing smaller microdevice sizes and increasingly closely spaced devices per wafer.

[0033] As a specific example of the above problem, Figure 3 Schematic diagram of a sheet F of dielectric film extruded out of the sides of the stack of thermocompression bonded semiconductor dies SD of the stacked die assembly, with the largest sheet F being located at the bottom of the stack between the lowermost die and the supporting substrate S. Similarly, Figure 4 is a schematic diagram of a dielectric sheet F extruded at and between the bases of semiconductor dies SD of a stack of semiconductor dies thermocompression bonded to a base wafer W in a C2W assembly, with the outermost sides of the sheet protruding substantially a common distance beyond the sides of the stack.

[0034] In addition to the aforementioned problems, the use of dielectric materials in the form of NCF or WLUF in stacking microelectronic devices (e.g., semiconductor dies) can result in outgassing of the dielectric material during the thermocompression bonding process, contaminating the surfaces of adjacent components, such as fiducial marks and bond pads, with the result that Figure 5 In addition, other materials such as solder, the use of non-conductive paste (NCF) in the bonding wire, and other materials present in the microelectronic device stack can also cause similar outgassing problems.

[0035] like Figure 6 As shown, a die stack DS of a plurality of semiconductor dies SD on a substrate S (eg, a wafer) is thermally compressed and bonded by a heated bonding tip BT of a bonding head BH of a thermal compression bonding tool. 1 The result of the outgassing of the contaminants of the dielectric and other materials M in the bonding wire BL is that the contaminant outgassing material C covers the adjacent die stack DS. 2 The stacking reference F on the upper surface of the top die SD leads to a stacking reference F for manipulating and bonding the adjacent die stack DS. 2 The optical sensor identification problem of the semiconductor die SD is in the adjacent die stack DS 2 Die misalignment occurs during bonding. In addition, outgassing of contaminants C may contaminate the bonding tip BT of the bonding head BH, which may be transferred to other die stacks or require replacement of expensive bonding tips. In addition, unknown reliability issues may be caused by coating epoxy or other contaminants in the under bump metallization (UBM) on the back of the semiconductor die, which are generated by outgassing contaminants of other materials present during NCF or thermocompression bonding. By way of example only, such problems include poor interconnections, such as poor soldering, cold meshing, open interconnections, pillar header (HIP) defects (i.e., the solder of the pillar collapses and pushes against the terminal pad and deforms, but is not hot enough to melt and form a connection), or higher resistance interconnections.

[0036] Similar to Figure 2 , Fig. 7A Schematically depicted is the thermocompression bonding of a semiconductor die SD in a chip-on-wafer (COW) arrangement to a semiconductor wafer W between a bonding tip BT of a thermocompression bonding head BH and a bonding table BS of a thermocompression bonding tool by applying heat H and a normal force N by a bonding tip BT to form interconnections between metal pillars MP of the semiconductor die SD and terminal pads TP of the wafer W by melting solder S to cover the metal pillars MP, drawing the molten solder S to the aligned terminal pads TP, and solidifying the solder S to bond to the metal pillars MP and the terminal pads TP. Ideally, a dielectric material D in the form of, for example, NCF is solidified by the applied heat H simultaneously with the melting of the solder S. However, as Figure 7B As shown, although the center area of ​​the semiconductor die SD and the metal pillar MP, solder S and dielectric material D may experience sufficient heat H S To melt the solder S and form a strong interconnect surrounded by the solidified dielectric material D, near the periphery of the semiconductor die SD, heat leak H through the die thickness, through the die periphery, through the dielectric material D, and through the wafer W L The heat H that can be caused to the solder S and the adjacent dielectric material D near the periphery of the die IInsufficient, thereby preventing strong interconnection between the solder S, the metal pillar MP and the terminal pad TP and insufficient solidification of the dielectric material D, wherein SO of the dielectric material D is excessively squeezed out, as shown by the dotted line.

[0037] In the attached figure Figure 8 is a finite element analysis heat map in grayscale, which shows the above Figure 7B The center line C L Heat is lost from the elongated, dark, highest temperature center region, with gradual heat loss in the surrounding gray region of the semiconductor die SD toward the die periphery P, and near the corners C 1 To C 4 The gradually darkening area shows excessive heat loss within the mold periphery P.

[0038] Fig. 9 is a graphical representation of heat loss in a semiconductor die during a thermocompression bonding operation, showing the lack of sufficient heat gain over time during the bonding operation at the corners of the semiconductor die as compared to the heat gain at the center of the semiconductor die, with the temperature at the center peaking and stabilizing at a level significantly higher than at the corners.

[0039] Reference now Fig.10 and 10A , schematically illustrates an embodiment of a thermocompression bonding tool 100. The thermocompression bonding tool 100 includes a bonding head 102 with a bonding tip assembly 104. The bonding head 102 with the bonding tip assembly 104 is movable in the X, Y, and Z planes under instructions from a controller and with the aid of position sensors (e.g., optical sensors) known in the art. The thermocompression bonding tool 100 also includes a bonding stage 106, which may optionally include a stage heating device 108, which may include a resistive heating element under closed-loop control of a thermocouple. In operation, the bonding station 106 supports, for example, a substrate 200 (e.g., a semiconductor wafer, an interposer, etc.) on which is stacked a stack 202 (only one shown) of a plurality of laterally spaced microelectronic devices 204 (e.g., semiconductor dies) having an array of conductive elements 206 in the form of, for example, metal pillars covered with solder and aligned with terminal pads of the next lower adjacent component, as described and illustrated with respect to FIGS. 1-4 , 7A, and 7B . Although in Fig.10Five microelectronic devices are shown in the stack 202 of FIG. 1 , such as four dynamic random access memory (DRAM in the form of DDR4, DDR5) dies stacked on a logic controller die in the form of a hybrid memory cube (HMC) or high bandwidth memory (HBM) stack of four dynamic random access memories (DRAM in the form of GDDR) on a device logic die, but the stack 202 of microelectronic devices 204 is not limited to a particular number of microelectronic devices 204. In practice, four, eight, twelve, sixteen, or more microelectronic devices in the form of memory dies (e.g., dynamic random access memory (DRAM) dies) may be employed in the stack 202.

[0040] With respect to the in-situ stack 202 of microelectronic devices 204, the bond head 102 is aligned (e.g., optically) with the stack 202, and the bond tip assembly 104 is lowered over the stack 202 such that a skirt 110 providing sidewalls of the bond tip assembly 104 surrounds the stack 202 and extends to a level proximate to the upper surface 208 of the substrate 200, thereby substantially enclosing the stack 202 within the chamber 112. The bond tip assembly 104 includes a primary heating device 114 located above a compression surface 116 that engages the uppermost microelectronic device 204 of the stack 202. The bond tip assembly 104 also includes one or more sidewall heating devices 118 (two shown) at or mounted to the skirt 110. In a thermocompression bonding operation, when the bonding tip assembly 104 is placed on the stack 202 of microelectronic devices 204, the main heating device 114 and the sidewall heating device 118 are activated to apply conductive, convective, and radiant heat to the top and sides of the stack 202, respectively, while a normal (i.e., perpendicular) force is applied to the stack 202 by the bonding tip assembly 104 through the compression surface 116, optionally with heat applied from the stage heating device 108. It is worth noting that, as Fig. 10A As shown, the sidewall heating devices 118 can be located on all sides of the stack 202 of microelectronic devices 204. The main heating device 114 and the sidewall heating devices 118 can be, for example, resistive heaters. The main heating device 114 can be ramped to operate at a temperature between about 400° C. and about 450° C., and the sidewall heating devices 118 can be ramped to operate at a temperature sufficient to substantially counteract the temperature of the microelectronic device 204 as shown in the figure. Figure 2 and 7BThe sidewall heater 118 may be operated at one or more temperatures to reduce heat loss vertically through and laterally from the stack 202 of the microelectronic devices 204 as shown in FIG. 1 and minimize thermal gradients from the top to the bottom of the stack 202. In this embodiment, the sidewall heater 118 may be, for example, a resistive type heater (e.g., a printed conductor on a dielectric substrate) that, for simplicity, is configured to operate substantially at a common temperature between, for example, about 200° C. to about 250° C. under the control of a temperature sensor (e.g., a thermocouple) to cycle power off at a preselected temperature to avoid overheating of the microelectronic devices 204 of the stack 202 while ensuring secure bonding of the conductive elements 206 and curing of the dielectric material 210 (e.g., NCF, WLUF) in and around the bond wires 212. The optional stage heater 108, if present, may be operated at a temperature between about 150° C. and about 160° C. under feedback control of the thermocouple to provide heat through the substrate 200 and into the stack 202. Alternatively, and as shown in dashed lines, an insulator 120, a heat reflective material 122, or both (with the insulator 120 placed outside the heat reflective material 122) may be placed within the skirt 110 laterally outside the sidewall heater 118 to contain heat within the chamber 112 and prevent heat from leaking into an adjacent stack of microelectronic devices 204 and initiating premature curing of the dielectric material 210 of the adjacent stack before its conductive elements 206 can be bonded. Alternatively, and as shown in FIG. Fig.13 and 14 As more fully described in the embodiments of the present invention, a low surface energy (LSE) material 126, as shown in dashed lines, may be applied to or formed on the inner wall 128 of the skirt 110. After the bonding tip assembly 104 is extended over the stack 202 of microelectronic devices 204, the power supplied to the main heating device 114 and the sidewall heating device 118 may be cycled on, or the bonding tip assembly 104 may be continuously preheated as is generally the case with the stage heating device 108. During the bonding process and between bonding of the stack 202, the power (i.e., current) supplied to the sidewall heating device 118 may be varied or cycled on and off to maintain the sidewall heating device 118 within an appropriate temperature range. In one embodiment, the sidewall heating device may be activated prior to placement on the stack 202 of microelectronic devices 204 to take into account that the sidewall heating device 118, unlike the main heating device 114 of the bonding tip assembly, will not physically contact the stack 202 and conduct heat. In any case, thermocompression bonding performed using this embodiment can be performed faster than conventional thermocompression bonding and produce a higher yield of interconnections of conductive elements 206 and fully cured dielectric material 210. Additionally, substantially enclosing each stack 202 of microelectronic devices 204 within chamber 112 during thermocompression bonding can substantially contain any contaminant materials that outgas from stack 202 and reduce the likelihood of contamination of adjacent stacks 202.

[0041] Reference now Fig.11 and 11A , schematically illustrates an embodiment of a thermocompression bonding tool 300. The thermocompression bonding tool 300 includes a bonding head 302 with a bonding tip assembly 304. The bonding head 302 with the bonding tip assembly 404 is movable in the X, Y, and Z planes under instructions from a controller and with the aid of position sensors (e.g., optical sensors) known in the art. The thermocompression bonding tool 300 also includes a bonding stage 306, which may optionally include a stage heating device 308, which may include a resistive heating element under closed-loop control of a thermocouple. In operation, the bonding station 306 supports, for example, a substrate 200 (e.g., a semiconductor wafer, an interposer, etc.) on which is stacked a stack 202 (only one shown) of a plurality of laterally spaced microelectronic devices 204 (e.g., semiconductor dies) having an array of conductive elements 206 in the form of, for example, metal pillars covered with solder and aligned with terminal pads of the next lower adjacent component, as described and illustrated with respect to FIGS. 1-4 , 7A, and 7B. Although in Fig.10 Five microelectronic devices are shown in the stack 202 of FIG. 1 , such as four dynamic random access memory (DRAM in the form of DDR4, DDR5) dies stacked on a logic controller die in the form of a hybrid memory cube (HMC) or high bandwidth memory (HBM) stack of four dynamic random access memories (DRAM in the form of GDDR) on a device logic die, but the stack 202 of microelectronic devices 204 is not limited to a particular number of microelectronic devices 204. In practice, four, eight, twelve, sixteen, or more microelectronic devices in the form of memory dies (e.g., dynamic random access memory (DRAM) dies) may be employed in the stack 202.

[0042] With respect to the in-place stack 202 of microelectronic devices 204, the bond head 302 is aligned (e.g., optically) with the stack 202, and the bond tip assembly 304 is lowered over the stack 202 such that the skirt 310 providing the sidewalls of the bond tip assembly 304 surrounds the stack 202 and extends to a level proximate the upper surface 208 of the substrate 200, thereby substantially enclosing the stack 202 in the chamber 312. Unlike the bond tip assembly 104 of the previous embodiment, the bond tip assembly 304 includes a separate bond tip compression member 304c having a compression surface 316 on its underside, which is surrounded by a bond tip barrel portion 304b of the skirt 310 and in which the bond tip compression member 304c is slidably disposed. The bond tip compression member 304c is biased downwardly against the stack 202 by a compression element 324 located between a top surface 331 of the bond tip barrel portion 304b and a top portion 333 of the bond tip compression member 304c. The compression element 324 may be, for example, a coil spring, a disc spring, a leaf spring, a resilient elastomeric element, etc., having a selected spring constant such that the joint tip compression member 304c applies a selected amount of normal force to the stack 202 of microelectronic devices 204 when the joint tip assembly is in place on the stack 202. The movement of the joint tip compression member 304c within the joint tip barrel portion 304b may be restricted to the vertical by, for example, a key 330 in a longitudinal slot 332 on the inside of the joint tip barrel portion 304b extending laterally from the side of the joint tip compression member 304c to the skirt 310 of the joint tip barrel portion 304b, which arrangement also keeps the joint tip compression member 304c within the joint tip barrel portion 304b when it is withdrawn from the stack 202.

[0043] The bonding tip compression member 304c of the bonding tip assembly 304 includes a primary heating device 314 immediately above the compression surface 316, which engages with the uppermost microelectronic device 204 of the stack 202. The bonding tip assembly 304 also includes one or more sidewall heating devices 318 (four are shown) in or mounted to each sidewall of the skirt 310 of the bonding tip barrel portion 304b. In a thermocompression bonding operation, when the bonding tip assembly 304 is placed on the stack 202 of microelectronic devices 204, the primary heating device 314 and the sidewall heating device 318 are activated to apply conductive radiation and convection heat to the top and sides of the stack 202, respectively, while a normal (i.e., perpendicular) force is applied by the bonding tip assembly 304 to the stack 202 through the compression surface 316, optionally with heat applied from the stage heating device 308. The main heating device 314 can be, for example, a resistive heater that is ramped to operate at a temperature between about 400° C. and about 450° C., and the side wall heating device 318 can be at a temperature sufficient to substantially offset the Figure 2 and 7BThe heat loss vertically through and laterally from the stack 202 of microelectronic devices is shown for operation at different temperatures. Fig.11 and 11A As shown in combination, discrete sidewall heating devices 318 may be located on each side of the stack 202 of microelectronic devices 204. Each sidewall heating device 318 may, for example, include a series of resistive elements (e.g., printed conductors on a dielectric substrate) oriented vertically or horizontally or in a zigzag pattern and extending substantially the height and width of each inner sidewall of the skirt 310. In one embodiment, the resistive heating elements may be configured to exhibit a gradually increasing resistance toward the lower end of the skirt 310 to provide higher heat to the stack 202 to offset heat loss through and from the stack 202 of microelectronic devices 204, thereby controlling and minimizing thermal gradients from the top to the bottom of the stack 202. In another embodiment, the resistive heating elements may be configured in an L-shaped cross-section and placed at the corners of the skirt 310 to concentrate heat near the corner areas of the stack 202 that are most susceptible to heat loss. In this embodiment, the resistive element of the sidewall heating device 318 can be, for example, configured to operate at a temperature ranging from about 100° C. at the upper extent of the skirt near the compression surface 316 to about 200° C. to about 300° C. (depending on the number of microelectronic devices 204 in the stack 202) near the lower extent of the skirt 310. The resistive element can be operated under feedback control of a temperature sensor (e.g., a thermocouple) to cycle power off at a preselected temperature at each vertical level within the skirt 310 to avoid overheating of the microelectronic devices 204 of the stack 202 while ensuring secure bonding of the conductive elements 206 and curing of the dielectric material 210 (e.g., NCF, WLUF) in the bond wires 212 and surrounding the conductive elements 206. Alternatively, the sidewall heating device 318 can be operated at substantially the same temperature from the top to the bottom of the skirt 310 under the control of the temperature sensor, for example, between about 200° C. to about 250° C. The optional stage heater 308, if present, may be operated at a temperature between about 150° C. and about 160° C. under feedback control of a thermocouple to provide heat through the substrate 200 and into the stack 202. Alternatively, an insulator 320, a heat reflective material 322, or both may be placed laterally within the skirt 310 outside of the sidewall heater 318 to contain the heat within the chamber 312 and prevent the heat from leaking into the adjacent stack 202 of microelectronic devices 204 and initiating premature curing of the dielectric material 210 of the adjacent stack before its conductive elements 206 can be bonded. Alternatively, and as described with respect to Fig.13 and 14As more fully described in an embodiment of the present invention, a low surface energy (LSE) material 326, as shown in dashed lines, may be applied to or formed on the inner wall 328 of the skirt 310. After the bonding tip assembly 304 is extended over the stack 202 of microelectronic devices 204, the power supplied to the main heating device 314 and the sidewall heating device 318 may be cycled on, or the bonding tip assembly 304 may be continuously preheated as the stage heating device 308. During the bonding process and between bonding of the stack 202, the power (i.e., current) supplied to the sidewall heating device 318 may be changed or cycled on and off to maintain the sidewall heating device 318 within an appropriate temperature range. In one embodiment, the sidewall heating device may be activated prior to placement on the stack 202 of microelectronic devices 204 to take into account that the sidewall heating device 118, unlike the main heating device 114 of the bonding tip assembly, will not physically contact the stack 202 and conduct heat. In any case, thermocompression bonding performed using this embodiment of the thermocompression bonding tool 300 can be performed faster than conventional thermocompression bonding and produce a higher yield of interconnections of the conductive elements 206 and the fully cured dielectric material 210. Additionally, substantially enclosing each stack 202 of microelectronic devices 204 within the chamber 312 during thermocompression bonding can substantially contain any contaminant material that outgasses from the stack 202 and reduce the likelihood of contamination of adjacent stacks 202.

[0044] Reference now Fig.12 , schematically illustrating an embodiment of a thermocompression bonding tool 400. The thermocompression bonding tool 400 includes a bonding head 402 with a bonding tip assembly 404. The bonding head 402 with the bonding tip assembly 404 is movable in the X, Y, and Z planes under instructions from a controller and with the aid of position sensors (e.g., optical sensors) known in the art. The thermocompression bonding tool 400 also includes a bonding table 406, which optionally includes a table heating device 408, which may include a resistive heating element. In operation, the bonding table 406 supports (for example) a substrate 200 (e.g., a semiconductor wafer, an interposer, etc.) on which a stack 202 (only one is shown) of several laterally spaced microelectronic devices 204 (e.g., semiconductor dies) is stacked, the stack 202 having an array of conductive elements 206, for example in the form of metal pillars, which are covered with solder and aligned with the terminal pads of the next lower adjacent component, as described and illustrated with respect to Figures 1 to 4, 7A and 7B. Although in Fig.10Five microelectronic devices are shown in the stack 202 of FIG. 1 , such as four dynamic random access memory (DRAM in the form of DDR4, DDR5) dies stacked on a logic controller die in the form of a hybrid memory cube (HMC) or high bandwidth memory (HBM) stack of four dynamic random access memories (DRAM in the form of GDDR) on a device logic die, but the stack 202 of microelectronic devices 204 is not limited to a particular number of microelectronic devices 204. In practice, four, eight, twelve, sixteen, or more microelectronic devices in the form of memory dies (e.g., dynamic random access memory (DRAM) dies) may be employed in the stack 202.

[0045] With respect to the in-place stack 202 of microelectronic devices 204, the bond head 402 is aligned with the stack 202 (e.g., optically), and the bond tip assembly 404 is lowered onto the stack 202 such that the skirt 410 providing the sidewalls of the bond tip assembly 404 surrounds the stack 202 and extends to a level proximate to the upper surface 208 of the substrate 200, thereby substantially enclosing the stack 202 in the bottom-open chamber 412. Unlike the bond tip assembly 104 of the first embodiment, the bond tip assembly 404 includes a separate bond tip compression member 404c in the form of a piston having a compression surface 416 on its underside, the bond tip compression member 404c being surrounded by a bond tip barrel portion 404b, the bond tip compression member 404c being slidably disposed within its bore. The bond tip compression member 404c can be biased downwardly against the stack 202 by a resilient compression element 424 located between a top surface 431 of the bond tip barrel portion 404b and a top portion 433 of the bond tip compression member 404c. The resilient compression element 424 may be, for example, a coil spring, a Belleville spring, a leaf spring, a resilient elastomeric element, etc., having a selected spring constant such that the joint tip compression member 404c applies a selected amount of normal force to the stack 202 of microelectronic devices 204 when the joint tip assembly 404 is positioned over the stack 202. The movement of the joint tip compression member 404c within the joint tip barrel portion 404b may be restricted to the vertical by, for example, a key 430 in a longitudinal slot 432 extending laterally from the side of the joint tip compression member 404c to the inside of the skirt 410 of the joint tip barrel portion 404b, which arrangement also allows the joint tip compression member to be retained within the joint tip barrel portion 404b when withdrawn from the stack 202.

[0046] The bonding tip compression member 404c of the bonding tip assembly 404 includes a primary heating device 414 immediately above the compression surface 416, which engages the uppermost microelectronic device 204 of the stack 202. The bonding tip assembly 404 also includes a plurality of sidewall heating devices 418 (four are shown) mounted within or to each sidewall of the skirt 410 of the bonding tip barrel portion 404b, each stage of the sidewall heating devices 418 extending substantially around the chamber 412 relative to the sidewall heating devices 118 of the thermocompression bonding tool 100, as shown. Fig. 10A As shown. In the thermocompression bonding operation, when the bonding tip assembly 404 is placed on the stack 202 of microelectronic devices 204, the main heating device 414 and the sidewall heating device 418 are activated to apply conductive, radiant and convective heat to the top and sides of the stack 202, respectively, while the bonding tip assembly 404 applies a normal (i.e., vertical) force to the stack 202 through the compression surface 416, optionally with the heat applied from the stage heating device 408. The main heating device 414 can be, for example, a resistive heater that is ramped to operate at a temperature between about 400° C. and about 450° C., and the sidewall heating device 418 can be independently powered and controlled to operate at a temperature sufficient to substantially offset the temperature of the stack 202 as shown in the figure. Figure 2 and 7B4. It is noted that each level of discrete sidewall heating devices 418 surrounding the stack 202 of microelectronic devices 204 may, for example, include a series of horizontally extending resistive elements (e.g., printed conductors on a dielectric substrate), with it being understood that the resistive elements of a given level may include a zigzag configuration internally to provide enhanced surface area coverage for heat transfer. In one embodiment, the resistive heating elements of each level of sidewall heating devices 418 may be configured to exhibit progressively increasing resistances in the levels progressively advancing toward the lower end of the skirt 410 to provide higher heat to the stack 202, or may receive progressively higher power inputs to offset heat losses through and from the stack 202 of microelectronic devices 204. In this embodiment, the uppermost level of resistive elements of the sidewall heating devices 418a may, for example, be configured to operate at a temperature in the range of about 100° C. to about 125° C. near the upper extent of the skirt near the compression surface 416. The middle level sidewall heating devices 418b and 418c can be configured, for example, to operate at about 150° C. to about 175° C. and about 200° C. to about 225° C., respectively. The lowermost sidewall heating device 418d near the lower extent of the skirt 410 can be configured, for example, to operate at about 250° C. to about 275° C. Of course, the number of stages of sidewall heating devices and the operating temperatures and temperature ranges can be adjusted by tailoring the resistance of the resistive elements of the various stages, adjusting or switching the applied power (i.e., current), or both, to offset heat losses and improve the uniformity of the temperature experienced by the various microelectronic devices 204 in the stack 202 depending on the number of microelectronic devices 204. The resistive elements may be operated under the control of temperature sensors (e.g., thermocouples) to cycle power off at preselected temperatures at each vertical level within the skirt 410 to avoid overheating of the microelectronic devices 204 of the stack 202 while ensuring secure bonding of the conductive elements 206 and solidification of the dielectric material 210 (e.g., NCF, WLUF) in and around the bond wires 212. Alternatively, the sidewall heaters 418 may be operated under the control of the temperature sensors at substantially the same temperature from the top to the bottom of the skirt 410, e.g., between about 200° C. and about 250° C. The optional stage heater 408, if present, may be operated under feedback control of the thermocouples at a temperature between about 150° C. and about 160° C. to provide heat through the substrate 200 and into the stack 202. Alternatively, as described with respect to Fig.10 , 10A, 11 and 11A, an insulator, a heat reflective material, or both (the insulator is placed outside the heat reflective material) may be placed inside or outside the inner surface of the skirt 410 laterally outside the sidewall heating device 418 to contain heat within the chamber 412 and prevent heat from leaking into the adjacent stack 202 of microelectronic devices 204 and inducing premature curing of the dielectric material 210 of the adjacent stack before its conductive elements 206 can be bonded. As another option, as Fig.10 , 10A , 11 and 11A and as shown Fig.13 and 14 A layer of transparent, low surface energy (LSE) material as more fully shown and described may be applied to or formed on the compression surface 416 and the inner wall of the skirt 410. After the bonding tip assembly 404 is extended over the stack 202 of microelectronic devices 204, the power supplied to the main heating device 414 and the sidewall heating device 418 may be cycled on, or the bonding tip assembly 404 may be continuously preheated as the stage heating device 408. During the bonding process and between bonding of the stack 202, the power (i.e., current) supplied to the sidewall heating device 418 may be varied or cycled on and off to maintain the sidewall heating device 418 within an appropriate temperature range. In one embodiment, the sidewall heating device may be activated prior to placement on the stack 202 of microelectronic devices 204 to account for the fact that the sidewall heating device 118, unlike the main heating device 114 of the bonding tip assembly, will not physically contact the stack 202 and conduct heat. In any case, thermocompression bonding performed using this embodiment of the thermocompression bonding tool 400 can be performed faster than conventional thermocompression bonding and produce a higher yield of interconnections of the conductive elements 206 and the fully cured dielectric material 210. Additionally, substantially enclosing each stack 202 of microelectronic devices 204 within the chamber 412 during thermocompression bonding can substantially contain any contaminant material that is outgassed from the stack 202 and reduce the likelihood of contamination of adjacent stacks 202.

[0047] In the attached figure Fig.13 and 14An embodiment of a thermocompression bonding tool 500 is shown, which includes a bonding head 502 with a bonding tip 504. The bonding head 502 with the bonding tip 504 can be movable in the X, Y, and Z planes under instructions from a controller and with the aid of position sensors (e.g., optical sensors) known in the art. Thermocompression bonding tool 500 also includes a bonding stage 506, which can optionally include a stage heating device 508, which can include a resistive heating element controlled by a thermocouple in a temperature range of about 150° C. to about 160° C. In operation, the bonding station 506 supports, for example, a substrate 200 (e.g., a semiconductor wafer, an interposer, etc.) on which is stacked a stack 202 of a plurality of laterally spaced microelectronic devices 204 (e.g., semiconductor dies), the stack 202 having an array of conductive elements, for example, in the form of metal pillars, which are covered by solder and aligned with the terminal pads of the next lower adjacent component, as described and illustrated with respect to FIGS. 1 to 4, 7A and 7B, 10, 10A, 11, 11A, and 12. By way of example only, the stack 202 may include a plurality of dynamic random access memory (DRAM in the form of DDR4, DDR5) dies stacked on a logic controller die, in the form of a hybrid memory cube (HMC) or high bandwidth memory (HBM) stack of dynamic random access memory (DRAM in the form of GDDR) on a device logic die. However, the stack 202 of microelectronic devices 204 is not limited to a particular number of microelectronic devices 204. In practice, four, eight, twelve, sixteen, or more microelectronic devices in the form of memory dies (eg, dynamic random access memory (DRAM) dies) may be employed in stack 202 .

[0048] With respect to the in-situ stack 202 of microelectronic devices 204, a bond head 502 is aligned (e.g., optically) with the stack 202, and a bond tip 504 is lowered over the stack 202 such that a skirt 510 carried by the bond head 502 and surrounding the bond tip 504 extends to a level proximate to the upper surface 208 of the substrate 200, thereby substantially enclosing the stack 202 within the chamber 512. The bond tip 504 includes a primary heating device 514 immediately above a compression surface 516 that engages the uppermost microelectronic device 204 of the stack 202. In a thermocompression bonding operation, when the bond tip 504 is placed over the stack 202 of microelectronic devices 204, the primary heating device 514 is activated to apply heat from the top of the stack 202 while a normal (i.e., perpendicular) force is applied by the bond tip 504 through the compression surface 516 to the stack 202, optionally with heat applied from a stage heating device 508. To contain the heat applied to the stack 202 of microelectronic devices 204, the skirt 510 surrounding the stack 202 may include an assembly of different materials. For example, for structural integrity and heat reflection, the skirt 510 may be configured as a heat reflective material in the form of a thin (i.e., foil) metal (e.g., titanium, tungsten, copper) rectangular tube 530 that presents an internal highly reflective (e.g., mirror) finish, which can be achieved by chemical plating or electroplating or sputtering the metal finish. The size and configuration of the rectangular tube 530 are designed to surround the stack 202 relatively tightly with sufficient gap C to prevent contact with the microelectronic device 204 while reflecting heat into the stack 202 and dissipating the heat vertically through the conductive foil material. On the outside of the tube 530, a layer of thermal insulation material 532 (e.g., silicon oxide, silicon nitride) may be optionally provided to further contain the heat to the stack 202 and prevent undesirable heat transfer to adjacent stacks 202.

[0049] Alternatively, a layer of transparent low surface energy (LSE) material 534, such as polyparaxylene HT or N material, fluoropolymer (such as polytetrafluoroethylene (PTFE) material or perfluoroalkoxy (PFA) material), graphene or diamond-like carbon (DLC). Specific materials of the foregoing type may be or may be formulated to accommodate the application of heat and remain solid without decomposition at temperatures such as about 300°C or higher, such as used in thermocompression bonding processes. Thermocompression bonding temperatures are known to be as high as about 400°C, and theoretically can be as low as about 220°C, the melting point of Sn. By definition, such LSE materials resist wetting by liquids, exhibit large contact angles with droplets placed on the surface of the LSE material, and resist adhesion to other materials. The LSE material 534 may cover the compression surface 516 and line the interior of the skirt 510 at a thickness of, for example, about 2 μm to about 10 μm, although other thicknesses may be used. For example, polyparaxylene may be conformally applied at a thickness of about 0.1 μm to about 76 μm. For the sake of clarity, the drawings herein exaggerate the thickness of the LSE material and are therefore not drawn to scale. The LSE material 534 can prevent flakes (e.g., NCF, WLUF) of the dielectric material 210 from excessively flowing from the bond wires 212 along the perimeter of the stack 202 to limit the flakes from protruding from the bond wires 212 along the perimeter of the stack 202, while preventing the dielectric material 210 from adhering to the skirt 510 and preventing contamination of the dielectric material 210. In addition, the presence of the skirt 510 will prevent the flakes of the dielectric material 210 of the adjacent stack 202 of the microelectronic device 204 from meshing, which can induce or enhance wafer warpage in downstream processing steps.

[0050] The main heating device 514, which may be, for example, a resistive heater that is ramped to operate at a temperature between about 400° and about 450°, may not be sufficient to ensure bonding of conductive elements and complete solidification of dielectric materials at corners, perimeters, and lower device levels of the stack 202, even with the addition of heat from the stage heating device 508 but without the presence of the skirt 510. However, the presence of the skirt 510 with the metal foil tube 530 as a component of the thermocompression bonding tool 500 can ensure secure bonding of conductive elements (e.g., metal pillars covering terminal pads with solder) and solidification of dielectric materials (e.g., NCF, WLUF) in the bonding wires between the microelectronic devices 204 and around the conductive elements by reflecting heat and distributing the heat applied to the stack 202 of microelectronic devices 204 within the chamber 512. The insulating material 532 and the heat reflective metal foil 530 contain the heat within the chamber 512 while preventing the heat from leaking into the adjacent stack 202 of microelectronic devices 204 and inducing premature curing of the dielectric material of the adjacent stack 202 before its conductive elements are bonded. After the bonding tip 504 extends over the stack 202 of microelectronic devices 204, the power supplied to the main heating device 514 can be cycled on (i.e., ramped up), or the bonding tip 504 can be continuously preheated as the stage heating device 508. During the bonding process and between bonding of the stacks 202, the power (i.e., current) supplied to the main heating device 514 can be changed, or cycled on and off, to keep the main heating device 514 within an appropriate temperature range. In any case, the thermocompression bonding performed using this embodiment can be performed faster than conventional thermocompression bonding and produce a higher yield of interconnections of conductive elements and fully cured dielectric materials. Additionally, substantially enclosing each stack 202 of microelectronic devices 204 within the chamber 512 may substantially contain any contaminant materials that outgas from the stack 202 and reduce the likelihood of contamination of adjacent stacks 202 during thermocompression bonding.

[0051] As additional features, such as Fig.13 and 14 As shown, one or more ports 550 may be disposed in the bonding head 502, as shown in phantom, or otherwise positioned to open into the chamber 512, the ports 550 being in communication with a vacuum source 554 through one or more conduits 552 to reduce the atmospheric pressure within the chamber 512, thereby removing contaminant material contained within the chamber 512 through the skirt 510 to a filter or trap 556. The vacuum source 554 may be selectively activated before or when the bonding tip 504 contacts each stack 202 of microelectronic devices 204 to be thermocompressively bonded, or may be operated continuously. Although reference is made to Fig.13 and 14 Although only one embodiment of the present disclosure has been described and illustrated, the feature can be incorporated into every other embodiment of the present disclosure and function in the same manner.

[0052] It should be noted that the size and width of the elements of the bonding head and skirt of the illustrated embodiment have been exaggerated for clarity. In an embodiment, the skirt of the bonding head and bonding tip assembly can be very thin in the transverse direction to accommodate the close spacing of adjacent stacks of microelectronic devices. This spacing can currently be in the range of about 300 μm to about 500 μm, and is expected to become smaller. In addition, the interior of the skirt can be laterally spaced outside the stack periphery because contact with the die stack should be avoided. In addition, since the length, width, and stack height of microelectronic devices of different stacks vary due to differences in device thickness and the number of devices in the stack, it will be understood by those of ordinary skill in the art that the bonding head and bonding tip assembly implementing the embodiments of the present disclosure can be customized for specific applications.

[0053] Fig.15 6 is a flow chart of a thermocompression bonding process 600 according to an embodiment of the present disclosure. In action 602, a stack of microelectronic devices is formed on a substrate. In action 604, a bonding head including a bonding tip assembly and a skirt extending downward from the bonding tip and surrounding the bonding tip is placed on and around the stack of microelectronic devices to substantially enclose the stack. In action 606, a thermocompression bonding process is performed by applying heat and a normal force to the enclosed stack of microelectronic devices by the bonding tip. In action 608, during the thermocompression bonding process, additional heat is optionally applied to the stack of microelectronic devices from the sidewalls of the skirt that encloses the stack of microelectronic devices. In action 610, during the thermocompression bonding process, heat is optionally reflected from the skirt back to the stack of microelectronic devices, optionally contained within the skirt by an insulating material, and contaminant material is prevented from adhering to the interior of the skirt through an optional LSE material liner. Of course, optional process action 608 can be combined with any or all of optional process actions 610.

[0054] As used herein, the terms "comprising," "including," "containing," "characterized by," and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional, unrecited elements or methodological actions, and also encompass the more restrictive terms "consisting of," and "consisting essentially of," and their grammatical equivalents.

[0055] As used herein, the term “may” with respect to materials, structures, features, or method acts indicates that such terms are intended for use in implementing embodiments of the present disclosure, and such terms are used in preference to the more restrictive term “are” to avoid any suggestion that other compatible materials, structures, features, and methods that may be used in combination therewith should or must be excluded.

[0056] As used herein, the terms "longitudinal", "vertical", "lateral", and "horizontal" refer to the major plane of a substrate (e.g., a substrate material, a substrate structure, a substrate configuration, etc.) in which or on which one or more structures and / or features are formed, and are not necessarily defined by the Earth's gravitational field. A "lateral" or "horizontal" direction is a direction substantially parallel to the major plane of the substrate, while a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the major plane of the substrate. The major plane of a substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate.

[0057] As used herein, spatially relative terms, such as "under," "below," "lower," "bottom," "above," "on," "upper," "top," "front," "rear," "left," "right," and the like, may be used for ease of description to describe the relationship of one element or feature to another element or feature as shown. Unless otherwise indicated, spatially relative terms are intended to encompass different orientations of the material other than the orientation depicted in the accompanying drawings. For example, if the material in the accompanying drawings is inverted, an element described as "above" or "above" or "above" or "on top" of other elements or features will be oriented "below" or "below" or "below" or "on the bottom" of the other elements or features. Thus, the term "above" may encompass both above and below orientations, depending on the context in which the term is used, which will be apparent to one of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptors used herein are interpreted accordingly.

[0058] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0059] As used herein, the terms "configured" and "configuration" refer to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device that facilitates operation of the one or more structures and devices in a predetermined manner.

[0060] As used herein, the term "substantially" with respect to a given parameter, property, or condition refers to and encompasses the extent to which the given parameter, property, or condition is satisfied with a degree of variation (such as within acceptable manufacturing tolerances) as would be understood by one of ordinary skill in the art. As an example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be satisfied by at least 90.0%, satisfied by at least 95.0%, satisfied by at least 99.0%, or even satisfied by at least 99.9%.

[0061] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes that numerical value and the degree of variance of that numerical value as will be understood by one of ordinary skill in the art to be within an acceptable tolerance for that particular parameter. For example, "about" or "approximately" with respect to a numerical value may include other numerical values ​​within the range of 90.0% to 110.0% of the numerical value, such as within the range of 95.0% to 105.0% of the numerical value, within the range of 97.5% to 102.5% of the numerical value, within the range of 99.0% to 101.0% of the numerical value, within the range of 99.5% to 100.5% of the numerical value, or within the range of 99.9% to 100.1% of the numerical value.

[0062] As used herein, the terms "layer" and "film" mean and encompass a level, sheet, or coating of material present on a structure, which level or coating may be continuous or discontinuous between portions of the material and may be conformal or non-conformal, unless otherwise specified.

[0063] As used herein, the term "substrate" means and includes a base material or structure on which additional materials are formed. The substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, a semiconductor substrate on which one or more materials, layers, structures or regions are formed. The materials on the semiconductor substrate can include but are not limited to semiconductor materials, insulating materials, conductive materials, etc. The substrate can be a conventional silicon substrate or other bulk substrates including a semiconductor material layer. As used herein, the term "bulk substrate" means and includes not only silicon wafers, but also silicon on insulator ("SOI") substrates, such as silicon on sapphire ("SOS") substrates and silicon on glass ("SOG") substrates, silicon epitaxial layers on the base semiconductor basis, and other semiconductor or optoelectronic materials, such as silicon, germanium, germanium, gallium arsenide, gallium nitride and indium phosphide. The substrate can be doped or undoped. The term "substrate" also means and includes an organic substrate, for example, a substrate having multiple metal layers in the form of traces and interposed with a dielectric layer (e.g., a resin glass woven polymer). For example, a conventional BGA package contains multiple dies and packaging (eg, epoxy molding compound (EMC)) on one side of an organizational substrate and an array of solder balls on the other side.

[0064] As used herein, the term "microelectronic device" means, by way of non-limiting example, and includes semiconductor dies, dies that exhibit functionality through activities other than semiconductor activity, microelectromechanical systems (MEM) devices, substrates comprising multiple dies (including conventional wafers and other bulk substrates as described above), and partial wafers and substrate segments containing more than one die location.

[0065] As used herein, the term "memory device" means, by way of non-limiting example, and includes semiconductor and other microelectronic devices that exhibit memory functionality, but does not exclude other functionalities unless the context in which the term is used clearly indicates otherwise.

[0066] As used herein, unless expressly stated otherwise, the terms "metal" and "metallic material" mean and include elemental metals, metal alloys, and combinations (eg, layers) of different and adjacent metals or metal alloys.

[0067] As used herein, the terms "dielectric film" and "dielectric material" mean and include preformed or dispensed dielectric material films applied prior to microelectronic device stacking and referred to as NCF and WLUF, as well as non-conductive glue (NCF) dielectric materials. Such dielectric films typically include a B-stage partially cured silica particle-filled epoxy-type thermosetting resin, provide consistent thickness, may include flux for the aforementioned solder reflow (where applicable), and facilitate stacking of microelectronic devices, wherein segments of the dielectric film are already in place on each individual device prior to stacking.

[0068] Embodiments of the present disclosure include a thermocompression bonding apparatus including a bonding stage and a bonding head movable in the X, Y, and Z directions. The bonding head includes a bonding tip having a compression surface on its underside, the bonding tip including a primary heating device and a skirt extending downwardly from the bonding head, surrounding the bonding tip and laterally enclosing a bottom-open chamber.

[0069] An embodiment of the present disclosure includes a method comprising: aligning a bonding head of a thermocompression bonding tool with a stack of microelectronic devices; and lowering the bonding head over the stack of microelectronic devices to substantially enclose the stack in a chamber within a skirt extending downwardly from the bonding head, and contacting an uppermost microelectronic device of the stack with a bonding tip of the bonding head within the chamber. Heat is applied from the bonding tip to the stack of microelectronic devices through the uppermost microelectronic device, and heat loss from the bonding tip through the stack of microelectronic devices and from the periphery of the stack is reduced by the skirt.

[0070] An embodiment of the present disclosure includes a method comprising: aligning a bonding head of a thermocompression bonding tool with a stack of microelectronic devices; lowering the bonding head of the thermocompression bonding tool over the stack of microelectronic devices; heating the stack of microelectronic devices with the bonding head; and substantially containing contaminant material degassed from bonding wires between the stacked microelectronic devices within a skirt that is carried by the bonding head and substantially encloses the stack.

[0071] Although certain illustrative embodiments have been described in conjunction with the accompanying drawings, those skilled in the art will recognize and appreciate that the embodiments encompassed by the present disclosure are not limited to those embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications may be made to the embodiments described herein without departing from the scope of the embodiments encompassed by the present disclosure, such as those claimed below, including legal equivalents. Additionally, features from one disclosed embodiment may be combined with features of one or more other disclosed embodiments while still being encompassed within the scope of the present disclosure.

Claims

1. A thermocompression bonding device, comprising: Jointing table; A bonding head movable in X, Y and Z directions, the bonding head comprising: an engagement tip having a compression surface on its underside, the engagement tip containing a primary heating device; and A skirt is carried by the bond head and is movable therewith, the skirt extending vertically downwardly from the bond head around the bond tip and laterally surrounding an open-bottomed chamber sized to accommodate a single stack of two or more microelectronic devices.

2. The thermocompression bonding apparatus of claim 1, wherein the skirt and the bonding tip combination comprises a bonding tip assembly, and the skirt includes one or more sidewall heating devices.

3. The thermocompression bonding apparatus of claim 2, wherein one or more of the one or more sidewall heating devices extend substantially around the chamber. 4 . The thermocompression bonding apparatus according to claim 2 , wherein the one or more side wall heating devices include two or more side wall heating devices that are horizontally oriented and vertically stacked. 5 . The thermocompression bonding apparatus of claim 4 , wherein the two or more side wall heating devices extend substantially around the chamber.

6. The thermocompression bonding apparatus of claim 4, wherein each of the two or more horizontally-oriented and vertically stacked sidewalls is configured to provide a different amount of heat, or is controllable to provide a different amount of heat.

7. The thermocompression bonding apparatus of claim 3, wherein the one or more sidewall heating devices include sidewall heating devices extending vertically and horizontally along each side of the skirt.

8. The thermocompression bonding apparatus of claim 6, wherein each sidewall heating device is configured to provide increasing heat with increasing vertical distance from the bonding tip, or is controllable to provide different amounts of heat with increasing vertical distance from the bonding tip.

9. The thermocompression bonding apparatus according to any one of claims 1 to 8, wherein the bonding stage includes a stage heating device.

10. The thermocompression bonding device according to any one of claims 1 to 8, wherein the skirt further comprises one or more thermal insulation materials, thermal reflective materials and low surface energy (LSE) materials, the thermal insulation material vertically extends along the skirt from near the top of the chamber to near the bottom of the chamber, and extends around the chamber circumference on the lateral outside of the one or more side wall heating devices, the thermal reflective material vertically extends along the skirt from near the top of the chamber to near the bottom of the chamber, and extends around the chamber circumference on the lateral outside of the one or more side wall heating devices, and the low surface energy (LSE) material lines the inner surface of the skirt. 11 . The thermocompression bonding apparatus according to claim 10 , wherein the skirt includes the heat insulating material surrounding the heat reflecting material, and the LSE material lining an inner surface of the skirt.

12. A thermocompression bonding apparatus according to any one of claims 2 to 8, wherein the one or more sidewall heating devices are configured to provide sufficient heat to the stack of microelectronic devices located on the bonding stage to at least partially offset the loss of heat applied by the main heating device of the bonding tip, thereby initiating the bonding of discrete conductive elements between the stacked microelectronic devices and the curing of dielectric materials located in the bonding lines between the microelectronic devices and surrounding the discrete conductive elements.

13. A hot compression bonding device according to any one of claims 1 to 8, wherein the bonding tip is configured as a bonding tip compression member vertically slidably disposed in the chamber, and further comprises an elastic compression element located above the bonding tip compression member, the elastic compression element being between the top surface of the hole of the bonding tip barrel from which the skirt extends downward and the top of the bonding tip compression member.

14. The heat-compression bonding apparatus of claim 13, further comprising a mating key and groove arrangement between the bonding tip compression member and at least one of the bonding tip barrel and the skirt, the mating key and groove arrangement being configured to constrain movement of the bonding tip compression member to a vertical direction.

15. Thermocompression bonding apparatus according to any one of claims 1 to 8, wherein the skirt comprises a tube of heat reflective material extending downwardly from the bonding head.

16. The thermocompression bonding apparatus of claim 15, wherein the tube comprises a metal material having a polished inner surface.

17. The thermocompression bonding apparatus of claim 15, further comprising a thermal insulation material surrounding and carried by the tube.

18. The thermocompression bonding apparatus of claim 17, further comprising a transparent coating of a low surface energy (LSE) material lining an inner surface of the heat reflective material.

19. The thermocompression bonding apparatus of claim 18, wherein the LSE material covers the compression surface of the bonding tip.

20. The thermocompression bonding apparatus of claim 15, further comprising a transparent coating of a low surface energy (LSE) material lining an inner surface of the heat reflective material.

21. The hot compression bonding device according to claim 15, wherein the bonding tip is configured to be vertically slidably disposed in a bonding tip compression member within the chamber, and further comprises an elastic compression element located above the bonding tip compression member, the elastic compression element being between the top surface of the chamber and the top of the bonding tip compression member.

22. The thermocompression bonding apparatus of any one of claims 1 to 8, further comprising one or more ports carried by the bonding head and leading to the bottom-open chamber, and a vacuum source in communication with the one or more ports.

23. A method for performing an operation on a microelectronic device, comprising: aligning a bond head of a thermocompression bonding tool with a stack having two or more microelectronic devices supported on a substrate; lowering the bond head over the stack of microelectronic devices to surround and substantially enclose the stack in a chamber within a skirt and to contact an uppermost microelectronic device of the stack with a bond tip of the bond head within the chamber, the skirt being secured to the bond head and extending vertically downwardly from the bond head; applying heat from the bonding tip to the stack of microelectronic devices through the uppermost microelectronic device; as well as Heat losses from the engagement tip through the stack of microelectronic devices and from the periphery of the stack are reduced by the skirt.

24. The method of claim 23, further comprising adding heat to the stack of microelectronic devices from one or more heating devices carried by the skirt.

25. The method of claim 24, further comprising using the one or more heating devices to add different amounts of heat from different vertical portions of the skirt.

26. The method of claim 23, further comprising adding heat to the stack of microelectronic devices from one or more heating devices carried by the skirt from substantially the entire periphery of the skirt.

27. The method of claim 23, wherein reducing heat loss from the engagement tip through the stack of microelectronic devices and from a periphery of the stack by the skirt comprises using a material for the skirt that includes thermal insulation.

28. The method of claim 23, wherein reducing heat loss from the engagement tip through the stack of microelectronic devices and from the periphery of the stack by the skirt comprises utilizing a polished metal material forming an inner surface of the skirt to reflect heat lost from the stack of microelectronic devices from the skirt.

29. The method of claim 23, further comprising preventing dielectric material squeezed out along the perimeter from bond wires between microelectronic devices of the skirt from adhering to and contacting an inner surface of the skirt.

30. The method of claim 29, wherein preventing dielectric material squeezed out from bond wires between microelectronic devices along the perimeter of the skirt from adhering to and contacting an inner surface of the skirt comprises preventing adhering with a low surface energy (LSE) material lining the inner surface.

31. The method of claim 30, further comprising coating the bonding tip with the LSE material to prevent dielectric material squeezed out along the perimeter of a bonding wire between microelectronic devices of the skirt from adhering to the bonding tip.

32. A method for performing an operation on a microelectronic device, comprising: aligning a bond head of a thermocompression bonding tool with the stack of microelectronic devices; lowering a bond head of a thermocompression bonding tool onto the stack of microelectronic devices; heating the stack of microelectronic devices with the bond head; as well as Contaminant material outgassed from bond wires between the stacked microelectronic devices in response to the heating is substantially contained within a chamber surrounded by a skirt carried by the bond head and substantially enclosing the stack.

33. The method of claim 32, further comprising preventing dielectric material extruded from the bond wire along the perimeter from adhering to the interior of the skirt.

34. The method of claim 32, further comprising reflecting heat lost from the stack of microelectronic devices from an interior of the skirt.

35. The method of claim 32, further comprising reducing heat loss from a stack of the microelectronic devices with a material of the skirt.

36. The method of claim 32, further comprising removing at least a portion of the contaminant material contained within the chamber prior to lifting the bond head from the stack of microelectronic devices.

37. The method of claim 36, wherein removing comprises reducing the atmospheric pressure within the chamber with a vacuum source in communication with the chamber.

Images