Time synchronization method, network device and storage medium

Abstract

The embodiments of the present invention relate to the field of communication technology, and disclose a time synchronization method, a network device, and a storage medium. In some embodiments of the present invention, the time synchronization method includes: obtaining system time; synchronizing the system time to a counter of a programming module and a switching module, so as to synchronize the system time with an upper-level device and a lower-level device through the switching module and the programming module, respectively. This embodiment enables the production cost of network devices to be reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communication technology, and in particular to a time synchronization method, a network device and a storage medium. Background Art

[0002] With the continuous development of communication technology, synchronous base station technology has been widely used. The switching and roaming of base station work require high-precision time synchronization to improve precise time control. The IEEE 1588v2 time synchronization technology based on hardware timestamp technology and network time synchronization protocol can achieve nanosecond-level time synchronization accuracy and has become the current mainstream time synchronization technology. According to different application scenarios, the time synchronization model is divided into three models: ordinary clock (OC), boundary clock (BC), and transparent clock (TC). The OC model has only one 1588 port and only works in the master state or slave state; the BC model has multiple 1588 ports, one of which is a slave, and the system time can be synchronized with the upper-level device through this port. The other ports are masters and provide time synchronization for the lower-level devices; TC is a transparent transmission mode, which does not terminate the 1588 message and only forwards the message.

[0003] When a device uses the BC time model, a first switching chip and a second switching chip are usually provided, which results in the device having problems of large size and high cost. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a time synchronization method, a network device and a storage medium, so as to reduce the production cost of the network device.

[0005] To solve the above technical problems, an embodiment of the present invention provides a time synchronization method, including: acquiring system time; synchronizing the system time to the counter of the programming module and the switching module, so as to synchronize the system time with the upper-level device and the lower-level device through the switching module and the programming module respectively.

[0006] An embodiment of the present invention also provides a network device, including: an acquisition module and a synchronization module; the acquisition module is used to acquire system time; the synchronization module is used to synchronize the system time to the counter of the programming module and the switching module, so as to synchronize the system time with the upper-level device and the lower-level device respectively through the switching module and the programming module.

[0007] An embodiment of the present invention also provides a network device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the above-mentioned time synchronization method.

[0008] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program, which implements the time synchronization method mentioned in the above embodiment when the computer program is executed by a processor.

[0009] The embodiment of the present invention synchronizes the system time to the switching module and the programming module, so that the time bases of the switching module and the programming module are the same, and the time of the switching module is synchronized with the system time, so that the network device can perform system time synchronization with the upper-level device and the lower-level device respectively through one switching module, thereby reducing the number of switching modules in the network device, reducing the production cost of the network device, and reducing the size of the network device. The problem that the prior art must use two switching modules to complete the time synchronization with the upper-level device and the lower-level device due to the different time bases adopted, which makes the equipment cost too high, is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] One or more embodiments are exemplarily described by the pictures in the corresponding drawings, and these exemplary descriptions do not constitute limitations on the embodiments.

[0011] Figure 1 is a flow chart of a time synchronization method according to a first embodiment of the present invention;

[0012] Figure 2 yes Figure 1 A schematic diagram of a process of performing system time synchronization between a network device and an upper-level device in a time synchronization method in a first embodiment of the present invention is shown;

[0013] Figure 3 yes Figure 1 A schematic diagram of a process in which a network device synchronizes system time to a next-level device through a lower network port in a time synchronization method in a first embodiment of the present invention is shown;

[0014] Figure 4 is a flow chart of a time synchronization method according to a second embodiment of the present invention;

[0015] Figure 5 yes Figure 4 FIG. 1 is a diagram showing a process of handling an abnormality of CF1 and an abnormality of CF1 in a time synchronization method according to a second embodiment of the present invention;

[0016] Figure 6 yes Figure 4A diagram showing a process of handling an abnormality of CF2 and an abnormality of CF2 in a time synchronization method in a second embodiment of the present invention;

[0017] Figure 7 is a schematic structural diagram of a network device according to a third embodiment of the present invention;

[0018] Figure 8 is a schematic structural diagram of a network device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0019] To make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented. The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined and referenced with each other without contradiction.

[0020] The first embodiment of the present invention relates to a time synchronization method, comprising the following steps: obtaining system time; synchronizing the system time to a counter of a programming module and a switching module, so as to synchronize the system time with an upper-level device and a lower-level device through the switching module and the programming module, respectively. When the time synchronization method is adopted, the system time is synchronized to the switching module and the programming module, so that the time bases of the switching module and the programming module are the same, and the time of the switching module is synchronized with the system time, so that the network device can synchronize the system time with the upper-level device and the lower-level device through one switching module, thereby reducing the number of switching modules in the network device, reducing the production cost of the network device, and reducing the size of the network device.

[0021] The implementation details of the time synchronization method of this embodiment are described below. The following content is only the implementation details provided for the convenience of understanding and is not necessary for implementing this solution.

[0022] The time synchronization method in this embodiment is applied to network devices, such as Figure 1 As shown, the specific steps include:

[0023] Step 101, obtaining system time.

[0024] Specifically, the network device obtains the current system time in real time to perform subsequent operations. The obtained system time may be the system time in the programming module or the system time in other modules, which is not limited in this embodiment.

[0025] Step 102: Synchronize the system time to the counter of the programming module and the switching module, so as to synchronize the system time with the upper-level device and the lower-level device through the switching module and the programming module respectively.

[0026] Specifically, in the prior art, two switching chips are often required to be set in the network device. Among them, the port of the first switching chip is used as the uplink port of the network device, and a continuous timer / counter (T / C) time base is adopted. The port of the second switching chip is used as the downlink port of the network device, and a system time base is adopted. The uplink port of the network device is used as the slave port, and the system time is synchronized with the upper-level device through the first switching chip and the field programmable gate array (Field Programmable Gate Array, FPGA) chip. The downlink port of the network device is used as the master port, and the time is synchronized with the lower-level device through the second switching chip and the FPGA chip. Therefore, the existing network device must be provided with two switching chips to realize the system time synchronization of the network device with the upper-level device and the lower-level device. In this embodiment, the network device synchronizes the system time to the counter and the switching module of the programming module, so that the counter time of the programming module and the time of the switching module are synchronized with the system time, so that the network device performs system time synchronization with the upper-level device and the lower-level device through the switching module and the programming module respectively.

[0027] In one example, the programming module may be a programmable gate array (FPGA chip), and the switching module may be a switching chip. The clocks of the FPGA chip and the switching chip are of the same source, so that the FPGA chip and the switching chip are in a synchronous state.

[0028] In one example, the time synchronization method is executed by an FPGA chip, the system time is the system time in the FPGA chip, and the process of the network device synchronizing the system time with the upper-level device is as follows: Figure 2 As shown, the following steps are included:

[0029] Step 201: Synchronize the system time to the counter of the FPGA chip and the counter of the switch chip.

[0030] Specifically, the FPGA chip synchronizes the system time of the FPGA chip to the counter of the FPGA chip and the counter of the switching chip. Since the counter of the FPGA chip and the counter of the switching chip are both synchronized with the system time, the timestamps issued by the FPGA chip and the timestamps issued by the switching chip are based on the same time reference, so that the residence time can be calculated based on the timestamps issued by the FPGA chip and the timestamps issued by the switching chip, thereby ensuring the accuracy of the calculated residence time.

[0031] Step 202: After the synchronization (sync) message arrives at the switch chip, the switch chip adds a timestamp A.

[0032] Specifically, after the sync message based on the 1588 protocol reaches the switching chip from the uplink port, the switching chip adds a timestamp A. In order to calculate the residence time of the sync message inside the network device, the switching chip adds a timestamp A when receiving the sync message.

[0033] Step 203: After the sync message reaches the FPGA chip, a timestamp B is stamped on the FPGA chip, and the system time T2 of the current network device is recorded.

[0034] Step 204: The central processing unit (CPU) of the network device calculates CF1 based on timestamp A and timestamp B, and records timestamp T1 carried in the sync message. CF1 is the residence time of the sync message inside the network device. T1 is the system time of the upper-level device when the upper-level device sends the sync message.

[0035] It should be noted that the calculation step of CF1 can be executed in any step after the step of stamping timestamp B and before the step of calculating the deviation. This implementation is only for example. In actual applications, the execution order of the calculation step of CF1 and other steps can be set as needed.

[0036] Step 205: When the FPGA chip sends a delay request (delay_req) message, the system time T3 is recorded and timestamped C is added.

[0037] Specifically, when the FPGA chip sends a delay_req message, it records the system time T3 when the delay_req message is sent, and based on the counter of the FPGA chip, determines the current counter time and adds a timestamp C.

[0038] Step 206: When the delay_req message arrives at the switch chip, it is stamped with a timestamp D, and the CPU calculates CF2 based on timestamp C and timestamp D. CF2 is the residence time of the delay_req message inside the network device.

[0039] Specifically, the CPU can calculate CF2 immediately after the switching chip is stamped with timestamp D, or it can calculate CF2 according to timestamp C and timestamp D after executing step 207. This embodiment does not limit the order of the calculation steps of CF2 and step 207.

[0040] Step 207: The FPGA chip receives the delay_resp message from the upper-level device, and records T4 carried in the delay_resp message, where T4 is the system time of the upper-level device when the upper-level device sends the delay_resp message.

[0041] Step 208: The CPU calculates the offset between the system time of the network device and the system time of the upper-level device based on T1, T2, T3, T4, CF1 and CF2, and then calibrates the system time of the network device based on the offset. Then, the process returns to step 201 to enter the next cycle of time synchronization.

[0042] Specifically, the CPU can derive the following set of equations based on T1, T2, T3, and T4:

[0043]

[0044] Where delay is the network delay between the upper-level device and the uplink port of the local network device, and offset is the deviation between the system time of the network device and the reference time of the upper-level device. Based on the above equations, we can get:

[0045] Formula a: offset=[(T2-T1)-(T4-T3)] / 2;

[0046] Among the four timestamps T1, T2, T3 and T4, the timestamp T2 and timestamp T3 printed by the network device's uplink port include the residence time CF1 of the sync message inside the network device and the residence time CF2 of the delay_req message inside the network device. Therefore, in the actual calculation process, the residence time needs to be subtracted, that is:

[0047] Formula b: offset={[(T2-CF1)-T1]-[T4-(T3-CF2)]} / 2;

[0048] After the network device calculates the offset value according to formula b, it adjusts the system time of the network device according to the offset value, so that the time of the network device is consistent with the upstream device at the opposite end. While synchronizing the time with the upstream device, the network device also synchronizes its own system time to the next-level device through the downstream port, thereby achieving accurate time transmission.

[0049] It should be noted that, those skilled in the art can understand that, in this implementation, for the sake of clarity, the step of synchronizing the system time to the counter of the programming module and the switching module is taken as the previous step of receiving the sync message. In actual applications, the timing for the network device to synchronize the system time to the counter of the programming module and the switching module can be set as needed. This implementation does not limit the sequence of the step of the network device synchronizing the system time to the counter of the programming module and the switching module and other steps.

[0050] It should be noted that those skilled in the art can understand that in practical applications, the triggering conditions for synchronizing the system time to the counter of the programming module and the switching module can be set as needed.

[0051] In an example, the process of a network device synchronizing its system time to the next level device through the downstream network port is as follows: Figure 3 As shown, the following steps are included:

[0052] Step 301: When sending a sync message, the switch chip adds a timestamp T5 to the sync message.

[0053] Specifically, since the counter time of the switching chip is synchronized with the system time of the network device, the timestamp on the switching chip is the system time of the network device. Figure 2 Steps 201 to 206 record various data required for calculating the deviation of the system time between the next-level device and the network device, and send a delay_req message to the network device.

[0054] Step 302: After receiving the delay_req message, the network device sends a delay_resp message to the next-level device through the switching chip. When sending the delay_resp message, the switching chip adds a timestamp T6 to the delay_resp message.

[0055] Specifically, after receiving the delay_resp message, the next-level device can refer to Figure 2 From step 207 to step 208, the deviation of the system time of the next-level device and the network device is calculated, and the system time of the next-level device is adjusted according to the calculated deviation to synchronize the system time of the next-level device with the system time of the network device.

[0056] It should be noted that, in this implementation, the method of synchronizing the system time of a network device to a next-level device in the 1588 mode is taken as an example to illustrate the method of synchronizing the system time of a network device to a next-level device. Those skilled in the art can understand that in actual applications, the system time can also be synchronized to the next-level device by other methods. This implementation is only for example.

[0057] From the above description, it can be seen that in this implementation, the system time is synchronized to the switching chip and the FPGA chip, so that the timestamp of the switching chip can be reused. The timestamp of the switching chip can be used to calculate the residence time and can also be used to synchronize the time with the next level device, thereby optimizing the chip processing process, saving the number of chips, reducing the production cost of network equipment, and reducing the size of network equipment.

[0058] Therefore, this embodiment provides a time synchronization method, which synchronizes the system time to the switching module and the programming module, so that the time bases of the switching module and the programming module are the same, and the time of the switching module is synchronized with the system time. Since the time bases of the switching module and the programming module are the same, when performing system time synchronization with the upper-level device, the timestamp of the switching module can be used to calculate the residence time of each message inside the network device. Since the time of the switching module is synchronized with the system time, when performing time synchronization with the lower-level device, the timestamp of the switching module can be used as the system time of the network device and transmitted to the lower-level device. The network device can synchronize the system time with the upper-level device and the lower-level device through one switching module, which reduces the number of switching modules in the network device, reduces the production cost of the network device, and reduces the size of the network device. It solves the problem that the prior art must use two switching modules to complete the time synchronization with the upper-level device and the lower-level device due to the different time bases adopted, which makes the equipment cost too high.

[0059] The second embodiment of the present invention relates to a time synchronization method. The second embodiment is substantially the same as the first embodiment. In this embodiment, before synchronizing the system time to the counter of the programming module and the switching module, the synchronization time is determined according to the abnormality of the residence time. In this implementation, after the residence time is abnormal, the synchronization time is adjusted in time to avoid affecting the synchronization effect of the system time of the network device and the system time of the upper-level device due to inappropriate synchronization time.

[0060] The specific flow chart of the time synchronization method in this embodiment is as follows Figure 4 As shown, it includes steps 401 to 403, wherein step 401 and step 403 are substantially the same as step 101 and step 102 respectively, and will not be described in detail here, and the differences are mainly introduced below:

[0061] Step 401: Obtain system time.

[0062] Step 402: Determine the synchronization time according to the abnormal situation of the residence time.

[0063] Specifically, when the programming module synchronizes the system time with the switching module, it also takes a certain amount of time (microsecond level) to synchronize the system time. If the network device just receives the sync message at this time, when the sync message is stamped with timestamp A in the switching chip, the programming module has not synchronized the system time with the counters of the switching module and the programming module. In the process of sending the sync message to the programming module, the system time is synchronized to the counter of the programming module and the switching module. The sync message arrives at the programming module and is stamped with timestamp B. At this time, the time base of timestamp B and timestamp A are different, resulting in inaccurate CF1. Similarly, if delay_req messages are being sent before and after the synchronization of the system time, the bases of timestamp C and timestamp D will also be different, resulting in inaccurate CF2. Therefore, when the device finds that the residence time is abnormal, it is necessary to fine-tune the time of synchronizing the system time, for example, delaying it backward by 0.1 seconds to stagger the reception time of the sync message and the sending time of the delay_req message.

[0064] In one example, if the dwell time is abnormal, the original synchronization time can be adjusted according to the preset adjustment value to obtain the subsequent synchronization time. For example, the re-determined synchronization time = the original synchronization time + u, where u is any time length less than the synchronization period. For example, the original synchronization time is 1s, u is equal to 0.1 seconds, and the synchronization period is 1s, then the re-determined synchronization time is 1.1s, and the subsequent synchronization time is 2.1s, 3.1s, 4.1s... and so on.

[0065] In one example, the period of synchronizing the system time to the programming module and the switching module is N times the period of sending synchronization messages sent by the upper-level device, where N is a positive integer. Specifically, since the synchronization period is N times the period of sending synchronization messages sent by the upper-level device (i.e., the synchronization period between the system time of the network device and the system time of the upper-level device), if no residence time abnormality occurs when synchronizing the system time to the counter of the programming module and the switching module at the initial synchronization time, then synchronization operations performed at other synchronization times determined based on the initial synchronization time and the synchronization period will not cause residence time abnormality, which can reduce the situation where residence time abnormality is caused by inappropriate synchronization time.

[0066] The following is an example of a method for detecting whether the residence time is abnormal.

[0067] Method 1: If the network device determines that the system time convergence is abnormal, it determines that the residence time is abnormal.

[0068] Specifically, when the residence time is abnormal, it will affect the calculation of the offset, causing the system time to be unable to converge and lock. Therefore, when the offset is adjusted a certain number of times and the system time still cannot be locked, it can be considered that the residence time is abnormal, and the time to synchronize the system time needs to be fine-tuned.

[0069] In one example, the process of determining that the system time convergence is abnormal by the network device includes: if the deviation between the system time after M system time synchronizations with the upper-level device and the system time of the upper-level device is greater than a first preset value, then determining that the system time convergence is abnormal, where M is a positive integer greater than 1. Among them, M can be set according to requirements for various aspects such as the speed of system time synchronization, or according to an empirical value of the number of synchronizations required for the network device to complete the synchronization of its own system time with the upper-level device. The first preset value can be set according to the project's requirements for the accuracy of the system time, for example, to 3ns.

[0070] Method 2: If the network device determines that the residence time is greater than the second preset value, then the network device determines that the residence time is abnormal.

[0071] Specifically, since the dwell time is the sum of the delays of various systems within the network device, its duration is generally within an empirical value range. When the dwell time exceeds this empirical value, it can be considered that the dwell time is abnormal, and it is necessary to fine-tune the synchronization dwell time. The second preset value can be set based on experience.

[0072] It should be noted that those skilled in the art can understand that in actual applications, thresholds can be set for the residence time CF1 of the sync message in the network device and the residence time CF2 of the delay_req message in the network device to monitor whether CF1 and CF2 are abnormal. If the network device determines that CF1 is greater than the threshold corresponding to CF1, or CF2 is greater than the threshold corresponding to CF2, the residence time is considered to be abnormal. Among them, the threshold corresponding to CF1 and the threshold corresponding to CF2 can be the same or different, and this embodiment does not limit it.

[0073] Based on the above-mentioned judgment method, the process of discovering the residence time anomaly and the anomaly handling process are briefly described below.

[0074] Taking the programming module as an FPGA chip and the switching module as a switching chip as an example, the CF1 exception and the CF1 exception processing process are as follows: Figure 5 As shown, the following steps are included:

[0075] Step 501: After the sync message reaches the switch chip from the upstream network port, the switch chip adds a timestamp A.

[0076] Step 502: The FPGA chip synchronizes the system time to its own counter and the switching chip. At this time, the counting reference of the counter of the FPGA chip has changed.

[0077] Step 503: After the sync message arrives at the FPGA chip, a timestamp B is added to the FPGA chip and the system time T2 is recorded.

[0078] Step 504: The CPU calculates CF1 according to timestamp A and timestamp B, and records timestamp T1 carried in the sync message.

[0079] Step 505: The CPU finds that CF1 exceeds a reasonable range or finds that the system time cannot converge for a long time, and adjusts the synchronization time.

[0080] Specifically, since the counting bases of timestamp A and timestamp B are different, CF1 calculated by using timestamp A and timestamp B is abnormal.

[0081] Based on the adjusted synchronization time, the system time is synchronized to the counter of the programming module and the switching module.

[0082] Taking the programming module as an FPGA chip and the switching module as a switching chip as an example, the CF2 exception and the CF2 exception processing process are as follows: Figure 6 As shown, the following steps are included:

[0083] Step 601, when the FPGA chip sends a delay_req message, the system time T3 is recorded and a timestamp C is added based on the counter time.

[0084] Step 602: The FPGA chip synchronizes the system time to its own counter and the switching chip. At this time, the counting bases of the FPGA chip counter and the switching chip have changed.

[0085] Step 603: The delay_req message arrives at the switch chip and is stamped with a timestamp D. The CPU calculates CF2 based on timestamps C and D.

[0086] Step 604: The CPU finds that CF2 exceeds a reasonable range or finds that the system time cannot converge for a long time, and adjusts the synchronization time.

[0087] Specifically, since the counting bases of timestamp C and timestamp D are different, CF2 calculated by using timestamp C and timestamp D is abnormal, and the synchronization time needs to be adjusted.

[0088] Based on the adjusted synchronization time, the system time is synchronized to the counter of the programming module and the switching module.

[0089] Optionally, when the network device finds that the residence time is abnormal, it can adjust the residence time to restore the normal residence time as much as possible. Specifically, the network device adjusts the residence time; calculates the deviation between the system time and the system time of the upper-level device according to the adjusted residence time; and adjusts the system time according to the calculated deviation.

[0090] The following is an example of how to adjust the dwell time.

[0091] In the first example, after determining that the residence time is abnormal, the network device obtains the deviation calculated during the previous T system time synchronization processes; adjusts the residence time according to the deviations of the previous T times; wherein T is the number of times the system time is synchronized with the upper-level device from the first time to the second time; the first time is the time of the last execution of synchronizing the system time to the counter of the programming module and the switching module, and the second time is the time of the current execution of synchronizing the system time to the counter of the programming module and the switching module. The method for determining the number of times the system time is synchronized with the upper-level device can be: a counter specifically used for calculating the number of times is set in the network device, the counter is cleared at the first time, and the count value of the counter is increased by 1 each time the network device sends a synchronization message from the upper-level device. When the second time comes, the count value of the counter is the number of times the system time is synchronized with the upper-level device from the first time to the second time.

[0092] For example, from the first time to the second time, the number of times the network device synchronizes the system time with the upper-level device is 3, then the adjusted residence time = the residence time before adjustment - the sum of the deviations calculated during the first three system time synchronization processes.

[0093] In the second example, after determining that the residence time is abnormal, the network device obtains the first timestamp of the programming module before the counter time of the synchronous programming module, and the second timestamp of the programming module after the counter time of the synchronous programming module; or obtains the first timestamp of the switching module before the time of the synchronous switching module, and the second timestamp of the switching module after the time of the synchronous switching module; determines the adjustment amount according to the first timestamp and the second timestamp; and adjusts the residence time according to the adjustment amount. Specifically, in the process of monitoring whether the residence time is abnormal, if the monitoring result is that CF1 is abnormal, CF1 is adjusted according to the adjustment amount, and if the monitoring result is that CF2 is abnormal, CF2 is adjusted according to the adjustment amount. After adjusting the residence time, the network device recalculates the offset based on the adjusted residence time and resynchronizes the system time.

[0094] It is worth mentioning that the network device adjusts the abnormal residence time and resynchronizes the system time based on the adjusted residence time, which can reduce the deviation between the system time of the network device and the system time of the upper-level device.

[0095] The following is an example of the method for adjusting the dwell time provided in the second example to illustrate the process of adjusting the dwell time.

[0096] Case 1, the monitoring result is that CF1 is abnormal. If the adjustment amount = the second timestamp of the programming module after the counter time of the synchronous programming module - the first timestamp of the programming module before the counter time of the synchronous programming module, or the adjustment amount = the second timestamp of the switching module after the time of the synchronous switching module - the first timestamp of the switching module before the time of the synchronous switching module, then the adjusted CF1 = CF1 before adjustment - adjustment amount. If the adjustment amount = the first timestamp of the programming module before the counter time of the synchronous programming module - the second timestamp of the programming module after the counter time of the synchronous programming module, or the adjustment amount = the first timestamp of the switching module before the time of the synchronous switching module - the second timestamp of the switching module after the time of the synchronous switching module, then the adjusted CF1 = CF1 before adjustment + adjustment amount.

[0097] Case 2, the monitoring result is that CF2 is abnormal. If the adjustment amount = the second timestamp of the programming module after the counter time of the synchronous programming module - the first timestamp of the programming module before the counter time of the synchronous programming module, or the adjustment amount = the second timestamp of the switching module after the time of the synchronous switching module - the first timestamp of the switching module before the time of the synchronous switching module, then the adjusted CF2 = CF2 before adjustment - adjustment amount. If the adjustment amount = the first timestamp of the programming module before the counter time of the synchronous programming module - the second timestamp of the programming module after the counter time of the synchronous programming module, or the adjustment amount = the first timestamp of the switching module before the time of the synchronous switching module - the second timestamp of the switching module after the time of the synchronous switching module, then the adjusted CF2 = CF2 before adjustment - adjustment amount.

[0098] In one example, after determining that the system time convergence is abnormal, the network device adds 1 to the number of abnormalities, wherein the initial value of the number of abnormalities is 0; if the updated number of abnormalities is greater than the third preset value, a system failure is prompted. Specifically, if the system time convergence is still abnormal after multiple adjustments to the synchronization time, it means that the system time convergence is abnormal due to other reasons. At this time, the network device can send information to the operation and maintenance personnel, or issue an alarm prompt, etc., to prompt the operation and maintenance personnel that the network device system has a fault, so that the operation and maintenance personnel can maintain the network device.

[0099] It is worth mentioning that when it is determined that the asynchronous time causes the system time convergence abnormality, the operation and maintenance personnel are promptly prompted to maintain the network equipment, thereby reducing the maintenance cost of the network equipment.

[0100] Step 403: according to the synchronization time, the system time is synchronized to the counter of the programming module and the switching module, so as to perform system time synchronization with the upper-level device and the lower-level device through the switching module and the programming module respectively.

[0101] Therefore, this embodiment provides a time synchronization method, which synchronizes the system time to the switching module and the programming module, so that the time bases of the switching module and the programming module are the same, and the time of the switching module is synchronized with the system time. Since the time bases of the switching module and the programming module are the same, when synchronizing the system time with the upper-level device, the timestamp of the switching module can be used to calculate the residence time of each message in the network device. Since the time of the switching module is synchronized with the system time, when synchronizing the time with the lower-level device, the timestamp of the switching module can be used as the system time of the network device and transmitted to the lower-level device. The network device can synchronize the system time with the upper-level device and the lower-level device through one switching module, which reduces the number of switching modules in the network device, reduces the production cost of the network device, and reduces the size of the network device. The problem that the time synchronization between the upper-level device and the lower-level device must be completed through two switching modules due to the different time bases used in the prior art, which makes the equipment cost too high, is solved. Whether the residence time is abnormal is monitored, and after the residence time is abnormal, the synchronization time is adjusted in time to avoid affecting the synchronization effect of the system time of the network device and the system time of the upper-level device due to inappropriate synchronization time.

[0102] In addition, those skilled in the art can understand that the step division of the above methods is only for clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the protection scope of this patent; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the protection scope of this patent.

[0103] A third embodiment of the present invention relates to a network device, such as Figure 7 As shown, it includes: an acquisition module 701 and a synchronization module 702; the acquisition module 701 is used to acquire the system time. The synchronization module 702 is used to synchronize the system time to the counter of the programming module and the switching module, so as to synchronize the system time with the upper-level device and the lower-level device respectively through the switching module and the programming module.

[0104] In one example, before synchronizing the system time to the counter and switching module of the programming module, it also includes: determining the synchronization time according to the abnormal situation of the residence time; synchronizing the system time to the counter and switching module of the programming module, including: synchronizing the system time to the counter and switching module of the programming module according to the synchronization time.

[0105] In one example, determining the abnormality of the residence time includes: if it is determined that the system time convergence is abnormal, then determining that the residence time is abnormal.

[0106] In one example, determining a system time convergence abnormality includes: if the deviation between the system time after M system time synchronizations with the upper-level device and the system time of the upper-level device is greater than a first preset value, determining a system time convergence abnormality, where M is a positive integer greater than 1.

[0107] In one example, determining that the dwell time is abnormal includes: if it is determined that the dwell time is greater than a second preset value, determining that the dwell time is abnormal.

[0108] In one example, the network device also includes an adjustment module, which is used to: if it is determined that the residence time is abnormal, further include: adjusting the residence time; calculating the deviation between the system time and the system time of the upper-level device based on the adjusted residence time; adjusting the system time based on the calculated deviation.

[0109] In one example, adjusting the residence time includes: obtaining the deviation calculated during the previous T system time synchronization processes; adjusting the residence time according to the deviation of the previous T times; wherein T is the number of times the system time is synchronized with the upper-level device from the first time to the second time; the first time is the time of the last execution to synchronize the system time to the counter and switching module of the programming module, and the second time is the time of the current execution to synchronize the system time to the counter and switching module of the programming module; or, obtaining the first timestamp of the programming module before the time of synchronizing the counter of the programming module, and the second timestamp of the programming module after the time of synchronizing the counter of the programming module; or, obtaining the first timestamp of the switching module before the time of synchronizing the switching module, and the second timestamp of the switching module after the time of synchronizing the switching module; determining the adjustment amount according to the first timestamp and the second timestamp; and adjusting the residence time according to the adjustment amount.

[0110] In one example, the network device also includes a prompt module, which is used to increase the number of abnormalities by 1 after determining that the system time convergence is abnormal, wherein the initial value of the number of abnormalities is 0; if the updated number of abnormalities is greater than a third preset value, a system failure is prompted.

[0111] In one example, a period for synchronizing the system time to the programming module and the switching module is N times a period for the upper-level device to send synchronization messages, where N is a positive integer.

[0112] It is not difficult to find that this embodiment is a device embodiment corresponding to the first or second embodiment, and this embodiment can be implemented in conjunction with the first or second embodiment. The relevant technical details mentioned in the first or second embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the first or second embodiment.

[0113] It is worth mentioning that all modules involved in this embodiment are logic modules. In practical applications, a logic unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the present invention, this embodiment does not introduce units that are not closely related to solving the technical problem proposed by the present invention, but this does not mean that there are no other units in this embodiment.

[0114] A fourth embodiment of the present invention relates to a network device, such as Figure 8 As shown, it includes: at least one processor 801; and a memory 802 that is communicatively connected to the at least one processor 801; wherein the memory 802 stores instructions that can be executed by the at least one processor 801, and the instructions are executed by the at least one processor 801 so that the at least one processor 801 can execute the above-mentioned time synchronization method.

[0115] Among them, the memory and the processor are connected in a bus manner, and the bus may include any number of interconnected buses and bridges, and the bus connects various circuits of one or more processors and memories together. The bus can also connect various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be one element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices on a transmission medium. The data processed by the processor is transmitted on a wireless medium via an antenna, and further, the antenna also receives data and transmits the data to the processor.

[0116] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory can be used to store data used by the processor when performing operations.

[0117] A fifth embodiment of the present invention relates to a computer-readable storage medium storing a computer program, which implements the above method embodiment when executed by a processor.

[0118] That is, those skilled in the art can understand that all or part of the steps in the above method embodiments can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0119] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present invention, and that in actual applications, various changes may be made in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A time synchronization method, characterized in that: include: Get system time; The system time is synchronized to the counter of the programming module and the switching module, so that the time bases of the switching module and the programming module are the same, and the time of the switching module is synchronized with the system time, so as to synchronize the system time with the upper-level device and the lower-level device respectively through the switching module and the programming module.

2. The time synchronization method according to claim 1, characterized in that: Before synchronizing the system time to the counter and the switching module of the programming module, it also includes: Determine the synchronization time based on the abnormal situation of the residence time; The counter and switching module for synchronizing the system time to the programming module comprises: According to the synchronization time, the system time is synchronized to the counter of the programming module and the switching module.

3. The time synchronization method according to claim 2, characterized in that: Determine abnormalities of the dwell time, including: If it is determined that the system time convergence is abnormal, or if it is determined that the residence time is greater than a second preset value, then it is determined that the residence time is abnormal.

4. The time synchronization method according to claim 3, characterized in that: The determining that the system time convergence is abnormal includes: If the deviation between the system time after M system time synchronizations with the upper-level device and the system time of the upper-level device is greater than a first preset value, it is determined that the system time convergence is abnormal, where M is a positive integer greater than 1.

5. The time synchronization method according to claim 2, characterized in that: If it is determined that the residence time is abnormal, the time synchronization method further includes: adjusting the dwell time; Calculate the deviation between the system time and the system time of the upper-level device according to the adjusted residence time; The system time is adjusted according to the calculated deviation.

6. The time synchronization method according to claim 5, characterized in that: The adjusting the dwell time comprises: Obtain the deviation calculated during the previous T system time synchronization processes; adjust the residence time according to the deviation of the previous T times; wherein T is the number of times the system time is synchronized with the upper-level device from the first time to the second time; the first time is the time of the last execution of synchronizing the system time to the counter and the switching module of the programming module, and the second time is the time of this execution of synchronizing the system time to the counter and the switching module of the programming module; or, Obtain a first timestamp of the programming module before synchronizing the counter time of the programming module, and a second timestamp of the programming module after synchronizing the counter time of the programming module; or, obtain a first timestamp of the switching module before synchronizing the switching module, and a second timestamp of the switching module after synchronizing the switching module; determine an adjustment amount based on the first timestamp and the second timestamp; and adjust the residence time based on the adjustment amount.

7. The time synchronization method according to claim 3, characterized in that: After determining that the system time convergence is abnormal, the time synchronization method further includes: Add 1 to the number of exceptions, where the initial value of the number of exceptions is 0; If the updated abnormal number is greater than the third preset value, a system failure is prompted.

8. The time synchronization method according to any one of claims 1 to 7, characterized in that: The period of synchronizing the system time to the programming module and the switching module is N times the period of sending synchronization messages by the upper-level device, where N is a positive integer.

9. A network device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the time synchronization method according to any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the time synchronization method according to any one of claims 1 to 8 is implemented.

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