Memory chip and manufacturing method thereof, and positioning method of designated storage unit

Abstract

The present invention provides a memory chip and a manufacturing method thereof, and a method for locating a designated memory cell, wherein a virtual bit line mark and a virtual word line mark are added to the memory block, and an equal number of bit lines are spaced between two adjacent virtual bit line marks, and an equal number of word lines are spaced between two adjacent virtual word line marks, thereby, the position of the virtual bit line mark and the number of spaced bit lines can be used to mark the number of bit lines of the memory block, and the position of the virtual word line mark and the number of spaced word lines can be used to mark the number of word lines of the memory block. Moreover, without affecting the bit line connection and the word line connection, the position of the designated bit line can be quickly located by the position of the added virtual bit line mark during the chip manufacturing and testing process, and the position of the designated word line can be quickly located by the position of the added virtual word line mark, and then the designated unit can be quickly located for subsequent analysis.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory chip and a manufacturing method thereof, and a positioning method for a designated storage unit. Background Art

[0002] The memory array of existing memory chips (such as three-dimensional phase-change memory) is mainly composed of a large number of memory blocks (or called memory sectors) arranged in an array. Each memory block includes several word lines, several bit lines, and memory cells located at the intersections of each word line and each bit line.

[0003] The design of existing memory chips has the following defects: during the manufacturing and testing processes of memory chips, it is difficult or impossible to quickly and accurately find the specified memory cell from the memory cell of the memory chip to perform problem analysis on it, which poses a huge challenge to problem analysis and yield improvement in chip manufacturing. Summary of the Invention

[0004] The object of the present invention is to provide a memory chip and a manufacturing method thereof, as well as a method for locating a specified memory unit, so as to solve the problem that it is difficult or impossible to quickly and accurately find the specified memory unit from the memory units of the memory chip in order to perform problem analysis on it during the manufacturing and testing processes of the memory chip.

[0005] In order to solve the above technical problems, the present invention provides a memory chip, comprising a plurality of memory blocks arranged in an array, each of the memory blocks comprising a first bit line layer, a first storage unit layer and a first word line layer stacked in sequence from bottom to top, the first bit line layer having a plurality of first parallel lines extending in the column direction, the first word line layer having a plurality of first word lines extending in the row direction, the first storage unit layer comprising a plurality of first storage units, each first storage unit being located at the intersection of a corresponding first word line and a corresponding first bit line; wherein the memory block further comprises a plurality of first virtual word line marks distributed in the same column and at equal intervals and a plurality of first virtual bit line marks distributed in the same row and at equal intervals, each first virtual word line mark is aligned with the corresponding first word line and the number of first word lines spaced between any two adjacent first virtual word line marks is the same, each first virtual bit line mark is aligned with the corresponding first bit line, and the number of first lines spaced between any two adjacent first virtual bit line marks is the same.

[0006] Optionally, the storage block has a first word line connection portion arranged corresponding to the first word line and electrically connected to the first word line, and a first bit line connection portion arranged corresponding to the first bit line and electrically connected to the first bit line; the memory chip is provided with a word line control transistor area and a first bit line control transistor area for controlling the storage block, the first virtual word line mark and the first word line connection portion of the storage block are both arranged in the first word line control transistor area, and the first virtual bit line mark and the first bit line connection portion of the storage block are both arranged in the first bit line control transistor area.

[0007] Optionally, the first dummy bit line mark has the same structure as the first bit line connection portion, and the first word line dummy mark has the same structure as the first word line connection portion.

[0008] Optionally, the memory block further includes a second memory cell layer and a second bit line layer sequentially stacked on the first word line layer, the second bit line layer having a plurality of second bit lines that are parallel and extend along the column direction, and the second memory cell layer including second memory cells located at intersections of the first word lines and the second bit lines; wherein the memory block further includes a plurality of second dummy bit line marks that are arranged in the same row and are equally spaced, each second dummy bit line mark is aligned with a corresponding second bit line, and the number of second bit lines spaced between any two adjacent second dummy bit line marks is the same;

[0009] And / or, the storage block also includes a third storage cell layer located below the first bit line layer and a second word line layer located below the third storage cell layer, the second word line layer has a plurality of parallel second word lines extending along the row direction, and the third storage cell layer includes a third storage cell located at the intersection of the second word line and the first bit line; wherein, the storage block also has a plurality of second virtual word line marks distributed in the same column and at equal intervals, each second virtual word line mark is aligned with the corresponding second word line, and the number of second word lines spaced between any two adjacent second virtual word line marks is the same.

[0010] Optionally, the memory chip is a three-dimensional phase change memory chip, and each of the first storage units and each of the second storage units is a phase change memory unit having a phase change material layer.

[0011] Optionally, when the memory block has the second bit line layer and the second memory cell layer, the memory block further has a second bit line connection portion arranged corresponding to the second bit line and electrically connected to the second bit line, the memory chip further has a second bit line control transistor region for controlling the memory block, and the second dummy bit line mark and the second bit line connection portion of the memory block are both arranged in the second bit line control transistor region;

[0012] When the storage block has the second word line layer and the third storage cell layer, the storage block also has a second word line connection portion arranged corresponding to the second word line and electrically connected to the second word line, and the memory chip is also provided with a second word line control transistor area for controlling the storage block, and the second virtual word line mark and the second word line connection portion of the storage block are both arranged in the second word line control transistor area.

[0013] Optionally, when the storage block has the second bit line layer and the second storage cell layer, the projections of the first bit line and the second bit line of the storage block in the stacking direction are misaligned; when the storage block has the second word line layer and the third storage cell layer, the projections of the first word line and the second word line of the storage block in the stacking direction are misaligned.

[0014] Optionally, when the storage block has the second bit line layer and the second storage cell layer, insulating media are filled between adjacent first lines, between adjacent first storage cells, between adjacent first word lines, between adjacent second storage cells, between adjacent second bit lines, between the first bit line and the first word line, between the first word line and the second bit line, and between the first bit line and the second bit line; when the storage block has the second word line layer and the third storage cell layer, insulating media are filled between adjacent first lines, between adjacent first storage cells, between adjacent first word lines, between adjacent second storage cells, between adjacent second word lines, between the first bit line and the first word line, between the first bit line and the second word line, and between the first word line and the second word line.

[0015] Based on the same inventive concept, the present invention further provides a method for manufacturing the memory chip of the present invention, which comprises the following steps:

[0016] Providing a substrate, wherein a first bit line connection portion and first dummy bit line marks distributed in the same row and at equal intervals are formed in the substrate;

[0017] forming a first bit line layer on the substrate, wherein a plurality of first bit lines are formed in the first bit line layer and are parallel and extend in a column direction, wherein each first bit line is in electrical contact with a corresponding first bit line connection portion, and each first bit line is aligned with a first dummy bit line mark, and the number of first bit lines spaced between any two adjacent first dummy bit line marks is the same;

[0018] forming a first memory cell layer having a plurality of first memory cells arranged in an array on the first bit line layer, wherein the first memory cells in the same column are all located on the same first bit line and are all in electrical contact with the first bit line;

[0019] forming a first word line connection portion and first dummy word line marks arranged in the same column and at equal intervals on the substrate, wherein the first memory cell layer exposes top surfaces of the first word line connection portion and the first dummy word line mark, and the first word line connection portion is electrically connected to the substrate;

[0020] A first word line layer is formed on the first memory cell layer, the first word line connection portion and the first virtual word line mark, a plurality of parallel word lines extending along the row direction are formed in the first word line layer, each of the first memory cells is located at the intersection of the corresponding first word line and the corresponding first bit line, and the first memory cells on the same row are all electrically in contact with the same first word line, and each of the first word lines is electrically in contact with the corresponding first word line connection portion, and the corresponding first word lines are aligned with the corresponding first virtual word line mark, and the number of word lines spaced between any two adjacent first virtual word line marks is the same.

[0021] Optionally, after forming the first word line layer, the manufacturing method further includes:

[0022] forming a second memory cell layer having a plurality of second memory cells arranged in an array on the first word line layer, wherein the second memory cells in the same row are all located on the same first word line and are all in electrical contact with the first word line;

[0023] forming a second bit line connection portion and second dummy bit line marks in the same row and distributed at equal intervals on the substrate, wherein the second memory cell layer exposes top surfaces of the second bit line connection portion and the second dummy bit line marks, and the second bit line connection portion is electrically connected to the substrate;

[0024] forming a second bit line layer on the second memory cell layer, the second bit line connection portion, and the second dummy bit line mark, wherein a plurality of second bit lines are formed in the second bit line layer in parallel and extending in a column direction, wherein each second memory cell is located at an intersection of a corresponding first word line and a corresponding second bit line, wherein all second memory cells in the same column are electrically in contact with the same second bit line, and each second bit line is electrically in contact with a corresponding second bit line connection portion, wherein corresponding second bit lines are aligned with corresponding second dummy bit line marks, and the number of second bit lines spaced between any two adjacent second dummy bit line marks is the same;

[0025] Alternatively, the manufacturing method, before forming the first bit line layer on the substrate, further includes:

[0026] forming a second word line connection portion and second dummy word line marks distributed in the same column and at equal intervals in the substrate;

[0027] forming a second word line layer on the substrate, wherein a plurality of second word lines are formed in the second word line layer and are parallel and extend in a row direction, each second word line is in electrical contact with a corresponding second word line connection portion, and each second word line is aligned with a second dummy word line mark, and the number of second word lines spaced between any two adjacent second dummy word line marks is the same;

[0028] A third memory cell layer is formed on the second word line layer and has a plurality of third memory cells arranged in an array. Each third memory cell is located at an intersection of a corresponding first bit line and a second word line. The third memory cells on the same row are all located on the same second word line and are all in electrical contact with the second word line.

[0029] Based on the same inventive concept, the present invention further provides a method for locating a designated storage unit in a memory chip as described in the present invention, comprising:

[0030] Grinding or slicing the memory chip to expose the first dummy word line mark and / or the first dummy bit line mark of the corresponding memory block;

[0031] Determining the position of a designated word line of the memory block using the position of the exposed first virtual word line mark; and / or determining the position of a designated bit line of the memory block using the position of the exposed first virtual bit line mark;

[0032] The determined position of the designated word line and / or the determined position of the designated bit line are used to find the designated memory cell for subsequent analysis.

[0033] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0034] 1. Virtual bit line marks and virtual word line marks are added to the word lines and bit lines connected to the storage unit layer in the storage block. The same number of bit lines are spaced between two adjacent virtual bit line marks, and the same number of word lines are spaced between two adjacent virtual word line marks. Therefore, the position of the virtual bit line mark and the number of bit lines spaced can be used to mark the number of bit lines in the storage block, and the position of the virtual word line mark and the number of word lines spaced can be used to mark the number of word lines in the storage block.

[0035] 2. Without affecting the bit line and word line connections, during the chip manufacturing and testing process, the position of the specified bit line (i.e., the specified bit line number) can be quickly located by the position of the added virtual bit line mark, and the position of the specified word line (i.e., the specified word line number) can be quickly located by the position of the added virtual word line mark. Then, the specified cell in the memory cell layer can be quickly located for subsequent analysis, which has great benefits for problem analysis and yield improvement of memory chips.

[0036] 3. The virtual bit line mark can have the same structure as the bit line connection part, and the virtual word line mark can have the same structure as the word line connection part. Therefore, the virtual bit line mark can be manufactured together with the bit line connection part, and the virtual word line mark can be manufactured together with the word line connection part. Therefore, there is no need to add additional process steps, it can be fully compatible with the existing process, and the implementation cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a schematic diagram of the storage block matrix (or array) distribution of a conventional memory chip.

[0038] Figure 2 It is a schematic diagram of the distribution of the first bit line, word line, second bit line and the connecting parts of each line (or called conductive contact holes) in two adjacent memory blocks in a memory chip.

[0039] Figure 3 This is a schematic diagram of the distribution of first bit lines, word lines, second bit lines, connecting parts of each line (or called conductive contact holes), and virtual marks (or called virtual contact holes) in two adjacent memory blocks in a memory chip according to an embodiment of the present invention.

[0040] Figure 4 FIG. 1 is a schematic diagram of the three-dimensional structure of a memory block in a memory chip according to an embodiment of the present invention.

[0041] Figure 5 FIG. 4 is a schematic diagram of the three-dimensional structure of a storage bit in a memory chip according to another embodiment of the present invention.

[0042] Figure 6 FIG. 1 is a schematic cross-sectional view of a memory cell in a memory chip according to an embodiment of the present invention.

[0043] Figure 7 FIG. 4 is a flow chart of a method for manufacturing a memory chip according to an embodiment of the present invention.

[0044] Figures 8 to 13 FIG. 1 is a schematic diagram of a device cross-sectional structure along a column direction in a method for manufacturing a memory chip according to an embodiment of the present invention.

[0045] The specific reference numerals in the accompanying drawings are as follows:

[0046] BBL - first bit line (or bottom bit line); TBL - second bit line (or top bit line); WL - word line; Bcell - first storage cell; Tcell - second storage cell; BWL - bottom word line; TWL - top word line; BE - bottom electrode; OTS - selector; ME - middle electrode; PCM - phase change material layer; TE - top electrode;

[0047] 10, 20 - memory block; 10a, 10b, 20a, 20b - blocks of the memory block; 10c, 20c - word line control transistor region; 10d, 20d - first bit line control transistor region; 10e, 20e - second bit line control transistor region; 200 - substrate; 200a - first electrical structure; 200b - second electrical structure; 200c - third electrical structure; 101, 201a - word line connection; 201b - dummy word line marker; 102, 202a - first bit line connection; 202b - first dummy bit line marker; 103, 203a - second bit line connection; 203b - second dummy bit line marker; 201a1-lower structure of the word line connection portion; 201b1-lower structure of the virtual word line mark; 203a1-lower structure of the second bit line connection portion; 201a2-upper structure of the word line connection portion; 201b2-upper structure of the virtual word line mark; 203a2-middle structure of the second bit line connection portion; 203a3-upper structure of the second bit line connection portion; 2041-first insulating protection layer; 2042-second insulating protection layer; 2043-third insulating protection layer; 2011-first dielectric layer; 2012-second dielectric layer; 2013-third dielectric layer; 2014-fourth dielectric layer; 2015-fifth dielectric layer. DETAILED DESCRIPTION

[0048] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0049] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0050] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0051] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0052] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0053] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] As mentioned in the background technology, existing memory chips are usually composed of a large number of memory blocks arranged and stacked. Figure 1 and Figure 2A minimum memory block in a three-dimensional memory chip, constructed by stacking memory chips in three dimensions, has at least one first bit line (BBL), one word line (WL), and one second bit line (TBL). First memory cells (Bcells) are located at the intersections of the first bit line (BBL) and the word line (WL), and second memory cells (Tcells) are located at the intersections of the second bit line (TBL) and the word line (WL). Current three-dimensional memory chips also have many blank areas, such as the word line contact transistor (WLT) region 10c for forming each word line connection (or word line contact hole) 101, the bottom bit line contact transistor (BLT) region 10d for forming each first bit line connection (or first bit line contact hole) 102, and the top bit line contact transistor (BLT) region 10e for forming each second bit line connection (or first bit line contact hole) 103. The WLT region 10c divides the centerline of a memory block along the Y direction into blocks 10a and 10b.

[0055] Furthermore, the inventors have discovered that, regardless of whether the minimum memory block size of existing memory chips is 4K*2K or 4K*4K, it is difficult to find a specific memory cell within the memory block. This poses a significant challenge to problem analysis and yield improvement in chip manufacturing. Therefore, the inventors have proposed the following technical solution of this application.

[0056] Please refer to Figures 3 to 5 One embodiment of the present invention provides a memory chip comprising a plurality of memory blocks 20 arranged in an array, each memory block comprising a first bit line layer, a first memory cell layer, and a word line layer stacked in sequence from bottom to top. The first bit line layer has a plurality of parallel lines arranged in a column direction (i.e., Figure 3 The word line layer has a first bit line BBL extending in the Y-axis direction as shown in FIG. 1 , and a plurality of word line layers extending in parallel along the row direction (ie, as shown in FIG. Figure 3 The first memory cell layer includes a plurality of first memory cells Bcell, and each first memory cell Bcell is located at an intersection of a corresponding word line WL and a corresponding first bit line BBL.

[0057] In this embodiment, each memory block further includes a second memory cell layer and a second bit line layer sequentially stacked on the word line layer. The second bit line layer includes a plurality of parallel second bit lines TBL extending along a column direction Y. The second memory cell layer includes a plurality of second memory cells Tcell, and each second memory cell Tcell is located at an intersection of a corresponding word line WL and a corresponding second bit line TBL.

[0058] As an example, the first bit line BBL and the second bit line TBL are parallel, and each second bit line TBL and the corresponding first bit line BBL located therebelow are misaligned in the Z direction, that is, each second bit line TBL and the corresponding first bit line BBL located therebelow are misaligned (that is, offset) between their projections on the surface of the substrate 200 along the Z direction, and thus the positions of the first storage cell Bcell and the corresponding second storage cell Tcell thereover are also offset.

[0059] In this embodiment, the memory chip is constructed based on a substrate 200. The substrate 200 can be a single-element semiconductor material substrate (e.g., a silicon Si substrate, a germanium Ge substrate, etc.) or a compound semiconductor material substrate (e.g., a silicon germanium SiGe substrate), or a silicon-on-insulator SOI substrate, a germanium-on-insulator GeOI substrate, etc. The substrate 200 has a first electrical structure 200a, a second electrical structure 200b, and a third electrical structure (e.g., Figure 8 As shown in FIG200c , the first electrical structure 200a may include a first bit line control transistor (not shown) for controlling the first bit line BBL and a first metal interconnect structure (not shown) electrically connected to the first bit line control transistor. The second electrical structure 200b may include a second bit line control transistor (not shown) for controlling the second bit line TBL and a second metal interconnect structure (not shown) electrically connected to the second bit line control transistor. The third electrical structure may include a word line control transistor (not shown) for controlling the word line WL and a third metal interconnect structure (not shown) electrically connected to the word line control transistor. The first bit line control transistor, the second bit line control transistor, and the word line control transistor may be formed together, and the first metal interconnect structure, the second metal interconnect structure, and the third metal interconnect structure may be formed together.

[0060] In this embodiment, each memory block 20 further comprises a plurality of word line connections 201a, a plurality of dummy word line marks 201b, a plurality of first bit line connections 202a, a plurality of first dummy bit line marks 202b, a plurality of second bit line connections 203a, and a plurality of second dummy bit line marks 203b. Each word line connection 201a, first bit line connection 202a, and second bit line connection 203a is also referred to as a conductive contact (via) or contact. Each word line connection 201a can be provided in a one-to-one correspondence with a word line WL, with each word line connection 201a connecting a corresponding third metal interconnect structure to a word line WL to electrically connect a corresponding word line transistor to the word line WL. Each first bit line connection 202a can also be provided in a one-to-one correspondence with a first bit line BBL, with each first bit line connection 202a connecting a corresponding first metal interconnect structure to the first bit line BBL to electrically connect a corresponding first bit line transistor to the first bit line BBL. Each second bit line connection portion 203a may also be provided in one-to-one correspondence with a second bit line TBL. Each second bit line connection portion 203a connects a corresponding second metal interconnect structure and the second bit line TBL to achieve electrical connection between the corresponding second bit line transistor and the second bit line TBL.

[0061] As an example, each dummy word line mark 201b can be formed together with the word line connection portion 201a, that is, each dummy word line mark 201b can be made of the same material and structure as the word line connection portion 201a, but the bottom of each dummy word line mark 201b is not electrically connected to any electrical structure in the substrate 200, and the top is electrically in contact with the bottom of the corresponding word line WL, thereby forming a dummy structure such as a dummy word line contact hole; each first dummy bit line mark 202b can be formed together with the first bit line connection portion 202a, that is, each first dummy bit line mark 202b can be made of the same material and structure as the first bit line connection portion 202a, but each first dummy The bottom of the bit line mark 202b is not electrically connected to any electrical structure in the substrate 200, and the top is electrically connected to the bottom of the corresponding first bit line BBL, thereby forming a virtual structure such as a virtual bit line contact hole at the bottom; each second virtual bit line mark 203b can be formed together with the second bit line connection portion 203a, and each second virtual bit line mark 203b can be made of the same material and structure as the second bit line connection portion 203a, but the bottom of each second virtual bit line mark 203b is not electrically connected to any electrical structure in the substrate 200, and the top is electrically connected to the bottom of the corresponding second bit line TBL, thereby forming a virtual structure such as a virtual bit line contact hole at the top.

[0062] The virtual word line marks 201b are arranged in the same column and at equal intervals, so that the same number of word lines WL are spaced between any two adjacent virtual word line marks 201b, so that the word lines WL can be counted by using the virtual word line marks 201b (that is, the word line WL electrically contacted by the virtual word line mark 201b can be determined to be the number of word lines WL of the memory block); the first virtual bit line marks 202b are arranged in the same column and at equal intervals, so that the same number of first bit lines BBL are spaced between any two adjacent first virtual bit line marks 202b, so that the first virtual bit line marks 202b can be used to count the word lines WL. The first bit lines BBL are counted (i.e., the first bit line BBL electrically contacted by the first virtual bit line mark 202b can be determined to be the first bit line BBL number of the memory block); the second virtual bit line marks 203b are arranged in the same row and at equal intervals, so that an equal number of second bit lines TBL are spaced between any two adjacent second virtual bit line marks 203b, so that the second bit lines TBL can be counted by using the second virtual bit line marks 203b (i.e., the second bit line TBL electrically contacted by the second virtual bit line mark 203b can be determined to be the second bit line TBL number of the memory block). When it is necessary to analyze the memory chip during manufacturing or after manufacturing, the first virtual bit line marker 202b and the virtual word line marker 201b can be used to locate the word line WL and the first bit line BBL connected to the specified first storage cell Bcell, thereby quickly and accurately locating the specified first storage cell Bcell; the second virtual bit line marker 203b and the virtual word line marker 201b can be used to locate the word line WL and the second bit line TBL connected to the specified second storage cell Tcell, thereby quickly and accurately locating the specified second storage cell Tcell.

[0063] In the above example, the meaning of "alignment" in the alignment of each virtual word line mark 201b with the corresponding word line WL is alignment in the conventional sense, that is, the virtual word line mark 201b at least partially overlaps with the corresponding word line WL in the Z direction, but the technical solution of the present invention is not limited to this. In other embodiments of the present invention, the meaning of "alignment" in the alignment of each virtual word line mark 201b with the corresponding word line WL is alignment in the unconventional sense, and the virtual word line mark 201b does not overlap with the corresponding word line WL in the Z direction. The virtual word line mark 201b is set between the corresponding two adjacent word lines WL. The virtual word line mark 201b can mark the number of word lines between any one of its two adjacent word lines WL and the first word line WL in the storage block. Similarly, the meaning of "alignment" in aligning each first virtual bit line mark 202b with the corresponding first bit line BBL can be either alignment in the conventional sense or alignment in the unconventional sense, and the meaning of "alignment" in aligning each second virtual bit line mark 203b with the corresponding second bit line TBL can be either alignment in the conventional sense or alignment in the unconventional sense.

[0064] It should be noted that the main function of the virtual word line mark 201b, the first virtual bit line mark 202b and the second virtual bit line mark 203b is to count the word line WL, the first bit line BBL and the second bit line TBL. Therefore, in other embodiments of the present invention, if the process and cost permit, the material and / or structure of the virtual word line mark 201b and the word line connection part 201a may also be different, the material and / or structure of the first virtual bit line mark 202b and the first bit line connection part 202a may also be different, and the material and / or structure of the second virtual bit line mark 203b and the second bit line connection part 203a may also be different.

[0065] In this embodiment, the memory chip further includes the following blank areas corresponding to each memory block 20: a word line control transistor area 20c, a first bit line control transistor area 20d, and a second bit line control transistor area 20e. In which, each word line control transistor for controlling the corresponding word line WL is formed in the substrate 200 of the word line control transistor area 20c of the storage block 20, and each word line connection portion (or called word line contact hole) 201a of the storage block 20 and each virtual word line mark 201b are all formed in the word line control transistor area 20c; each first bit line control transistor for controlling the corresponding first bit line BBL is formed in the substrate 200 of the first bit line control transistor area 20d, and each first bit line connection portion (or called first bit line contact hole) 202a of the storage block and each first virtual bit line mark 202b are all formed in the first bit line control transistor area 20d; each second bit line control transistor for controlling the corresponding second bit line TBL is formed in the substrate 200 of the second bit line control transistor area 20e, and each second bit line connection portion (or called first bit line contact hole) 203a of the storage block and each second virtual bit line mark 203b are all formed in the second bit line control transistor area 20e.

[0066] Optionally, the word line control transistor region 20c of each memory block 20 is disposed on a centerline axis of the memory block 20 extending in the X direction, thereby dividing the memory block 20 into two blocks 20a and 20b located on either side of the word line control transistor region 20c. The first bit line control transistor region 20d of each memory block 20 is disposed on a side boundary of the memory block 20 extending in the X direction, and the second bit line control transistor region 20e of each memory block is disposed on a centerline axis of the memory block 20 extending in the Y direction.

[0067] Further optionally, the virtual word line marks 201b in each storage block 20 are arranged in a column along the Y direction in the word line control transistor area 20c, and the word line connection parts 201a of the storage block 20 are evenly arranged on both sides of the column formed by the virtual word line marks 201b; the first virtual bit line marks 202b are arranged in a row along the X direction in the first bit line control transistor area 20d, and the first bit line connection parts 202a of the storage block 20 are evenly arranged on both sides of the row formed by the first virtual bit line marks 202b; the second virtual bit line marks 203b are arranged in a row along the X direction in the second bit line control transistor area 20e, and the second virtual bit line marks 203b of the storage block 20 are evenly arranged on both sides of the row formed by the second virtual bit line marks 203b.

[0068] Alternatively, refer to Figure 6The memory chip of this embodiment is a three-dimensional phase-change memory chip, in which the first memory cell Bcell and the second memory cell Tcell are both phase-change memory cells having a phase-change material layer PCM. As an example, the first memory cell Bcell and the second memory cell Tcell each include a bottom electrode BE (bottom electrode electrode), an ovonic threshold switch OTS (bidirectional threshold switch), a middle electrode ME (middle electrode), a phase-change material layer PCM (phase change material), and a top electrode TE (top electrode), stacked sequentially from bottom to top.

[0069] The bottom electrode BE, the middle electrode ME, the top electrode TE, the first bit line BBL, the word line WL, the second bit line TBL, the word line connection portion 201a, the first bit line connection portion 202a, and the second bit line connection portion 203a are all made of conductive materials and may or may not be identical. The bottom electrode BE, the middle electrode ME, the top electrode TE, the first bit line BBL, the word line WL, the second bit line TBL, the word line connection portion 201a, the first bit line connection portion 202a, and the second bit line connection portion 203a may each be a single-layer conductive film structure, or any one of them may be a structure formed by stacking multiple layers of conductive films. Their materials may be selected from a single metal (such as W, Co, Cu, Al, Ru, Rh, Pd, Ag, Pt, Au, Ir, or Ta), a conductive metal nitride (such as TiN, TaN, WN, or TaCN), a conductive metal silicide (such as tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide, or titanium silicide), and the like.

[0070] The gate OTS is called a switching device or an access device, which is a current control layer used to control current conduction. The gate OTS can be a bidirectional threshold switch. When a voltage lower than the threshold voltage is applied to the gate OTS, the gate OTS can be in a high-resistance state where almost no current flows. When a voltage higher than the threshold voltage is applied to the gate OTS, the gate OTS can be in a low-resistance state where current can flow. For example, if the gate OTS of the first memory cell is in a high-resistance state, its bottom electrode BE and middle electrode ME cannot conduct the current input by the first bit line BBL to its phase change material layer PCM. If the gate OTS of the first memory cell is in a low-resistance state, its bottom electrode BE and middle electrode ME can conduct the current input by the first bit line BBL to its phase change material layer PCM. In addition, in other embodiments of the present invention, the gate OTS can also be a device with the ability to control current conduction, such as a diode or a magnetic tunnel junction (MTJ). Furthermore, the material of the gate OTS may be a chalcogenide, including one or more elements of Group VI in the periodic table, or any one or more elements of Group III, Group IV, and Group V.

[0071] Optionally, the first memory cell Bcell and / or the second memory cell Tcell may further include interface barrier layers formed between the middle electrode ME and the phase change material layer PCM and between the top electrode TE and the phase change material layer PCM, respectively.

[0072] Optionally, an adhesion layer or the like may be provided between the first storage cell Bcell and the first bit line BBL, between the first storage cell Bcell and the word line WL, between the second storage cell Tcell and the second bit line TBL, and between the second storage cell Tcell and the word line WL.

[0073] It should be noted that in this embodiment, an insulating medium is filled between adjacent first bit lines BBL, between adjacent first storage cells Bcell, between adjacent word lines WL, between adjacent second storage cells Tcell, between adjacent second bit lines TBL, between the first bit line BBL and the word line WL, between the word line WL and the second bit line TBL, and between the first bit line BBL and the second bit line TBL of each storage block 20, and the insulating medium is formed by stacking multiple layers of dielectric material films, and the side walls of the word line connection part 201a, the virtual word line mark 201b, the first bit line connection part 202a, the first virtual bit line mark 202b, the second bit line connection part 203a and the second virtual bit line connection part 203b are all surrounded by the insulating medium to achieve insulation isolation between these structures.

[0074] Based on the same invention concept, please refer to Figure 7 This embodiment further provides a method for manufacturing the memory chip according to this embodiment, which includes:

[0075] S1, providing a substrate, wherein a first bit line connection portion and first dummy bit line marks distributed in the same row and at equal intervals are formed on the substrate;

[0076] S2, forming a first bit line layer on the substrate, wherein a plurality of first bit lines are formed in the first bit line layer in parallel and extending in a column direction, wherein each first bit line is electrically contacted with a corresponding first bit line connection portion, and each first bit line is aligned with a corresponding first dummy bit line mark, and the number of first bit lines spaced between any two adjacent first dummy bit line marks is the same;

[0077] S3, forming a first memory cell layer having a plurality of first memory cells arranged in an array on the first bit line layer, wherein the first memory cells in the same column are all located on the same first bit line and are all in electrical contact with the first bit line;

[0078] S4, forming first word line connectors and first dummy word line marks arranged in the same column and at equal intervals on the substrate, with the first memory cell layer exposing top surfaces of the first word line connectors and the first dummy word line marks, and the first word line connectors being electrically connected to the substrate;

[0079] S5, forming a word line layer on the first memory cell layer, the first word line connection portion, and the first dummy word line mark, wherein a plurality of parallel word lines extending along a row direction are formed in the word line layer, each of the first memory cells is located at an intersection of the word line and the first bit line, and the first memory cells on the same row are all electrically in contact with the same word line, and each word line is electrically in contact with a corresponding word line connection portion, and the corresponding word line is aligned with the corresponding dummy word line mark, and the number of word lines spaced between any two adjacent dummy word line marks is the same;

[0080] S6, forming a second memory cell layer having a plurality of second memory cells arranged in an array on the word line layer, wherein the second memory cells in the same row are all located on the same word line and are all in electrical contact with the word line;

[0081] S7, forming a second bit line connection portion and second dummy bit line marks in the same row and distributed at equal intervals on the substrate, with the second memory cell layer exposing top surfaces of the second bit line connection portion and the second dummy bit line mark, and the second bit line connection portion being electrically connected to the substrate;

[0082] S8. Form a second bit line layer on the second memory cell layer, wherein a plurality of second bit lines are formed in parallel and extend in the column direction, and each second memory cell is located at the intersection of the word line and the second bit line, and the second memory cells on the same column are all electrically in contact with the same second bit line, and each second bit line is electrically in contact with the corresponding second bit line connection portion, and the corresponding second bit lines are aligned with the corresponding second virtual bit line marks, and the number of second bit lines spaced between any two adjacent second virtual bit line marks is the same.

[0083] Please combine Figure 3 、 Figure 4 and Figure 8 In step S1, a substrate 200 is provided. The substrate 200 may be made of any suitable semiconductor material and may be processed through the front-end-of-line (FEOL) and at least part of the back-end-of-line (BEOL) processes of integrated circuit manufacturing. The front-end-of-line (FEOL) process is used to fabricate various required electronic components (not shown) such as transistors on a semiconductor substrate (not shown). The back-end-of-line (BEOL) process includes a metal interconnection process, or a metal interconnection process and a bonding process. The back-end-of-line (BEOL) process is used to form at least one dielectric layer (not shown) covering the semiconductor substrate, a metal interconnection structure (including conductive plugs and metal interconnection lines, etc.) formed in the dielectric layer, a first bit line connection portion 202a, first dummy bit line marks 202b distributed at equal intervals, a lower structure 201a1 of the word line connection portion 201a, a lower structure 201b1 of dummy word line marks 201b distributed at equal intervals, a lower structure 203a1 of the second bit line connection portion 203a, and a lower structure (not shown) of second dummy bit line marks 203b distributed at equal intervals. Among them, the metal interconnection structure in the substrate 200 includes a first metal interconnection structure to a third metal interconnection structure (none of which are shown in the figure), a first bit line control transistor (not shown) for controlling the first bit line BBL and a first metal interconnection structure (not shown) electrically connected to the first bit line control transistor constitute a first electrical structure 200a, a second bit line control transistor (not shown) for controlling the second bit line TBL and a second metal interconnection structure (not shown) electrically connected to the second bit line control transistor constitute a second electrical structure 200b, and a word line control transistor (not shown) for controlling the word line WL and a third metal interconnection structure (not shown) electrically connected to the word line control transistor constitute a third electrical structure 200c.

[0084] In this embodiment, the substrate 200 includes, for each memory block, at least a region for forming memory cells, a word line transistor region 20c for forming a word line control transistor for controlling a word line WL, a first bit line control transistor region 20d for forming a first bit line control transistor for controlling a first bit line BBL, and a second bit line control transistor region 20e for forming a second bit line control transistor for controlling a second bit line TBL. Each first bit line connection 202a and each first dummy bit line mark 202b in the substrate corresponding to each memory block are formed in the first bit line control transistor region 20d, with the first bit line connection 202a electrically connected to the first electrical structure 200a below it. The lower structure 203a1 of each second bit line connection 203a and the lower structure of each second dummy bit line mark 203b in the substrate corresponding to each memory block are formed in the second bit line control transistor region 20e, with the second bit line connection 203a electrically connected to the second electrical structure 200b below it. The lower structure 201a1 of each word line connection part 201a corresponding to each storage block in the substrate and the lower structure 201b1 of each virtual word line mark 201b are both formed in the word line control transistor area 20c and the lower structure 201a1 of the word line connection part 201a is electrically connected to the third electrical structure 200c thereunder.

[0085] In the actual manufacturing process, the substrate 200 having the above-mentioned structures can be formed by conventional technical means in the art, such as material deposition and filling, photolithography, etching, chemical mechanical polishing (CMP) and other processes, which will not be described in detail here.

[0086] It should be noted that when the designed first bit line connection part 202a, the lower structure 203a1 of the second bit line connection part 203a, the lower structure 201a1 of the word line connection part 201a, the first virtual bit line mark 202b, the lower structure of the second virtual bit line mark 203b, and the lower structure 201b1 of the virtual word line mark 201b use the same structure and materials, the first bit line connection part 202a, the lower structure 203a1 of the second bit line connection part 203a, the lower structure 201a1 of the word line connection part 201a, the first virtual bit line mark 202b, the lower structure of the second virtual bit line mark 203b, and the lower structure 201b1 of the virtual word line mark 201b can be manufactured together. However, when the materials or structures of at least two of the designed first bit line connection part 202a, the lower structure 203a1 of the second bit line connection part 203a, the lower structure 201a1 of the word line connection part 201a, the first virtual bit line mark 202b, the lower structure of the second virtual bit line mark 203b, and the lower structure 201b1 of the virtual word line mark 201b are different, these different components need to be manufactured separately.

[0087] It should be noted that the materials and structures of the substrate 200 and the electronic elements and components therein can be reasonably selected as needed and will not be described in detail here.

[0088] Please continue to combine Figure 3 、 Figure 4 and Figure 8 In step S2, a first bit line (BBL) layer, a first memory cell (Bcell) layer, and a mask layer (not shown) are sequentially stacked on the substrate 200, and the first bit line (BBL) is fabricated through a multi-patterning process. Specifically, the stacked layers from the first bit line (BBL) layer to the mask layer are patterned by photolithography and etching to form a first bit line (BBL) extending along a column direction (Y) and a first memory cell (Bcell) layer (i.e., a first memory stack bar) located on the first bit line (BBL). The multi-patterning process may include, but is not limited to, a light-etch-light-etch (Light-Etch-Light-Etch) double patterning process or a self-aligned double patterning (SADP) process to control the critical dimensions of the first bit line (BBL) and the first memory cell (Bcell) to be formed.

[0089] In some specific examples of this embodiment, a double patterning process may be first used to pattern a mask layer. Then, using the mask layer as a mask, the first memory cell Bcell layer and the first bit line BBL layer may be etched to the surface of the substrate 200 by one or more wet etching and / or dry etching processes (e.g., deep reactive ion etching (DRIE)) to form a plurality of parallel first bit lines BBL extending along the column direction Y and first memory stack bars (not shown) connected to the first bit lines BBL. The bottom surfaces of the first bit lines BBL are in contact with the top surfaces of the corresponding first bit line connection portions 202a and the first dummy bit line marks 202b. The number of first bit lines BBL spaced between adjacent first dummy bit line marks 202b is the same.

[0090] Please continue to combine Figure 3 、 Figure 4 and Figure 8In step S3, first, a first insulating protection layer 2041 and a second insulating protection layer 2042 are formed to protect the sidewalls of the first memory stack strips. The mask layer is then removed, and a new mask layer (not shown) is formed and patterned using a double patterning process. Using the mask layer as a mask, the first memory stack strips are further etched along the row direction X to the top surface of the first bit line BBL using one or more wet and / or dry etching processes, thereby forming a plurality of mutually independent first memory cells Bcell. A third insulating protection layer 2043 may then be formed on the sidewalls of the first memory cells Bcell to protect the sidewalls of the first memory cells Bcell. The materials of the first insulating protection layer 2041, the second insulating protection layer 2042, and the third insulating protection layer 2043 can be selected from silicon oxide, silicon nitride, silicon oxynitride, and combinations of any two or three thereof. Optionally, in this example, a groove (not marked) may be formed between each first memory cell BCell and located in the substrate 200 . The groove is used to isolate two adjacent first memory cells BCell to avoid mutual influence.

[0091] Optionally, the material of the first bit line BBL layer is a conductive material; the first memory cell BCell layer is a stacked structure, including a bottom electrode BE layer, a gate OTS layer, an intermediate electrode ME layer, a phase change material layer PCM and a top electrode TE layer stacked in sequence. The materials of the bottom electrode BE layer, the intermediate electrode ME layer and the top electrode TE layer may include conductive materials, such as but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), carbon (C), polysilicon, doped silicon, silicide or any combination thereof. The material of the gate OTS layer may include ZnTe, GeTe, NbO, SiAsTe, etc. or any combination thereof. The material of the phase change material layer PCM may be a chalcogenide compound, such as germanium antimony telluride alloy, antimony telluride alloy, germanium telluride alloy, titanium antimony telluride alloy, tantalum antimony telluride alloy or any other chalcogenide compound. Of course, the material of the phase change material layer PCM may also be other suitable phase change materials, which is not limited in this application.

[0092] Please combine Figure 3 、 Figure 4 and Figures 9 and 10 In step S4, a first dielectric layer 2011 is formed and a word line connection portion 201a and a dummy word line mark 201b are formed. The specific process includes:

[0093] First, a first dielectric layer 2011 is deposited to fill the gap between the first memory cell BCell layer and the first bit line BBL. A chemical mechanical polishing (CMP) process is used to planarize the top of the first dielectric layer 2011 .

[0094] Then, the first dielectric layer 2011 is etched to form a contact hole (not shown) aligned with the lower structure 201a1 of the word line connection portion 201a, a contact hole aligned with the lower structure 201b1 of the dummy word line mark 201b, a contact hole aligned with the lower structure 203a1 of the second bit line connection portion 203a, and a contact hole (not shown) aligned with the lower structure of the second dummy bit line mark 203b.

[0095] Next, corresponding conductive materials are filled in these contact holes, and the tops are flattened by a chemical mechanical polishing (CMP) process until the top electrode TE layer of the first memory cell BCell layer is exposed, thereby forming the upper structure 201a2 of the word line connection 201a, the upper structure 201b2 of the virtual word line mark 201b, the middle structure 203a2 of the second bit line connection 203a, and the middle structure of the second virtual bit line mark (not shown) in these contact holes. At this time, the upper structure 201a2 and the lower structure 201a1 of the word line connection 201a are electrically connected to form the word line connection 201a, and the lower structure 201b1 and the upper structure 201b2 of the virtual word line mark 201b are connected to form the virtual word line mark 201b.

[0096] The material of the first dielectric layer 2011 may be a dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, and other materials with high filling rate and low thermal conductivity.

[0097] Optionally, after forming the word line connection portion 201a and the dummy word line mark 201b or before forming the word line connection portion 201a and the dummy word line mark 201b and after the top of the first dielectric layer 2011 is planarized, the redundant first bit line BBL and the first dielectric layer 2011 and other structures can be removed by a suitable process such as edge cutting.

[0098] Please continue to combine Figure 3 、 Figure 4 and Figures 9 and 10 The specific process of forming a word line WL layer having a plurality of word lines WL arranged in parallel in step S5 includes:

[0099] First, a word line WL layer is deposited on the first dielectric layer 2011, the first memory cell Bcell layer, the word line connection portion 201a, the dummy word line mark 201b and the middle structure 203a2 of the second bit line connection portion 203a. Figure 5 When the word line WL layer includes a bottom word line BWL layer and a top sublayer TWL layer, the bottom word line BWL layer is deposited first.

[0100] Next, a patterned mask layer for forming bottom word lines BWL is produced through a multiple patterning process; the deposited bottom word line BWL layer is then etched along the row direction X using the patterned mask layer to form a plurality of bottom word lines BWL, wherein the bottom surfaces of the bottom word lines BWL are in contact with the top surfaces of the corresponding word line connection portions 201a and the dummy word line marks 201b, and the number of bottom word lines BWL spaced between adjacent dummy word line marks 201b is the same.

[0101] Optionally, after forming the bottom word line BWL, a second dielectric layer 2012 is further deposited to fill the gap between the bottom word line BWL and the first memory cell Bcell layer, and the top of the interlayer dielectric layer is planarized, and then redundant structures such as the bottom word line BWL are removed through appropriate processes such as edge cutting.

[0102] Please continue to combine Figure 3 、 Figure 4 and Figures 9 to 11 In step S6, the specific process of forming the second storage unit Tcell layer includes:

[0103] First, the top word line TWL layer, the second storage cell Tcell layer and the mask layer are stacked in sequence on the bottom word line BWL layer and the exposed film layer surface, wherein the film layers of the second storage cell Tcell layer correspond one to one and are the same as the film layers of the first storage cell layer, and are not described in detail here.

[0104] Next, a multi-patterning process is used to pattern the stack from the top wordline (TWL) layer to the mask layer to form a top wordline (TWL) extending along the row direction (X) and a second memory stack strip (i.e., the remaining second memory cell (Tcell) layer) located above the top wordline (TWL). This multi-patterning process may include, but is not limited to, a double patterning process (lithography-etching-lithography-etching) or a self-aligned double patterning process to control the critical dimensions of the top wordline (WL) and the second memory cell (Bcell) to be formed. The top wordline (TWL) and the bottom wordline (BWL) are aligned (process misalignment is acceptable) and electrically contact each other.

[0105] Next, a first insulating protection layer 2041 and a second insulating protection layer 2042 similar to the first insulating protection layer 2041 and the second insulating protection layer 2042 are formed on the sidewalls of the second storage stack bar to protect the sidewalls of the second storage stack bar.

[0106] Afterwards, the second memory stack strips are further etched along the column direction Y to the top surface of the top word line TWL by one or more wet etching and / or dry etching processes, thereby forming a plurality of mutually independent second memory cells Tcell.

[0107] Please continue to combine Figure 3 、 Figure 4 and Figures 9 to 12The specific process of forming the third dielectric layer 2013 and forming the second bit line connection portion 203a and the second dummy bit line mark 203b in step S7 includes:

[0108] First, a third dielectric layer 2013 is deposited to fill the gap between the second memory cell TCell layer and the top bit line TWL. A chemical mechanical polishing (CMP) process is used to planarize the top of the third dielectric layer 2013 .

[0109] Then, the third dielectric layer 2013 is etched to form a contact hole (not shown) aligned with the middle structure 203 a 2 of the second bit line connection portion 203 a and a contact hole aligned with the middle structure of the second dummy bit line mark 203 b .

[0110] Next, corresponding conductive materials are filled in these contact holes, and the top is flattened by a chemical mechanical polishing (CMP) process until the top electrode TE layer of the second memory cell TCell layer is exposed, thereby forming the upper structure 203a3 of the second bit line connection portion 203a and the upper structure (unmarked) of the second virtual bit line mark 203b. At this time, the upper structure 203a3, the middle structure 203a2 and the lower structure 203a1 of the second bit line connection portion 203a are electrically connected in sequence to form the second bit line connection portion 203a, and the upper structure, the middle structure and the lower structure of the second virtual bit line mark are connected in sequence to form the second virtual bit line mark 203b.

[0111] The material of the third dielectric layer 2013 may be a dielectric material, such as silicon oxide, aluminum oxide, silicon nitride, or other materials with high filling rate and low thermal conductivity.

[0112] Optionally, after forming the upper structure 203a3 of the second bit line connection portion 203a and the upper structure of the second dummy bit line mark 203b, or before forming the upper structure 203a3 of the second bit line connection portion 203a and the upper structure of the second dummy bit line mark 203b and after top planarization treatment is performed on the third dielectric layer 2013, redundant top word lines WL and other structures may be removed by a suitable process such as edge cutting.

[0113] Please continue to combine Figure 3 、 Figure 4 and Figures 9 to 12 The specific process of forming the second bit line TBL layer having a plurality of second bit lines TBL arranged in parallel in step S8 includes:

[0114] First, a second bit line TBL layer is deposited on the third dielectric layer 2013 , the second memory cell Tcell layer, the upper structure 203 a 3 of the second bit line connection portion 203 a , and the upper structure of the second dummy bit line mark 203 b .

[0115] Afterwards, a patterned mask layer for forming the second bit lines TBL is fabricated through a multiple patterning process. The deposited second bit line TBL layer is then etched along the column direction X using the patterned mask layer to form a plurality of second bit lines TBL. The bottom surfaces of the second bit lines TBL are in contact with the top surfaces of the corresponding second bit line connecting portions 203a and the second dummy bit line marks 203b, and the number of second bit lines TBL spaced between adjacent second dummy bit line marks 203b is the same.

[0116] Optionally, after forming the second bit line TBL, an interlayer dielectric layer (not shown) is further deposited to fill the gap between the second bit line TBL and the second memory cell Tcell layer, and the top of the interlayer dielectric layer is planarized, and then redundant second bit line TBL and other structures are removed by a suitable process such as edge cutting.

[0117] It should be noted that, in the above example, before covering the bottom word line layer, mutually independent first memory cells have been formed in the first memory cell layer, and before covering the second bit line layer, mutually independent second memory cells have been formed in the second memory cell layer. However, the technical solution of the present invention is not limited to this. In other embodiments of the present invention, steps S2 to S8 are re-divided so that when the first bit line layer is etched to form the first bit line BBL, the first memory cell layer is synchronously cut into a first memory stack bar, and then when the word line WL layer and the second memory cell layer are deposited in sequence, the first memory stack bar and the second memory cell layer are synchronously cut when the word line layer is etched to form the word line WL, thereby forming mutually independent first memory cells and a second memory stack bar located above the word line WL while forming the word line WL, and then when the second bit line layer is deposited and etched to form the second bit line TBL, the second memory stack bar is synchronously cut into mutually independent second memory cells.

[0118] Based on the same inventive concept, this embodiment further provides a method for locating a designated storage unit in a memory chip as described in this embodiment, which includes:

[0119] Grinding or slicing the memory chip to expose the dummy word line mark and / or the first dummy bit line mark of the corresponding memory block;

[0120] Determining the position of a designated word line of the memory block using the exposed virtual word line mark; and / or determining the position of a designated bit line of the memory block using the exposed first virtual bit line mark;

[0121] The determined position of the designated word line and / or the determined position of the designated bit line are used to find the designated memory cell for subsequent analysis.

[0122] It should also be noted that in the above example, the word lines WL include a bottom word line BWL and a top word line TWL, but the technical solution of the present invention is not limited to this. In other embodiments of the present invention, only one layer of word lines may be provided as needed. In the above example, a first bit line BBL, a second bit line TBL, and two layers of memory cells are provided, but the technical solution of the present invention is not limited to this. In other embodiments of the present invention, one layer of bit lines and the layer of memory cells sandwiched between the bit line and the word line may be omitted as needed.

[0123] It should be noted that in the memory chips and manufacturing methods thereof described in the above embodiments, the second memory cell layer and the first memory cell layer of the memory block share the same word line layer, but the technical solution of the present invention is not limited to the above examples.

[0124] For example, in the memory chips of other embodiments of the present invention, the memory blocks thereof can omit structures such as the second memory cell layer and the second bit line layer, the second bit line connection portion and the second virtual bit line relative to the above example. Thus, the manufacturing method of the memory chip omits the above steps S6 to S8 relative to the manufacturing method in the above embodiment.

[0125] For another example, in the memory chip and the manufacturing method thereof in other embodiments of the present invention, the memory block thereof can be compared with the above embodiments, on the basis of omitting the second memory cell layer and the second bit line layer, the second bit line connection portion and the second virtual bit line and other structures, further adding another word line layer and another memory cell layer stacked on the substrate in sequence between the substrate and the first bit line layer, so as to realize that two adjacent memory cell layers share the same bit line layer. Specifically, the word line layer located above the first bit line layer is recorded as the "first word line layer", the word line connection portion corresponding to the first word line layer is recorded as the "first word line connection portion", the corresponding virtual word line mark is recorded as the "first virtual word line mark", and the word line layer located above the first bit line layer is recorded as the "first word line connection portion". The wordline layer below the first bitline layer is referred to as the "second wordline layer," and the memory cell layer between the first bitline layer and the second wordline layer is referred to as the "third memory cell layer." Similar to the descriptions in the aforementioned embodiments, the second wordline layer includes a plurality of parallel second wordlines extending along the row direction, and the third memory cell layer includes third memory cells located at the intersections of the second wordlines and the first bitlines. The memory block further includes a plurality of second dummy wordline marks distributed in the same column and at equal intervals, each second dummy wordline mark being aligned with a corresponding second wordline, and the number of second wordlines spaced between any two adjacent second dummy wordline marks being the same. Based on this, the manufacturing method of this memory chip, compared to the manufacturing method in the aforementioned embodiments, omits steps S6 through S8. However, before forming the first bitline connection portion and the first dummy bitline mark, the second wordline layer, the second wordline connection portion, and the second dummy bitline mark are first fabricated in the substrate using methods similar to those for fabricating the first bitline connection portion, the first dummy bitline mark, and the first bitline in steps S1 through S2 of the aforementioned embodiments. The third memory cell layer is then fabricated using methods similar to those for fabricating the first memory cell layer in step S3.

[0126] For another example, in a memory chip according to another embodiment of the present invention, its memory block not only has a second memory cell layer, a second bit line layer, a second bit line connection portion, a second dummy bit line, and other structures, but also has a third memory cell layer, a second word line layer, a second word line connection portion, a second dummy word line mark, and the like located below the first bit line layer. The manufacturing method of this memory chip is similar to the manufacturing method of the aforementioned embodiments and will not be further described here.

[0127] In addition, the memory chip of the present invention is not only used for phase change memory, but also can replace the storage layer of the storage unit of the memory chip with other storage materials other than the phase change material layer, such as magnetoresistive material, etc. In this case, the memory chip is a magnetic memory.

[0128] Furthermore, it should be understood that when the technical solution of the present invention is applied to a three-dimensional stack of multi-layer memory blocks, the memory blocks described in the above embodiments can be stacked in multiple layers in the Z direction to achieve multi-bit storage at the same location, thereby increasing the storage density of the memory chip. In this case, optionally, the word lines WL of each memory block in the same row of the same layer are formed from the same word line layer and aligned one-to-one, and the word lines WL aligned between two adjacent memory blocks in the same row of the same layer are not connected, thereby achieving insulation isolation between the word lines WL of the two memory blocks. The first bit lines BBL of each memory block in the same column of the same layer are formed from the same first bit line layer and aligned one-to-one, and the first bit lines BBL aligned between two adjacent memory blocks in the same column of the same layer are not connected, thereby achieving insulation isolation between the first bit lines BBL of the two memory blocks. The second bit lines TBL of each memory block in the same column of the same layer are formed from the same second bit line layer and aligned one-to-one, and the second bit lines TBL aligned between two adjacent memory blocks in the same column of the same layer are not connected, thereby achieving insulation isolation between the second bit lines TBL of the two memory blocks.

[0129] It should be understood that the “in an embodiment of the present application” or “in some embodiments” mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, “in an embodiment of the present application” or “in some embodiments” appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0130] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0131] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A memory chip, comprising a plurality of memory blocks arranged in an array, each of the memory blocks comprising a first bit line layer, a first memory cell layer and a first word line layer stacked in sequence from bottom to top, the first bit line layer having a plurality of first bit lines extending in parallel in a column direction, the first word line layer having a plurality of first word lines extending in parallel in a row direction, the first memory cell layer comprising a plurality of first memory cells, each of the first memory cells being located at an intersection of a corresponding first word line and a corresponding first bit line; characterized in that The storage block further comprises a plurality of first virtual word line marks which are arranged in the same column and at equal intervals, and a plurality of first virtual bit line marks which are arranged in the same column and at equal intervals, each of the first virtual word line marks being aligned with the corresponding first word line, and the number of first word lines spaced between any two adjacent first virtual word line marks being the same, each of the first virtual bit line marks being aligned with the corresponding first bit line, and the number of first bit lines spaced between any two adjacent first virtual bit line marks being the same; Among them, the storage block has a first word line connection portion arranged corresponding to the first word line and electrically connected to the first word line, and a first bit line connection portion arranged corresponding to the first bit line and electrically connected to the first bit line; the memory chip is provided with a word line control transistor area and a first bit line control transistor area for controlling the storage block, the first virtual word line mark and the first word line connection portion of the storage block are both arranged in the first word line control transistor area, and the first virtual bit line mark and the first bit line connection portion of the storage block are both arranged in the first bit line control transistor area.

2. The memory chip according to claim 1, wherein: The first dummy bit line mark has the same structure as the first bit line connection portion, and the first word line dummy mark has the same structure as the first word line connection portion.

3. The memory chip according to any one of claims 1 to 2, characterized in that: The storage block further comprises a second storage unit layer and a second bit line layer sequentially stacked on the first word line layer, the second bit line layer comprises a plurality of second bit lines which are parallel and extend along the column direction, and the second storage unit layer comprises a second storage unit located at the intersection of the first word line and the second bit line; wherein the storage block further comprises a plurality of second virtual bit line marks which are arranged in the same row and are equally spaced, each of the second virtual bit line marks is aligned with the corresponding second bit line, and the number of second bit lines spaced between any two adjacent second virtual bit line marks is the same; And / or, the storage block also includes a third storage cell layer located below the first bit line layer and a second word line layer located below the third storage cell layer, the second word line layer has a plurality of parallel second word lines extending along the row direction, and the third storage cell layer includes a third storage cell located at the intersection of the second word line and the first bit line; wherein, the storage block also has a plurality of second virtual word line marks distributed in the same column and at equal intervals, each second virtual word line mark is aligned with the corresponding second word line, and the number of second word lines spaced between any two adjacent second virtual word line marks is the same.

4. The memory chip according to claim 3, wherein: The memory chip is a three-dimensional phase-change memory chip, and each of the first memory cells and each of the second memory cells are phase-change memory cells having a phase-change material layer.

5. The memory chip according to claim 3, wherein: When the memory block has the second bit line layer and the second memory cell layer, the memory block further has a second bit line connection portion arranged corresponding to the second bit line and electrically connected to the second bit line, the memory chip further has a second bit line control transistor region for controlling the memory block, and the second virtual bit line mark and the second bit line connection portion of the memory block are both arranged in the second bit line control transistor region; When the storage block has the second word line layer and the third storage unit layer, the storage block also has a second word line connection portion arranged corresponding to the second word line and electrically connected to the second word line, and the memory chip is also provided with a second word line control transistor area for controlling the storage block, and the second virtual word line mark and the second word line connection portion of the storage block are both arranged in the second word line control transistor area.

6. The memory chip according to claim 3, wherein: When the storage block has the second bit line layer and the second storage unit layer, the projections of the first bit line and the second bit line of the storage block in the stacking direction are misaligned; when the storage block has the second word line layer and the third storage unit layer, the projections of the first word line and the second word line of the storage block in the stacking direction are misaligned.

7. The memory chip according to claim 3, wherein: When the storage block has the second bit line layer and the second storage cell layer, insulating media are filled between adjacent first lines, between adjacent first storage cells, between adjacent first word lines, between adjacent second storage cells, between adjacent second bit lines, between the first bit line and the first word line, between the first word line and the second bit line, and between the first bit line and the second bit line; when the storage block has the second word line layer and the third storage cell layer, insulating media are filled between adjacent first lines, between adjacent first storage cells, between adjacent first word lines, between adjacent second storage cells, between adjacent second word lines, between the first bit line and the first word line, between the first bit line and the second word line, and between the first word line and the second word line.

8. A method for manufacturing a memory chip according to any one of claims 1 to 7, characterized in that: include: Provide a substrate, wherein a first bit line connection portion and first virtual bit line marks in the same row and distributed at equal intervals are formed in the substrate; forming a first bit line layer on the substrate, wherein a plurality of first bit lines are formed in the first bit line layer and are parallel and extend in a column direction, each first bit line is in electrical contact with a corresponding first bit line connection portion, and a corresponding first bit line is aligned with a first dummy bit line mark, and the number of first bit lines spaced between any two adjacent first dummy bit line marks is the same; forming a first memory cell layer having a plurality of first memory cells arranged in an array on the first bit line layer, wherein the first memory cells on the same column are all located on the same first bit line and are all in electrical contact with the first bit line; Forming a first word line connection portion and first virtual word line marks arranged in the same column and at equal intervals on the substrate, wherein the first memory cell layer exposes the top surfaces of the first word line connection portion and the first virtual word line mark, and the first word line connection portion is electrically connected to the substrate; A first word line layer is formed on the first storage cell layer, the first word line connection portion and the first virtual word line mark, a plurality of parallel word lines extending along the row direction are formed in the first word line layer, each of the first storage cells is located at the intersection of the corresponding first word line and the corresponding first bit line, and the first storage cells on the same row are all electrically contacted with the same first word line, and each of the first word lines is electrically contacted with the corresponding first word line connection portion, and the corresponding first word line is aligned with the corresponding first virtual word line mark, and the number of word lines spaced between any two adjacent first virtual word line marks is the same.

9. The manufacturing method according to claim 8, characterized in that: After forming the first word line layer, the method further includes: forming a second memory cell layer having a plurality of second memory cells arranged in an array on the first word line layer, wherein the second memory cells on the same row are all located on the same first word line and are all in electrical contact with the first word line; Forming a second bit line connection portion and second dummy bit line marks in the same row and distributed at equal intervals on the substrate, wherein the second memory cell layer exposes the top surfaces of the second bit line connection portion and the second dummy bit line mark, and the second bit line connection portion is electrically connected to the substrate; A second bit line layer is formed on the second memory cell layer, the second bit line connection portion and the second virtual bit line mark, a plurality of second bit lines are formed in the second bit line layer in parallel and extending in a column direction, each of the second memory cells is respectively located at an intersection of a corresponding first word line and a corresponding second bit line, the second memory cells on the same column are all electrically in contact with the same second bit line, and each of the second bit lines is electrically in contact with a corresponding second bit line connection portion, the corresponding second bit line is aligned with the corresponding second virtual bit line mark, and the number of second bit lines spaced between any two adjacent second virtual bit line marks is the same; Alternatively, before forming the first bit line layer on the substrate, the method further includes: forming a second word line connection portion and second dummy word line marks distributed in the same column and at equal intervals in the substrate; forming a second word line layer on the substrate, wherein a plurality of second word lines are formed in the second word line layer and are parallel and extend in a row direction, each second word line is in electrical contact with a corresponding second word line connection portion, and a corresponding second word line is aligned with a second virtual word line mark, and the number of second word lines spaced between any two adjacent second virtual word line marks is the same; A third storage cell layer having a plurality of third storage cells arranged in an array is formed on the second word line layer, each third storage cell is located at the intersection of the corresponding first bit line and the second word line, and the third storage cells on the same row are all located on the same second word line and are in electrical contact with the second word line.

10. A method for locating a designated storage unit in a memory chip according to any one of claims 1 to 7, characterized in that: include: Grinding or slicing the memory chip to expose the first virtual word line mark and / or the first virtual bit line mark of the corresponding memory block; Determining the position of a designated word line of the memory block by using the position of the exposed first virtual word line mark; and / or, determining the position of a designated bit line of the memory block using the position of the exposed first virtual bit line mark; The determined position of the designated word line and / or the determined position of the designated bit line are used to find the designated memory cell for subsequent analysis.

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