Airborne data comprehensive acquisition and recording system and method

Abstract

The invention relates to an airborne data comprehensive acquisition and recording system and method, which comprises an integrated data collector, a cache record card and a protection recorder located on an airborne part; the integrated data collector is electrically connected to the protection recorder through Ethernet; the integrated data collector is electrically connected to an onboard power supply; an input end of the integrated data collector is used to collect onboard signals on the airborne part, the onboard signals including switch signals, frequency signals, voltage signals, vibration signals, ARINC429 bus, RS422 bus, MIL-STD-155B bus, AFDX bus, audio signals and video signals; and the data of the collected onboard signals are packaged according to the IRIG-106 standard and then sent to the cache record card and the protection recorder for recording; the invention has reasonable design, compact structure and convenient use.

Description

Technical Field

[0001] The invention relates to an airborne data comprehensive acquisition and recording system and method. Background Art

[0002] Traditional aircraft are mainly based on mechanical aircraft controls and analog operating systems. With the rapid development of technology, they are gradually being replaced by fully electronic control equipment. In the past, when pilots, especially test pilots, were faced with a large number of mechanical instruments and various complex data when operating aircraft. They often needed pilots to have rich personal experience to collect and record them. The heavy workload was not conducive to the accurate collection and analysis of data.

[0003] The comprehensive data acquisition and recording system mainly collects on-board switch signals, frequency signals, voltage signals, vibration signals, ARINC429 bus, RS422 bus, MIL-STD-155B bus, AFDX bus, audio signals, video signals and other signals, and records data in accordance with the IRIG-106 standard.

[0004] CN201120265010.X provides an airborne computer data acquisition and recording system, which includes a computer acquisition recorder connected to a bus, a track guidance display and an airborne power supply module; the computer acquisition recorder includes a first embedded processor module, an analog parameter acquisition module and a serial data acquisition module respectively connected to the bus, and the first embedded processor module is also connected to a detachable reinforced electronic disk; the track guidance display includes a digital I / O parameter acquisition module and a second embedded processor module respectively connected to the bus, the digital I / O parameter acquisition module is connected to a keyboard control interface, and the second embedded processor module is connected to an EL display screen. However, its structure is complex, the test accuracy is low, and effective recording cannot be achieved. Summary of the invention

[0005] The technical problem to be solved by the present invention is generally to provide an airborne data comprehensive acquisition and recording system and method.

[0006] To solve the above problems, the technical solution adopted by the present invention is:

[0007] An airborne data integrated collection and recording system includes an integrated data collector, a cache recording card and a protection recorder located on an airborne part; the integrated data collector is electrically connected to the protection recorder via Ethernet;

[0008] The integrated data collector is electrically connected to the onboard power supply; its input end is used to collect onboard signals on the airborne part, the onboard signals include switch signals, frequency signals, voltage signals, vibration signals, ARINC429 bus, RS422 bus, MIL-STD-155B bus, AFDX bus, audio signals and video signals; and the collected onboard signal data is packaged according to the IRIG-106 standard, and then sent to the cache record card and the protection recorder for recording;

[0009] The cache record card uses SATA bus to connect with the comprehensive data collector to complete the recording of all collected data;

[0010] The protection recorder uses a Gigabit Ethernet bus to connect with the integrated data collector to complete the recording of important data; important data includes data used for accident analysis;

[0011] On the ground, there are unloading verifiers and ground comprehensive analysis and processing systems for flight parameter data;

[0012] The unloading verifier is interconnected with the protection recorder and the comprehensive data collector through Ethernet; the output end of the unloading verifier is electrically connected to the input end of the ground comprehensive analysis and processing system of the flight parameter data to import data.

[0013] As a further improvement of the above technical solution:

[0014] The chassis structure of the integrated data collector adopts a backplane-free form, and the communication and power supply between modules are interconnected through inter-board connectors;

[0015] The integrated data collector includes a power module, a main control module with an integrated cache record card, a voltage signal acquisition module I, a voltage signal acquisition module II, a switch signal acquisition module, a vibration signal acquisition module, a bus acquisition module, and an audio and video acquisition module;

[0016] The main control module, voltage signal acquisition module I, voltage signal acquisition module II, switch signal acquisition module, vibration signal acquisition module, bus acquisition module, audio and video acquisition module have

[0017] BIT test capability module; BIT test capability module has three self-test modes, including PBIT power-on self-test, CBIT periodic self-test and IBIT maintenance self-test;

[0018] Fault logging module, each module provides fault logging means through the LAN bus, the fault information is stored in the non-volatile memory, and each fault record information must contain timestamp information;

[0019] Time synchronization module, each module uses IRIG-B code to achieve time synchronization, uses hardware time stamping, and the time synchronization accuracy is 100ns.

[0020] In the integrated data logger, the power module, including the PCU power conversion unit, combines the normal power supply and the emergency power supply into a combined input, converting the DC 28V input voltage into a DC 24Vd baseboard voltage;

[0021] The voltage range of normal power supply is 22V~30V; the voltage range of emergency power supply is 18V~30V;

[0022] The PSA power supply has an output voltage monitoring and switch control module interconnected with the NIU module; working under the control of the NIU module, the output voltage monitoring and switch control module is responsible for connecting, disconnecting and monitoring the different power outputs of other modules in the rack;

[0023] The NIU module, which connects the CPU module and the PHY module through internal MII signals, is used to manage the power supply in the rack and detect power distribution failures; the CPU module controls the PSA according to the information received from the system to provide power to the desired module; the PHY module communicates with the system through the LAN channel.

[0024] The PCU power conversion unit includes an energy storage capacitor, a holding module, a filter module, and a DC-DC module I; the input end of the filter module is connected to an external power supply, and the input end of the holding module is respectively connected to the output end of the energy storage capacitor and the filter module; the output end of the holding module is connected to the input end of the DC-DC module I; the DC-DC module I outputs a +24V voltage;

[0025] A voltage signal acquisition module I for inputting 32 voltage signals, a voltage signal acquisition module II for inputting 32 voltage signals, a switch signal acquisition module for inputting switch signals and frequency signals, a vibration signal acquisition module for inputting vibration signals, a bus acquisition module for inputting ARINC429, RS422, MIL-STD-1553B and / or AFDX signals, and an audio and video acquisition module for inputting audio signals and video signals complete the exchange of collected data with the main control module through the PCIe bus and complete the exchange of maintenance information with the main control module through the LAN bus, and the maintenance information includes self-test information, software upgrade, log information and parameter monitoring;

[0026] The main control module integrates FPGA integrated circuit, LAN switch chip, PCIe switch chip, CPU, synchronization signal module, and RTC chip; wherein the PCIe switch chip exchanges with the voltage signal acquisition module I, the voltage signal acquisition module II, the switch signal acquisition module, the vibration signal acquisition module, the bus acquisition module, and the audio and video acquisition module through the PCIe bus and the input end of the synchronization signal module through the IRIG-B channel;

[0027] The LAN switch chip interconnects the maintenance information with the offload verifier through the LAN; the maintenance log information is stored in the SATA hard disk integrated on the main control module; the LAN switch chip interconnects with the CPU through the LAN;

[0028] The PCIe switch chip exchanges with the CPU via the PCIe bus; the CPU is electrically connected to the cache card via the SATA channel;

[0029] The synchronization signal module receives the RTC timing signal from the RTC chip;

[0030] In the physical link of the PCIe bus, the PCIe link uses an end-to-end data transmission method, and both the sending end and the receiving end contain TX sending logic and RX receiving logic; the PCIe link includes multiple data paths Lane; in the data path Lane, it includes the sending link of the sending end and the sending link of the receiving end;

[0031] The transmitting link of the receiving end, that is, the receiving link of the receiving end, the TX component of the transmitting end and the RX component of the receiving end are connected using a set of differential signals;

[0032] The RX component of the transmitting end is connected to the TX component of the receiving end using another set of differential signals. This link is also called the receiving link of the transmitting end, that is, the sending link of the receiving end;

[0033] The PCIe link transmits data via differential signals, which include D+ and D-. The signal receiving end determines whether the sending end sends a logic 1 or a logic 0 by comparing the difference between the D+ and D- signals.

[0034] The voltage signal acquisition module comprises a voltage signal conditioning module, an AD sampling module, a self-checking circuit, an FPGA integrated circuit I, a CPU1, and a port PHYI;

[0035] A voltage signal conditioning module, whose input terminal inputs 32 voltage signals; an AD sampling module, whose input terminal is electrically connected to the output terminal of the voltage signal conditioning module, the output of the AD sampling module is electrically connected to the input terminal of the FPGA integrated circuit 1, and the FPGA integrated circuit 1 is electrically connected to the CPU1; a self-test circuit is electrically connected to the voltage signal conditioning module, the AD sampling module, the FPGA integrated circuit 1 and the CPU1 respectively;

[0036] FPGA integrated circuit I receives IRIG-B synchronization signal and cross-links PCIe bus;

[0037] CPU1 crosslinks LAN signals through port PHYI;

[0038] A switch signal acquisition module, including a switch signal conditioning module, a frequency signal conditioning module, a switch signal self-test circuit, a switch signal CPU, a switch signal CPU, a switch signal port and a switch signal integrated circuit;

[0039] A switch signal conditioning module, whose input end receives 96 switch signal inputs and whose output end is electrically connected to a switch signal integrated circuit;

[0040] The frequency signal conditioning module receives 6-channel frequency signal inputs and is interconnected with the switch signal conditioning module, and its output end is electrically connected to the switch signal integrated circuit.

[0041] Switch signal integrated circuit, receiving IRIG-B synchronization signal, cross-linking PCle bus;

[0042] The switch signal CPU is interconnected with the switch signal integrated circuit and connected to the LAN port through the switch signal port;

[0043] Switch signal self-check circuit, self-check switch signal conditioning module, frequency signal conditioning module and switch signal CPU;

[0044] Vibration data acquisition module, a vibration signal conditioning module for receiving vibration signals, an azimuth signal conditioning module for receiving azimuth signals, a vibration data AD sampling module, a vibration data self-checking circuit, a vibration circuit FPGA module, an oscillation data CPU and a vibration data PHY port;

[0045] The vibration signal conditioning module is connected to the input end of the vibration circuit FPGA module through the vibration data AD sampling module, and the output end of the azimuth signal conditioning module is connected to the input end of the vibration circuit FPGA module;

[0046] The oscillation data CPU is interconnected with the vibration circuit FPGA module and connected to the LAN channel through the vibration data PHY port; the vibration circuit FPGA module receives and receives the IRIG-B synchronization signal and interconnects the PCle bus; the vibration data self-check circuit self-checks the vibration signal conditioning module, the azimuth signal conditioning module, the vibration data AD sampling module and the oscillation data CPU.

[0047] Bus acquisition module, including RS422 interface conditioning module, ARINC429 interface conditioning module, MIL-STD-1553B interface conditioning module, AFDX bus interface conditioning module, bus FPGA module, bus self-test circuit, bus CPU, bus PHY;

[0048] The input terminal of the RS422 interface conditioning module is connected to the RS422 bus, the ARINC429 interface conditioning module is connected to the ARINC429 bus, the MIL-STD-1553B interface conditioning module is connected to the MIL-STD-1553B bus, and the AFDX bus interface conditioning module is connected to the AFDX bus;

[0049] The output terminals of RS422 interface conditioning module, ARINC429 interface conditioning module, MIL-STD-1553B interface conditioning module and AFDX bus interface conditioning module are connected to the input terminal of bus FPGA module;

[0050] The bus FPGA module is connected to the IRIG-B synchronization signal, PCIe bus and bus CPU; the bus CPU is connected to the LAN channel through the bus PHY;

[0051] Bus self-test circuit self-tests RS422 interface conditioning module, ARINC429 interface conditioning module, MIL-STD-1553B interface conditioning module, AFDX bus interface conditioning module and bus CPU;

[0052] The audio and video data acquisition module includes a video signal conditioning module for receiving video signals, an audio signal conditioning module for receiving audio signals, a video acquisition module, an audio and video AD sampling module, an audio and video self-test circuit, an audio and video FPGA module, an audio and video self-test circuit, an audio and video CPU and an audio and video PHY;

[0053] The audio and video FPGA module receives the output signal of the video signal conditioning module through the video acquisition module; receives the audio signal conditioning module through the audio and video AD sampling module; the audio and video FPGA module is connected to the IRIG-B synchronization signal, PCIe bus and bus CPU; the audio and video CPU is connected to the LAN channel through the audio and video PHY;

[0054] The audio and video self-checking circuit self-checks the video signal conditioning module, the audio signal conditioning module and the audio and video CPU.

[0055] The cache record card is integrated on the main control module and uses the SATA bus to communicate with the main control module. The cache record card uses a reinforced FLASH hard disk and is connected to the outside world through an adapter board with a DMU connector.

[0056] The protection recorder adopts fixed storage, uses circular recording mode, and has a Gigabit Ethernet interface;

[0057] The cache record card is integrated on the main control module and uses the SATA bus to communicate with the main control module. The cache record card uses a reinforced FLASH hard disk and is connected to the outside world through an adapter board with a DMU connector.

[0058] The protection recorder adopts fixed storage, uses circular recording, and has a Gigabit Ethernet interface.

[0059] The collector includes a plurality of boxes; holes are formed on the boxes, and the boxes are separated and detachably connected; it includes one of the following solutions;

[0060] Solution 1: A connecting rod is passed through the through hole, a washer is sleeved on the connecting rod, and the washer is between the box bodies; a nut and a washer are arranged at the end of the connecting rod;

[0061] Solution 2: Transverse slots are respectively arranged on the upper and lower parts of the outer side walls on both sides of the box body, and transverse connecting blocks are arranged between the adjacent side walls of the box body. The two sides of the transverse connecting blocks are respectively inserted into the corresponding transverse slots, and slot holes are arranged on the transverse slots to connect the positioning bolts with threads; the lower ends of the positioning bolts are connected to the transverse connecting blocks;

[0062] Solution three, a connecting rod passes through the through hole, a washer is sleeved on the connecting rod, and the washer is between the box bodies; nuts and washers are arranged at the ends of the connecting rod; transverse slots are arranged horizontally at the upper and lower parts of the outer walls on both sides of the box body, respectively, and transverse connecting blocks are arranged between the adjacent box body side walls, and the two sides of the transverse connecting blocks are respectively inserted in the corresponding transverse slots, and slot holes are arranged on the transverse slots to connect the positioning bolts with threads; the lower end of the positioning bolt is connected to the transverse connecting block;

[0063] Solution four, transverse slots are respectively arranged horizontally on the upper and lower parts of the outer walls on both sides of the box body, and transverse connecting blocks are arranged between adjacent box body side walls. The two sides of the transverse connecting blocks are respectively inserted into the corresponding transverse slots, and slot holes are arranged on the transverse slots to connect the positioning bolts with threads; the lower end of the positioning bolt is connected to the transverse connecting block, and there are several alternative double-sided transverse slots, which are the same width as the box body. When a collector is removed, it is installed to that position through the double-sided transverse slots, thereby ensuring that the position of the overall module remains unchanged.

[0064] An airborne data comprehensive collection and recording method, using an airborne data comprehensive collection and recording system,

[0065] First, the onboard signal is sent to the integrated data collector; then, the collector stores the signal in a cache card and connects it to the unloading verifier; thirdly, the unloading verifier imports the data into the ground integrated analysis and processing system of the flight parameter data.

[0066] As a further improvement of the above technical solution:

[0067] In the work of the integrated data collector, the main control module performs the PCIe switch function to exchange data, performs the LAN switch function, performs maintenance functions, realizes the time synchronization function module, generates IRIG-B code output through RTC or GPS timing, realizes the hardware time stamping function through FPGA, exchanges data with the main control module through the PCIe bus, and realizes module self-check and software upgrade through LAN;

[0068] The voltage signal acquisition module collects voltage signals. The voltage signal input range is set by software. The hardware time stamping function is realized through FPGA. Data exchange with the main control module is realized through PCIe bus. Module self-check and software upgrade are realized through LAN.

[0069] The switch signal acquisition module performs the following steps: acquiring switch signals, acquiring frequency signals, performing hardware time stamping through FPGA, realizing data exchange with the main control module through the PCIe bus, and realizing module self-checking and software upgrade through LAN;

[0070] The vibration data acquisition module performs the following steps: collecting azimuth signals, collecting vibration signals, realizing hardware time stamping function through FPGA, realizing data exchange with the main control module through PCIe bus, and realizing module self-check and software online upgrade through LAN;

[0071] The bus acquisition module performs the following steps: acquiring RS422 bus, acquiring 8-way ARINC429 bus, acquiring dual-redundancy MIL-STD-1553B bus, acquiring dual-redundancy AFDX bus, realizing hardware time stamping function through FPGA, realizing data exchange with main control module through PCIe bus, and realizing module self-check and software online upgrade through LAN;

[0072] The audio and video data acquisition module performs the following steps: collecting video signals, collecting 4-channel audio signals, realizing hardware time stamping function through FPGA, realizing data exchange with the main control module through PCIe bus, and realizing module self-check and software online upgrade through LAN.

[0073] The invention has reasonable design, low cost, durability, safety and reliability, simple operation, time and labor saving, money saving, compact structure and convenient use. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] Figure 1 It is a system composition block diagram of the present invention.

[0075] Figure 2 It is a cross-linking block diagram of the internal modules of the collector of the present invention.

[0076] Figure 3 It is a physical link diagram of the PCIe bus of the present invention.

[0077] Figure 4 It is a relationship diagram of the PCIe bus specification of the present invention and bus frequency and encoding.

[0078] Figure 5 It is a peak bandwidth diagram of the PCIe bus of the present invention.

[0079] Figure 6 It is the IRIG B code diagram of the present invention.

[0080] Figure 7 It is a cross-link diagram of the internal maintenance bus of the collector of the present invention.

[0081] Figure 8 It is a principle block diagram of the voltage signal acquisition module of the present invention.

[0082] Fig. 9 It is a principle block diagram of the power conversion module of the present invention.

[0083] Fig.10 It is a principle block diagram of the main control module of the present invention.

[0084] Fig.11 It is a schematic diagram of the switch signal acquisition module of the present invention.

[0085] Fig.12 It is a principle block diagram of the vibration data acquisition module of the present invention.

[0086] Fig.13 It is a principle block diagram of the bus acquisition module of the present invention.

[0087] Fig.14 It is a principle block diagram of the audio and video data acquisition module of the present invention.

[0088] Fig.15 It is a principle block diagram of the cache record card of the present invention.

[0089] Fig.16 It is a table diagram of the flight parameter recording system of the present invention.

[0090] Fig.17 It is a table diagram of the comprehensive data acquisition system and vibration monitoring system under development of the present invention.

[0091] Fig.18 It is a schematic diagram of the collector structure of the present invention.

[0092] Fig.19 It is a schematic diagram of the collector connection structure of the present invention.

[0093] Among them: 1. box body; 2. through hole; 3. connecting rod; 4. transverse slot; 5. transverse connecting block; 6. positioning bolt; 7. slot hole. DETAILED DESCRIPTION

[0094] like Figure 1-19 , the integrated data acquisition and recording system of this embodiment includes an integrated data acquisition device, a cache recording card and a protection recorder located on the airborne part; the integrated data acquisition device is electrically connected to the protection recorder via Ethernet;

[0095] The integrated data collector is electrically connected to the onboard power supply; its input end is used to collect onboard signals on the airborne part, the onboard signals include switch signals, frequency signals, voltage signals, vibration signals, ARINC429 bus, RS422 bus, MIL-STD-155B bus, AFDX bus, audio signals and video signals; and the collected onboard signal data is packaged according to the IRIG-106 standard, and then sent to the cache record card and the protection recorder for recording;

[0096] The cache record card uses SATA bus to connect with the comprehensive data collector to complete the recording of all collected data;

[0097] The protection recorder uses a Gigabit Ethernet bus to connect with the integrated data collector to complete the recording of important data; important data includes data used for accident analysis;

[0098] On the ground, there are unloading verifiers and ground comprehensive analysis and processing systems for flight parameter data;

[0099] The unloading checker is respectively connected with the protection recorder and the comprehensive data collector through Ethernet; the output end of the unloading checker is electrically connected with the input end of the ground comprehensive analysis and processing system of the flight parameter data to import data;

[0100] The chassis structure of the integrated data logger adopts a backplane-free form, and the communication and power supply between modules are interconnected through inter-board connectors. This method brings challenges to the high-speed bus. The high-speed bus needs to pass through multiple connectors from the main control board to the farthest acquisition board, and there are certain difficulties in signal integrity.

[0101] One embodiment of the present invention uses long screws for mutual fixing, and this mode has better maintainability. Each module adopts a structural sealing design, and the EMC performance is relatively good.

[0102] The comprehensive data collector is based on a modular chassis, including a power module, a main control module with an integrated cache record card, a voltage signal acquisition module I, a voltage signal acquisition module II, a switch signal acquisition module, a vibration signal acquisition module, a bus acquisition module, and an audio and video acquisition module;

[0103] The main control module, voltage signal acquisition module I, voltage signal acquisition module II, switch signal acquisition module, vibration signal acquisition module, bus acquisition module, audio and video acquisition module have

[0104] BIT test capability module; BIT test capability module has three self-test modes, including PBIT power-on self-test, CBIT periodic self-test and IBIT maintenance self-test;

[0105] Fault logging module, each module provides fault logging means through the LAN bus, the fault information is stored in the non-volatile memory, and each fault record information must contain timestamp information;

[0106] Time synchronization module, each module uses IRIG-B code to achieve time synchronization, uses hardware time stamping, and the time synchronization accuracy is 100ns;

[0107] The power module, including the PCU power conversion unit, combines the normal power supply and the emergency power supply into a combined input, converting the DC 28V input voltage into a DC 24Vd baseboard voltage;

[0108] The voltage range of normal power supply is 22V~30V; the voltage range of emergency power supply is 18V~30V;

[0109] The PSA power supply has an output voltage monitoring and switch control module interconnected with the NIU module; working under the control of the NIU module, the output voltage monitoring and switch control module is responsible for connecting, disconnecting and monitoring the different power outputs of other modules in the rack;

[0110] NIU module, the CPU module and PHY module interconnected by internal MII signals, are used to manage the power supply in the rack and detect power distribution failures; the CPU module controls the PSA according to the information received from the system to provide power to the desired module; the PHY module communicates with the system through the LAN channel;

[0111] The PCU power conversion unit includes an energy storage capacitor, a holding module, a filter module, and a DC-DC module I; the input end of the filter module is connected to an external power supply, and the input end of the holding module is respectively connected to the output end of the energy storage capacitor and the filter module; the output end of the holding module is connected to the input end of the DC-DC module I; the DC-DC module I outputs a +24V voltage;

[0112] A voltage signal acquisition module I for inputting 32 voltage signals, a voltage signal acquisition module II for inputting 32 voltage signals, a switch signal acquisition module for inputting switch signals and frequency signals, a vibration signal acquisition module for inputting vibration signals, a bus acquisition module for inputting ARINC429, RS422, MIL-STD-1553B and / or AFDX signals, and an audio and video acquisition module for inputting audio signals and video signals complete the exchange of collected data with the main control module through the PCIe bus and complete the exchange of maintenance information with the main control module through the LAN bus, and the maintenance information includes self-test information, software upgrade, log information and parameter monitoring;

[0113] The main control module integrates FPGA integrated circuit, LAN switch chip, PCIe switch chip, CPU, synchronization signal module, and RTC chip; wherein the PCIe switch chip exchanges with the voltage signal acquisition module I, the voltage signal acquisition module II, the switch signal acquisition module, the vibration signal acquisition module, the bus acquisition module, and the audio and video acquisition module through the PCIe bus and the input end of the synchronization signal module through the IRIG-B channel;

[0114] The LAN switch chip interconnects the maintenance information with the offload verifier through the LAN; the maintenance log information is stored in the SATA hard disk integrated on the main control module; the LAN switch chip interconnects with the CPU through the LAN;

[0115] The PCIe switch chip exchanges with the CPU via the PCIe bus; the CPU is electrically connected to the cache card via the SATA channel;

[0116] The synchronization signal module receives the RTC timing signal from the RTC chip;

[0117] In the physical link of the PCIe bus, the PCIe link uses an end-to-end data transmission method, and both the sending end and the receiving end contain TX sending logic and RX receiving logic; the PCIe link includes multiple data paths Lane; in the data path Lane, it includes the sending link of the sending end and the sending link of the receiving end;

[0118] The transmitting link of the receiving end, that is, the receiving link of the receiving end, the TX component of the transmitting end and the RX component of the receiving end are connected using a set of differential signals;

[0119] The RX component of the transmitting end is connected to the TX component of the receiving end using another set of differential signals. This link is also called the receiving link of the transmitting end, that is, the sending link of the receiving end;

[0120] The PCIe link transmits data through differential signals, which include D+ and D-. The signal receiving end determines whether the sending end sends a logic "1" or a logic "0" by comparing the difference between the D+ and D- signals.

[0121] The main control module realizes the PCIe switch function: used for data exchange with other functional modules, with no less than 7 ports; realizes the LAN switch function: used for maintenance functions, with no less than 8 ports; 3) The CPU adopts the PowerPC series processor, and the operating system adopts Wind River's VxWorks; realizes one Gigabit Ethernet for interfacing with the protection recorder; realizes two SATA: one for interfacing with the cache record card, and the other for the onboard SATA hard disk, used to store log information, etc.; realizes the time synchronization function module: through RTC or GPS timing, 8 IRIG-B codes are generated and sent to other functional modules; the hardware time stamping function is realized through FPGA, and the time synchronization accuracy can reach 100ns; realizes data exchange with the main control module through the PCIe bus; realizes module self-test, software upgrade and other functions through LAN.

[0122] The electrical specification of high-speed differential signals requires a capacitor to be connected in series at the transmitting end for AC coupling. This capacitor is also called an AC coupling capacitor. Compared with single-ended signals, differential signals have stronger anti-interference capabilities because differential signals require "equal length", "equal width", "closeness" and are on the same layer when wiring. Therefore, external interference noise will be "same value" and "simultaneously" loaded on the D+ and D- signals, and the difference is 0 in an ideal case, which has little impact on the logic value of the signal. Therefore, differential signals can use higher bus frequencies.

[0123] In addition, using differential signals can effectively suppress electromagnetic interference (EMI). Since the differential signals D+ and D- are very close and have equal signal amplitudes and opposite polarities, the amplitudes of the coupled electromagnetic fields between these two wires and the ground wire are equal and will cancel each other out, so the differential signal has less electromagnetic interference to the outside world. Of course, the disadvantages of differential signals are also obvious. First, differential signals use two signals to transmit one bit of data; second, the wiring of differential signals is relatively strict.

[0124] Different PCIe bus specifications use different bus frequencies and different data encoding methods. PCIe bus V1.x and V2.0 specifications use 8 / 10b encoding in the physical layer, which means that 8 bits of valid data are contained in 10 bits on the PCIe link; while the V3.0 specification uses 128 / 130b encoding, which means that 128 bits of valid data are contained in 130 bits on the PCIe link. As shown in the chart, although the bus frequency used by the V3.0 specification is only 4GHz, its effective bandwidth is twice that of V2.x. Taking the V2.x specification as an example, the peak bandwidth that can be provided by PCIe links of different widths is explained.

[0125] The effective bandwidth provided by the PCIe bus is still much higher than that of the PCI bus. The PCIe bus also has its weaknesses, the most prominent of which is transmission delay. The PCIe link uses a serial method to transmit data, but inside the chip, the data bus is still parallel, so the PCIe link interface needs to perform serial-to-parallel conversion, which will produce a large delay. In addition, the data packets of the PCIe bus need to pass through the transaction layer, data link layer, and physical layer, and these data packets will also cause delays when passing through these layers.

[0126] Data transmission between physical links of the PCIe bus uses a clock-based synchronous transmission mechanism, but there is no clock line on the physical link. The receiving end of the PCIe bus contains a clock recovery module CDR (Clock Data Recovery), which extracts the receiving clock from the received message to perform synchronous data transmission.

[0127] The main control module receives GPS signals or uses the built-in RTC clock to form a unified synchronization signal, which is sent to other modules for use. The synchronization signal uses IRIG-B code.

[0128] Since the Global Positioning System (GPS) has become a globally shared and highly accurate time publishing system, GPS-based timing signals have been widely used in many fields. Currently, many manufacturers have launched synchronous timing devices based on GPS. These devices use a variety of methods to provide accurate time signals, such as pulse synchronization, serial port information synchronization, IRIG-B code information synchronization, etc., each of which has its own advantages and disadvantages. As an internationally universal time code, IRIG-B code has accurate timing, simplifies the timing loop, and contains complete absolute time scale information, so it has been widely used. This code has been widely used in missile, aerospace, telemetry and other time synchronization equipment, with high implementation accuracy and strong stability.

[0129] There are 4 parallel binary time code formats and 6 serial binary time code formats in IRIG code. The most commonly used one is the IRIG-B time code format, which sends time information at a frequency of once per second. It not only contains second pulse information, but also absolute time information including year, day, hour, minute, second, binary second day, etc.

[0130] As shown in the figure, it is a serial time code with one frame per second. The total width of each code element is 10ms. One time frame cycle includes 100 code elements, which is pulse width coding. Each code element has three code types: binary 0, 1 and position identifier. It is divided into 3 fields for coding: the first field is the year time (year, day, hour, minute, second), the second field is the control function field, and the third field is the time information of the day directly represented by the binary second symbol, which is circulated once every 24 hours. The "punctual" reference point of the code element is its pulse leading edge. The reference mark of the time frame consists of a position identification mark and an adjacent reference code element, and its pulse width is 8ms; there is a position identification mark for every 10 code elements, so there are 10 position identification marks in 1 second, namely: P1, P2, P3, ..., P9, P0, all of which are 8ms pulse width; PR is the frame reference point; the pulse widths of binary "1" and "0" are 5ms and 2ms respectively.

[0131] The voltage signal acquisition module comprises a voltage signal conditioning module, an AD sampling module, a self-checking circuit, an FPGA integrated circuit I, a CPU1, and a port PHYI;

[0132] A voltage signal conditioning module, whose input terminal inputs 32 voltage signals; an AD sampling module, whose input terminal is electrically connected to the output terminal of the voltage signal conditioning module, the output of the AD sampling module is electrically connected to the input terminal of the FPGA integrated circuit 1, and the FPGA integrated circuit 1 is electrically connected to the CPU1; a self-test circuit is electrically connected to the voltage signal conditioning module, the AD sampling module, the FPGA integrated circuit 1 and the CPU1 respectively;

[0133] FPGA integrated circuit I receives IRIG-B synchronization signal and cross-links PCIe bus;

[0134] CPU1 crosslinks LAN signals through port PHYI;

[0135] The functions of the voltage signal acquisition module are as follows: 1) Collect 32 voltage signals; 2) The voltage signal input range can be set by software; 3) The hardware time stamping function is realized through FPGA, and the time synchronization accuracy can reach 100ns; 4) Data exchange with the main control module is realized through the PCIe bus; 5) Module self-test, software upgrade and other functions are realized through LAN.

[0136] A switch signal acquisition module, including a switch signal conditioning module, a frequency signal conditioning module, a switch signal self-test circuit, a switch signal CPU, a switch signal CPU, a switch signal port and a switch signal integrated circuit;

[0137] A switch signal conditioning module, whose input end receives 96 switch signal inputs and whose output end is electrically connected to a switch signal integrated circuit;

[0138] A frequency signal conditioning module receives 6 frequency signal inputs and is interconnected with the switch signal conditioning module, and an output end thereof is electrically connected to the switch signal integrated circuit;

[0139] Switch signal integrated circuit, receiving IRIG-B synchronization signal, cross-linking PCle bus;

[0140] The switch signal CPU is interconnected with the switch signal integrated circuit and connected to the LAN port through the switch signal port;

[0141] Switch signal self-check circuit, self-check switch signal conditioning module, frequency signal conditioning module and switch signal CPU;

[0142] The switch signal acquisition module realizes the following functions: 1) Collect 96 switch signals; 2) Collect 6 frequency signals; 3) Realize hardware time stamping function through FPGA, and the time synchronization accuracy can reach 100ns; 4) Realize data exchange with the main control module through PCIe bus; 5) Realize module self-test, software upgrade and other functions through LAN.

[0143] Vibration data acquisition module, a vibration signal conditioning module for receiving vibration signals, an azimuth signal conditioning module for receiving azimuth signals, a vibration data AD sampling module, a vibration data self-checking circuit, a vibration circuit FPGA module, an oscillation data CPU and a vibration data PHY port;

[0144] The vibration signal conditioning module is connected to the input end of the vibration circuit FPGA module through the vibration data AD sampling module, and the output end of the azimuth signal conditioning module is connected to the input end of the vibration circuit FPGA module;

[0145] The oscillation data CPU is interconnected with the vibration circuit FPGA module and connected to the LAN channel through the vibration data PHY port; the vibration circuit FPGA module receives and receives the IRIG-B synchronization signal and interconnects the PCle bus; the vibration data self-check circuit self-checks the vibration signal conditioning module, the azimuth signal conditioning module, the vibration data AD sampling module and the oscillation data CPU;

[0146] The vibration data acquisition module realizes the following functions: 1) Collecting 4 azimuth signals; 2) Collecting 16 vibration signals; 3) Implementing hardware time stamping function through FPGA, with time synchronization accuracy up to 100ns; 4) Realizing data exchange with the main control module through PCIe bus; 5) Realizing module self-check, software online upgrade and other functions through LAN.

[0147] Bus acquisition module, including RS422 interface conditioning module, ARINC429 interface conditioning module, MIL-STD-1553B interface conditioning module, AFDX bus interface conditioning module, bus FPGA module, bus self-test circuit, bus CPU, bus PHY;

[0148] The input terminal of the RS422 interface conditioning module is connected to the RS422 bus, the ARINC429 interface conditioning module is connected to the ARINC429 bus, the MIL-STD-1553B interface conditioning module is connected to the MIL-STD-1553B bus, and the AFDX bus interface conditioning module is connected to the AFDX bus;

[0149] The output terminals of RS422 interface conditioning module, ARINC429 interface conditioning module, MIL-STD-1553B interface conditioning module and AFDX bus interface conditioning module are connected to the input terminal of bus FPGA module;

[0150] The bus FPGA module is connected to the IRIG-B synchronization signal, PCIe bus and bus CPU; the bus CPU is connected to the LAN channel through the bus PHY;

[0151] Bus self-test circuit self-tests RS422 interface conditioning module, ARINC429 interface conditioning module, MIL-STD-1553B interface conditioning module, AFDX bus interface conditioning module and bus CPU;

[0152] The functions implemented are as follows: 1) Acquisition of 8-way RS422 bus; 2) Acquisition of 8-way ARINC429 bus; 3) Acquisition of 1-way dual-redundancy MIL-STD-1553B bus; 4) Acquisition of 1-way dual-redundancy AFDX bus; 5) Hardware time stamping function is realized through FPGA, and the time synchronization accuracy can reach 100ns; 6) Data exchange with the main control module is realized through PCIe bus; 7) Module self-test, software online upgrade and other functions are realized through LAN.

[0153] The audio and video data acquisition module includes a video signal conditioning module for receiving video signals, an audio signal conditioning module for receiving audio signals, a video acquisition module, an audio and video AD sampling module, an audio and video self-test circuit, an audio and video FPGA module, an audio and video self-test circuit, an audio and video CPU and an audio and video PHY;

[0154] The audio and video FPGA module receives the output signal of the video signal conditioning module through the video acquisition module; receives the audio signal conditioning module through the audio and video AD sampling module; the audio and video FPGA module is connected to the IRIG-B synchronization signal, PCIe bus and bus CPU; the audio and video CPU is connected to the LAN channel through the audio and video PHY;

[0155] Audio and video self-test circuit self-tests video signal conditioning module, audio signal conditioning module and audio and video CPU;

[0156] The functions of the audio and video data acquisition module are as follows: 1) Collect 2-channel video signals; 2) Collect 4-channel audio signals; 3) Realize the hardware time stamping function through FPGA, and the time synchronization accuracy can reach 100ns; 4) Realize data exchange with the main control module through the PCIe bus; 5) Realize module self-test, software online upgrade and other functions through LAN.

[0157] The cache record card is integrated on the main control module and uses the SATA bus to communicate with the main control module. The cache record card uses a reinforced FLASH hard disk and is connected to the outside world through an adapter board with a DMU connector.

[0158] The memory capacity is not less than 256G. Since the cache record card often needs to unload the recorded data, the cache record card needs to be frequently plugged in and out, and the ordinary SATA connector does not have such durability. The SATA connector of the present invention is converted into an HJ30J-18 high-reliability rectangular connector through an adapter plate. The transmission speed of HJ30J-18 can reach 3Gbps, which meets the SATA signal transmission requirements. The FLASH hard disk uses aluminum alloy to reinforce the shell to improve the reliability of the product.

[0159] The protection recorder adopts fixed storage and circular recording mode, and has a Gigabit Ethernet interface. Its crash resistance complies with TSO-C123b, TSO-C124b or other relevant standards.

[0160] The software architecture of this system uses VxWorks6.6 or above as the operating system, and the data recording format adopts the IRIG-106 standard; the PCIe communication protocol realizes the data exchange between the internal acquisition module and the main control module of the collector, and the goal is plug-and-play.

[0161] The collector comprises a plurality of boxes 1; through holes 2 on the boxes 1, and the boxes 1 can be separated and detachably connected;

[0162] Solution 1: A connecting rod 3 passes through the through hole 2, a washer is sleeved on the connecting rod 3, and the washer is between the box bodies 1; nuts and washers are provided at the ends of the connecting rod 3; thus, a modular design is realized, and disassembly and maintenance are convenient.

[0163] Solution 2, transverse slots 4 are respectively arranged on the upper and lower parts of the outer walls on both sides of the box body 1, and transverse connecting blocks 5 are arranged between the adjacent side walls of the box body 1. The two sides of the transverse connecting blocks 5 are respectively inserted into the corresponding transverse slots 4, and slot holes 7 are arranged on the transverse slots 4 to be threadedly connected with positioning bolts 6; the lower end of the positioning bolts 6 is connected to the transverse connecting blocks 5. Solution 1 has the problem that when a certain collector module is damaged, it needs to be removed as a whole, and space for moving the side connecting rod needs to be reserved, which is inconvenient to use.

[0164] Solution 3: a connecting rod 3 is passed through the through hole 2, a washer is sleeved on the connecting rod 3, and the washer is between the box bodies 1; a nut and a washer are arranged at the end of the connecting rod 3; transverse slots 4 are arranged horizontally on the upper and lower parts of the outer walls on both sides of the box body 1, and a transverse connecting block 5 is arranged between the adjacent side walls of the box body 1. The two sides of the transverse connecting block 5 are respectively inserted in the corresponding transverse slots 4, and slot holes 7 are arranged on the transverse slots 4 to be threadedly connected with positioning bolts 6; the lower end of the positioning bolt 6 is connected to the transverse connecting block 5. When there is enough space and the stability requirement is relatively high, Solution 1 and Solution 2 are used in combination, so that the overall stability of the box body is enhanced while maintaining convenient disassembly.

[0165] Solution four, transverse slots 4 are respectively arranged transversely on the upper and lower parts of the outer side walls on both sides of the box body 1, and transverse connecting blocks 5 are arranged between the adjacent side walls of the box body 1. The two sides of the transverse connecting blocks 5 are respectively inserted into the corresponding transverse slots 4, and slot holes 7 are arranged on the transverse slots 4 to connect the positioning bolts 6 with threads; the lower end of the positioning bolt 6 is connected to the transverse connecting block 5, and there are also several alternative double-sided transverse slots, which are the same width as the box body 1. When a collector is removed, it is installed to that position through the double-sided transverse slots, thereby ensuring that the position of the overall module remains unchanged.

Claims

1. An airborne data comprehensive acquisition and recording system, characterized in that: It includes an integrated data collector, a cache record card and a protection recorder located on the airborne part; the integrated data collector is electrically connected to the protection recorder via Ethernet; The integrated data collector is electrically connected to the onboard power supply; its input end is used to collect onboard signals on the airborne part, the onboard signals include switch signals, frequency signals, voltage signals, vibration signals, ARINC429 bus, RS422 bus, MIL-STD-155B bus, AFDX bus, audio signals and video signals; and the collected onboard signal data is packaged according to the IRIG-106 standard, and then sent to the cache record card and the protection recorder for recording; The cache record card uses SATA bus to connect with the comprehensive data collector to complete the recording of all collected data; The protection recorder uses a Gigabit Ethernet bus to connect with the integrated data collector to complete the recording of important data; important data includes data used for accident analysis; On the ground, there are unloading verifiers and ground comprehensive analysis and processing systems for flight parameter data; The uninstall checker is respectively interconnected with the protection recorder and the comprehensive data collector via Ethernet; The output terminal of the unloading checker is electrically connected to the input terminal of the ground comprehensive analysis and processing system of the flight parameter data to import the data; The chassis structure of the integrated data collector adopts a backplane-free form, and the communication and power supply between modules are interconnected through inter-board connectors; The integrated data collector includes a power module, a main control module with an integrated cache record card, a voltage signal acquisition module I, a voltage signal acquisition module II, a switch signal acquisition module, a vibration signal acquisition module, a bus acquisition module, and an audio and video acquisition module; The main control module, voltage signal acquisition module I, voltage signal acquisition module II, switch signal acquisition module, vibration signal acquisition module, bus acquisition module, audio and video acquisition module have BIT test capability module; BIT test capability module has three self-test modes, including PBIT power-on self-test, CBIT periodic self-test and IBIT maintenance self-test; Fault logging module, each module provides fault logging means through the LAN bus, the fault information is stored in the non-volatile memory, and each fault record information must contain timestamp information; Time synchronization module, each module uses IRIG-B code to achieve time synchronization, uses hardware time stamping, and the time synchronization accuracy is 100ns; The cache record card is integrated on the main control module and uses the SATA bus to communicate with the main control module. The cache record card uses a reinforced FLASH hard disk and is connected to the outside world through an adapter board with a DMU connector. The protection recorder adopts fixed storage, uses circular recording mode, and has a Gigabit Ethernet interface; The cache record card is integrated on the main control module and uses the SATA bus to communicate with the main control module. The cache record card uses a reinforced FLASH hard disk and is connected to the outside world through an adapter board with a DMU connector. The protection recorder adopts fixed storage, uses circular recording, and has a Gigabit Ethernet interface.

2. The airborne data comprehensive acquisition and recording system according to claim 1, characterized in that: In the integrated data logger, the power module, including the PCU power conversion unit, combines the normal power supply and the emergency power supply into a combined input, converting the DC 28V input voltage into a DC 24Vd baseboard voltage; The voltage range of normal power supply is 22V~30V; the voltage range of emergency power supply is 18V~30V; The PSA power supply has an output voltage monitoring and switch control module interconnected with the NIU module; working under the control of the NIU module, the output voltage monitoring and switch control module is responsible for connecting, disconnecting and monitoring the different power outputs of other modules in the rack; The NIU module, which connects the CPU module and the PHY module through internal MII signals, is used to manage the power supply in the rack and detect power distribution failures; the CPU module controls the PSA according to the information received from the system to provide power to the desired module; the PHY module communicates with the system through the LAN channel.

3. The airborne data comprehensive acquisition and recording system according to claim 2, characterized in that: The PCU power conversion unit includes an energy storage capacitor, a holding module, a filter module, and a DC-DC module I; the input end of the filter module is connected to an external power supply, and the input end of the holding module is respectively connected to the output end of the energy storage capacitor and the filter module; the output end of the holding module is connected to the input end of the DC-DC module I; the DC-DC module I outputs a +24V voltage; A voltage signal acquisition module I for inputting 32 voltage signals, a voltage signal acquisition module II for inputting 32 voltage signals, a switch signal acquisition module for inputting switch signals and frequency signals, a vibration signal acquisition module for inputting vibration signals, a bus acquisition module for inputting ARINC429, RS422, MIL-STD-1553B and / or AFDX signals, and an audio and video acquisition module for inputting audio signals and video signals complete the exchange of collected data with the main control module through the PCIe bus and complete the exchange of maintenance information with the main control module through the LAN bus, and the maintenance information includes self-test information, software upgrade, log information and parameter monitoring; The main control module integrates FPGA integrated circuit, LAN switch chip, PCIe switch chip, CPU, synchronization signal module, and RTC chip; wherein the PCIe switch chip exchanges with the voltage signal acquisition module I, the voltage signal acquisition module II, the switch signal acquisition module, the vibration signal acquisition module, the bus acquisition module, and the audio and video acquisition module through the PCIe bus and the input end of the synchronization signal module through the IRIG-B channel; The LAN switch chip interconnects the maintenance information with the offload verifier through the LAN; the maintenance log information is stored in the SATA hard disk integrated on the main control module; the LAN switch chip interconnects with the CPU through the LAN; The PCIe switch chip exchanges with the CPU via the PCIe bus; the CPU is electrically connected to the cache card via the SATA channel; The synchronization signal module receives the RTC timing signal from the RTC chip; In the physical link of the PCIe bus, the PCIe link uses an end-to-end data transmission method, and both the sending end and the receiving end contain TX sending logic and RX receiving logic; the PCIe link includes multiple data paths Lane; in the data path Lane, it includes the sending link of the sending end and the sending link of the receiving end; The transmitting link of the receiving end, that is, the receiving link of the receiving end, the TX component of the transmitting end and the RX component of the receiving end are connected using a set of differential signals; The RX component of the transmitting end is connected to the TX component of the receiving end using another set of differential signals. This link is also called the receiving link of the transmitting end, that is, the sending link of the receiving end; The PCIe link transmits data via differential signals, which include D+ and D-. The signal receiving end determines whether the sending end sends a logic 1 or a logic 0 by comparing the difference between the D+ and D- signals. The voltage signal acquisition module comprises a voltage signal conditioning module, an AD sampling module, a self-checking circuit, an FPGA integrated circuit I, a CPU1, and a port PHYI; A voltage signal conditioning module, whose input terminal inputs 32 voltage signals; an AD sampling module, whose input terminal is electrically connected to the output terminal of the voltage signal conditioning module, the output of the AD sampling module is electrically connected to the input terminal of the FPGA integrated circuit 1, and the FPGA integrated circuit 1 is electrically connected to the CPU1; a self-test circuit is electrically connected to the voltage signal conditioning module, the AD sampling module, the FPGA integrated circuit 1 and the CPU1 respectively; FPGA integrated circuit I receives IRIG-B synchronization signal and cross-links PCIe bus; CPU1 crosslinks LAN signals through port PHYI; A switch signal acquisition module, including a switch signal conditioning module, a frequency signal conditioning module, a switch signal self-test circuit, a switch signal CPU, a switch signal port and a switch signal integrated circuit; A switch signal conditioning module, whose input end receives 96 switch signal inputs and whose output end is electrically connected to a switch signal integrated circuit; The frequency signal conditioning module receives 6-channel frequency signal inputs and is interconnected with the switch signal conditioning module, and its output end is electrically connected to the switch signal integrated circuit.

4. The airborne data comprehensive acquisition and recording system according to claim 3, characterized in that: Switch signal integrated circuit, receiving IRIG-B synchronization signal, cross-linking PCle bus; The switch signal CPU is interconnected with the switch signal integrated circuit and connected to the LAN port through the switch signal port; Switch signal self-check circuit, self-check switch signal conditioning module, frequency signal conditioning module and switch signal CPU; Vibration data acquisition module, a vibration signal conditioning module for receiving vibration signals, an azimuth signal conditioning module for receiving azimuth signals, a vibration data AD sampling module, a vibration data self-checking circuit, a vibration circuit FPGA module, an oscillation data CPU and a vibration data PHY port; The vibration signal conditioning module is connected to the input end of the vibration circuit FPGA module through the vibration data AD sampling module, and the output end of the azimuth signal conditioning module is connected to the input end of the vibration circuit FPGA module; The oscillation data CPU is interconnected with the vibration circuit FPGA module and connected to the LAN channel through the vibration data PHY port; the vibration circuit FPGA module receives and receives the IRIG-B synchronization signal and interconnects the PCle bus; the vibration data self-check circuit self-checks the vibration signal conditioning module, the azimuth signal conditioning module, the vibration data AD sampling module and the oscillation data CPU.

5. The airborne data comprehensive acquisition and recording system according to claim 4, characterized in that: Bus acquisition module, including RS422 interface conditioning module, ARINC429 interface conditioning module, MIL-STD-1553B interface conditioning module, AFDX bus interface conditioning module, bus FPGA module, bus self-test circuit, bus CPU, bus PHY; The input terminal of the RS422 interface conditioning module is connected to the RS422 bus, the ARINC429 interface conditioning module is connected to the ARINC429 bus, the MIL-STD-1553B interface conditioning module is connected to the MIL-STD-1553B bus, and the AFDX bus interface conditioning module is connected to the AFDX bus; The output terminals of RS422 interface conditioning module, ARINC429 interface conditioning module, MIL-STD-1553B interface conditioning module and AFDX bus interface conditioning module are connected to the input terminal of bus FPGA module; The bus FPGA module is connected to the IRIG-B synchronization signal, PCIe bus and bus CPU; the bus CPU is connected to the LAN channel through the bus PHY; Bus self-test circuit self-tests RS422 interface conditioning module, ARINC429 interface conditioning module, MIL-STD-1553B interface conditioning module, AFDX bus interface conditioning module and bus CPU; The audio and video data acquisition module includes a video signal conditioning module for receiving video signals, an audio signal conditioning module for receiving audio signals, a video acquisition module, an audio and video AD sampling module, an audio and video self-test circuit, an audio and video FPGA module, an audio and video self-test circuit, an audio and video CPU and an audio and video PHY; The audio and video FPGA module receives the output signal of the video signal conditioning module through the video acquisition module; and receives the audio signal conditioning module through the audio and video AD sampling module; The audio and video FPGA module is connected to the IRIG-B synchronization signal, PCIe bus and bus CPU; the audio and video CPU is connected to the LAN channel through the audio and video PHY; The audio and video self-checking circuit self-checks the video signal conditioning module, the audio signal conditioning module and the audio and video CPU.

6. The airborne data comprehensive acquisition and recording system according to claim 1, characterized in that: The collector includes a plurality of boxes; holes are formed on the boxes, and the boxes are separated and detachably connected; it includes one of the following solutions; Solution 1: A connecting rod passes through the through hole, a washer is sleeved on the connecting rod, and the washer is between the box bodies; a nut and a washer are arranged at the end of the connecting rod; Solution 2: Transverse slots are respectively arranged on the upper and lower parts of the outer side walls on both sides of the box body, and transverse connecting blocks are arranged between the adjacent side walls of the box body. The two sides of the transverse connecting blocks are respectively inserted into the corresponding transverse slots, and slot holes are arranged on the transverse slots to connect the positioning bolts with threads; the lower ends of the positioning bolts are connected to the transverse connecting blocks; Solution three, a connecting rod passes through the through hole, a washer is sleeved on the connecting rod, and the washer is between the box bodies; nuts and washers are arranged at the ends of the connecting rod; transverse slots are arranged horizontally at the upper and lower parts of the outer walls on both sides of the box body, respectively, and transverse connecting blocks are arranged between the adjacent box body side walls, and the two sides of the transverse connecting blocks are respectively inserted in the corresponding transverse slots, and slot holes are arranged on the transverse slots to connect the positioning bolts with threads; the lower end of the positioning bolt is connected to the transverse connecting block; Solution four, transverse slots are respectively arranged horizontally on the upper and lower parts of the outer walls on both sides of the box body, and transverse connecting blocks are arranged between adjacent box body side walls. The two sides of the transverse connecting blocks are respectively inserted into the corresponding transverse slots, and slot holes are arranged on the transverse slots to connect the positioning bolts with threads; the lower end of the positioning bolt is connected to the transverse connecting block, and there are several alternative double-sided transverse slots, which are the same width as the box body. When a collector is removed, it is installed to that position through the double-sided transverse slots, thereby ensuring that the position of the overall module remains unchanged.

7. A method for comprehensive collection and recording of airborne data, characterized in that: With the aid of the airborne data comprehensive acquisition and recording system described in claim 1, First, the onboard signal is sent to the integrated data collector; then, the collector stores the signal in a cache card and connects it to the unloading verifier; thirdly, the unloading verifier imports the data into the ground integrated analysis and processing system of the flight parameter data.

8. The method for comprehensive airborne data collection and recording according to claim 7, characterized in that: In the work of the integrated data collector, the main control module performs the PCIe switch function to exchange data, performs the LAN switch function, performs maintenance functions, realizes the time synchronization function module, generates IRIG-B code output through RTC or GPS timing, realizes the hardware time stamping function through FPGA, exchanges data with the main control module through the PCIe bus, and realizes module self-check and software upgrade through LAN; The voltage signal acquisition module collects voltage signals. The voltage signal input range is set by software. The hardware time stamping function is realized through FPGA. Data exchange with the main control module is realized through PCIe bus. Module self-check and software upgrade are realized through LAN. The switch signal acquisition module performs the following steps: acquiring switch signals, acquiring frequency signals, performing hardware time stamping through FPGA, realizing data exchange with the main control module through the PCIe bus, and realizing module self-checking and software upgrade through LAN; The vibration data acquisition module performs the following steps: collecting azimuth signals, collecting vibration signals, implementing hardware time stamping function through FPGA, implementing data exchange with the main control module through PCIe bus, and implementing module self-check and software online upgrade through LAN; The bus acquisition module performs the following steps: acquiring RS422 bus, acquiring 8-way ARINC429 bus, acquiring dual-redundancy MIL-STD-1553B bus, acquiring dual-redundancy AFDX bus, realizing hardware time stamping function through FPGA, realizing data exchange with the main control module through PCIe bus, and realizing module self-check and software online upgrade through LAN; The audio and video data acquisition module performs the following steps: collecting video signals, collecting 4-channel audio signals, realizing hardware time stamping function through FPGA, realizing data exchange with the main control module through PCIe bus, and realizing module self-check and software online upgrade through LAN.

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