Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate having a high-voltage device region and a medium-voltage device region; forming a plurality of shallow trench isolation structures; etching the substrate of the high-voltage device region to form a first trench; forming a first gate oxide structure in the first trench and forming a second gate oxide structure on the surface of the substrate of the medium-voltage device region. The present invention also provides a semiconductor device. The present application reduces the height of the first gate oxide structure of the high-voltage device region by forming a first gate oxide structure in the substrate of the high-voltage device region, improves the height uniformity of the dummy poly formed above the first gate oxide structure subsequently, avoids the situation where the dummy poly of the high-voltage device region is excessively mis-polished in the subsequent ILD0CMP process, and lays a foundation for the smooth filling of the subsequent metal gate.

Description

Technical Field

[0001] The present application relates to the technical field of MOS devices, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] 28nm HV MOS devices have the characteristics of high voltage, high current and strong driving capability. Among HV MOS devices, MV (medium voltage) devices and HV (high voltage) devices have operating voltages of 8V and 32V respectively. Therefore, high voltage devices need to use thicker gate oxides, deeper junction depths and longer channel lengths. The huge difference in operating voltages of different devices leads to greatly different gate oxide thicknesses of devices. The gate oxide of high voltage devices is at least 100% thicker than that of medium voltage devices.

[0003] In HV MOS devices, the more common metal gate manufacturing process is usually to first make a pseudo gate (dummy poly) on the gate oxide layer, and then remove the pseudo gate through the ILD0 CMP (interlayer insulation chemical mechanical polishing) process, dry and / or wet etching process in the subsequent process to leave a groove, and finally fill the original groove with metal material to finally form a metal gate. Among them, when performing the ILD0 CMP (interlayer insulation chemical mechanical polishing) process, because the thickness of the gate oxide layer of the high-voltage device is greater than the thickness of the gate oxide layer of the medium-voltage device, and because all devices (medium voltage and high voltage) on the HVMOS device are polished by ILD0 CMP at the same time, the pseudo gate above the gate oxide layer of the high-voltage device is excessively mistakenly polished because it is higher than the pseudo gate of the medium-voltage device, which will affect the formation of the metal gate in the high-voltage device. Even in extreme cases, after the ILD0 CMP process, the pseudo gate of the high-voltage device is completely polished, thereby affecting the filling of the metal material, that is, affecting the formation of the metal gate of the high-voltage device, which is easy to cause the performance failure of the device.

[0004] In addition, since the thermal oxidation growth process for forming the gate oxide layer has certain limitations, void defects exist in the gate oxide layer at the corners of the junction between the AA and STI (shallow trench isolation structure) of the medium voltage device, thereby reducing the reliability of the medium voltage device. Summary of the invention

[0005] The present application provides a semiconductor device and a manufacturing method thereof, which can solve the problem that the height of the gate oxide layer of the high-voltage device is too high and the gate oxide layer of the medium-voltage device has defects in the HV MOS device.

[0006] On the one hand, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0007] Providing a substrate having a high voltage device region and a medium voltage device region;

[0008] forming a plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are located at the junction of the high voltage device area and the medium voltage device area and are spaced apart and distributed in the high voltage device area and the medium voltage device area;

[0009] Etching the substrate between two adjacent shallow trench isolation structures in the high-voltage device region to form a first trench;

[0010] forming a first gate oxide structure, wherein the first gate oxide structure fills the first trench; and

[0011] A second gate oxide structure is formed, wherein the second gate oxide structure is located on the surface of the substrate between two adjacent shallow trench isolation structures in the medium voltage device region.

[0012] Optionally, in the method for manufacturing the semiconductor device, two adjacent shallow trench isolation structures in the high-voltage device region and a substrate between the shallow trench isolation structures are etched to form a first trench.

[0013] Optionally, in the method for manufacturing the semiconductor device, the width of the shallow trench isolation structure opened by etching is

[0014] Optionally, in the method for manufacturing the semiconductor device, the etching thickness is The shallow trench isolation structure is etched to a thickness of of the substrate to form a stepped first trench.

[0015] Optionally, in the method for manufacturing the semiconductor device, the step of forming the second gate oxide structure includes:

[0016] forming a mask layer, wherein the mask layer covers the shallow trench isolation structure, the first gate oxide structure and a portion of the substrate;

[0017] Etching the mask layer on two adjacent shallow trench isolation structures in the medium voltage device area to form a second trench in the mask layer;

[0018] forming a first gate oxide layer by a thermal oxidation process, wherein the first gate oxide layer covers a bottom wall of the second trench;

[0019] Forming a second gate oxide layer by an ALD process, wherein the second gate oxide layer covers the first gate oxide layer, the sidewall of the second trench and the mask layer;

[0020] removing the mask layer and the second gate oxide layer on the sidewalls of the second trench; and,

[0021] The remaining mask layer is removed.

[0022] Optionally, in the method for manufacturing the semiconductor device, the thickness of the first gate oxide layer is

[0023] Optionally, in the method for manufacturing the semiconductor device, the thickness of the second gate oxide layer is

[0024] Optionally, in the method for manufacturing the semiconductor device, a thermal oxidation process is used to form the first gate oxide structure.

[0025] Optionally, in the method for manufacturing the semiconductor device, the thickness of the first gate oxide structure is

[0026] On the other hand, an embodiment of the present application further provides a semiconductor device, including:

[0027] A substrate having a high voltage device region and a medium voltage device region;

[0028] A plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are located at the junction of the high voltage device area and the medium voltage device area and are spaced apart in the high voltage device area and the medium voltage device area, wherein a first trench is formed in the substrate between two adjacent shallow trench isolation structures in the high voltage device area;

[0029] a first gate oxide structure, wherein the first gate oxide structure fills the first trench; and

[0030] A second gate oxide structure, wherein the second gate oxide structure is located on the surface of the substrate between two adjacent shallow trench isolation structures in the medium voltage device region.

[0031] The technical solution of this application has at least the following advantages:

[0032] The present application forms a first gate oxide structure in the substrate of the high-voltage device area to reduce the height of the first gate oxide structure in the high-voltage device area, improves the height uniformity of the dummy poly subsequently formed above the first gate oxide structure, avoids the situation where the dummy poly in the high-voltage device area is excessively mis-polished in the subsequent ILD0 CMP process, lays a foundation for the smooth filling of the subsequent metal gate, and thus improves the performance and reliability of the high-voltage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1-Figure 9 is a schematic diagram of a semiconductor structure in each process step of manufacturing a semiconductor device according to an embodiment of the present invention;

[0035] 100 - substrate, 101 - shallow trench isolation structure, 102 - first trench, 103 - second trench;

[0036] 10-high voltage device region, 11-first gate oxide structure, 12-mask layer;

[0037] 20 - medium voltage device region, 21 - second gate oxide structure, 211 - first gate oxide layer, 212 - second gate oxide layer. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0040] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0041] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0042] An embodiment of the present application provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device comprising:

[0043] The first step: providing a substrate having a high voltage device region and a medium voltage device region;

[0044] Step 2: forming a plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are located at the junction of the high voltage device area and the medium voltage device area and are spaced apart and distributed in the high voltage device area and the medium voltage device area;

[0045] Step three: etching the substrate between two adjacent shallow trench isolation structures in the high-voltage device area to form a first trench;

[0046] Step 4: forming a first gate oxide structure, wherein the gate oxide structure fills the first trench;

[0047] Step 5: forming a second gate oxide structure, wherein the second gate oxide structure is located on the surface of the substrate between two adjacent shallow trench isolation structures in the medium voltage device region.

[0048] Specifically, refer to Figure 1-Figure 9 , Figure 1-Figure 9 It is a schematic diagram of a semiconductor structure in each process step of manufacturing a semiconductor device according to an embodiment of the present invention.

[0049] First, refer to Figure 1 , a substrate 100 having a high voltage device region 10 and a medium voltage device region 20 is provided. Specifically, the substrate 100 may be one of single crystal silicon, polycrystalline silicon, and amorphous silicon, the substrate 100 may also be gallium arsenide, silicon gallium compound, etc., the substrate 100 may also have a silicon on insulating layer or an epitaxial layer on silicon structure; the substrate 100 may also be other semiconductor materials, which are not listed here one by one. The high voltage device region 10 and the medium voltage device region 20 are on the same wafer and are adjacent to each other.

[0050] Then, continue to refer to Figure 1, forming a plurality of shallow trench isolation structures 101, wherein the shallow trench isolation structures 101 are located at the junction of the high voltage device area 10 and the medium voltage device area 20 and are spaced apart in the high voltage device area 10 and the medium voltage device area 20. Specifically, the shallow trench isolation structures 101 located at the junction of the high voltage device area 10 and the medium voltage device area 20 isolate the high voltage device area 10 from the medium voltage device area 20. An AA (active area) will be subsequently formed in the substrate between two adjacent shallow trench isolation structures 101 in the high voltage device area 10, and similarly, an AA (active area) will be subsequently formed in the substrate between two adjacent shallow trench isolation structures 101 in the medium voltage device area 20. This embodiment only focuses on the process of forming gate oxide structures in each AA region.

[0051] Next, refer to Figure 2 , etching the substrate 100 between two adjacent shallow trench isolation structures 101 in the high-voltage device area 10 to form a first trench 102. Specifically, when opening the area in the high-voltage device area 10, a hard mask layer is formed on the surface of the entire substrate 100, and then the high-voltage device area 10 is subjected to a photolithography process and an etching process. This can protect other substrates 10 and shallow trench isolation structures 101 that do not need to be etched, and prevent the substrates 10 and shallow trench isolation structures 101 that do not need to be etched from being mistakenly etched. Furthermore, in this embodiment, while etching the substrate 100 between the shallow trench isolation structures 101 in the high-voltage device area 10, the edges of the two adjacent shallow trench isolation structures 101 can also be etched, that is, the first trench extends in width 102 to the shallow trench isolation structures 101 on both sides thereof. Preferably, the width dimensions of the shallow trench isolation structures 101 opened by etching can be Furthermore, the present embodiment can etch a thickness of The shallow trench isolation structure 101 is etched to a thickness of The substrate 100 is formed to form the first trench 102 in a stepped manner.

[0052] For further reference, Figure 3 , forming a first gate oxide structure 11, the first gate oxide structure 11 fills the first trench 102. Specifically, the first gate oxide structure 11 is formed by a thermal oxidation process. Due to the particularity of the thermal oxidation process, a portion of the substrate 100 at the bottom wall of the first trench 102 will also be oxidized to become a part of the first gate oxide structure 11, and the ratio of the depth of the first trench 102 to the thickness of the first gate oxide structure 11 finally formed is about 0.54:1. The thickness of the substrate 100 etched in the previous step is That is, the depth of the first groove 102 is The thickness of the first gate oxide structure 11 finally formed is about The upper surface of the first gate oxide structure 11 finally formed is flush with the upper surfaces of the two adjacent shallow trench isolation structures 101. The present application forms a deeply buried first gate oxide structure 11 in the substrate 100 of the high-voltage device area 10 to reduce the height of the first gate oxide structure 11 of the high-voltage device area 10, improve the height uniformity of the dummypoly subsequently formed above the first gate oxide structure 11, avoid the situation where the dummypoly of the high-voltage device area 10 is excessively mis-polished in the subsequent ILD0 CMP process, lay a foundation for the smooth filling of the subsequent metal gate, and thus improve the performance and reliability of the high-voltage device.

[0053] Finally, reference Figure 4-Figure 9 , forming a second gate oxide structure 21 , wherein the second gate oxide structure 21 is located on the substrate surface between two adjacent shallow trench isolation structures 101 in the medium voltage device region 20 .

[0054] Specifically, the steps of forming the second gate oxide structure 21 include:

[0055] Step 1: Reference Figure 4 , forming a mask layer 12, the mask layer 12 covers the shallow trench isolation structure 101, the first gate oxide structure 11 and a portion of the substrate 100. Specifically, the mask layer 12 can be silicon nitride. In this embodiment, a photoresist is coated on the mask layer 12, and then the photoresist on the mask layer 12 is opened by a photolithography process to form a defined photolithography window.

[0056] Step 2: Reference Figure 5 , etching the mask layer 12 on the two adjacent shallow trench isolation structures 101 in the medium voltage device area 20 to form a second trench 103 in the mask layer. Specifically, according to the photolithography window defined in the previous step (first step), a dry etching process is performed on the mask layer 12 on the two adjacent shallow trench isolation structures 101 in the medium voltage device area 20, and the mask layer 12 under the defined photolithography window is etched away to expose the substrate 100 between the two adjacent shallow trench isolation structures 101 in the medium voltage device area 20.

[0057] Step 3: Reference Figure 6 The first gate oxide layer 211 is formed by a thermal oxidation process, and the first gate oxide layer 211 covers the bottom wall of the second trench 103. Specifically, due to the particularity of the thermal oxidation process, the first gate oxide layer 211 is only formed on the bottom wall of the second trench 103. The thickness of the grown first gate oxide layer 211 can be

[0058] Step 4: Reference Figure 7 A second gate oxide layer 212 is formed by an ALD (atomic layer deposition) process, and the second gate oxide layer 212 covers the first gate oxide layer 211, the sidewall of the second trench 103 and the mask layer 12. Specifically, the thickness of the second gate oxide layer 212 can be

[0059] Step 5: Reference Figure 8 , removing the mask layer 12 and the second gate oxide layer 212 on the sidewalls of the second trench 103. Specifically, the mask layer 12 and the second gate oxide layer 212 on the sidewalls of the second trench 103 may be removed by a wet etching process.

[0060] refer to Fig. 9 , remove the remaining mask layer 12. Specifically, the remaining mask layer 12 can be removed by using dry etching, wet etching or wet cleaning process.

[0061] Due to the particularity of the thermal oxidation process, voids may appear at the corners of the interface between the first gate oxide layer 211 and the shallow trench isolation structure 101 (close to both sides of the lower surface of the first gate oxide layer 211), so that the coverage ratio of the first gate oxide layer 211 at the corners is lower than the coverage ratio of the first gate oxide layer 211 in other areas of the second trench 103. Therefore, after the first gate oxide layer 211 is formed on the substrate surface of the medium voltage device area 20 by the thermal oxidation process, the second gate oxide layer 212 is formed by the ALD process. Because the second gate oxide layer 212 is grown by the ALD process, the second gate oxide layer 212 can fill and cover the void defects at the corners of the first gate oxide layer 211. The second gate oxide structure 21 finally formed by the two processes of the present application is complete in structure, which makes up for the void defects at the corners of the first gate oxide layer 211. The second gate oxide structure 21 with a complete structure is not easily broken down by high voltage, which improves the high voltage resistance of the second gate oxide structure 21, thereby improving the performance and reliability of the medium voltage device.

[0062] Based on the same inventive concept, an embodiment of the present application further provides a semiconductor device, comprising: a substrate 100, a plurality of shallow trench isolation structures 101, a first gate oxide structure 11, and a second gate oxide structure 21, wherein the substrate 100 has a high voltage device region 10 and a medium voltage device region 20. The shallow trench isolation structure 101 is located at the junction of the high voltage device region 10 and the medium voltage device region 20 and is spaced apart in the high voltage device region 10 and the medium voltage device region 20, wherein a first trench 102 is formed in the substrate 100 between two adjacent shallow trench isolation structures 101 in the high voltage device region 10. The first gate oxide structure 11 fills the first trench 102. The second gate oxide structure 21 is located on the surface of the substrate 100 between two adjacent shallow trench isolation structures 101 in the medium voltage device region 20.

[0063] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate having a high voltage device region and a medium voltage device region; forming a plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are located at the junction of the high voltage device area and the medium voltage device area and are spaced apart and distributed in the high voltage device area and the medium voltage device area; Etching the substrate between two adjacent shallow trench isolation structures in the high-voltage device region to form a first trench; forming a first gate oxide structure, wherein the first gate oxide structure fills the first trench, and an upper surface of the first gate oxide structure is flush with upper surfaces of two adjacent shallow trench isolation structures; and A second gate oxide structure is formed, wherein the second gate oxide structure is located on the surface of the substrate between two adjacent shallow trench isolation structures in the medium voltage device region.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Two adjacent shallow trench isolation structures in the high-voltage device region and a substrate between the shallow trench isolation structures are etched to form a first trench.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The width of the shallow trench isolation structure opened by etching is 4. The method for manufacturing a semiconductor device according to claim 2, wherein: The etching thickness is The shallow trench isolation structure is etched to a thickness of of the substrate to form a stepped first trench.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming the second gate oxide structure includes: forming a mask layer, wherein the mask layer covers the shallow trench isolation structure, the first gate oxide structure and a portion of the substrate; Etching the mask layer on two adjacent shallow trench isolation structures in the medium voltage device area to form a second trench in the mask layer; forming a first gate oxide layer by a thermal oxidation process, wherein the first gate oxide layer covers a bottom wall of the second trench; Forming a second gate oxide layer by an ALD process, wherein the second gate oxide layer covers the first gate oxide layer, the sidewall of the second trench and the mask layer; removing the mask layer and the second gate oxide layer on the sidewalls of the second trench; and, The remaining mask layer is removed.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The thickness of the first gate oxide layer is 7. The method for manufacturing a semiconductor device according to claim 5, wherein: The thickness of the second gate oxide layer is 8. The method for manufacturing a semiconductor device according to claim 1, wherein: The first gate oxide structure is formed by a thermal oxidation process.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness of the first gate oxide structure is 10. A semiconductor device, characterized in that: include: A substrate having a high voltage device region and a medium voltage device region; A plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are located at the junction of the high voltage device area and the medium voltage device area and are spaced apart in the high voltage device area and the medium voltage device area, wherein a first trench is formed in the substrate between two adjacent shallow trench isolation structures in the high voltage device area; A first gate oxide structure, wherein the first gate oxide structure fills the first trench, and an upper surface of the first gate oxide structure is flush with upper surfaces of two adjacent shallow trench isolation structures; and A second gate oxide structure, wherein the second gate oxide structure is located on the surface of the substrate between two adjacent shallow trench isolation structures in the medium voltage device region.

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