Semiconductor structure and method for manufacturing the same

Abstract

The present invention relates to a semiconductor structure and a preparation method thereof. In the preparation method of the semiconductor structure, a first support layer covering the first structure is formed on the surface of the first structure, and a second support layer covering the first support is formed on the surface of the first support layer. After removing the first support layer and the second support layer on the upper surface of the first structure, and the first support layer between the first structure and the second support layer, the top surface of the second support layer is higher than the top surface of the first structure. Among them, the first support layer and the second support layer can provide support for the first structure during the preparation process of the semiconductor structure, ensuring that the structure retained after etching the first structure will not be distorted or tilted. Since the top surface of the second support layer is higher than the top surface of the first structure, a mask layer can be formed on the upper surface of the first structure in a horizontal direction with the second support layer as the center in the subsequent process, so as to achieve self-alignment during the etching process of the first structure and improve the preparation accuracy of the semiconductor structure.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. With the development of semiconductor technology, the manufacturing process of DRAM is continuously miniaturized, so the bit line (BL) in DRAM is also miniaturized.

[0003] However, after bit line etching, the thin layer of bit line wall is prone to distortion or tilt, resulting in the sidewall spacer subsequently deposited on the sidewall of the bit line not being able to wrap the sidewall well, and the conductor between the transistor and the capacitor not being able to be filled well, affecting the performance of the DRAM. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a method for preparing the same in order to solve the problem in the prior art that the DRAM performance is affected by the distortion or tilt of the bit line wall.

[0005] The present application provides a method for preparing a semiconductor structure, comprising:

[0006] Providing a substrate, and forming a first structure on the substrate;

[0007] forming a first supporting layer, wherein the first supporting layer covers the first structure;

[0008] forming a second supporting layer, wherein the second supporting layer covers the first supporting layer;

[0009] The first supporting layer and the second supporting layer on the upper surface of the first structure and the first supporting layer between the first structure and the second supporting layer are removed, wherein a top surface of the second supporting layer is higher than a top surface of the first structure.

[0010] In one embodiment, forming a first structure on the substrate includes:

[0011] forming a double bit line to-be-etched structure on the upper surface of the substrate;

[0012] A first sidewall structure is formed on the sidewall of the double bit line structure to be etched, and the double bit line structure to be etched and the first sidewall structure together constitute the first structure.

[0013] In one embodiment, forming a dual bit line to-be-etched structure on the upper surface of the substrate includes:

[0014] forming a bit line material layer including a bit line barrier layer, a bit line conductive layer and a covering insulating layer on the upper surface of the substrate;

[0015] The bit line material layer is etched to obtain the double bit line to-be-etched structure, and the substrate is exposed between adjacent double bit line to-be-etched structures.

[0016] In one embodiment, after removing the first supporting layer between the first structure and the second supporting layer, the method further comprises:

[0017] Forming a bit line mask layer on the surface of the dual bit line to-be-etched structure and the surface of the bit line support structure, wherein the bit line mask layer has an opening, and the opening defines two adjacent bit lines, and the first support layer and the second support layer together constitute the bit line support structure;

[0018] Etching the dual bit line to-be-etched structure based on the bit line mask layer to obtain two adjacent bit lines;

[0019] forming a second spacer structure on the exposed side walls of two adjacent bit lines;

[0020] The bit line mask layer and the bit line support structure are removed to expose the first spacer structure.

[0021] In one embodiment, a center line of the opening of the bit line mask layer coincides with a center line of the second supporting layer on both sides of the first structure.

[0022] In one embodiment, forming a bit line mask layer on the surface of the dual bit line to-be-etched structure and the surface of the bit line support structure comprises:

[0023] forming a bit line mask material layer on the surface of the dual bit line to-be-etched structure and the surface of the second supporting layer, wherein a part of the bit line mask material layer is recessed to form a step;

[0024] The bit line mask material layer is etched based on the step of the bit line mask material layer to obtain the bit line mask layer.

[0025] In one embodiment, the thickness of the bit line is positively correlated with the thickness of the bit line mask material layer.

[0026] In one embodiment, forming a bit line mask layer on the surface of the dual bit line to-be-etched structure and the surface of the bit line support structure comprises:

[0027] forming a bit line mask material layer on a surface of the bit line support structure;

[0028] The bit line mask material layer is patterned to obtain the bit line mask layer.

[0029] In one embodiment, the material of the first supporting layer and the material of the bit line mask layer both include silicon oxide; and the second supporting layer includes a polysilicon layer.

[0030] In one embodiment, the first sidewall structure includes a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer stacked in sequence from the sidewall of the double bit line structure to be etched to the outside; the second silicon nitride layer also covers the upper surface of the double bit line structure to be etched and the exposed upper surface of the substrate.

[0031] Based on the same inventive concept, the present application also provides a semiconductor structure, which is manufactured using the semiconductor structure manufacturing method described in any of the above embodiments.

[0032] The method for preparing the semiconductor structure is as follows: a first structure is formed on a substrate, a first supporting layer covering the first structure is formed on the surface of the first structure, and a second supporting layer covering the first supporting layer is formed on the surface of the first supporting layer. The first supporting layer and the second supporting layer on the upper surface of the first structure, as well as the first supporting layer between the first structure and the second supporting layer, are removed, wherein the top surface of the second supporting layer is higher than the top surface of the first structure. Since the first supporting layer and the second supporting layer are formed on the sidewalls of the first structure, the first supporting layer and the second supporting layer can provide support for the first structure during the preparation of the semiconductor structure, ensuring that the structure retained after etching the first structure will not be distorted or tilted. In addition, since the top surface of the second supporting layer is higher than the top surface of the first structure, a mask layer can be formed on the upper surface of the first structure in a horizontal direction with the second supporting layer as the center in the subsequent process, so as to achieve self-alignment during the etching process of the first structure, thereby improving the preparation accuracy of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0035] Figure 2 A schematic cross-sectional view of a structure obtained after a bit line material layer including a bit line barrier layer, a bit line conductive layer and a covering insulating layer is formed on an upper surface of a substrate in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0036] Figure 3 A schematic cross-sectional view of a structure obtained after a photoresist layer is formed on an upper surface of a bit line material layer and a photoresist layer is patterned to form a photolithography mask layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0037] Figure 4 In the method for preparing the semiconductor structure provided in one embodiment of the present application, after etching the bit line material layer and removing the photoresist layer, a top view structural schematic diagram of a dual bit line to-be-etched structure is obtained;

[0038] Figure 5 In the method for preparing a semiconductor structure provided in an embodiment of the present application, after etching the bit line material layer and removing the photoresist layer, the edge of the double bit line to be etched structure is obtained. Figure 4 Schematic diagram of the cross-section structure in the AA direction;

[0039] Figure 6 It is a schematic cross-sectional structural diagram of a structure obtained after a first sidewall spacer is formed on a sidewall of a double bit line to-be-etched structure in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0040] Figure 7 It is a schematic cross-sectional structural diagram of a structure obtained after forming a second sidewall spacer layer on the surface of a first sidewall spacer layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0041] Figure 8 A schematic cross-sectional view of a structure obtained after a third sidewall spacer is formed on an upper surface of a double bit line to-be-etched structure, a surface of a second sidewall spacer, and an upper surface of a substrate in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0042] Fig. 9 A schematic cross-sectional view of a structure obtained after a first supporting layer is formed on an upper surface of a double bit line to-be-etched structure, a surface of a second sidewall spacer layer, and an upper surface of a substrate in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0043] Fig.10 It is a schematic cross-sectional structural diagram of a structure obtained after forming a second supporting layer in a gap in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0044] Fig.11 A schematic diagram of the cross-sectional structure of a structure obtained after etching the second supporting layer to expose the first supporting layer on top of the double bit line to-be-etched structure in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0045] Fig.12This is a schematic diagram of the cross-sectional structure of a structure obtained after etching the first supporting layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0046] Fig.13 Another schematic cross-sectional view of a structure obtained after etching the first supporting layer in the method for preparing a semiconductor structure provided in one embodiment of the present application;

[0047] Fig.14 A schematic cross-sectional view of a structure obtained after a bit line mask material layer is formed on the surface of a dual bit line to-be-etched structure and the surface of a second supporting layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0048] Fig.15 A schematic diagram of a cross-sectional structure of a structure obtained after etching a bit line mask material layer based on a recessed pattern of the bit line mask material layer to obtain the bit line mask layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0049] Fig.16 A schematic diagram of a cross-sectional structure of a structure obtained after etching a dual bit line to-be-etched structure based on a bit line mask layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0050] Fig.17 A schematic cross-sectional view of a structure obtained after forming a first sidewall spacer on exposed sidewalls of two adjacent bit lines in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0051] Fig.18 It is a schematic cross-sectional structural diagram of a structure obtained after forming a second sidewall spacer layer on the surface of a first sidewall spacer layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0052] Fig.19 It is a schematic cross-sectional structural diagram of a structure obtained after a third sidewall spacer layer is formed on the surface of a second sidewall spacer layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0053] Fig. 20 A schematic cross-sectional view of a structure obtained after removing a bit line mask layer and a bit line support structure in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0054] Fig.21 A schematic cross-sectional view of a structure obtained after removing a third sidewall spacer material layer located on an upper surface of a substrate to form a first sidewall structure in a method for preparing a semiconductor structure provided in an embodiment of the present application.

[0055] Description of reference numerals:

[0056] 10. substrate; 20. first structure; 210. dual bit line etched structure; 220. gap; 30. bit line; 310. bit line material layer; 311. bit line barrier layer; 312. bit line conductive layer; 313. covering insulating layer; 320. photolithography mask layer; 40. first sidewall structure; 410. first sidewall spacer layer; 420. second sidewall spacer layer; 430. third sidewall spacer layer; 431. third sidewall spacer material layer; 50. bit line supporting structure; 510. first supporting layer; 520. second supporting layer; 60. bit line mask layer; 610. opening; 620. bit line mask material layer; 70. second sidewall structure. DETAILED DESCRIPTION

[0057] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0059] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0060] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0061] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0062] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0063] See also Figure 1 The present application provides a method for preparing a semiconductor structure. The method for preparing a semiconductor structure includes:

[0064] Step S10, providing a substrate 10, and forming a first structure 20 on the substrate 10;

[0065] Step S20, forming a first supporting layer 510, wherein the first supporting layer 510 covers the first structure 20;

[0066] Step S30, forming a second supporting layer 520, wherein the second supporting layer 520 covers the first supporting layer 510;

[0067] Step S40 , removing the first supporting layer 510 and the second supporting layer 520 on the upper surface of the first structure 20 , as well as the first supporting layer 510 between the first structure 20 and the second supporting layer 520 , wherein the top surface of the second supporting layer 520 is higher than the top surface of the first structure 20 .

[0068] In the method for preparing the semiconductor structure, a first structure 20 is formed on a substrate 10, a first supporting layer 510 covering the first structure 20 is formed on the surface of the first structure 20, and a second supporting layer 520 covering the first supporting layer 510 is formed on the surface of the first supporting layer 510. The first supporting layer 510 and the second supporting layer 520 on the upper surface of the first structure 20 and the first supporting layer 510 between the first structure 20 and the second supporting layer 520 are removed, wherein the top surface of the second supporting layer 520 is higher than the top surface of the first structure 20. Since the first supporting layer 510 and the second supporting layer 520 are formed on the sidewalls of the first structure 20, the first supporting layer 510 and the second supporting layer 520 can provide support for the first structure 20 during the preparation of the semiconductor structure, ensuring that the structure retained after etching the first structure 20 will not be distorted or tilted. In addition, since the top surface of the second supporting layer 520 is higher than the top surface of the first structure 20, a mask layer can be formed on the upper surface of the first structure 20 in a horizontal direction with the second supporting layer 520 as the center in the subsequent process to achieve self-alignment during the etching process of the first structure 20 and improve the preparation accuracy of the semiconductor structure.

[0069] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0070] In one embodiment, the substrate 10 provided in step S10 may include any existing semiconductor substrate 10. In this embodiment, the substrate 10 may include but is not limited to a silicon substrate. A shallow trench isolation structure may be formed in the substrate 10, and the shallow trench isolation structure isolates a plurality of spaced active areas in the substrate 10.

[0071] In one embodiment, in step S10, forming the first structure 20 on the substrate 10 includes:

[0072] Step S110, forming a dual bit line to-be-etched structure 210 on the upper surface of the substrate 10;

[0073] In step S120 , a first spacer structure 40 is formed on the sidewall of the double bit line structure 210 . The double bit line structure 210 and the first spacer structure 40 together constitute the first structure 20 .

[0074] In one embodiment, step S110, forming a dual bit line to-be-etched structure 210 on the upper surface of the substrate 10 includes:

[0075] Step S111 , forming a bit line material layer 310 including a bit line barrier layer 311 , a bit line conductive layer 312 and a covering insulating layer 313 on the upper surface of the substrate 10 ;

[0076] In step S112 , the bit line material layer 310 is etched to obtain a double bit line etched structure 210 , wherein the substrate 10 is exposed between adjacent double bit line etched structures 210 .

[0077] Please also see Figure 2 In one embodiment, in step S111, a bit line barrier layer 311, a bit line conductive layer 312 and a cover insulating layer 313 may be sequentially formed on the upper surface of the substrate 10 by a deposition process. The materials and thicknesses of the bit line barrier layer 311, the bit line conductive layer 312 and the cover insulating layer 313 may be set according to actual needs. In this embodiment, the bit line barrier layer 311 may include but not limited to a titanium nitride (TiN) layer. The bit line conductive layer 312 may include but not limited to a tungsten (Tungsten) layer. The cover insulating layer 313 may include but not limited to a silicon nitride layer.

[0078] Please also see Figure 3-Figure 5 In one embodiment, in step S112, a photoresist layer may be formed on the upper surface of the bit line material layer 310 by a spin coating process, but not limited to the spin coating process, and the photoresist layer may be patterned to form a photolithography mask layer 320. The bit line material layer 310 is etched based on the photolithography mask layer 320, and is etched to the upper surface of the substrate 10, so that a plurality of dual bit line structures to be etched 210 may be formed. Finally, the photolithography mask layer 320 may be removed. In this embodiment, the width of the dual bit line structure to be etched 210 may be the sum of the width between two adjacent bit lines 30 and the width of the two bit lines 30, so as to ensure that after the dual bit line structure to be etched 210 is etched, two adjacent bit lines 30 may be formed on the upper surface of the substrate 10.

[0079] In one embodiment, step S120, forming a first spacer structure 40 on the sidewall of the double bit line to-be-etched structure 210 includes:

[0080] Step S121, forming a first sidewall spacer 410 on the sidewall of the double bit line to-be-etched structure 210;

[0081] Step S122 , forming a second sidewall spacer 420 on the surface of the first sidewall spacer 410 ;

[0082] Step S123 , forming a third sidewall spacer 430 on the upper surface of the dual bit line to-be-etched structure 210 , the surface of the second sidewall spacer 420 , and the upper surface of the substrate 10 ;

[0083] The first sidewall spacer 410 , the second sidewall spacer 420 and the third sidewall spacer 430 together constitute a first spacer structure 40 .

[0084] Please also see Figure 6 In one embodiment, in step S121, a first sidewall spacer material layer may be formed by a deposition process but not limited thereto. In this embodiment, since the ALD process has good step coverage, a single atomic layer deposition (Atomic Layer Deposition, ALD) process may be used to form a first sidewall spacer material layer on the upper surface and sidewall of the double bit line to be etched structure 210, and the upper surface of the substrate 10. Subsequently, the first sidewall spacer material layer may be etched by a dry etching process but not limited thereto to remove the first sidewall spacer material on the upper surface of the double bit line to be etched structure 210 and the upper surface of the substrate 10, to form a first sidewall spacer layer 410. The dry etching process may use SF6, CF4, CHF3, O2, Ar or a mixture of the above gases, and the specific gas selection may be set according to actual needs. In addition, the material and thickness of the first sidewall spacer layer 410 may be set according to actual needs. In this embodiment, the first sidewall spacer layer 410 may include but not limited to a silicon nitride layer.

[0085] Please also see Figure 7In one embodiment, in step S122, a second sidewall spacer material layer may be formed by a deposition process but not limited thereto. In this embodiment, since the ALD process has good step coverage, the ALD process may be used to form a second sidewall spacer material layer on the upper surface of the double bit line structure to be etched 210, the surface of the first sidewall spacer layer 410, and the upper surface of the substrate 10. Subsequently, the second sidewall spacer material layer may be etched by a dry etching process but not limited thereto to remove the second sidewall spacer material on the upper surface of the double bit line structure to be etched 210 and the upper surface of the substrate 10 to form a second sidewall spacer layer 420. The dry etching process may use SF6, CF4, CHF3, O2, Ar, or a mixture of the above gases, and the specific gas selection may be set according to actual needs. In addition, the material and thickness of the second sidewall spacer layer 420 may be set according to actual needs. In this embodiment, the second sidewall spacer layer 420 may include but not limited to a silicon oxide layer.

[0086] Please also see Figure 8 In one embodiment, in step S123, the third sidewall spacer material layer 431 may be formed by a deposition process but not limited thereto. In this embodiment, since the ALD process has good step coverage, the third sidewall spacer material layer 431 may be formed by an ALD process on the upper surface of the dual bit line to-be-etched structure 210, the surface of the second sidewall spacer layer 420, and the upper surface of the substrate 10. The material and thickness of the third sidewall spacer layer 430 may be set according to actual needs. In this embodiment, the third sidewall spacer layer 430 may include but not limited to a silicon nitride layer.

[0087] In one embodiment, after forming the third sidewall spacer material layer 431 on the upper surface of the dual bit line etched structure 210, the surface of the second sidewall spacer layer 420 and the upper surface of the substrate 10, the third sidewall spacer material layer 431 may not be etched, that is, the entire third sidewall spacer material layer 431 is retained to protect the dual bit line etched structure 210 and the substrate 10 during the process of forming and removing the bit line support structure 50.

[0088] In one embodiment, the first spacer structure 40 includes a first silicon nitride layer, a silicon oxide layer, and a second silicon nitride layer stacked in sequence from the sidewall to the outside of the dual bit line etched structure 210; the second silicon nitride layer also covers the upper surface of the dual bit line etched structure 210 and the exposed upper surface of the substrate 10. In this embodiment, the second silicon nitride layer is used as a protective layer to protect the dual bit line etched structure 210 and the substrate 10 during the process of forming and removing the bit line support structure 50.

[0089] Please also see Fig. 9In one embodiment, in step S20, the first support layer 510 may be formed by a deposition process but is not limited thereto. In this embodiment, the first support layer 510 may be formed on the upper surface of the dual bit line to be etched structure 210, the surface of the first sidewall structure 40, and the upper surface of the substrate 10 by an ALD process. After the first support layer 510 is formed, there is a gap 220 between adjacent dual bit line to be etched structures 210. The material and thickness of the first support layer 510 may be set according to actual needs. In this embodiment, the first support layer 510 may include a silicon oxide layer.

[0090] Please also see Fig.10 In one embodiment, in step S30, the second support layer 520 may be formed by, but not limited to, a deposition process. In this embodiment, a low pressure chemical vapor deposition (LPCVD) process may be used to fill the gap 220 to form the second support layer 520 in the gap 220. The height of the second support layer 520 may be greater than the dual bit line to-be-etched structure 210. The material and thickness of the second support layer 520 may be set according to actual needs. In this embodiment, the second support layer 520 may include a polysilicon layer.

[0091] Please also see Fig.11 In one embodiment, in step S40, the second supporting layer 520 may be etched by, but not limited to, a dry etching process to expose the first supporting layer 510 on the top of the dual bit line etched structure 210. In this embodiment, the first supporting layer 510 may be a silicon oxide layer, and the second supporting layer 520 may be a polysilicon layer.

[0092] Please also see Figure 12-13 In one embodiment, in step S40, the first support layer 510 may be etched by, but not limited to, a wet etching process. In this embodiment, the first support layer 510 may be wet-etched by, but not limited to, a mixed liquid of HF, H2SO4, and H2O, so that the top surface of the first support layer 510 is lower than the top surface of the double bit line to be etched structure 210, that is, lower than the top surface of the first structure 20. The top surface of the first support layer 510 is lower than the top surface of the double bit line to be etched structure 210, so that the double bit line to be etched structure 210 and the second support layer 520 can be exposed in the horizontal direction, so the first support layer 510 can be etched downward for a distance, or the first support layer 510 can be etched until the substrate 10 is exposed.

[0093] In one embodiment, after removing the first support layer 510 between the first structure 20 and the second support layer 520, the method further includes:

[0094] Step S50, forming a bit line mask layer 60 on the surface of the dual bit line to-be-etched structure 210 and the surface of the bit line support structure 50, wherein the bit line mask layer 60 has an opening 610, and the opening 610 defines two adjacent bit lines 30, and the first support layer 510 and the second support layer 520 together constitute the bit line support structure 50;

[0095] Step S60, etching the dual bit line to-be-etched structure 210 based on the bit line mask layer 60 to obtain two adjacent bit lines 30;

[0096] Step S70, forming a second spacer structure 70 on the exposed sidewalls of two adjacent bit lines 30;

[0097] In step S80 , the bit line mask layer 60 and the bit line support structure 50 are removed to expose the first spacer structure 40 .

[0098] In one embodiment, in step S50, forming a bit line mask layer 60 on the surface of the dual bit line etched structure 210 and the surface of the bit line support structure 50 includes:

[0099] Step S510, forming a bit line mask material layer 620 on the surface of the dual bit line to-be-etched structure 210 and the surface of the second support layer 520, wherein a part of the bit line mask material layer 620 is recessed to form a step;

[0100] Step S520 , etching the bit line mask material layer 620 based on the step of the bit line mask material layer 620 to obtain the bit line mask layer 60 .

[0101] Please also see Fig.14 In one embodiment, in step S510, an ALD process may be used to form a bit line mask material layer 620 on the surface of the dual bit line to-be-etched structure 210 and the surface of the second support layer 520. The material and thickness of the first support layer 510, the material and thickness of the second support layer 520, and the material and thickness of the bit line mask layer 60 may be set according to actual needs. In one embodiment, the material of the first support layer 510 is the same as that of the bit line mask layer 60.

[0102] In one embodiment, the material of the first support layer 510 and the material of the bit line mask layer 60 both include silicon oxide; the second support layer 520 includes a polysilicon layer. In this embodiment, the first support layer 510 and the bit line mask material layer 620 may include a silicon oxide layer. When the silicon oxide layer is deposited on the surface of the dual bit line to be etched structure 210 and the surface of the second support layer 520 by the ALD process, the formed silicon oxide layer has the same thickness from top to bottom and from left to right, and as the thickness of the silicon oxide layer increases, the opening 610 of the bit line mask material layer 620 gradually becomes smaller, that is, a concave pattern is formed. Therefore, when the silicon oxide layer is deposited by the ALD process, the second support layer 520 can be used as the starting point for depositing the silicon oxide layer, so the opening 610 of the deposited bit line mask material layer 620 becomes smaller and can be symmetrical about the center of the dual bit line to be etched structure 210, so as to complete the self-alignment of the etching process of the bit line 30. Therefore, the thickness of the bit line 30 is positively correlated with the thickness of the bit line mask material layer 620, and the center line of the opening 610 of the bit line mask layer 60 coincides with the center line of the second support layer 520 on both sides of the first structure 20. In this embodiment, the size of the opening 610 of the bit line mask material layer 620 can be controlled by the deposition rate of the ALD process, so that the size of the finally formed bit line 30 can be controlled, which simplifies the process of preparing the bit line 30 and improves the accuracy of preparing the bit line 30.

[0103] Please also see Fig.15 In one embodiment, in step S520, the bit line mask material layer 620 may be etched based on the step of the bit line mask material layer 620 by, but not limited to, a dry etching process to obtain the bit line mask layer 60. The bit line mask layer 60 may expose the dual bit line etched structure 210. In one embodiment, if all of the third sidewall spacer material layer 431 in the first sidewall structure 40 is retained, the third sidewall spacer material layer 431 may continue to be etched to expose the dual bit line etched structure 210.

[0104] In one embodiment, in step S50, forming a bit line mask layer 60 on the surface of the dual bit line etched structure 210 and the surface of the bit line support structure 50 includes:

[0105] Step S530 , forming a bit line mask material layer 620 on the surface of the bit line support structure 50 ;

[0106] Step S540 , patterning the bit line mask material layer 620 to obtain the bit line mask layer 60 .

[0107] In one embodiment, in step S530, a deposition process may be used but is not limited to form a bit line mask material layer 620 on the surface of the bit line support structure 50. The material and thickness of the bit line mask material layer 620 may be set according to actual needs. In this embodiment, the bit line mask material layer 620 may include a silicon oxide layer.

[0108] In one embodiment, in step S540, a photoresist layer may be formed on the upper surface of the bit line mask material layer 620 by a spin coating process but is not limited thereto, and the photoresist layer is patterned to form a photolithography mask layer. The photolithography mask layer defines two adjacent bit lines 30. Based on the photolithography mask layer, the bit line mask material layer 620 or the bit line mask material layer 620 and the third sidewall spacer material layer 431 located on the upper surface of the dual bit line to be etched structure 210 are etched to expose the dual bit line to be etched structure 210, thereby obtaining the bit line mask layer 60.

[0109] Please also see Fig.16 In one embodiment, in step S60 , the dual bit line etched structure 210 may be etched based on the bit line mask layer 60 using, but not limited to, an etching process to expose the substrate 10 and obtain two adjacent bit lines 30 .

[0110] In one embodiment, in step S70, forming a second spacer structure 70 on the exposed sidewalls of two adjacent bit lines 30 includes:

[0111] Step S710 , forming a first sidewall spacer 410 on the exposed sidewalls of two adjacent bit lines 30 ;

[0112] Step S720 , forming a second sidewall spacer 420 on the surface of the first sidewall spacer 410 ;

[0113] Step S730 , forming a third sidewall spacer 430 on the surface of the second sidewall spacer 420 ;

[0114] The first sidewall spacer 410 , the second sidewall spacer 420 and the third sidewall spacer 430 together constitute a second spacer structure 70 .

[0115] Please also see Fig.17In one embodiment, in step S710, a first sidewall spacer material layer may be formed by a deposition process but not limited thereto. In this embodiment, an ALD process may be used to form a first sidewall spacer material layer on the exposed sidewalls of two adjacent bit lines 30, the exposed surface of the first support layer 510, and the upper surface of the second support layer 520. Subsequently, a dry etching process may be used but not limited thereto to etch the first sidewall spacer material layer to remove the first sidewall spacer material on the exposed surface of the first support layer 510 and the upper surface of the second support layer 520, to form a first sidewall spacer layer 410. The dry etching process may use SF6, CF4, CHF3, O2, Ar, or a mixture of the above gases, and the specific gas selection may be set according to actual needs. In addition, the material and thickness of the first sidewall spacer layer 410 may be set according to actual needs. In this embodiment, the first sidewall spacer layer 410 may include but not limited to a silicon nitride layer.

[0116] Please also see Fig.18 In one embodiment, in step S720, a second sidewall spacer material layer may be formed by a deposition process but not limited thereto. In this embodiment, a single atomic layer deposition ALD process may be used to form a second sidewall spacer material layer on the surface of the first sidewall spacer layer 410, the exposed surface of the first support layer 510, and the upper surface of the second support layer 520. Subsequently, a dry etching process may be used but not limited thereto to etch the second sidewall spacer material layer to remove the second sidewall spacer material on the exposed surface of the first support layer 510 and the upper surface of the second support layer 520, so as to form the second sidewall spacer layer 420. The dry etching process may use SF6, CF4, CHF3, O2, Ar or a mixture of the above gases, and the specific gas selection may be set according to actual needs. In addition, the material and thickness of the second sidewall spacer layer 420 may be set according to actual needs. In this embodiment, the second sidewall spacer layer 420 may include but not limited to a silicon oxide layer.

[0117] Please also see Fig.19In one embodiment, in step S730, a deposition process may be used but is not limited to form a third sidewall spacer material layer 431. In this embodiment, a single atomic layer deposition ALD process may be used to form a first sidewall spacer material layer on the surface of the second sidewall spacer layer 420, the exposed surface of the first support layer 510, and the upper surface of the second support layer 520. Subsequently, a dry etching process may be used but is not limited to etch the third sidewall spacer material layer to remove the third sidewall spacer material on the exposed surface of the first support layer 510 and the upper surface of the second support layer 520 to form a third sidewall spacer layer 430. The dry etching process may use SF6, CF4, CHF3, O2, Ar or a mixture of the above gases, and the specific gas selection may be set according to actual needs. In addition, the material and thickness of the third sidewall spacer layer 430 may be set according to actual needs. In this embodiment, the third sidewall spacer layer 430 may include but is not limited to a silicon nitride layer.

[0118] Please also see Fig. 20 In one embodiment, in step S80, the bit line mask layer 60 may be removed by, but not limited to, an etching process. When the bit line mask layer 60 and the first support layer 510 are made of the same material, the bit line mask layer 60 may be removed while the first support layer 510 is removed. In one embodiment, the first support layer 510 and the second support layer 520 in the support structure may be etched by, but not limited to, a wet etching process to remove all of the first support layer 510 and the second support layer 520. In this embodiment, a mixed liquid of HF, H2SO4 and H2O may be used to wet-etch the first support layer 510 and the second support layer to expose the first spacer structure 40. In one embodiment, the first support layer 510 may include a silicon oxide layer, and the second support layer 520 may include a polysilicon layer. In this embodiment, the polysilicon layer and the silicon oxide layer may be removed in sequence by, but not limited to, wet etching to expose the first spacer structure 40.

[0119] Please also see Fig.21 In one embodiment, if all the third sidewall spacer material layer 431 in the first sidewall structure 40 is retained, the third sidewall spacer material layer 431 located on the upper surface of the substrate 10 needs to be removed to form the first sidewall structure 40 .

[0120] In one embodiment, a double bit line to be etched structure 210 is formed on the upper surface of the substrate 10, and the width of the double bit line to be etched structure 210 is the sum of the width between two adjacent bit lines 30 and the width of the two bit lines 30. A first spacer structure 40 is formed on the sidewall of the double bit line to be etched structure 210, which can ensure good adhesion between the first spacer structure 40 and the two adjacent bit lines 30. A first supporting layer 510 is formed on the upper surface of the double bit line to be etched structure 210, the surface of the first spacer structure 40, and the upper surface of the substrate 10, and a second supporting layer 520 is formed in the gap 220 between the adjacent double bit line to be etched structures 210 after the first supporting layer 510 is formed. The first supporting layer 510 and the second supporting layer 520 can support the bit line 30 when the second spacer structure 70 of the bit line 30 is formed, thereby preventing the bit line 30 from being distorted or tilted. A bit line mask layer 60 is formed on the surface of the dual bit line to be etched structure 210 and the surface of the bit line support structure 50. Two adjacent bit lines 30 can be obtained by etching the dual bit line to be etched structure 210 based on the bit line mask layer 60. A second spacer structure 70 is formed on the exposed sidewalls of the two adjacent bit lines 30, and the bit line support structure 50 is removed, so that the preparation of the two adjacent bit lines 30 can be completed. Therefore, in the preparation method of the semiconductor structure, the first spacer structure 40 and the second spacer structure 70 can wrap the sidewall of the bit line 30 well, thereby ensuring that the subsequent transistor-capacitor can be well filled with wires, and ensuring the performance of the DRAM.

[0121] Based on the same inventive concept, the present application also provides a semiconductor structure, which is manufactured using the semiconductor structure manufacturing method of any of the above embodiments, which will not be described in detail here.

[0122] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0123] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, and forming a first structure on the substrate; forming a first supporting layer, wherein the first supporting layer covers the first structure; forming a second supporting layer, wherein the second supporting layer covers the first supporting layer; removing the first supporting layer and the second supporting layer on the upper surface of the first structure, and the first supporting layer between the first structure and the second supporting layer, wherein the top surface of the second supporting layer is higher than the top surface of the first structure; Wherein, forming a first structure on the substrate comprises: forming a dual bit line to-be-etched structure on the upper surface of the substrate; A first sidewall structure is formed on the sidewall of the double bit line structure to be etched, and the double bit line structure to be etched and the first sidewall structure together constitute the first structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The forming of a double bit line to-be-etched structure on the upper surface of the substrate comprises: forming a bit line material layer including a bit line barrier layer, a bit line conductive layer and a covering insulating layer on the upper surface of the substrate; The bit line material layer is etched to obtain the double bit line to-be-etched structure, and the substrate is exposed between adjacent double bit line to-be-etched structures.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: After removing the first supporting layer between the first structure and the second supporting layer, the method further includes: Forming a bit line mask layer on the surface of the dual bit line to-be-etched structure and the surface of the bit line support structure, wherein the bit line mask layer has an opening, and the opening defines two adjacent bit lines, and the first support layer and the second support layer together constitute the bit line support structure; Etching the dual bit line to-be-etched structure based on the bit line mask layer to obtain two adjacent bit lines; forming a second spacer structure on the exposed side walls of two adjacent bit lines; The bit line mask layer and the bit line support structure are removed to expose the first spacer structure.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: A center line of the opening of the bit line mask layer coincides with a center line of the second supporting layer on both sides of the first structure.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that: The forming of a bit line mask layer on the surface of the dual bit line to-be-etched structure and the surface of the bit line support structure comprises: forming a bit line mask material layer on the surface of the dual bit line to-be-etched structure and the surface of the second supporting layer, wherein a part of the bit line mask material layer is recessed to form a step; The bit line mask material layer is etched based on the step of the bit line mask material layer to obtain the bit line mask layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The thickness of the bit line is positively correlated with the thickness of the bit line mask material layer.

7. The method for preparing a semiconductor structure according to claim 3, characterized in that: The forming of a bit line mask layer on the surface of the dual bit line to-be-etched structure and the surface of the bit line support structure comprises: forming a bit line mask material layer on a surface of the bit line support structure; The bit line mask material layer is patterned to obtain the bit line mask layer.

8. The method for preparing a semiconductor structure according to claim 3, characterized in that: The material of the first supporting layer and the material of the bit line mask layer both include silicon oxide; and the second supporting layer includes a polysilicon layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The first sidewall structure includes a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer stacked in sequence from the sidewall of the double bit line to be etched structure to the outside; the second silicon nitride layer also covers the upper surface of the double bit line to be etched structure and the exposed upper surface of the substrate.

10. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method for manufacturing the semiconductor structure according to any one of claims 1 to 9.

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