A method for manufacturing a flash memory device
By using the dual coating process of the barrier layer and the photoresist layer in the manufacturing process of super flash memory devices, the word line is protected from misetching, solving the problem that word line polysilicon is prone to misetching, and improving the device yield and performance.
Patent Information
- Application Number
- CN202111058811.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-09-08
- Publication Date
- 2025-02-07
- Estimated Expiration
- 2041-09-08
AI Technical Summary
During the manufacturing process of super flash memory devices, word line polysilicon is easily misetched, resulting in uncontrollable line width and morphology, affecting device performance.
The double coating process of the barrier layer and the photoresist layer is adopted to expose the polysilicon layer when removing the barrier layer of partial thickness, and the remaining thickness barrier layer is used to protect the word lines during the etching process to avoid misetching.
It effectively protects the line width and morphology of the word line, ensures the control of the word line gate threshold voltage, does not affect device performance, and reduces process cost and complexity.
Smart Images
Figure CN113948522B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing a flash memory device. Background Art
[0002] In the current semiconductor industry, memory devices account for a considerable proportion of integrated circuit products, and the development of super flash memory devices in memory is particularly rapid. Its main feature is that it can retain stored information for a long time without power supply, and has many advantages such as high integration, fast access speed and easy erasure. It can be flexibly applied to many fields such as microcomputers and automation control.
[0003] In the manufacturing process of super flash memory devices, when using CH mask to etch excess erasable gate polysilicon, because the minimum line width of the existing CH (Cave Hole) mask is 0.168 microns and the Y-direction width is 0.112 microns, it is inevitable that the word line polysilicon is also located in the photoresist open area. Therefore, when etching away excess erasable gate polysilicon, the word line polysilicon will also be mistakenly etched, causing damage to the word line polysilicon, resulting in uncontrolled line width and morphology of the word line polysilicon, thereby affecting the control of the word line gate threshold voltage, and thus affecting the performance of the device. Summary of the invention
[0004] The object of the present invention is to provide a method for manufacturing a flash memory device to solve the problem that the word line is mistakenly etched when forming an erase gate.
[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a flash memory device, comprising:
[0006] A substrate is provided, on which a stacked silicon oxide layer and a polysilicon layer are formed, a groove for filling a source line is formed in the silicon oxide layer, and word lines are formed on both sides of the silicon oxide layer, wherein the upper surface of the word line is lower than the lower surface of the polysilicon layer;
[0007] coating a barrier layer on the word line and the polysilicon layer;
[0008] Etching back a portion of the barrier layer to completely expose the polysilicon layer;
[0009] Coating an anti-reflective layer and a photoresist layer on the polysilicon layer and the remaining thickness of the barrier layer;
[0010] performing a photolithography process to obtain a patterned photoresist layer on the barrier layer;
[0011] etching the anti-reflection layer, the polysilicon layer and the silicon oxide layer using the patterned photoresist layer to obtain an erase gate on the surface of the silicon oxide layer on the source line; and,
[0012] The patterned photoresist layer, the anti-reflective layer and the remaining thickness of the barrier layer are removed.
[0013] Optionally, in the method for manufacturing the flash memory device, a selective etching process is used to etch back a portion of the thickness of the barrier layer to completely expose the polysilicon layer.
[0014] Optionally, in the manufacturing method of the flash memory device, after etching back a portion of the thickness of the barrier layer to expose the polysilicon layer, the upper surface of the remaining thickness of the barrier layer is lower than the lower surface of the polysilicon layer, and the upper surface of the remaining thickness of the barrier layer is higher than the upper surface of the word line.
[0015] Optionally, in the method for manufacturing the flash memory device, the barrier layer is a spin-coated carbon film.
[0016] Optionally, in the method for manufacturing the flash memory device, the thickness of the barrier layer removed by etching back is
[0017] Optionally, in the method for manufacturing the flash memory device, the remaining thickness of the barrier layer is
[0018] Optionally, in the method for manufacturing the flash memory device, the thickness of the photoresist layer is
[0019] Optionally, in the method for manufacturing the flash memory device, a Ti / TiN layer and an OON layer are sequentially formed between the source line and the sidewall of the trench.
[0020] Optionally, in the method for manufacturing the flash memory device, the OON layer includes a first silicon oxide film, a second silicon oxide film and a silicon nitride film.
[0021] In the early stage of the experiment, the inventor calculated and found that if the word line is to be in the safe area covered by the photoresist layer, the minimum line width of the CH mask used to etch the polysilicon layer needs to be 0.104 microns, and the width in the Y direction is 0.06 microns. However, the experimental data on the test mask showed that there would be some swelling in the center of the hole, which would affect the process window. This target size poses great challenges to optical proximity correction and lithography. The printing suitability is insufficient, the mask cost has increased significantly, and the process cost and complexity have increased. Therefore, a new method for manufacturing flash memory devices is needed to solve the problem of word lines being mistakenly etched when forming the erase gate, and at the same time, there is no need to change the mask (no need to increase process cost and complexity).
[0022] In summary, the present invention provides a method for manufacturing a flash memory device, comprising: providing a substrate, on which a silicon oxide layer and a polysilicon layer are formed, word lines are formed on both sides of the silicon oxide layer, and the upper surface of the word line is lower than the lower surface of the polysilicon layer; coating a barrier layer; etching back a portion of the thickness of the barrier layer; coating an anti-reflection layer and a photoresist layer; exposing and developing the photoresist layer; etching the polysilicon layer to obtain an erase gate; and removing the excess photoresist layer, the anti-reflection layer and the barrier layer. The present invention adopts a double coating process of a barrier layer and a photoresist layer, and when removing a portion of the thickness of the barrier layer, the polysilicon layer is exposed, and the barrier layer of the remaining thickness is used to protect the word line in the process of etching and removing the excess polysilicon layer to obtain the erase gate, so that it is not mistakenly etched, thereby protecting the integrity of the line width and morphology of the word line, ensuring that the control of the word line gate threshold voltage is not affected, and improving the yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 is a flow chart of a method for manufacturing a flash memory device according to an embodiment of the present invention;
[0024] Figure 2-Figure 8 is a schematic diagram of a semiconductor structure in each process step of manufacturing a flash memory device according to an embodiment of the present invention;
[0025] The reference numerals are described as follows:
[0026] 10-substrate, 20-silicon oxide layer, 30-polysilicon layer, 31-erase gate, 40-source line, 50-word line, 60-Ti / TiN layer, 70-OON layer, 81-barrier layer, 811-barrier layer of remaining thickness, 82-anti-reflective layer, 83-photoresist layer, 833-patterned photoresist layer, 100-groove. DETAILED DESCRIPTION
[0027] The manufacturing method of the flash memory device proposed in the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often a part of the actual structure. In particular, the emphasis that each accompanying drawing needs to show is different, and sometimes different proportions are used.
[0028] The present invention provides a method for manufacturing a flash memory device. Figure 1 , Figure 1 1 is a flow chart of a method for manufacturing a flash memory device according to an embodiment of the present invention, wherein the method for manufacturing a flash memory device comprises:
[0029] S01: providing a substrate, on which a stacked silicon oxide layer and a polysilicon layer are formed, a groove for filling a source line is formed in the silicon oxide layer, and word lines are formed on both sides of the silicon oxide layer, wherein an upper surface of the word line is lower than a lower surface of the polysilicon layer;
[0030] S02: coating a barrier layer on the word line and the polysilicon layer;
[0031] S03: etching back a portion of the barrier layer to completely expose the polysilicon layer;
[0032] S04: coating an anti-reflection layer and a photoresist layer on the polysilicon layer and the remaining thickness of the barrier layer;
[0033] S05: performing a photolithography process to obtain a patterned photoresist layer on the barrier layer;
[0034] S06: etching the anti-reflection layer, the polysilicon layer and the silicon oxide layer using the patterned photoresist layer to obtain an erase gate on the surface of the silicon oxide layer on the source line; and
[0035] S07: removing the patterned photoresist layer, the remaining anti-reflection layer and the remaining thickness of the barrier layer.
[0036] For details, please refer to Figure 2-Figure 8 , Figure 2-Figure 8 It is a schematic diagram of a semiconductor structure in each process step of manufacturing a flash memory device according to an embodiment of the present invention.
[0037] First, please refer to Figure 2 , a substrate 10 is provided, on which a stacked silicon oxide layer 20 and a polysilicon layer 30 are formed, a groove 100 for filling a source line 40 is formed in the silicon oxide layer 20, and word lines 50 are formed on both sides of the silicon oxide layer 20, wherein the upper surface of the word line 50 is lower than the lower surface of the polysilicon layer 30. Specifically, the substrate 10 can be one of single crystal silicon, polycrystalline silicon, amorphous silicon, or gallium arsenide, silicon gallium compound, etc., and can also have a silicon on insulating layer or epitaxial layer structure on silicon, etc., which are not listed here one by one. In this embodiment, the silicon oxide layer 20 and the polysilicon layer 30 can be formed by an existing CVD process or PVD process.
[0038] Preferably, a Ti / TiN layer 60 and an OON layer 70 are sequentially formed between the source line 40 and the sidewall of the trench 100. The Ti / TiN layer 60 plays a role of blocking and bonding, and the OON layer 70 plays a role of isolation and insulation; the OON layer 70 includes a first silicon oxide film, a second silicon oxide film and a silicon nitride film (not shown). Specifically, in this embodiment, after etching the silicon oxide layer 20 to form the trench 100 and before filling the source line 40, the OON layer 70 and the Ti / TiN layer 60 can be sequentially deposited on the sidewall and bottom wall of the trench 100 by an existing CVD process or PVD process. Further, before filling the source line 40, it can also include: the steps of removing the OON layer 70 and the Ti / TiN layer 60 on the bottom wall of the trench 100, and the step of injecting P-type ions (such as arsenic ions) into the bottom wall of the trench 100 to form an ion implantation region in the substrate 10 at the bottom wall of the trench 100. The ion implantation region is equivalent to a barrier film layer, and its main function is to prevent device breakdown when high voltage is subsequently applied to the source line.
[0039] Next, please refer to Figure 3 A barrier layer 81 is coated on the word line 50 and the polysilicon layer 30. Specifically, the barrier layer 81 may be a spin-on carbon film (SOC). The barrier layer may also be other organic polymer liquid spin-on materials.
[0040] For further information, please refer to Figure 4 , partially etch back the barrier layer 81 to fully expose the polysilicon layer 30. Specifically, a selective etching process is used to etch back partially the barrier layer 81 to fully expose the polysilicon layer 30. That is, the selective etching process only removes partially the barrier layer 81, and does not etch the polysilicon layer 30 and the silicon oxide layer 20. The selective etching process of the present invention can be a wet etching process or a dry etching process, which can be determined according to the material properties of the barrier layer 81. The thickness of the barrier layer 81 removed by etching back can be The (remaining) thickness of the barrier layer 811 may be In this embodiment, after etching back a portion of the thickness of the barrier layer 81 to expose the polysilicon layer 30 , the upper surface of the remaining thickness of the barrier layer 81 is lower than the lower surface of the polysilicon layer 30 , and the upper surface of the remaining thickness of the barrier layer 81 is higher than the upper surface of the word line 50 , that is, the remaining thickness of the barrier layer 81 still covers the word line 50 .
[0041] Next, please refer to Figure 5, an anti-reflection layer 82 and a photoresist layer 83 are coated on the polysilicon layer 30 and the remaining thickness of the barrier layer 811. Specifically, the thickness of the coated anti-reflection layer 82 can be The thickness of the spin-coated photoresist layer 83 can be .
[0042] The present invention adopts a double coating process of the barrier layer 81 and the photoresist layer 82. When a portion of the thickness of the barrier layer 81 is removed, the polysilicon layer 30 is exposed and still covers the word line 50. The remaining thickness of the barrier layer 811 is subsequently used to etch and remove the polysilicon layer 30 in the open area of the mask to obtain the erase gate 31 to protect the word line 50 from being mistakenly etched, thereby protecting the line width of the word line 50 and the integrity of its morphology.
[0043] For further information, please refer to Figure 6 , a photolithography process is performed to obtain a patterned photoresist layer 833 on the barrier layer 811 and the anti-reflection layer 82. Specifically, the photoresist layer 82 is exposed and developed using a CH mask to obtain the patterned photoresist layer 833. Because the minimum line width of the CH mask does not reach 0.104 μm, the process window opened by the patterned photoresist layer 833 will overlap with the word line 50 below in the Y-axis direction. However, when etching the anti-reflection layer 82, the polysilicon layer 30 and the silicon oxide layer 20, due to the presence of the barrier layer 811, the etching will stop on the surface of the barrier layer 811 with the remaining thickness, thereby avoiding the situation where the word line 50 covered by the barrier layer 811 is mistakenly etched. Furthermore, the present invention utilizes the remaining thickness of the barrier layer 811 to protect the word line 50 during the process of etching away the polysilicon layer 30 in the open area of the mask to obtain the erase gate 31. There is no need to prepare a new CH mask with a smaller minimum line width, thereby reducing the cost of the mask, reducing the difficulty of optical proximity correction and lithography, and thus greatly reducing the process cost and process complexity.
[0044] For further information, please refer to Figure 7 , the anti-reflection layer 82, the polysilicon layer 30 and the silicon oxide layer 20 are etched using the patterned photoresist layer 833 to obtain the erase gate 31 on the surface of the silicon oxide layer 20 on the source line 40. Specifically, the anti-reflection layer 82, the polysilicon layer 30 and a part of the thickness of the silicon oxide layer 20 can be etched by a dry etching process, and a certain width of the polysilicon layer 30 above the source line 40 is retained as the erase gate 31.
[0045] Finally, please refer to Figure 8, remove the patterned photoresist layer 833, the remaining anti-reflection layer 82 and the remaining thickness of the barrier layer 811. Specifically, in this embodiment, the patterned photoresist layer 833 can be removed by ashing, and the remaining anti-reflection layer 82 and the remaining thickness of the barrier layer 811 can be removed by dry etching or wet etching or organic solvent or other processes.
[0046] In summary, the present invention adopts a double coating process of the barrier layer 81 and the photoresist layer 83, removes a portion of the thickness of the barrier layer 81 to expose the polysilicon layer, and utilizes the remaining thickness of the barrier layer 811 to protect the word line from being mistakenly etched during the process of etching away the polysilicon layer 30 in the mask opening area and retaining the polysilicon layer 30 above the source line 10 to form the erase gate 31, thereby protecting the integrity of the line width and morphology of the word line, ensuring that the word line gate threshold voltage control is not affected when the subsequent device is working, optimizing the performance of the device, and improving the yield of the device.
[0047] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for manufacturing a flash memory device, characterized in that: include: A substrate is provided, on which a stacked silicon oxide layer and a polysilicon layer are formed, a groove for filling a source line is formed in the silicon oxide layer, and word lines are formed on both sides of the silicon oxide layer, wherein the upper surface of the word line is lower than the lower surface of the polysilicon layer; coating a barrier layer on the word line and the polysilicon layer; Etching back a portion of the barrier layer to completely expose the polysilicon layer; Coating an anti-reflective layer and a photoresist layer on the polysilicon layer and the remaining thickness of the barrier layer; performing a photolithography process to obtain a patterned photoresist layer on the barrier layer; etching the anti-reflection layer, the polysilicon layer and the silicon oxide layer using the patterned photoresist layer to obtain an erase gate on the surface of the silicon oxide layer on the source line; and, The patterned photoresist layer, the anti-reflective layer and the remaining thickness of the barrier layer are removed.
2. The method for manufacturing a flash memory device according to claim 1, wherein: A selective etching process is used to etch back a portion of the barrier layer to fully expose the polysilicon layer.
3. The method for manufacturing a flash memory device according to claim 1, wherein: After etching back a portion of the barrier layer to expose the polysilicon layer, the upper surface of the remaining barrier layer is lower than the lower surface of the polysilicon layer, and the upper surface of the remaining barrier layer is higher than the upper surface of the word line.
4. The method for manufacturing a flash memory device according to claim 1, wherein: The barrier layer is a spin-coated carbon film.
5. The method for manufacturing a flash memory device according to claim 1, wherein: The thickness of the barrier layer removed by etching back is 6. The method for manufacturing a flash memory device according to claim 1, wherein: The remaining thickness of the barrier layer is 7. The method for manufacturing a flash memory device according to claim 1, wherein: The thickness of the photoresist layer is 8. The method for manufacturing a flash memory device according to claim 1, wherein: A Ti / TiN layer and an OON layer are sequentially formed between the source line and the sidewall of the trench.
9. The method for manufacturing a flash memory device according to claim 8, characterized in that: The OON layer includes a first silicon oxide film, a second silicon oxide film and a silicon nitride film.
Citation Information
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