A method for loading target code of digital signal processor

Abstract

The present invention provides a method for loading a digital signal processor target code, the method comprising: parsing the file header information of a digital signal processor target code file, obtaining the segment header information and the program execution entry address; traversing each segment header, identifying the .cinit segment, if its segment attribute is copysection, indicating that the .cinit segment needs to be copied; allocating a temporary buffer for each continuous memory block according to the length of the memory block; creating a virtual memory area for each continuous memory block according to the length of the continuous memory block, copying the content in the temporary buffer to the virtual memory area; initializing the virtual memory area according to the physical address of the first segment in the continuous memory block; and hanging all virtual memory areas on the system memory root address. The virtual memory blocks can be merged and allocated according to the segment header information and the loading mode, avoiding the allocation of unnecessary virtual memory space.

Description

Technical Field

[0001] The invention relates to the technical field of digital signal processor system simulation, and in particular to a digital signal processor target code loading method. Background Art

[0002] Digital signal processors are widely used to analyze, collect, synthesize, transform, filter, estimate and compress signals in digital form. There are many manufacturers of digital signal processors, with hundreds of processor models, and they have become the most common target processors supported by simulation platforms.

[0003] In the simulation platform, the loading of digital signal processor target code usually adopts a "customized" loading method, which implements the allocation of virtual machine memory and content loading in a "hard-coded" manner according to the memory layout of the processor user manual or by reading configuration files related to the processor model.

[0004] In the simulation platform, the shortcomings of the existing digital signal processor target code loading method mainly exist in two aspects: insufficient versatility or flexibility; there are many digital signal processor models with large differences. In the simulation platform, the target code loading module needs to rely on the memory layout of the specific digital signal processor model, and the versatility and flexibility are seriously insufficient. Waste of simulation platform memory resources In the existing simulation platform, the target processor memory layout is allocated according to the maximum length supported by the processor. This method will cause a waste of simulation platform memory resources and is not suitable for simulation platforms with limited computing resources. Summary of the invention

[0005] In view of the above problems, the present invention is proposed to provide a digital signal processor target code loading method that overcomes the above problems or at least partially solves the above problems.

[0006] According to one aspect of the present invention, a method for loading target code of a digital signal processor is provided, the loading method comprising:

[0007] Parse the file header information of the digital signal processor target code file to obtain the segment header information and program execution entry address;

[0008] Traverse each of the segment headers, identify the .cinit segment, if its segment attribute is copy section, it means that the .cinit segment needs to be copied, and determine that the loading mode is running memory loading, otherwise the loading mode is storage memory loading;

[0009] Traversing each of the segment headers, identifying allocatable continuous memory blocks, and marking the state of each segment as a continuous state. If the segment is the first segment in a continuous memory block, it is marked as a "continuous block header". If the segment is connected after the first segment in a continuous memory block, it is marked as a "continuous block body". The initial state of all the segments is "undetermined".

[0010] Calculate the length of each continuous memory block according to the "continuous block header";

[0011] Length of continuous memory block = length of continuous block header + length of all continuous blocks belonging to the continuous block header;

[0012] There are some differences depending on the determined loading mode: if the running memory loading mode is used, the length of the .cinit segment is not included in the continuous memory block;

[0013] Allocating a temporary buffer for each continuous memory block according to the length of the memory block, and copying the content of each segment from the target code to the corresponding temporary buffer;

[0014] Get the root address of the virtual machine system memory;

[0015] Creating a virtual memory area for each continuous memory block according to the length of the continuous memory block, and copying the content in the temporary buffer to the virtual memory area;

[0016] Initialize the virtual memory area according to the physical address of the first segment in the continuous memory block to ensure that the virtual memory area is bound to the physical address;

[0017] Mount all virtual memory areas to the system memory root address.

[0018] Optionally, the segment header information includes the starting address, size and attribute information of each segment.

[0019] Optionally, traversing each of the segment headers, identifying allocatable continuous memory blocks, and marking the status of each segment as a continuous state, if the segment is the first segment in a continuous memory block, marking it as a "continuous block header", if the segment is connected to the first segment in a continuous memory block, marking it as a "continuous block body", and the initial status of all the segments is "undetermined", specifically including:

[0020] If the current segment is a .cinit segment and the loading mode is to perform memory loading, mark the current segment as a "continuous block" and continue parsing the next segment;

[0021] If the current segment status is not "undecided", the segment status is not changed and the parsing continues with the next segment;

[0022] If the current segment is the last segment in the target file and it is not a "continuous block body", the current segment is marked as a "continuous block header" and the traversal stops;

[0023] Otherwise, start traversing from the next segment of the current segment until the last segment, check whether the address of each segment is a continuous address of the current segment. If it is a continuous address, mark the state of the segment as "continuous block" and find all "continuous blocks" for the current segment;

[0024] If no "continuous block body" is found for the current segment, the current segment is marked as a "continuous block header".

[0025] Optionally, allocating a temporary buffer for each continuous memory block according to the length of the memory block, and copying the content of each segment from the target code to the corresponding temporary buffer specifically includes:

[0026] If it is running memory loading, load the copy of the initial value of the variable in the .cinit segment to the corresponding address in the .bss segment;

[0027] If it is a storage memory load, copy the contents of the .cinit segment to the corresponding temporary buffer.

[0028] The present invention provides a general digital signal processor target code loading method suitable for a simulation platform. On the one hand, the digital signal processor target code can be loaded flexibly without having to understand the memory layout of a specific processor when building a simulation platform, and on the other hand, the simulation platform virtual memory space used to simulate the physical memory of the target processor can be effectively saved.

[0029] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0031] Figure 1 A flow chart of a method for loading target code of a digital signal processor provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0033] The terms "comprises" and "having" and any variations thereof in the description embodiments, claims and drawings of the present invention are intended to cover non-exclusive inclusions, for example, including a series of steps or units.

[0034] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0035] like Figure 1 As shown, a method for loading target code of a digital signal processor, the loading method comprising:

[0036] Parse the file header information of the digital signal processor target code file to obtain the segment header information and the program execution entry address; the segment header information includes the starting address, size and attribute information of each segment.

[0037] Traverse each of the segment headers to identify the .cinit segment. If its segment attribute is copy section, it means that the .cinit segment needs to be copied, and determine that the loading mode is running memory loading, otherwise the loading mode is storage memory loading.

[0038] Traverse each of the segment headers, identify the allocatable continuous memory blocks, and mark the status of each segment as a continuous state. If the segment is the first segment in a continuous memory block, mark it as a "continuous block header". If the segment is connected after the first segment in a continuous memory block, mark it as a "continuous block body". The initial status of all the segments is "undetermined".

[0039] If the current segment is a .cinit segment and the loading mode is to perform memory loading, mark the current segment as a "continuous block" and continue parsing the next segment;

[0040] If the current segment status is not "undecided", the segment status is not changed and the parsing continues with the next segment;

[0041] If the current segment is the last segment in the target file and it is not a "continuous block body", the current segment is marked as a "continuous block header" and the traversal stops;

[0042] Otherwise, start traversing from the next segment of the current segment until the last segment, check whether the address of each segment is a continuous address of the current segment. If it is a continuous address, mark the state of the segment as "continuous block" and find all "continuous blocks" for the current segment;

[0043] If no "continuous block body" is found for the current segment, the current segment is marked as a "continuous block header".

[0044] Calculate the length of each continuous memory block according to the "continuous block header";

[0045] Length of continuous memory block = length of continuous block header + length of all continuous blocks belonging to the continuous block header;

[0046] There are some differences depending on the determined loading mode: if the running memory loading mode is used, the length of the .cinit segment is not included in the continuous memory block;

[0047] Allocating a temporary buffer for each continuous memory block according to the length of the memory block, and copying the content of each segment from the target code to the corresponding temporary buffer;

[0048] If it is running memory loading, load the copy of the initial value of the variable in the .cinit segment to the corresponding address in the .bss segment;

[0049] If it is a storage memory load, copy the contents of the .cinit segment to the corresponding temporary buffer.

[0050] Get the root address of the virtual machine system memory.

[0051] A virtual memory area is created for each continuous memory block according to the length of the continuous memory block, and the content in the temporary buffer is copied to the virtual memory area.

[0052] The virtual memory area is initialized according to the physical address of the first segment in the continuous memory block to ensure that the virtual memory area is bound to the physical address.

[0053] Mount all virtual memory areas to the system memory root address.

[0054] On the simulation platform, the general steps for loading the digital signal processor target code are:

[0055] Get the root address of the virtual machine system memory;

[0056] According to the memory layout description provided in the processor user manual, virtual memory areas are allocated one by one to the physical memory areas that need to be loaded;

[0057] Initialize virtual memory areas one by one according to the addresses and sizes of physical memory areas specified in the memory layout description provided in the processor user manual;

[0058] Attach the initialized virtual memory areas to the system memory root addresses one by one;

[0059] Parse the target code file, read the segment header in the target code, and load the contents of the segment into the corresponding virtual machine memory area one by one according to the segment address and segment length provided in the segment header. Here we distinguish the loading modes of the digital signal processor: execution memory loading and storage memory loading.

[0060] Beneficial effects: The target code loading component in the simulation platform does not need to rely on the memory layout description of the specific digital signal processor model;

[0061] After analyzing the target code, virtual memory blocks are merged and allocated according to the segment header information and loading mode to avoid allocating unnecessary virtual memory space;

[0062] The present invention is applicable to simulation platforms with limited computing resources, such as embedded simulation platform systems used in the fields of aerospace, aviation, national defense, etc.

[0063] The above specific implementation methods further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for loading target code of a digital signal processor, characterized in that: The loading method comprises: Parse the file header information of the digital signal processor target code file to obtain the segment header information and program execution entry address; Traverse each of the segment headers, identify the .cinit segment, if its segment attribute is copy section, it means that the .cinit segment needs to be copied, and determine that the loading mode is running memory loading, otherwise the loading mode is storage memory loading; Traverse each of the segment headers, identify the allocatable continuous memory blocks, and mark the status of each segment as a continuous state. If the segment is the first segment in the continuous memory block, mark it as a "continuous block header". If the segment is connected after the first segment in the continuous memory block, mark it as a "continuous block body". The initial status of all the segments is "undetermined". Calculate the length of each continuous memory block according to the "continuous block header"; Length of continuous memory block = length of continuous block header + length of all continuous blocks belonging to the continuous block header; There are some differences depending on the determined loading mode: if the running memory loading mode is used, the length of the .cinit segment is not included in the continuous memory block; Allocating a temporary buffer for each continuous memory block according to the length of the memory block, and copying the content of each segment from the target code to the corresponding temporary buffer; Get the root address of the virtual machine system memory; Creating a virtual memory area for each continuous memory block according to the length of the continuous memory block, and copying the content in the temporary buffer to the virtual memory area; Initialize the virtual memory area according to the physical address of the first segment in the continuous memory block to ensure that the virtual memory area is bound to the physical address; Mount all virtual memory areas to the system memory root address.

2. A method for loading target code of a digital signal processor according to claim 1, characterized in that: The segment header information includes the starting address, size and attribute information of each segment.

3. A method for loading target code of a digital signal processor according to claim 1, characterized in that: The traversing of each segment header, identifying the allocatable continuous memory block, and marking the state of each segment as a continuous state, if the segment is the first segment in the continuous memory block, marking it as a "continuous block header", if the segment is connected after the first segment in the continuous memory block, marking it as a "continuous block body", and the initial state of all the segments is "undetermined" specifically includes: If the current segment is a .cinit segment and the loading mode is to perform memory loading, mark the current segment as a "continuous block" and continue parsing the next segment; If the current segment status is not "undecided", the segment status is not changed and the parsing continues to the next segment; If the current segment is the last segment in the target file and it is not a "continuous block body", the current segment is marked as a "continuous block header" and the traversal stops; Otherwise, traverse from the next segment of the current segment to the last segment, check whether the address of each segment is a continuous address of the current segment, if it is a continuous address, mark the state of the current segment as "continuous block", and find all "continuous blocks" for the current segment; If no "continuous block body" is found for the current segment, the current segment is marked as a "continuous block header".

4. A method for loading target code of a digital signal processor according to claim 1, characterized in that: The allocating a temporary buffer for each continuous memory block according to the length of the memory block, and copying the content of each segment from the target code to the corresponding temporary buffer specifically includes: If it is running memory loading, load the copy of the initial value of the variable in the .cinit segment to the corresponding address in the .bss segment; If it is a storage memory load, copy the contents of the .cinit segment to the corresponding temporary buffer.

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