FPGA Measurement Unit and Channel Delay Compensation Method and Device Based on FPGA Measurement Unit

Abstract

The present application provides an FPGA measurement unit, a channel delay compensation method and device based on the FPGA measurement unit. The measurement unit includes: a logic unit, a pulse signal sending unit connected to the logic unit, and a plurality of input / output units; the input / output unit includes: a receiver, a delay adjustment module and a sampling register connected in sequence; the sampling register and the pulse signal sending unit are connected to the same system clock; the pulse signal sending unit is connected to a plurality of connection points in the device under test; the plurality of connection points are respectively connected to a plurality of receivers in one-to-one correspondence; a complete path from one connection point to one sampling register is a channel; the delay adjustment module is used to compensate for the delay deviation between channels. The present application can accurately compensate for the delay between multiple channels, thereby eliminating the deviation influence of the measurement unit itself and completing the self-calibration of the measurement unit.

Description

Technical Field

[0001] This application relates to the field of software technologies, and in particular, to an FPGA measurement unit, a channel delay compensation method, and a device based on the FPGA measurement unit. Background Art

[0002] In an ATE device, an external measurement unit or device is usually used to measure the time delay deviation of all signals (such as 256 channels) in each SLOT slot to the POGO device under test. To ensure measurement accuracy, the measurement unit itself must not introduce additional deviation. In a measurement unit implemented based on an FPGA, there are often delay deviations between different channels, including trace delay, device delay, sampling clock delay, etc. In the prior art, in order to eliminate the deviation of the measurement unit based on the FPGA itself, timing constraints are usually set inside the FPGA, and through this constraint, the internal traces of the FPGA are preferentially arranged according to the set value. However, the constraint accuracy of this method is relatively low, usually in the order of nanoseconds, and the deviation introduced by the measurement unit itself cannot be completely eliminated, thus unable to meet the requirements of high-speed and high-precision applications. Summary of the Invention

[0003] The purpose of this application is to provide an FPGA measurement unit, a channel delay compensation method, and a device based on the FPGA measurement unit, which can accurately compensate for the delay between multiple channels, thereby eliminating the deviation influence of the measurement unit itself and completing the self-calibration of the measurement unit.

[0004] In a first aspect, an embodiment of this application provides an FPGA measurement unit, which includes: a logic unit, a pulse signal sending unit connected to the logic unit, and a plurality of input / output units; the input / output unit includes: a receiver, a delay adjustment module, and a sampling register connected in sequence; the sampling register and the pulse signal sending unit are connected to the same system clock; the pulse signal sending unit is connected to a plurality of connection points in the device under test; the plurality of connection points are respectively connected to a plurality of receivers in one-to-one correspondence; a complete path from one connection point to one sampling register is one channel; the delay adjustment module is used to compensate for the delay deviation between channels.

[0005] Second aspect, an embodiment of the present application provides a channel delay compensation method based on an FPGA measurement unit. The method is applied to the FPGA measurement unit as described in the first aspect, and the method includes: for each channel, the following steps are performed: sending a pulse signal to a connection point in the channel through a pulse signal sending unit, so that the pulse signal reaches a sampling register through a receiver and a delay adjustment module; detecting a first clock cycle and a second clock cycle corresponding to when the sampling register receives the pulse signal; the sampling values corresponding to the first clock cycle and the second clock cycle are 0 and 1 respectively; adjusting the delay time corresponding to the delay adjustment module until a sampling value jump condition is satisfied, and taking the delay time that satisfies the condition as the target delay time corresponding to the channel; the sampling value jump condition includes: the sampling value corresponding to the second clock cycle jumps to 0, or the sampling value corresponding to the first clock cycle jumps to 1; storing the target delay time corresponding to the channel; performing channel delay compensation according to the stored target delay times corresponding to multiple channels respectively.

[0006] Further, the above pulse signal sending unit includes: a synchronous pulse sending flip-flop, a data transmitter, and an SMA interface connected in sequence; the SMA interface is connected to the connection point of the device under test; the step of sending a pulse signal to the connection point in the channel through the pulse signal sending unit includes: sending a pulse signal synchronized with the system clock to the connection point in the channel through the synchronous pulse sending flip-flop, the data transmitter, and the SMA interface.

[0007] Further, the above sampling value jump condition includes: the sampling value corresponding to the second clock cycle jumps to 0; the initial value of the delay time corresponding to the delay adjustment module is 0; the step of adjusting the delay time corresponding to the delay adjustment module until the sampling value jump condition is satisfied includes: increasing the delay time corresponding to the delay adjustment module at a specified time interval, and taking the increased delay time as the candidate delay time; judging whether the current sampling value corresponding to the second clock cycle is 0 under the action of the candidate delay time; if not, continue to execute the step of increasing the delay time corresponding to the delay adjustment module at the specified time interval; if so, determining the candidate delay time when the sampling value jumps to 0 as the target delay time.

[0008] Further, the above sampling value jump condition includes: the sampling value corresponding to the first clock cycle jumps to 1; the initial value of the delay time corresponding to the delay adjustment module is the default maximum value; the step of adjusting the delay time corresponding to the delay adjustment module until the sampling value jump condition is satisfied includes: reducing the delay time corresponding to the delay adjustment module at a specified time interval, and taking the reduced delay time as the candidate delay time; determining whether the current sampling value corresponding to the first clock cycle is 1 under the action of the candidate delay time; if not, continuing to execute the step of reducing the delay time corresponding to the delay adjustment module at a specified time interval; if so, determining the candidate delay time when the sampling value jumps to 1 as the target delay time.

[0009] Further, the above logic unit is also connected to a memory; the step of storing the target delay time corresponding to the channel includes: storing the target delay time corresponding to the channel in the memory.

[0010] Further, the above step of performing multi-channel delay compensation according to the target delay times corresponding to multiple stored channels includes: when the measurement unit is started, loading the target delay times corresponding to multiple channels from the memory into the delay adjustment module, so that the delay adjustment module performs channel delay compensation according to the target delay times corresponding to multiple channels.

[0011] Further, after the step of sending a pulse signal to the connection point corresponding to the channel through the pulse signal sending unit, it further includes: recording the pulse signal sending time; the method further includes: for each channel, calculating the pulse signal receiving time corresponding to the channel according to the target delay time corresponding to the channel and the pulse signal sending time.

[0012] Further, the above step of calculating the pulse signal receiving time corresponding to the channel according to the target delay time corresponding to the channel and the pulse signal sending time includes: if the sampling value jump condition is: the sampling value corresponding to the second clock cycle jumps to 0, calculating the pulse signal receiving time corresponding to the channel according to the following formula:

[0013] t1 - t0 = count2 * period - idelay0;

[0014] where, t1 represents the pulse signal receiving time; t0 represents the pulse signal sending time; count2 represents the number of cycles corresponding to the second clock cycle; period represents the system clock cycle; idelay0 represents the target delay time;

[0015] If the sampling value jump condition is: the sampling value corresponding to the first clock cycle jumps to 1, calculating the pulse signal receiving time corresponding to the channel according to the following formula:

[0016] t2 - t0 = count1 * period + idelay0;

[0017] Among them, t2 represents the pulse signal reception time; t0 represents the pulse signal transmission time; count1 represents the number of cycles corresponding to the first clock cycle; period represents the system clock cycle; idelay0 represents the target delay time.

[0018] In a third aspect, an embodiment of the present application further provides a channel delay compensation device based on an FPGA measurement unit. The device is applied to the FPGA measurement unit as described in the first aspect. The device includes: a pulse signal transmission module, configured to, for each channel, send a pulse signal to a connection point in the channel through a pulse signal transmission unit, so that the pulse signal reaches a sampling register through a receiver and a delay adjustment module; a clock cycle detection module, configured to detect a first clock cycle and a second clock cycle corresponding to when the sampling register receives the pulse signal; the sampling values corresponding to the first clock cycle and the second clock cycle are 0 and 1 respectively; a delay time adjustment module, configured to adjust the delay time corresponding to the delay adjustment module until the sampling value jump condition is satisfied, and use the delay time that satisfies the condition as the target delay time corresponding to the channel; the sampling value jump condition includes: the sampling value corresponding to the second clock cycle jumps to 0, or the sampling value corresponding to the first clock cycle jumps to 1; a delay time storage module, configured to store the target delay time corresponding to the channel; a channel delay compensation module, configured to perform channel delay compensation according to the target delay times corresponding to multiple stored channels.

[0019] In the FPGA measurement unit and the channel delay compensation method and device based on the FPGA measurement unit provided by the embodiments of the present application, the FPGA measurement unit includes: a logic unit and a pulse signal transmission unit and multiple input / output units connected to the logic unit; the input / output unit includes: a receiver, a delay adjustment module, and a sampling register connected in sequence; the sampling register and the pulse signal transmission unit are connected to the same system clock; the pulse signal transmission unit is connected to multiple connection points in the device under test; multiple connection points are respectively connected to multiple receivers in one-to-one correspondence; a complete path from one connection point to one sampling register is one channel; the delay adjustment module is configured to compensate for the delay deviation between channels. The measurement unit can perform delay compensation on the delay times corresponding to each channel through the delay adjustment module, thereby eliminating the deviation influence of the measurement unit itself, completing the self-calibration of the measurement unit, and thus improving the measurement accuracy. Description of the Drawings

[0020] To more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings required for the description of the specific embodiments or the prior art. Obviously, the accompanying drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0021] Figure 1 A schematic diagram of the working of a test unit provided by an embodiment of the present application;

[0022] Figure 2 A block diagram of the structure of a measurement unit provided by an embodiment of the present application;

[0023] Figure 3 A schematic diagram of the circuit structure of a measurement unit provided by an embodiment of the present application;

[0024] Figure 4 A flowchart of a multi-channel delay compensation method for a measurement unit provided by an embodiment of the present application;

[0025] Figure 5 An effect diagram of delay deviation compensation provided by an embodiment of the present application;

[0026] Figure 6 A block diagram of the structure of a multi-channel delay compensation device for a measurement unit provided by an embodiment of the present application. Specific Embodiments

[0027] The following will clearly and completely describe the technical solutions of the present application in combination with the embodiments. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application.

[0028] See Figure 1As shown in the figure, in an ATE device, an external measurement unit or device is usually used to measure the time delay deviation of all signals in each SLOT slot to the POGO connector. To ensure the measurement accuracy, the measurement unit itself must not introduce additional deviation. However, there are often delay deviations between different channels in the measurement unit implemented based on FPGA, including trace delay, device delay, sampling clock delay, etc. To eliminate the delay of the measurement unit itself and improve the measurement accuracy, the prior art usually uses the method of setting timing constraints for processing. Through the constraints, the internal traces of the FPGA can be preferentially arranged according to the set values. However, the constraint accuracy of this method is relatively low, usually in the order of ns, and it cannot completely eliminate the influence of the deviation introduced by the measurement unit itself, thus unable to meet the requirements of high-speed and high-precision applications. Based on this, the embodiments of the present application provide an FPGA measurement unit, a channel delay compensation method and device based on the FPGA measurement unit, which can accurately compensate the delay between multiple channels, thereby eliminating the deviation influence of the measurement unit itself and completing the self-calibration of the measurement unit.

[0029] To facilitate the understanding of this embodiment, first, a measurement unit disclosed in the embodiments of the present application will be introduced in detail.

[0030] The embodiments of the present application provide a measurement unit. Refer to Figure 2 As shown in the figure, the measurement unit includes: a logic unit, a pulse signal sending unit connected to the logic unit, and a plurality of input / output units; the input / output unit includes: a receiver, a delay adjustment module, and a sampling register connected in sequence; the sampling register and the pulse signal sending unit are connected to the same system clock; the pulse signal sending unit is connected to a plurality of connection points in the device under test; the plurality of connection points are respectively connected to a plurality of receivers in one-to-one correspondence; a complete path from one connection point to one sampling register is a channel; the delay adjustment module is used to compensate for the delay deviation between channels.

[0031] The measurement unit can compensate for the delay time corresponding to each channel through the delay adjustment module, thereby eliminating the deviation influence of the measurement unit itself, completing the self-calibration of the measurement unit, and improving the measurement accuracy.

[0032] The above-mentioned device under test can be a connector, which is physically connected by inserting and unplugging cables, or can be a connection component such as a pad or via that can realize line connection. Hereinafter, the device under test is taken as an example of a connector for illustration. Refer to Figure 3 As shown in the figure, the devices corresponding to the reference numerals in the figure are as follows:

[0033] ① The IOB module inside the FPGA, that is, the above-mentioned input / output unit. The module internally includes a data transmitter TX, a data receiver RX, a delay adjustment module IDELAY, and a sampling register;

[0034] ② An SMA interface, used to output a synchronization pulse signal, and the signal can be sequentially connected to different connection points of the connector through a coaxial cable, such as TC0 - TC255;

[0035] ③ A connector, and the signal is connected to the test channel interface of the FPGA through physical traces;

[0036] ④ A system clock CLK, and all signal transmissions and samplings are synchronized with this clock;

[0037] ⑤ The FPGA test channel interface, usually including dozens to hundreds of channels, is connected to the signal under test through a connector or a cable;

[0038] ⑥ A synchronization pulse transmission trigger, used to send a pulse signal synchronized with the system clock;

[0039] ⑦ A signal reception sampling register, used to receive the pulse signal;

[0040] ⑧ An IDELAY module, with built - in PVT real - time compensation and supporting ps - level time delay adjustment;

[0041] From Figure 3 it can be seen that a channel refers to the total complete circuit corresponding to Tpcb, Tpackage, and Tiob, that is, the complete circuit from TC0 to the sampling register. Among them, Tpcb represents the trace delay, Tpackage represents the device delay, and Tiob represents the circuit logic synthesis delay. These delays will seriously affect the measurement accuracy when measured by the measurement unit. Therefore, it is necessary to perform deviation compensation on the above - mentioned multiple delays through the method in this application. The logic unit of the aforementioned measurement unit, that is, Logic corresponding to the figure, is used to execute the multi - channel delay compensation method of the measurement unit provided in the following embodiments. The specific implementation process is as follows.

[0042] Based on the above - mentioned FPGA measurement unit, an embodiment of the present application also provides a channel delay compensation method based on the FPGA measurement unit. This method is applied to the FPGA measurement unit as described in the previous embodiment; see Figure 4 As shown, the method of this embodiment specifically includes the following steps:

[0043] Step S402, for each channel, the following steps are all executed:

[0044] Step S4022, send a pulse signal to the connection point in the channel through the pulse signal transmission unit, so that the pulse signal reaches the sampling register through the receiver and the delay adjustment module.

[0045] From Figure 3As can be seen from the figure shown, the pulse signal sending unit includes: a synchronization pulse sending flip-flop, a data transmitter, and an SMA interface connected in sequence; the SMA interface is connected to the connection point of the connector, such as TCO; through the synchronization pulse sending flip-flop, the data transmitter, and the SMA interface, a pulse signal synchronized with the system clock can be sent to the connection point in the channel. Then, the pulse signal reaches the sampling register through the receiver and the delay adjustment module in the input-output unit.

[0046] Step S4024: Detect the first clock cycle and the second clock cycle corresponding to when the sampling register receives the pulse signal; the sampling values corresponding to the first clock cycle and the second clock cycle are 0 and 1 respectively.

[0047] That is, detect the rising edge time when the sampling register receives the pulse signal, such as Figure 5 As shown, the rising edge time corresponds to two consecutive clock cycles. For the previous clock cycle, that is, the first clock cycle mentioned above, the corresponding sampling value is 0, and for the subsequent clock cycle, that is, the second clock cycle mentioned above, the corresponding sampling value is 1. That is, a transition from 0 to 1 occurs, indicating that the pulse signal has been acquired. As Figure 3 shown, the cycle numbers corresponding to the first clock cycle and the second corresponding cycle are count1 and count2 respectively.

[0048] Step S4026: Adjust the delay time corresponding to the delay adjustment module until the sampling value jump condition is met, and use the delay time that meets the condition as the target delay time corresponding to the channel; the sampling value jump condition includes: the sampling value corresponding to the second clock cycle jumps to 0, or the sampling value corresponding to the first clock cycle jumps to 1.

[0049] Since a pulse signal corresponds to two clock cycles, the delay time corresponding to the delay adjustment module can be adjusted so that the time when all channels receive the pulse signal is aligned with the rising edge of any one of the clock cycles. That is, the sampling value jump condition includes two cases: the sampling value corresponding to the second clock cycle jumps to 0, or the sampling value corresponding to the first clock cycle jumps to 1.

[0050] When the sampling value jump condition is that the sampling value corresponding to the second clock cycle jumps to 0, when adjusting the delay time corresponding to the delay adjustment module, it can start from a delay time of 0 and gradually increase the delay time at a specified time interval, and judge in real time whether the sampling value has jumped, from 1 to 0, under the action of the currently increased delay time. Similarly, when the sampling value jump condition is that the sampling value corresponding to the first clock cycle jumps to 1, when adjusting the delay time corresponding to the delay adjustment module, it can start from the default maximum delay time and gradually decrease the delay time at a specified time interval, and judge in real time whether the sampling value has jumped, from 0 to 1, under the action of the currently decreased delay time.

[0051] Determine the delay time when the jump condition is satisfied as the target delay time corresponding to this channel.

[0052] Step S4028, store the target delay time corresponding to the channel.

[0053] Store the target delay time corresponding to the channel in a memory, such as FLASH, a non-volatile memory.

[0054] Step S404, perform channel delay compensation according to the stored target delay times corresponding to multiple channels respectively. When the measurement unit is started, the target delay times corresponding to multiple channels can be loaded from the memory into the delay adjustment module, so that the delay adjustment module performs channel delay compensation according to the target delay times corresponding to multiple channels respectively.

[0055] The channel delay compensation method based on the FPGA measurement unit provided by the embodiment of the present application can detect the time of the rising edge of the pulse signal received by the sampling register, that is, the first clock cycle and the second clock cycle, use the jump of the sampling value in any of the above cycles as the judgment condition, adjust the delay time until the above judgment condition is satisfied, obtain the target delay time corresponding to each channel, and further perform delay compensation on the target delay time corresponding to each channel, so as to eliminate the deviation influence of the measurement unit itself, complete the self-calibration of the measurement unit, and thus improve the measurement accuracy.

[0056] The embodiment of the present application also provides another channel delay compensation method based on the FPGA measurement unit, which is implemented on the basis of the above embodiment; this embodiment focuses on describing the determination process and compensation process of the target delay time.

[0057] In the case where the jump condition of the above sampling value is that the sampling value corresponding to the second clock cycle jumps to 0; the initial value of the delay time corresponding to the delay adjustment module is set to 0; the step of adjusting the delay time corresponding to the delay adjustment module until the sampling value jump condition is satisfied includes: increasing the delay time corresponding to the delay adjustment module at a specified time interval, and taking the increased delay time as the candidate delay time; judging whether the current sampling value corresponding to the second clock cycle is 0 under the action of the candidate delay time; if not, continue to execute the step of increasing the delay time corresponding to the delay adjustment module at a specified time interval; if so, determine the candidate delay time when the sampling value jumps to 0 as the target delay time.

[0058] For example, the initial value of the delay time is 0. Assuming that the specified time interval is 5, if the current sampling value corresponding to the detected second clock cycle is 1, then the delay time is continuously increased. For example, the delay time is set to 5. If the current sampling value corresponding to the detected second clock cycle is still 1, the delay time is continuously increased and adjusted to 10, and then the detection continues... For example, when the delay time is increased to 15, the current sampling value corresponding to the detected second clock cycle jumps to 0. At this time, the delay time 15 can be determined as the target delay time. It should be noted that in order to determine a more accurate delay time, the specified time interval can be set to a smaller value.

[0059] In the case where the sampling value jump condition is that the sampling value corresponding to the first clock cycle jumps to 1; the initial value of the delay time corresponding to the delay adjustment module can be set to the default maximum value; the steps of adjusting the delay time corresponding to the delay adjustment module until the sampling value jump condition is met include: reducing the delay time corresponding to the delay adjustment module at the specified time interval, and taking the reduced delay time as the candidate delay time; determining whether the current sampling value corresponding to the first clock cycle is 1 under the action of the candidate delay time; if not, continue to execute the step of reducing the delay time corresponding to the delay adjustment module at the specified time interval; if so, determining the candidate delay time when the sampling value jumps to 1 as the target delay time. This process is similar to the previous process and will not be elaborated here.

[0060] In order to detect the result of delay compensation, after the step of sending a pulse signal to the connection point corresponding to the channel through the pulse signal sending unit, the following steps may further be included: recording the pulse signal sending time; the method further includes: for each channel, calculating the pulse signal receiving time corresponding to the channel according to the target delay time and the pulse signal sending time corresponding to the channel. By comparing the pulse signal receiving times corresponding to each channel, the delay compensation effect can be obtained.

[0061] The specific calculation method of the pulse signal receiving time is as follows: If the sampling value jump condition is that the sampling value corresponding to the second clock cycle jumps to 0, calculate the pulse signal receiving time corresponding to the channel according to the following formula:

[0062] t1 - t0 = count2 * period - idelay0;

[0063] where, t1 represents the pulse signal receiving time; t0 represents the pulse signal sending time; count2 represents the number of cycles corresponding to the second clock cycle; period represents the system clock cycle; idelay0 represents the target delay time;

[0064] If the sampling value jump condition is that the sampling value corresponding to the first clock cycle jumps to 1, calculate the pulse signal reception time corresponding to the channel according to the following formula:

[0065] t2 - t0 = count1 * period + idelay0;

[0066] Where, t2 represents the pulse signal reception time; t0 represents the pulse signal transmission time; count1 represents the number of cycles corresponding to the first clock cycle; period represents the system clock cycle; idelay0 represents the target delay time.

[0067] The following takes the Figure 3 shown measurement unit as an example to illustrate the compensation process:

[0068] 1. The synchronization pulse transmission flip - flop sends a pulse signal synchronized with the system clock to the SMA port, and records the time at this moment, that is, the pulse transmission time, as t0(start) = 0;

[0069] 2. Connect the SMA port to the connection point TC0 of the connector through a coaxial cable. At this time, the pulse signal will pass through the Tpcb, Tpackage, Tiob, and IDELAY modules and finally be sampled by the sampling register;

[0070] 3. The sampling register first judges the rough position of the rising edge of the pulse signal according to the first clock cycle count1 (corresponding sampling value is 0) and the second clock cycle count2 (corresponding sampling value is 1);

[0071] 4. Then continuously adjust the delay value of the IDELAY module until the sampling value at count2 jumps to 0, or the sampling value at count1 jumps to 1, and record the adjustment value of the IDELAY module at this time as idelay0;

[0072] 5. Calculate the time when the pulse signal reaches the sampling register, that is, the above - mentioned pulse signal reception time, which can be obtained through the previous two methods;

[0073] 6. Connect the SMA signal to the remaining connection points of the connector in turn, and repeat the above operations to obtain the adjustment values of IDELAY corresponding to the remaining all channels as idelay1, idelay2,..., idelay255. This value is the delay time that needs to be compensated;

[0074] 7. Store the idelay values of all channels in the Flash, and load this value into the IDELAY module when the FPGA starts to ensure that the delay between all channels is calibrated.

[0075] See Figure 5As shown, the compensation final effect is illustrated. CLK0 and CLK255 respectively represent the clocks of the system clock to the sampling registers at connection point TC0 and connection point TC255. Since there is a certain delay in the clock line, there will be a certain phase deviation between the two. At the same time, there will also be a difference in the time when the pulse signal output by SMA is sent to the sampling registers of the two channels, that is Figure 6 t0 and t255 in Figure 6 . This part of the difference is mainly caused by the line deviation of Tpcb+Tpackage+Tiob. After measurement by the method described above, the delay compensation values idelay0 and idelay255 of the two channels are obtained respectively. After compensation by the IDELAY module, the rising edges of the pulse signals of the two channels are respectively aligned with the rising edge of their respective sampling clock count2, as shown by the red dotted line pulse. In this way, the deviation between channels caused by clock phase deviation and line deviation is compensated. Therefore, when actually measuring the measured signal sent by a certain SLOT single board, the measured deviation value is the real deviation of the measured signal, and does not include the deviation between channels of the measurement unit itself.

[0076] The channel delay compensation method based on the FPGA measurement unit provided in the embodiment of the present application can accurately measure the target delay time of the complete channel path inside the FPGA, including physical line delay, logic device delay and clock delay. Then, delay compensation is performed on the target delay time corresponding to each channel, so as to eliminate the deviation influence of the measurement unit itself, complete the self-calibration of the measurement unit, and improve the measurement accuracy of the measurement unit.

[0077] Based on the above method embodiment, the embodiment of the present application further provides a channel delay compensation device based on the FPGA measurement unit. This device is applied to the FPGA measurement unit described in the first embodiment; see Figure 6 As shown, this device includes:

[0078] The pulse signal sending module 602 is used to send a pulse signal to the connection point in the channel through the pulse signal sending unit for each channel, so that the pulse signal reaches the sampling register through the receiver and the delay adjustment module; the clock cycle detection module 604 is used to detect the first clock cycle and the second clock cycle corresponding to when the sampling register receives the pulse signal; the sampling values corresponding to the first clock cycle and the second clock cycle are 0 and 1 respectively; the delay time adjustment module 606 is used to adjust the delay time corresponding to the delay adjustment module until the sampling value jump condition is met, and use the delay time that meets the condition as the target delay time corresponding to the channel; the sampling value jump condition includes: the sampling value corresponding to the second clock cycle jumps to 0, or the sampling value corresponding to the first clock cycle jumps to 1; the delay time storage module 608 is used to store the target delay time corresponding to the channel; the channel delay compensation module 610 is used to perform channel delay compensation according to the target delay times corresponding to multiple channels stored respectively.

[0079] The above-mentioned pulse signal sending unit includes: a synchronous pulse sending flip-flop, a data transmitter and an SMA interface connected in sequence; the SMA interface is connected to the connection point of the device under test; the above-mentioned pulse signal sending module 602 is used to send a pulse signal synchronized with the system clock to the connection point in the channel through the synchronous pulse sending flip-flop, the data transmitter and the SMA interface.

[0080] The above-mentioned sampling value jump condition includes: the sampling value corresponding to the second clock cycle jumps to 0; the initial value of the delay time corresponding to the delay adjustment module is 0; the above-mentioned delay time adjustment module 606 is used to increase the delay time corresponding to the delay adjustment module at a specified time interval, and use the increased delay time as the candidate delay time; determine whether the current sampling value corresponding to the second clock cycle is 0 under the action of the candidate delay time; if not, continue to execute the step of increasing the delay time corresponding to the delay adjustment module at a specified time interval; if so, determine the candidate delay time when the sampling value jumps to 0 as the target delay time.

[0081] The above-mentioned sampling value jump condition includes: the sampling value corresponding to the first clock cycle jumps to 1; the initial value of the delay time corresponding to the delay adjustment module is the default maximum value; the above-mentioned delay time adjustment module 606 is used to decrease the delay time corresponding to the delay adjustment module at a specified time interval, and use the decreased delay time as the candidate delay time; determine whether the current sampling value corresponding to the first clock cycle is 1 under the action of the candidate delay time; if not, continue to execute the step of decreasing the delay time corresponding to the delay adjustment module at a specified time interval; if so, determine the candidate delay time when the sampling value jumps to 1 as the target delay time.

[0082] The above-mentioned logic unit is also connected to a memory; the above-mentioned delay time storage module 608 is used to store the target delay time corresponding to the channel in the memory.

[0083] The above-mentioned channel delay compensation module 610 is used to load the target delay times corresponding to multiple channels from the memory into the delay adjustment module when the measurement unit is started, so that the delay adjustment module performs channel delay compensation according to the target delay times corresponding to multiple channels.

[0084] The above-mentioned device further includes: a time recording module for recording the pulse signal transmission time; the above-mentioned device further includes: a time calculation module for calculating, for each channel, the pulse signal reception time corresponding to the channel according to the target delay time corresponding to the channel and the pulse signal transmission time.

[0085] The above-mentioned time calculation module is further used to calculate the pulse signal reception time corresponding to the channel according to the following formula if the sampling value jump condition is: the sampling value corresponding to the second clock cycle jumps to 0:

[0086] t1 - t0 = count2 * period - idelay0;

[0087] Wherein, t1 represents the pulse signal reception time; t0 represents the pulse signal transmission time; count2 represents the number of cycles corresponding to the second clock cycle; period represents the system clock cycle; idelay0 represents the target delay time;

[0088] If the sampling value jump condition is: the sampling value corresponding to the first clock cycle jumps to 1, calculate the pulse signal reception time corresponding to the channel according to the following formula:

[0089] t2 - t0 = count1 * period + idelay0;

[0090] Wherein, t2 represents the pulse signal reception time; t0 represents the pulse signal transmission time; count1 represents the number of cycles corresponding to the first clock cycle; period represents the system clock cycle; idelay0 represents the target delay time.

[0091] The device provided by the embodiment of the present application has the same implementation principle and the same technical effects as those of the foregoing method embodiment. For the sake of brief description, for the parts not mentioned in the device embodiment, reference may be made to the corresponding content in the foregoing method embodiment.

[0092] The embodiment of the present application further provides a computer-readable storage medium. The computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions cause the processor to implement the above-mentioned method. For the specific implementation, reference may be made to the foregoing method embodiment, and details are not described herein again.

[0093] The computer program product of the method, apparatus, and electronic device provided by the embodiments of the present application includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the method described in the foregoing method embodiments. For specific implementation, reference can be made to the method embodiments, which will not be elaborated herein.

[0094] Unless otherwise specifically stated, the relative steps, numerical expressions, and values of the components and steps set forth in these embodiments do not limit the scope of the present application.

[0095] If the above-mentioned functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program code.

[0096] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0097] Finally, it should be noted that the above-described embodiments are only specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, rather than limiting it. The protection scope of the present application is not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that any person skilled in the art within the technical scope disclosed by the present application can still modify the technical solutions recorded in the foregoing embodiments, or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An FPGA measurement unit, characterized in that, the measurement unit includes: a logic unit, a pulse signal sending unit connected to the logic unit, and a plurality of input / output units; the input / output unit includes: a receiver, a delay adjustment module, and a sampling register connected in sequence; the sampling register and the pulse signal sending unit are connected to the same system clock; the pulse signal sending unit is connected to a plurality of connection points in the device under test; a plurality of the connection points are respectively connected to a plurality of the receivers in one-to-one correspondence; a complete path from one of the connection points to one of the sampling registers is a channel; the delay adjustment module is used to compensate for the delay deviation between channels; the compensation process includes: sending a pulse signal to the connection point in the channel through the pulse signal sending unit, so that the pulse signal reaches the sampling register through the receiver and the delay adjustment module; detecting a first clock cycle and a second clock cycle corresponding to when the sampling register receives the pulse signal; the sampling values corresponding to the first clock cycle and the second clock cycle are 0 and 1 respectively; adjusting the delay time corresponding to the delay adjustment module until the sampling value jump condition is met, and taking the delay time that meets the condition as the target delay time corresponding to the channel; the sampling value jump condition includes: the sampling value corresponding to the second clock cycle jumps to 0, or the sampling value corresponding to the first clock cycle jumps to 1; storing the target delay time corresponding to the channel; performing channel delay compensation according to the target delay times respectively corresponding to the stored multiple channels.

2. A method for compensating channel delay based on an FPGA measurement unit, characterized in that, the method is applied to the FPGA measurement unit according to claim 1, and the method includes: for each of the channels, the following steps are performed: sending a pulse signal to the connection point in the channel through the pulse signal sending unit, so that the pulse signal reaches the sampling register through the receiver and the delay adjustment module; detecting a first clock cycle and a second clock cycle corresponding to when the sampling register receives the pulse signal; the sampling values corresponding to the first clock cycle and the second clock cycle are 0 and 1 respectively; adjusting the delay time corresponding to the delay adjustment module until the sampling value jump condition is met, and taking the delay time that meets the condition as the target delay time corresponding to the channel; the sampling value jump condition includes: the sampling value corresponding to the second clock cycle jumps to 0, or the sampling value corresponding to the first clock cycle jumps to 1; storing the target delay time corresponding to the channel; performing channel delay compensation according to the target delay times respectively corresponding to the stored multiple channels.

3. The method according to claim 2, characterized in that, the pulse signal sending unit includes: a synchronous pulse sending flip-flop, a data transmitter, and an SMA interface connected in sequence; the SMA interface is connected to the connection point of the device under test; the step of sending a pulse signal to the connection point in the channel through the pulse signal sending unit includes: Send a pulse signal synchronized with the system clock to the connection point in the channel through the synchronization pulse sending trigger, the data transmitter, and the SMA interface.

4. The method according to claim 2, wherein, the sampling value jump condition includes: the sampling value corresponding to the second clock cycle jumps to 0; the initial value of the delay time corresponding to the delay adjustment module is 0; the step of adjusting the delay time corresponding to the delay adjustment module until the sampling value jump condition is met includes: increasing the delay time corresponding to the delay adjustment module at a specified time interval, and using the increased delay time as the candidate delay time; judging whether the current sampling value corresponding to the second clock cycle is 0 under the action of the candidate delay time; if not, continue to execute the step of increasing the delay time corresponding to the delay adjustment module at the specified time interval; if so, determining the candidate delay time when the sampling value jumps to 0 as the target delay time.

5. The method according to claim 2, wherein, the sampling value jump condition includes: the sampling value corresponding to the first clock cycle jumps to 1; the initial value of the delay time corresponding to the delay adjustment module is the default maximum value; the step of adjusting the delay time corresponding to the delay adjustment module until the sampling value jump condition is met includes: decreasing the delay time corresponding to the delay adjustment module at a specified time interval, and using the decreased delay time as the candidate delay time; judging whether the current sampling value corresponding to the first clock cycle is 1 under the action of the candidate delay time; if not, continue to execute the step of decreasing the delay time corresponding to the delay adjustment module at the specified time interval; if so, determining the candidate delay time when the sampling value jumps to 1 as the target delay time.

6. The method according to claim 2, wherein, the logic unit is further connected to a memory; the step of storing the target delay time corresponding to the channel includes: storing the target delay time corresponding to the channel in the memory.

7. The method according to claim 6, wherein, the step of performing multi-channel delay compensation according to the target delay times respectively corresponding to multiple stored channels includes: when the measurement unit is started, loading the target delay times respectively corresponding to multiple channels from the memory into the delay adjustment module, so that the delay adjustment module performs channel delay compensation according to the target delay times respectively corresponding to multiple channels.

8. The method according to claim 2, wherein, after the step of sending a pulse signal to the connection point corresponding to the channel through the pulse signal sending unit, it further includes: recording the pulse signal sending time; the method further includes: for each channel, calculating the pulse signal reception time corresponding to the channel according to the target delay time corresponding to the channel and the pulse signal sending time.

9. The method according to claim 8, wherein, The step of calculating the received time of the pulse signal corresponding to the channel according to the target delay time corresponding to the channel and the transmission time of the pulse signal includes: If the sampling value jump condition is that the sampling value corresponding to the second clock period jumps to 0, calculate the received time of the pulse signal corresponding to the channel according to the following formula: t1 - t0 = count2 * period - idelay0; where, t1 represents the received time of the pulse signal; t0 represents the transmission time of the pulse signal; count2 represents the number of periods corresponding to the second clock period; period represents the system clock period; idelay0 represents the target delay time; If the sampling value jump condition is that the sampling value corresponding to the first clock period jumps to 1, calculate the received time of the pulse signal corresponding to the channel according to the following formula: t2 - t0 = count1 * period + idelay0; where, t2 represents the received time of the pulse signal; t0 represents the transmission time of the pulse signal; count1 represents the number of periods corresponding to the first clock period; period represents the system clock period; idelay0 represents the target delay time.

10. A channel delay compensation device based on an FPGA measurement unit, characterized in that the device is applied to the FPGA measurement unit as described in claim 1, and the device includes: A pulse signal transmission module, configured to send a pulse signal to a connection point in each channel through the pulse signal transmission unit for each channel, so that the pulse signal reaches the sampling register through the receiver and the delay adjustment module; A clock period detection module, configured to detect the first clock period and the second clock period corresponding to when the sampling register receives the pulse signal; the sampling values corresponding to the first clock period and the second clock period are 0 and 1 respectively; A delay time adjustment module, configured to adjust the delay time corresponding to the delay adjustment module until the sampling value jump condition is met, and use the delay time that meets the condition as the target delay time corresponding to the channel; the sampling value jump condition includes: the sampling value corresponding to the second clock period jumps to 0, or the sampling value corresponding to the first clock period jumps to 1; A delay time storage module, configured to store the target delay time corresponding to the channel; A channel delay compensation module, configured to perform channel delay compensation according to the target delay times corresponding to multiple stored channels respectively.

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