Power semiconductor module structure based on copper-clad ceramic substrate layout

Abstract

The invention discloses a power semiconductor module structure based on a copper-clad ceramic substrate. In the structure, the copper-clad ceramic substrate is provided with an upper bridge, a lower bridge source and a gate PIN pin respectively. The copper-clad ceramic substrate is provided with an upper bridge copper-clad pattern on both sides, and two rows of lower bridge copper-clad patterns are arranged in the middle. A plurality of upper bridge and lower bridge power semiconductor chips are arranged at intervals between the upper bridge copper-clad patterns and the lower bridge copper-clad patterns. The positive busbar is connected to the upper bridge copper-clad patterns, and the positive busbar current is shunted through the upper bridge copper-clad patterns and then merged into the three-phase busbar. The three-phase busbar is connected to the lower bridge copper-clad patterns, and the three-phase busbar is shunted through the lower bridge copper-clad patterns and then merged into the negative busbar. The source and gate of a plurality of upper bridge power semiconductor chips are connected to the upper bridge source and gate PIN pins, and the source and gate of a plurality of lower bridge power semiconductor chips are connected to the lower bridge source and gate PIN pins. The structure realizes current sharing characteristics, ensures the open-tube consistency of the power semiconductor module, and improves the service life and performance of the power semiconductor module.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and in particular to a power semiconductor module structure based on a copper-clad ceramic substrate. Background Art

[0002] Power semiconductor modules are circuit modules that combine power semiconductor chips into a whole according to certain functional combinations. They have the advantages of small size and high power density, so they are widely used in the field of new energy vehicles. With the development of high-power and long-range new energy vehicles, the application environment of power semiconductor modules is becoming increasingly harsh, and the current sharing characteristics of power semiconductor modules have received extensive attention.

[0003] With the rapid development of new energy vehicles, Si-based and SiC-based power semiconductor modules have continued to develop. In these high-power application fields, higher and higher requirements are placed on the switching frequency of power semiconductor modules. In order to obtain higher rated currents and lower manufacturing costs, these power semiconductor modules usually adopt a multi-chip parallel packaging structure. However, due to the asymmetry of the current loop of the copper-clad ceramic substrate and the inconsistency of the dynamic and static parameters of the power chip, a large transient unbalanced current will appear between the parallel chips, which brings considerable challenges to the safety and stability of the power semiconductor module.

[0004] In the three-phase AC motor control system, the circuit diagram of the power semiconductor module is as follows Figure 1 As shown, multiple power semiconductor chips a1 to a6, b1 to b6 are connected in parallel in each phase circuit. Figure 2 The U phase circuit diagram is shown in Figure 2 In the circuit diagram, when the upper bridge power semiconductor chips a1 to a6 are turned on and the lower bridge power semiconductor chips b1 to b6 are turned off, the current Ia flows from the positive busbar to the three-phase busbar. The resistance value of the source and gate control loop signals of each power semiconductor chip, the inductance generated by the length, the resistance and inductance between the power semiconductor chips, etc. determine the opening time of each power semiconductor chip. Assuming that the switching time of power semiconductor chip a1 is earlier than that of other power semiconductor chips, a large current will flow through power semiconductor chip a1. In extreme cases, it will cause damage to power semiconductor chip a1. At the same time, if Figure 3 As shown, when the lower bridge power semiconductor chips b1 to b6 are turned on and the upper bridge power semiconductor chips a1 to a6 are turned off, the current Ia flows from the three-phase busbar to the negative busbar. In this case, as mentioned above, if the power semiconductor chip b3 closest to the three-phase busbar is turned on earlier than other power semiconductor chips, the current will flow through the power semiconductor chip b3, and in extreme cases, it will damage the power semiconductor chip b3. In this way, the service life and performance of the power semiconductor module are reduced, the control performance of the motor is seriously affected, and there are certain safety hazards. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a power semiconductor module structure based on a copper-clad ceramic substrate. The structure overcomes the defect of transient current imbalance between parallel chips of traditional power semiconductor modules, and realizes current sharing characteristics by adjusting the opening time of each power semiconductor chip, thereby ensuring the opening consistency of the power semiconductor module, improving the service life and performance of the power semiconductor module, and ensuring stable and reliable control of the motor.

[0006] In order to solve the above technical problems, the power semiconductor module structure arranged based on the copper-clad ceramic substrate of the present invention includes a heat sink, a plastic shell, a copper-clad ceramic substrate, a positive busbar, a negative busbar, a three-phase busbar, a bonding wire, a plurality of upper bridge power semiconductor chips and a plurality of lower bridge power semiconductor chips, wherein the copper-clad ceramic substrate is arranged on the surface of the heat sink, the plastic shell is arranged on the heat sink and covers the copper-clad ceramic substrate, the copper-clad ceramic substrate is respectively provided with an upper bridge source PIN needle, an upper bridge gate PIN needle and a lower bridge source PIN needle, and a lower bridge gate PIN needle, the copper-clad ceramic substrate is respectively provided with connected upper bridge copper-clad patterns on both sides, and two rows of lower bridge copper-clad patterns are arranged at intervals in the middle, the plurality of upper bridge power semiconductor chips are respectively arranged at intervals on the upper bridge copper-clad patterns, and the plurality of lower bridge power semiconductor chips are respectively arranged at intervals on the The lower bridge copper-clad patterns, the positive busbar is connected to the upper bridge copper-clad patterns, and the positive busbar current is shunted through the upper bridge copper-clad patterns on both sides of the copper-clad ceramic substrate and then merged into the three-phase busbar, the three-phase busbar is connected to the two columns of lower bridge copper-clad patterns in the middle of the copper-clad ceramic substrate, and the three-phase busbar is shunted through the two columns of lower bridge copper-clad patterns and then merged into the negative busbar, the source electrodes of the plurality of upper bridge power semiconductor chips are sequentially connected in series through the bonding wires and then connected to the upper bridge source PIN pin, the source electrodes of the plurality of lower bridge power semiconductor chips are sequentially connected in series through the bonding wires and then connected to the lower bridge source PIN pin, the gate electrodes of the plurality of upper bridge power semiconductor chips are connected to the upper bridge gate PIN pin through the bonding wires, and the gate electrodes of the plurality of lower bridge power semiconductor chips are connected to the lower bridge gate PIN pin through the bonding wires.

[0007] Furthermore, the upper bridge copper clad patterns on both sides of the copper clad ceramic substrate are provided with raised floating copper contacts between adjacent upper bridge power semiconductor chips, and the sources of the plurality of upper bridge power semiconductor chips are connected in series via the bonding wires to the raised floating copper contacts.

[0008] Furthermore, the spacing between adjacent chips of the plurality of upper bridge power semiconductor chips on the upper bridge copper clad lines is at least greater than or equal to half of the minimum side length of the chip, and the copper clad thickness on the surface of the copper clad ceramic substrate is 0.3-0.8 mm.

[0009] Furthermore, a control signal between the upper bridge source PIN pin and the upper bridge gate PIN pin and a control signal between the lower bridge source PIN pin and the lower bridge gate PIN pin are input from the outside, and the positions of the upper bridge source PIN pin and the upper bridge gate PIN pin on the copper-clad ceramic substrate are located outside the upper bridge power semiconductor chip farthest from the positive busbar, and the positions of the lower bridge source PIN pin and the lower bridge gate PIN pin on the copper-clad ceramic substrate are located outside the lower bridge power semiconductor chip farthest from the three-phase busbar.

[0010] Furthermore, the sum of the distances from the center of each chip among the several upper bridge power semiconductor chips to the positive busbar and the upper bridge source PIN pin is equal, and the upper bridge power semiconductor chip closest to the positive busbar is farthest from the upper bridge source PIN pin, and the upper bridge power semiconductor chip farthest from the positive busbar is closest to the upper bridge source PIN pin, and the sum of the distances from the center of each chip among the several lower bridge power semiconductor chips to the three-phase busbar and the lower bridge source PIN pin is equal, and the lower bridge power semiconductor chip closest to the three-phase busbar is farthest from the lower bridge source PIN pin, and the lower bridge power semiconductor chip farthest from the three-phase busbar is closest to the lower bridge source PIN pin.

[0011] Furthermore, the plurality of upper bridge power semiconductor chips and the plurality of lower bridge power semiconductor chips are at least four power semiconductor chips connected in parallel.

[0012] Since the power semiconductor module structure based on the copper-clad ceramic substrate of the present invention adopts the above technical solution, that is, the copper-clad ceramic substrate of the present structure is arranged on the surface of the radiator, the plastic shell is arranged on the radiator and covers the copper-clad ceramic substrate, the copper-clad ceramic substrate is respectively provided with an upper bridge source and a gate PIN needle, a lower bridge source and a gate PIN needle, the copper-clad ceramic substrate is provided with a connected upper bridge copper-clad pattern on both sides, and two rows of lower bridge copper-clad patterns are arranged at intervals in the middle, a number of upper bridge power semiconductor chips are arranged at intervals on the upper bridge copper-clad patterns, a number of lower bridge power semiconductor chips are arranged at intervals on the lower bridge copper-clad patterns, the positive busbar is connected to the upper bridge copper-clad patterns, and the positive busbar current After being shunted by the upper bridge copper-clad lines on both sides of the copper-clad ceramic substrate, the current is merged into the three-phase busbar, which is connected to the two columns of lower bridge copper-clad lines in the middle of the copper-clad ceramic substrate, and the three-phase busbar is shunted by the two columns of lower bridge copper-clad lines and then merged into the negative busbar. The source electrodes of several upper bridge power semiconductor chips are connected in series through bonding lines and then connected to the upper bridge source PIN pins, and the source electrodes of several lower bridge power semiconductor chips are connected in series through bonding lines and then connected to the lower bridge source PIN pins, and the gate electrodes of several upper bridge power semiconductor chips are connected to the upper bridge gate PIN pins through bonding lines, and the gate electrodes of several lower bridge power semiconductor chips are connected to the lower bridge gate PIN pins through bonding lines. This structure overcomes the defect of transient current imbalance between parallel chips in traditional power semiconductor modules, and realizes current sharing characteristics by adjusting the opening time of each power semiconductor chip, ensuring the opening consistency of the power semiconductor module, improving the service life and performance of the power semiconductor module, and ensuring stable and reliable control of the motor. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments:

[0014] Figure 1 It is the circuit diagram of the power semiconductor module in the three-phase AC motor control system;

[0015] Figure 2 for Figure 1 Schematic diagram of the current flow direction of the single-phase upper bridge;

[0016] Figure 3 for Figure 1 Schematic diagram of the flow direction of the single-phase lower bridge current;

[0017] Figure 4 It is a schematic diagram of the structure of a power semiconductor module arranged on a copper-clad ceramic substrate according to the present invention;

[0018] Figure 5 Schematic diagram of the copper-clad ceramic substrate in this structure with raised floating copper contacts;

[0019] Figure 6 It is the overall block diagram of the power semiconductor module;

[0020] Figure 7This is a schematic diagram of the single-phase internal signal connection of the power semiconductor module;

[0021] Figure 8 It is a schematic diagram of the signal connection and current flow of the single-phase upper half bridge of the power semiconductor module;

[0022] Fig. 9 It is a schematic diagram of the signal connection and current flow of the single-phase lower half bridge of the power semiconductor module;

[0023] Fig.10 This is the single-phase circuit schematic diagram of the power semiconductor module;

[0024] Fig.11 This is a schematic diagram of a resistor and inductor series circuit. DETAILED DESCRIPTION

[0025] Implementation example Figure 4 As shown, the power semiconductor module structure based on the copper-clad ceramic substrate of the present invention includes a heat sink 8, a plastic shell 3, a copper-clad ceramic substrate 4, a positive busbar 1, a negative busbar 2, a three-phase busbar 5, a bonding wire 7, a plurality of upper bridge power semiconductor chips a and a plurality of lower bridge power semiconductor chips b, the copper-clad ceramic substrate 4 is arranged on the surface of the heat sink 8, the plastic shell 3 is arranged on the heat sink 8 and covers the copper-clad ceramic substrate 4, the copper-clad ceramic substrate 4 is respectively provided with an upper bridge source PIN needle S1, an upper bridge gate PIN needle G1 and a lower bridge source PIN needle S2, a lower bridge gate PIN needle G2, the copper-clad ceramic substrate 4 is respectively provided with connected upper bridge copper-clad patterns 41 on both sides, and two rows of lower bridge copper-clad patterns 42 are arranged at intervals in the middle, the plurality of upper bridge power semiconductor chips a are respectively arranged at intervals on the upper bridge copper-clad patterns 41, and the plurality of lower bridge power semiconductor chips b are respectively arranged at intervals on the lower bridge copper-clad patterns The positive busbar 1 is connected to the upper bridge copper-clad pattern 41, and the current of the positive busbar 1 is shunted through the upper bridge copper-clad patterns 41 on both sides of the copper-clad ceramic substrate 4 and then merged into the three-phase busbar 5. The three-phase busbar 5 is connected to the two columns of lower bridge copper-clad patterns 42 in the middle of the copper-clad ceramic substrate 4, and the three-phase busbar 5 is shunted through the two columns of lower bridge copper-clad patterns 42 and then merged into the negative busbar 2. The sources of the plurality of upper bridge power semiconductor chips a are connected in series in sequence through the bonding line 7 and then connected to the upper bridge source PIN pin S1. The sources of the plurality of lower bridge power semiconductor chips b are connected in series in sequence through the bonding line 7 and then connected to the lower bridge source PIN pin S2. The gates of the plurality of upper bridge power semiconductor chips a are connected to the upper bridge gate PIN pin G1 through the bonding line 7, and the gates of the plurality of lower bridge power semiconductor chips b are connected to the lower bridge gate PIN pin G2 through the bonding line 7.

[0026] Preferably, Figure 5As shown, the upper bridge copper-clad patterns 41 on both sides of the copper-clad ceramic substrate 4 are provided with protruding floating copper contacts c between adjacent upper bridge power semiconductor chips a, and the source electrodes of the plurality of upper bridge power semiconductor chips a are connected in series through the bonding wires 7 to the protruding floating copper contacts c. The provision of the protruding floating copper contacts can reduce the length of the bonding wires, improve the vibration resistance of the bonding wires, and thus improve the vibration resistance of the power semiconductor chips.

[0027] Preferably, the spacing between adjacent chips of the plurality of upper bridge power semiconductor chips a on the upper bridge copper clad pattern 41 is at least greater than or equal to half of the minimum side length of the chip, and the copper clad thickness on the surface of the copper clad ceramic substrate 4 is 0.3-0.8 mm. By increasing the distance between the chips, the inductance in the current path is increased, thereby suppressing the large current that flows through the power semiconductor chip when it is turned on.

[0028] Preferably, the control signal between the upper bridge source PIN pin S1 and the upper bridge gate PIN pin G1 and the control signal between the lower bridge source PIN pin S2 and the lower bridge gate PIN pin G2 are input from the outside, and the upper bridge source PIN pin S1 and the upper bridge gate PIN pin G1 are located on the copper-clad ceramic substrate 4 outside the upper bridge power semiconductor chip a farthest from the positive busbar 1, and the lower bridge source PIN pin S2 and the lower bridge gate PIN pin G2 are located on the copper-clad ceramic substrate 4 outside the lower bridge power semiconductor chip b farthest from the three-phase busbar 5. By adjusting the different positions of the control signal PIN pins from the power semiconductor chips, the resistance and inductance of the control signal to different power semiconductor chips are adjusted, and the delay time away from the control signal PIN pin is the longest, thereby suppressing the current of the farthest power semiconductor chip.

[0029] Preferably, the sum of the distances from the center of each chip in the plurality of upper bridge power semiconductor chips a to the positive busbar 1 and the upper bridge source PIN pin S1 is equal, and the upper bridge power semiconductor chip a closest to the positive busbar 1 is farthest from the upper bridge source PIN pin S1, and the upper bridge power semiconductor chip a farthest from the positive busbar 1 is closest to the upper bridge source PIN pin S1, and the sum of the distances from the center of each chip in the plurality of lower bridge power semiconductor chips b to the three-phase busbar 5 and the lower bridge source PIN pin S2 is equal, and the lower bridge power semiconductor chip b closest to the three-phase busbar 5 is farthest from the lower bridge source PIN pin S2, and the lower bridge power semiconductor chip b farthest from the three-phase busbar 5 is closest to the lower bridge source PIN pin S2. Through the above arrangement, the inductance of the current loop and the inductance of the control signal loop are balanced, and current balancing of different chips is achieved.

[0030] Preferably, the plurality of upper bridge power semiconductor chips a and the plurality of lower bridge power semiconductor chips b are at least four power semiconductor chips connected in parallel.

[0031] This structure utilizes the inductance of the source and gate control loop signal lines and the inductance of the current path applied to multiple power semiconductor chips connected in parallel, and achieves the purpose of delay by applying the source and gate signals to the upper bridge power semiconductor chip close to the positive bus later than other upper bridge power semiconductor chips, without the need to use a special delay circuit. In addition, the source and gate signals of the lower bridge power semiconductor chip near the three-phase bus are later than other lower bridge power semiconductor chips, so the large current will not be instantly concentrated on the lower bridge power semiconductor chip near the three-phase bus. In addition, by respectively providing an upper bridge copper-clad pattern and a lower bridge copper-clad pattern in the form of long copper plates on the copper-clad ceramic substrate, and respectively arranging the upper bridge power semiconductor chip and the lower bridge power semiconductor chip on the upper bridge copper-clad pattern and the lower bridge copper-clad pattern, a large inductance is formed between the power semiconductor chips, which can suppress the instantaneous large-scale current flowing when the power semiconductor chip is turned on.

[0032] like Figure 6 As shown, this structure is suitable for a power module in which a positive busbar 1 and a negative busbar 2 are provided on one side of a copper-clad ceramic substrate 4, a three-phase busbar 5 is provided on the other side, and four or more power semiconductor chips are connected in parallel in each phase to carry large current.

[0033] Figure 7 It is a schematic diagram of one phase of a power semiconductor module that generates three-phase alternating current, with six power semiconductor chips connected in parallel. The upper bridge power semiconductor chips a1, a2, a3, a4, a5, and a6 are respectively arranged on two rows of copper-clad patterns 41 on both sides of the copper-clad ceramic substrate, and the two rows of copper-clad patterns 41 are connected between the positive busbar 1; the lower bridge power semiconductor chips b1, b2, b3, b4, b5, and b6 are respectively arranged on two rows of copper-clad patterns 42 in the middle of the copper-clad ceramic substrate, and the three-phase busbar 5 is connected between the two rows of copper-clad patterns 42.

[0034] like Figure 8 As shown, the upper bridge power semiconductor chips a1, a2, a3, a4, a5, and a6 are respectively arranged on two rows of copper-clad lines 41 on the surface of the copper-clad ceramic substrate, and the positive busbar 1 is connected to the two rows of copper-clad lines 41. The current flowing into the positive busbar 1 is divided on the copper-clad lines 41 where the upper bridge power semiconductor chips are located, and then merged into the three-phase busbar 5. Fig. 9As shown, the lower bridge power semiconductor chips b1, b2, b3, b4, b5, and b6 are respectively arranged on two rows of copper-clad lines 42 in the middle of the surface of the copper-clad ceramic substrate, and the three-phase busbar 5 is connected to the two rows of copper-clad lines 42. The current flowing into the three-phase busbar 5 is divided on the copper-clad lines 42 where the lower bridge power semiconductor chips are located, and then merged into the negative busbar 2. The current is divided into two parts, which can reduce the current concentrated through a single power semiconductor chip. In addition, by dividing the current path into two, the distance between the power semiconductor chips can be lengthened, the inductance can be increased, and the current that flows instantly and significantly when the power module is turned on can be suppressed.

[0035] also, Fig.10 yes Figure 7 The equivalent circuit shown in FIG. In the gate signal of each power semiconductor chip connecting the upper bridge and the lower bridge, the inductance Lgt and Lgu formed by the length of the gate signal line are generated. In addition, between the positive busbar 1 and the upper bridge power semiconductor chip, and between the upper bridge power semiconductor chips, the inductance Ldt and Ldu formed by the width, length and thickness of the copper plate on the copper-clad ceramic substrate are generated.

[0036] The gate signal Vgt transmitted to the upper bridge power semiconductor chip is connected to the positive busbar 1 in sequence from the upper bridge power semiconductor chip farthest away. That is, the upper bridge power semiconductor chips a1 and a4 closest to the positive busbar 1 have the largest cumulative inductance to the gate signal compared with other upper bridge power semiconductor chips, so the tube opening time can be delayed, and the current flowing through the upper bridge power semiconductor chips a1 and a4 can be delayed immediately after the upper bridge is turned on. In addition, the gate signal Vgu transmitted to the lower bridge power semiconductor chip is connected in sequence from the power semiconductor chip close to the three-phase busbar 5. That is, the lower bridge power semiconductor chips b3 and b6 closest to the three-phase busbar 5 have the largest cumulative inductance to the gate signal compared with other lower bridge power semiconductor chips, so the tube opening time can be delayed, so that the current flowing to the lower bridge power semiconductor chip is delayed.

[0037] At the same time, the inductance Ldt and Ldu between the power semiconductor chips can suppress the instantaneous large current flowing into the power semiconductor chip when the power semiconductor chip is turned on. Fig.11 The figure shows a series circuit of an inductor L and a resistor R. The inductor L represents the inductance between the power semiconductor chips, and the resistor R represents the resistance of the power semiconductor chips when they are turned on. In this circuit, the current i (t) generated instantly when the switch K is turned on is as shown in the following formula.

[0038]

[0039] That is, when the inductance is large, the current i(t) does not flow immediately even if the voltage E is applied. Based on this principle, by applying this structure, the current in each power semiconductor chip can be gradually increased, thereby reducing the influence of current concentration.

[0040] This structure increases the length of the source and gate loop signal lines of the power semiconductor chip through the copper-clad pattern design of the copper-clad ceramic substrate and the bonding wire connection, adjusts the opening time of each power semiconductor chip, ensures the consistency of the opening of each power semiconductor chip, thereby achieving current sharing characteristics and ensuring the opening reliability of the power semiconductor module.

Claims

1. A power semiconductor module structure based on a copper-clad ceramic substrate, comprising a heat sink, a plastic shell, a copper-clad ceramic substrate, a positive busbar, a negative busbar, a three-phase busbar, a bonding wire, a plurality of upper bridge power semiconductor chips and a plurality of lower bridge power semiconductor chips, wherein the copper-clad ceramic substrate is arranged on the surface of the heat sink, the plastic shell is arranged on the heat sink and covers the copper-clad ceramic substrate, and is characterized in that: The copper-clad ceramic substrate is respectively provided with an upper bridge source PIN pin, an upper bridge gate PIN pin, a lower bridge source PIN pin, and a lower bridge gate PIN pin. The copper-clad ceramic substrate is respectively provided with connected upper bridge copper-clad patterns on both sides, and two rows of lower bridge copper-clad patterns are arranged at intervals in the middle. The plurality of upper bridge power semiconductor chips are respectively arranged at intervals on the upper bridge copper-clad patterns, and the plurality of lower bridge power semiconductor chips are respectively arranged at intervals on the lower bridge copper-clad patterns. The positive busbar is connected to the upper bridge copper-clad patterns, and the positive busbar current is shunted through the upper bridge copper-clad patterns on both sides of the copper-clad ceramic substrate and then merged into the three-phase busbar. The three-phase busbar is connected to the two rows of lower bridge copper-clad patterns in the middle of the copper-clad ceramic substrate, and the three-phase busbar is shunted through the two rows of lower bridge copper-clad patterns and then merged into the negative busbar. The sources of the plurality of upper bridge power semiconductor chips are connected in series in sequence through the bonding lines and then connected to the upper bridge source PI N pin, the sources of the plurality of lower bridge power semiconductor chips are connected in series in sequence through the bonding line and then connected to the lower bridge source PIN pin, the gates of the plurality of upper bridge power semiconductor chips are connected to the upper bridge gate PIN pin through the bonding line, the gates of the plurality of lower bridge power semiconductor chips are connected to the lower bridge gate PIN pin through the bonding line, the control signal between the upper bridge source PIN pin and the upper bridge gate PIN pin and the control signal between the lower bridge source PIN pin and the lower bridge gate PIN pin are input from the outside, the positions of the upper bridge source PIN pin and the upper bridge gate PIN pin on the copper-clad ceramic substrate are located outside the upper bridge power semiconductor chip farthest from the positive busbar, and the positions of the lower bridge source PIN pin and the lower bridge gate PIN pin on the copper-clad ceramic substrate are located outside the lower bridge power semiconductor chip farthest from the three-phase busbar.

2. The power semiconductor module structure based on the copper-clad ceramic substrate according to claim 1 is characterized in that: The upper bridge copper clad patterns on both sides of the copper clad ceramic substrate are provided with protruding floating copper contacts between adjacent upper bridge power semiconductor chips, and the sources of the upper bridge power semiconductor chips are connected to the protruding floating copper contacts through the bonding wires to realize series connection.

3. The power semiconductor module structure based on the copper-clad ceramic substrate according to claim 1 or 2, characterized in that: The spacing between adjacent chips of the plurality of upper bridge power semiconductor chips on the upper bridge copper clad lines is at least greater than or equal to half of the minimum side length of the chip, and the copper clad thickness on the surface of the copper clad ceramic substrate is 0.3-0.8 mm.

4. The power semiconductor module structure based on the copper-clad ceramic substrate according to claim 3 is characterized in that: The sum of the distances from the center of each chip among the several upper bridge power semiconductor chips to the positive busbar and the upper bridge source PIN pin is equal, and the upper bridge power semiconductor chip closest to the positive busbar is farthest from the upper bridge source PIN pin, and the upper bridge power semiconductor chip farthest from the positive busbar is closest to the upper bridge source PIN pin. The sum of the distances from the center of each chip among the several lower bridge power semiconductor chips to the three-phase busbar and the lower bridge source PIN pin is equal, and the lower bridge power semiconductor chip closest to the three-phase busbar is farthest from the lower bridge source PIN pin, and the lower bridge power semiconductor chip farthest from the three-phase busbar is closest to the lower bridge source PIN pin.

5. The power semiconductor module structure based on the copper-clad ceramic substrate according to claim 1, characterized in that: The plurality of upper bridge power semiconductor chips and the plurality of lower bridge power semiconductor chips are at least four power semiconductor chips connected in parallel.

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