Storage element, storage element array, and storage element driving method

Abstract

The present invention relates to a storage element, a storage element array and a storage element driving method. A storage element including a double PN junction and a driving method thereof are provided, characterized in that they include: a semiconductor layer including at least one double PN junction; and an anode and a cathode that are in contact with the semiconductor layer at the same time; the junction between the semiconductor layer and the anode is a Schottky junction, and the junction between the semiconductor layer and the cathode is an ohmic junction. In addition, a capacitor-free storage element including a double PN junction and a control gate and a driving method thereof are provided, characterized in that they include: a semiconductor layer including at least one double PN junction; a control gate connected to the semiconductor layer; and an anode and a cathode that are in contact with the semiconductor layer at the same time; the junction between the semiconductor layer and the anode is a Schottky junction, and the junction between the semiconductor layer and the cathode is an ohmic junction.

Description

Technical Field

[0001] The present invention relates to a storage element including a Schottky junction and a driving method thereof, and more particularly, to a storage element including a double PN junction and a driving method thereof, which does not require a high aspect ratio capacitor for physically storing electrons in the original DRAM and has a very simple structure.

[0002] In addition, the present invention relates to a capacitor-free storage element including a double PN junction and a control gate and a driving method thereof. More specifically, the present invention relates to a capacitor-free storage element including a double PN junction and a control gate and a driving method thereof, which is different from the original 1 transistor-1 capacitor (1T-1C) DRAM, does not require a capacitor with a high aspect ratio, and has a very simple structure. Background Art

[0003] The existing dynamic random access memory (DRAM), as the most typical memory device in semiconductor devices, consists of a field effect transistor for selecting a specific memory cell and a capacitor for storing carriers. It is widely used in industrial equipment such as computers, home appliances, and communication equipment. With the development of technology, the data storage capacity required of memory devices has increased significantly. In order to develop high-capacity memory devices, the miniaturization of memory cells is continuing. In order to miniaturize memory cells, it is necessary to develop high-aspect ratio capacitors to ensure high electrostatic capacitance in a narrow area, but stability and reliability problems are serious, which induces process complexity and process cost increases. In other words, the existing 1T-1C DRAM has limitations in achieving miniaturization and high integration of memory cells because it requires capacitors.

[0004] In order to overcome the limitations of conventional 1T-1C structured DRAMs, various types of capacitor-less DRAM devices have been proposed that can store carriers in the device without capacitors.

[0005] Among them, a thyristor random access memory (TRAM) with a PNPN structure consisting of a P-type anode region, an N-type base region, a P-type base region, and an N-type cathode region is introduced.

[0006] The memory does not store charge in a capacitor, but stores carriers in an N-type base and a P-type base, so that it can be used as a DRAM unit, and can have the advantages of easy miniaturization and high integration of storage elements. However, in order for TRAM to operate stably, a sufficiently long N-type base region and a P-type base region are required, which imposes many restrictions on device miniaturization. In addition, a steep doping profile is required for the P-type anode region-N-type base region junction, the N-type base region-P-type base region junction, and the P-type base region-N-type cathode region junction constituting TRAM, respectively, which presents process difficulties. In addition, when a two-terminal capacitor-free DRAM is used, for example, when a two-terminal TRAM is used to form a storage array, when performing a read / write operation of a specific storage cell, a "disturbance" voltage is inevitably applied to different storage cells located on the same bit line and word line, thereby causing a fatal reliability problem in which the data stored in the adjacent storage cells is damaged.

[0007] In addition, a switchable storage diode including a Schottky junction and an ohmic junction at both ends of a PN diode is introduced.

[0008] The memory has a diode including an active layer and a passive layer, and a simple structure composed of a Schottky junction and an ohmic junction at both ends, so that the process complexity can be effectively reduced, and the size and power consumption of the device can be significantly reduced. However, the performance of the memory element is greatly affected by the height of the Schottky barrier, so there is a disadvantage that the metal electrode material selection is greatly affected. In addition, even if a metal material with an optimal work function is used, multiple defects formed at the metal-semiconductor interface may make the memory element unable to operate or greatly reduce the operating performance.

[0009] Therefore, there is still a need for a capacitor-free memory structure and an operating method thereof that can save DRAM process costs, facilitate miniaturization of memory elements, and ensure excellent memory characteristics and reliability. Summary of the invention

[0010] The problem to be solved by the present invention is to avoid the dependence on metal electrode materials requiring specific work functions during Schottky junctions and the high electric field caused by semiconductor junctions, thereby actually providing a high-performance, highly integrated memory element manufacturing and driving method.

[0011] In addition, the problem to be solved by the present invention is to provide a highly integrated, high-reliability storage element and driving method, which does not require capacitors and has a simple structure, thereby achieving high integration. By applying a control gate, the "disturbance" problem of adjacent devices can be avoided in storage operations.

[0012] In order to solve the above-mentioned problem, the present invention provides a storage element including a double PN junction, characterized in that it includes: a semiconductor layer having at least one double PN junction; and an anode and a cathode that are in contact with the semiconductor layer at the same time; the junction between the semiconductor layer and the anode is a Schottky junction, and the junction between the semiconductor layer and the cathode is an ohmic junction.

[0013] In one embodiment of the present invention, the semiconductor layer is an NPN or PNP type semiconductor layer.

[0014] In one embodiment of the present invention, the storage layer is of NPN type, one of the N-type semiconductor layers has a low concentration, and the other has a high concentration.

[0015] In one embodiment of the present invention, the low-concentration N-type storage layer is connected to the anode, the high-concentration N-type storage layer is connected to the cathode, the junction between the anode and the low-concentration N-type storage layer is a Schottky junction, and the junction between the high-concentration N-type storage layer and the cathode is an ohmic junction.

[0016] The present invention also provides a storage element array including the above storage element as a unit device.

[0017] The present invention also provides a driving method for a storage element including a double PN junction. As a driving method for a storage element including a double PN junction, the method is characterized in that it includes: a step of applying a programming voltage to the storage element; a step of reducing the potential barrier of the double PN junction with the aid of the programming voltage, moving carriers to the semiconductor layer, and reducing the impedance of the semiconductor layer; and a step of reading the impedance of the semiconductor layer; the storage element including the double PN junction includes: a semiconductor layer having at least one double PN junction; and an anode and a cathode that are in contact with the semiconductor layer at the same time; the junction between the semiconductor layer and the anode is a Schottky junction, and the junction with the cathode is an ohmic junction.

[0018] In one embodiment of the present invention, the driving method of the storage element further includes: after the step of reducing the impedance of the semiconductor layer, the step of selectively applying an erase voltage to the storage element to increase the impedance of the semiconductor layer; and further includes: after applying the programming voltage, the step of selectively applying a refresh voltage to the storage element again to reduce the impedance of the semiconductor layer again.

[0019] On the other hand, in order to solve the above-mentioned problem, the present invention provides a capacitor-free storage element, characterized in that it includes: a semiconductor layer having at least one double PN junction; a control gate connected to the semiconductor layer; and an anode and a cathode simultaneously contacting the semiconductor layer; the junction between the semiconductor layer and the anode is a Schottky junction, and the junction with the cathode is an ohmic junction.

[0020] In one embodiment of the present invention, the semiconductor layer is of NPN type, one of the N-type semiconductor layers is of low concentration and the other is of high concentration, the low-concentration N-type semiconductor layer is connected to the anode, and the high-concentration N-type semiconductor layer is connected to the cathode.

[0021] In one embodiment of the present invention, the low-concentration N-type storage layer is connected to the anode, and the high-concentration N-type storage layer is connected to the cathode.

[0022] The present invention also provides a storage element array including the above storage element as a unit device.

[0023] The present invention also provides a method for driving a capacitor-free storage element including a double PN junction and a control gate. As a driving method for a capacitor-free storage element including a double PN junction and a control gate, the method is characterized in that it includes: a step of applying a programming voltage to the storage element; a step of reducing the potential barrier of the double PN junction with the aid of the programming voltage, moving carriers to the semiconductor layer, and reducing the impedance of the semiconductor layer; and a step of reading the impedance of the semiconductor layer; the capacitor-free storage element including a double PN junction and a control gate includes: a semiconductor layer having at least one double PN junction; and an anode and a cathode that are in contact with the semiconductor layer at the same time; the junction between the semiconductor layer and the anode is a Schottky junction, and the junction between the semiconductor layer and the cathode is an ohmic junction.

[0024] In one embodiment of the present invention, the semiconductor layer is of NPN type, one of the N-type semiconductor layers is of low concentration and the other is of high concentration, the low-concentration N-type semiconductor layer is connected to the anode, and the high-concentration N-type semiconductor layer is connected to the cathode.

[0025] In one embodiment of the present invention, the driving method of the storage element further includes: after the step of lowering the impedance of the semiconductor layer, the step of selectively applying an erase voltage to the storage element to increase the impedance of the semiconductor layer, and also includes: the step of using a control gate to suppress operational errors of unselected cells in a storage cell array that can be composed of storage elements.

[0026] According to one embodiment of the present invention, the storage element includes a semiconductor layer having a double PN junction (NPN junction and PNP junction), and the anode (Anode) and the cathode (Cathode) connected to the semiconductor layer constitute a Schottky junction and an ohmic junction respectively. At this time, when the programming voltage is applied, carriers accumulate in the semiconductor layer, and the semiconductor layer becomes low impedance. This low impedance of the semiconductor layer is maintained in the semiconductor layer for a predetermined time before the erase voltage is applied.

[0027] When the N-type semiconductor layer is not inserted between the anode electrode and the P-type semiconductor layer, but a Schottky junction is directly formed, the performance of the storage element is greatly affected by the height of the Schottky barrier, and thus the selection of metal electrode materials is greatly restricted. In addition, multiple defects formed at the metal-semiconductor interface promote the recombination of carriers stored in the P-type semiconductor layer, which greatly reduces the storage operation performance.

[0028] On the contrary, the storage element of one embodiment of the present invention is a structure in which an N-type semiconductor layer is inserted between the P-type semiconductor layer and the anode electrode constituting the Schottky junction. The carriers stored in the P-type semiconductor layer are greatly affected by the potential barrier formed at the NP junction, and the potential barrier can be easily controlled by controlling the concentration of impurities contained in the N-type semiconductor layer. In addition, the P-type semiconductor layer is not in direct contact with the metal electrode, but forms an NP junction with the N-type semiconductor layer, so the stored carriers are not affected by the multiple defects formed at the metal-semiconductor interface, which can ensure the excellent operating performance of the storage element. Therefore, the storage element including a double PN junction of one embodiment of the present invention can easily overcome the limitation of the electrode material selection required to determine the height of the Schottky barrier, can improve the practical possibility, and can avoid the problem of device degradation caused by applying a high electric field to the junction, which can ensure excellent operating performance with stability.

[0029] In addition, according to one embodiment of the present invention, the storage element is composed of an anode, a semiconductor layer including a double PN junction (NPN junction and PNP junction), and a cathode. The anode and cathode connected to the semiconductor layer respectively form a Schottky junction and an ohmic junction, and a control gate is formed on the semiconductor layer. When a programming voltage is applied, carriers accumulate in the semiconductor layer, and the semiconductor layer becomes low impedance. This low impedance of the semiconductor layer is maintained in the semiconductor layer for a predetermined time before an erase voltage is applied.

[0030] As described above, the storage element of the present invention does not require a capacitor, is not only a simple device structure, but also easy to manufacture vertically, and can greatly improve the integration of storage elements compared to conventional DRAM. In addition, unlike conventional two-terminal capacitor-less DRAMs that are vulnerable to "disturbance" voltages, the carriers accumulated in the semiconductor layer are controlled by the control gate, thereby protecting the data of adjacent storage elements, thereby improving the reliability of storage array operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic diagram of a storage element according to an embodiment of the present invention, Figure 2 As a comparative example, this is a schematic diagram of a memory element in which an N-type semiconductor layer is not inserted between a P-type semiconductor layer and an anode.

[0032] Figures 3 to 6 is an energy diagram illustrating the operating mechanism of a storage element (NPN+) according to one embodiment of the present invention.

[0033] Figures 7 to 10 is an energy diagram illustrating the operating mechanism of a memory element in which an N-type semiconductor layer is not inserted between a P-type and an anode.

[0034] Fig.11 is the hole concentration of the P-type semiconductor layer of an embodiment and a comparative example over time after programming.

[0035] Fig.12 This is a schematic diagram of a memory element array including the memory element of one of the above-described embodiments as a unit device.

[0036] Fig.13 This is a schematic diagram of a memory element according to an embodiment of the present invention.

[0037] Figures 14 to 16 is an energy diagram illustrating the programming operation mechanism of a storage element according to one embodiment of the present invention.

[0038] Fig.17 Before programming (T ST,0 ) and 10 seconds after programming (T ST,1 =10s) after 1s / s.

[0039] Figures 18 to 19 is an energy diagram illustrating the erase operation mechanism of a memory element according to one embodiment of the present invention.

[0040] Fig. 20 After programming, 10 seconds have passed (T ST,1 =10s) after an embodiment of a read operation performed, the operating voltage and anode current of the storage element.

[0041] Fig.21 FIG. 1 is a schematic diagram of a memory cell array that can be formed by a memory element according to an embodiment of the present invention.

[0042] Fig. 22 1 is a table showing various operating voltage conditions (anode, gate, cathode voltages) of selected cells and unselected cells in various operating modes (standby, programming, erasing, reading) of a device according to an embodiment of the present invention.

[0043] Figure 23 to Figure 25 The figure shows the storage characteristics caused by array disturbance pulses that may occur in various operation modes of a device according to an embodiment of the present invention.

[0044] Fig.23 is Fig. 22An energy band diagram of a storage element according to an embodiment resulting from a program disturbance pulse applied to unselected cells during a programming operation of FIG.

[0045] Fig.24 Shown in Fig. 22 In an embodiment, the hole concentration (N) stored in the storage element is reduced due to the repeated application of the erase disturbance pulse to the unselected cells in the erase operation. P ).

[0046] Fig.25 is Fig. 22 After the erase operation, the operating voltage and anode current of the storage element of one embodiment are obtained by repeatedly applying the read pulse 10 times. Fig.26 This is a schematic diagram of a memory element array including the memory element of one of the above-described embodiments as a unit device. DETAILED DESCRIPTION

[0047] The present invention may be subjected to various changes and may have various forms. Specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, but should be understood to include all changes, equivalents and substitutes included in the concept and technical scope of the present invention. When describing each of the drawings, similar reference numerals are used for similar constituent elements.

[0048] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which the present invention belongs. Terms that are the same as those defined in commonly used dictionaries should be interpreted as having the same meaning as that in the context of the relevant art and should not be interpreted excessively or excessively as formal meanings unless explicitly defined in this application.

[0049] In addition, in this specification, the terms such as anode, cathode, control gate, N-type region, P-type region, PN junction, Schottky junction, ohmic junction, etc., explain the level of understanding of ordinary technicians in the technical field to which the present invention belongs, and their types can also be changed in various ways, which also belong to the scope of the present invention. In addition, the semiconductor layer, as a device layer containing semiconductor material, is not limited to horizontal, vertical and other forms, and any semiconductor structure including at least one NPN or PNP junction belongs to this. In addition, although the control gate is described as being located on the semiconductor layer, it is not limited to the lower or surrounding gate (Gate-all around) and other forms, and all control gate structures connected to the semiconductor layer belong to this. In the present invention, the so-called "capacitor-free" means that there is no capacitor.

[0050] In order to solve the above problems, the present invention combines an energy barrier based on a Schottky junction with an energy barrier between a PN or NP junction, and avoids the dependence on the metal work function compared to the comparative example of using an energy barrier based on a Schottky junction alone, thereby having the advantage of improving the practical possibility of the storage element. Therefore, the semiconductor layer of the storage element of one embodiment of the present invention includes a double PN junction such as an NPN or PNP, one of which forms a Schottky junction with the anode, and the other forms an ohmic junction.

[0051] In addition, in order to solve the above-mentioned problem, the present invention is composed of an anode, a semiconductor layer including a double PN junction (NPN junction and PNP junction), and a cathode. The anode and cathode connected to the semiconductor layer respectively form a Schottky junction and an ohmic junction, and a control gate is formed on the semiconductor layer. Therefore, since a simple device structure of a capacitor is not required, the device integration can be greatly improved. When the storage element is used to form a storage array, the control gate can suppress the disturbance problem of the adjacent storage element, thereby having the advantage of ensuring the reliability of the storage array operation. Furthermore, the present invention can protect the data of the adjacent storage element by suppressing the control gate and controlling the carriers accumulated in the semiconductor layer, thereby ensuring the reliability of the storage array operation.

[0052] The present invention will be described in more detail below using a memory element according to an embodiment of the present invention using an NPN-type semiconductor layer.

[0053] Figure 1 A schematic diagram of a storage element according to an embodiment of the present invention is shown in FIG. Figure 2 is a schematic diagram of a memory element of a comparative example.

[0054] If reference Figure 1 and 2 The storage element of one embodiment of the present invention is an NPN semiconductor layer including an NP junction by inserting another N-type semiconductor layer between the semiconductor layer including the anode and the PN junction, the anode and the NPN semiconductor layer form a Schottky junction, and the cathode and the N-type semiconductor layer form an ohmic junction. Figure 2 The storage element has a structure in which a Schottky junction is formed between the anode and the P-type semiconductor layer, and an ohmic junction is formed between the N-type semiconductor layer and the cathode.

[0055] An NPN type memory element according to an embodiment of the present invention has a structure in which a high concentration N type semiconductor layer is connected to a cathode and a low concentration N type semiconductor is connected to an anode.

[0056] When a low-concentration N-type semiconductor layer is connected to the cathode, an ohmic junction is replaced by a Schottky junction. At this time, it is difficult to supply sufficient electrons from the cathode for impact ionization to occur in the semiconductor layer. In addition, if a high-concentration N-type semiconductor layer is connected to the anode, the storage erase operation will be difficult. That is, when a high-concentration N-type semiconductor layer is connected to the anode, an ohmic junction is formed. At this time, when a negative voltage is applied to the anode, impact ionization occurs while electrons overflow, which induces carrier accumulation.

[0057] Figure 2 The biggest problem of the comparative example shown is that the retention performance of the resistance state of the memory element is greatly influenced by the height of the Schottky barrier.

[0058] exist Figure 2 In the storage element of the structure, based on the Schottky barrier energy The holding time (T ret )The differences are as follows.

[0059]

[0060] If we refer to the above results, we can see that the retention time differs by nearly 100 times according to the 0.15 eV difference. This means that for the stable operation of the storage element, the energy barrier of the Schottky junction needs to be precisely controlled, which ultimately limits the selection of anode electrode materials. In addition, even if there is a metal material with the best work function, due to multiple defects formed at the interface between the anode metal electrode and the P-type semiconductor layer when making the device, the storage element cannot be operated or the performance is greatly reduced.

[0061] Figures 3 to 6 A storage element (NPN) according to an embodiment of the present invention is shown. + ) in which the Schottky barrier height is set to 0.815 eV.

[0062] Figure 3 This is the energy band diagram when the anode voltage is 0V (equilibrium state). + The energy barrier of the junction is formed high, and it becomes a high resistance state (HRS) showing low current. In the comparative example, the energy barrier formed at the Schottky junction is determined by the work function of the anode. On the contrary, the storage element including two PN junctions of one embodiment of the present invention can adjust the energy barrier height of the NP junction by adjusting the doping concentration of the N-type semiconductor layer contacting the anode. In addition, the NP junction has a lower defect concentration than the metal contact interface, so the manufactured storage element can easily ensure excellent retention time performance.

[0063] Figure 4 This is the energy band diagram when the anode voltage is 2.4 V (the trigger voltage for programming operation). As the anode voltage is applied, the Schottky junction and PN + The energy barrier of the junction is lowered. Then, the high concentration N-type semiconductor layer (N + )'s electrons cross the P-type semiconductor layer and flow into the anode.

[0064] Figure 5 is the energy band when the anode voltage is maintained at 2.4V (the trigger voltage for programming operation) during the pulse period. Figure 5 Due to the impact ionization effect caused by the high electric field of the NP junction, electrons and holes are generated. At this time, the generated electrons accumulate in the N-type region and remain for a predetermined time, and the generated holes accumulate in the P-type region, reducing the potential barrier. At this time, due to the reduced potential barrier, a low resistance state (LRS) is realized in which electrons can move easily.

[0065] Figure 6 It is the energy band diagram when the anode voltage is reduced from 2.4V (trigger voltage of programming operation) to 0V. Although the anode voltage is reduced, holes accumulate in the P-type semiconductor layer, maintaining a low energy barrier. At this time, the present invention is a structure in which an N-type semiconductor layer is inserted, and more holes are accumulated after programming, showing a lower electron energy barrier, and the retention time is 600ms. In this structure, the same Schottky barrier height (0.815eV) as the comparative example is shown, but due to the energy barrier of the NP junction, the retention time of the stored holes can be increased.

[0066] Figures 7 to 10 1 is an energy diagram illustrating the operation mechanism of a memory element in which an N-type semiconductor layer is not inserted between a P-type semiconductor layer and an anode. The Schottky barrier height is set to 0.815 eV, which is the same as in the case of one embodiment of the present invention.

[0067] If reference Figures 7 to 10 , if a voltage (1.8V) is applied to the anode for programming operation, then PN + The energy barrier of the high-concentration N-type semiconductor layer (N + )'s electrons cross the P-type semiconductor layer and flow into the anode.

[0068] Fig. 9 This is the energy band diagram when the anode voltage is maintained at 1.8V (trigger voltage for programming operation) during the pulse period. As the anode voltage is applied, more electrons flow in, and the high electric field between the anode and the P-type semiconductor layer generates electrons and holes through impact ionization.

[0069] Fig.10This is an energy band diagram when the anode voltage is reduced from 1.8 V (trigger voltage for programming operation) to 0 V. Although the anode voltage decreases, holes accumulate in the P-type semiconductor layer, maintaining a low energy barrier. The memory element of the comparative example exhibits a retention time of 3 ms.

[0070] Fig.11 It is the concentration of holes accumulated in the P-type semiconductor layer in an embodiment and a comparative example as time passes after a programming operation.

[0071] If reference Fig.11 , as the energy barrier height of the Schottky junction of the comparative example From 0.966eV to 0.815eV, a relatively small concentration of holes is accumulated after programming, and the data retention time (T ret ) is reduced from 300ms to 3ms level.

[0072] However, in the case of inserting an N-type semiconductor layer, it can be seen that although the Schottky barrier height is low, 0.815 eV, more holes are accumulated than in the comparative example after the programming operation, and the retention time (T ret ) is greatly improved to 600ms level.

[0073] Fig.12 is a schematic diagram of a memory element array including a memory element of one of the above-mentioned embodiments as a unit device. Fig.12 , it is possible to implement a storage element array of a unit device by configuring the storage element of one of the above embodiments, which all falls within the scope of the present invention.

[0074] In addition, the present invention provides a driving method for a storage element including a double PN junction. The driving method includes: a step of selectively applying a programming voltage to a storage element including at least one double PN junction; a step of lowering the potential barrier of the semiconductor layer by means of the programming voltage, moving carriers to the semiconductor layer, and lowering the impedance of the semiconductor layer; a step of selectively applying an erasing voltage to the storage element; a step of erasing the carriers of the semiconductor layer by means of the erasing voltage, thereby returning the impedance of the semiconductor layer to an initial level; and a step of reading the impedance of the semiconductor layer.

[0075] That is, the present invention can apply a programming voltage to a storage element including a Schottky junction to change the impedance value of the semiconductor layer from high impedance to low impedance, and apply an erase voltage to change the impedance value of the semiconductor layer from low impedance to high impedance, thereby performing a data write operation. In addition, after the programming operation, the low impedance value of the semiconductor layer is maintained for a predetermined time, and within the retention time, a voltage (update voltage) below the trigger voltage for the programming operation can be selectively applied to continuously maintain the impedance value of the semiconductor layer, and a read voltage can be applied to confirm the low impedance state of the semiconductor layer. That is, the data of the storage element can be confirmed.

[0076] The above storage element driving method can effectively perform data writing, erasing, reading, and holding without using additional complicated structures such as capacitors.

[0077] The present invention will be described in more detail below by using a memory element according to an embodiment of the present invention using an NPN type semiconductor layer and a control gate.

[0078] Fig.13 This is a schematic diagram of a memory element according to an embodiment of the present invention.

[0079] If reference Fig.13 The storage element of one embodiment of the present invention is composed of an anode, an NPN semiconductor layer, a cathode, and a control gate. The anode and the cathode connected to the semiconductor layer form a Schottky junction and an ohmic junction respectively, and the control gate is formed on the P-type semiconductor layer. In addition, an insulating film may be arranged between the P-type semiconductor layer and the control gate.

[0080] An NPN type memory element according to an embodiment of the present invention has a structure in which a high concentration N type semiconductor layer is connected to a cathode and a low concentration N type semiconductor is connected to an anode.

[0081] The high-concentration N-type semiconductor layer forms an ohmic junction with the cathode, so that a sufficient electron source is supplied through the cathode, and the impact ionization caused thereby can generate sufficient storage carriers required for storage operation.

[0082] The low-concentration N-type semiconductor layer and the anode form a Schottky junction, so that the energy barrier height and storage operation current of the storage holes stored in the P-type semiconductor layer can be adjusted by adjusting the doping concentration. Furthermore, the substantial device operating characteristics can be effectively controlled together with the doping concentration by controlling the gate.

[0083] Figures 14 to 16 is an energy diagram illustrating the programming operation mechanism of a storage element according to one embodiment of the present invention.

[0084] Fig.14It is the standby state anode-cathode voltage (V AC,ST ,1.3V) before programming. Before programming, the storage element forms a PN + The high energy barrier of the junction becomes a high resistance state (HRS) showing a low current.

[0085] Fig.15 The energy band diagram is shown when the cathode voltage is -1.0V (the trigger cathode voltage for programming operation). With the cathode voltage of -1.0V applied, the anode-cathode voltage (V AC,P ) and a gate-to-cathode voltage of 1.0V (V GC,P ) is applied to storage elements. As a negative cathode voltage is applied, the Schottky junction and PN + The energy barrier of the junction is lowered. Then, the high concentration N-type semiconductor layer (N + ) passes through the P-type semiconductor layer and flows into the anode. The inflowing electrons meet the high electric field of the NP junction, and electrons and holes are generated due to the impact ionization effect. The generated holes accumulate in the P-type region, reducing the PN + At this time, due to the lowered potential barrier, a low resistance state (LRS) is realized in which electrons can move easily.

[0086] Fig.16 is the energy band diagram when the cathode voltage returns from -1.0V (the trigger cathode voltage required for programming operation) to the initial 0.0V. AC ) and the gate-cathode voltage (V GC ) drop to 1.3V and 0.0V respectively, but the generated holes accumulate in the P-type semiconductor layer, maintaining a low PN + Energy barrier.

[0087] Fig.17 Before programming (T ST,0 ) and 10 seconds after programming (T ST,1 =10s) after the storage element of an embodiment is switched off. Since a standby anode-cathode voltage (V AC,ST ,1.3V), so the programmed device can maintain a low resistance state (LRS) even after 10 seconds.

[0088] Figures 18 to 19is an energy diagram illustrating the erase operation mechanism of a memory element according to one embodiment of the present invention.

[0089] Fig.18 To erase the Fig.16 The energy band diagram when 1.0V (the gate voltage required for the erase operation) is applied to the holes stored in the P-type semiconductor layer. With the application of 1.0V gate voltage, 1.0V gate-cathode voltage (V GC,E ) is applied to a storage element. When a positive gate voltage is applied to the storage element of this embodiment, the holes stored in the P-type semiconductor layer are depleted.

[0090] Fig.19 It is the energy band diagram when the gate voltage returns from 1.0V (the gate voltage required for the erase operation) to the initial 0.0V. Due to the holes erased from the P-type semiconductor layer, the PN + The junction energy barrier becomes a high state, and the storage state returns to the high resistance state (HRS: High Resistance State) before programming.

[0091] Fig. 20 After programming, 10 seconds have passed (T ST,1 =10s) after the operation of the read operation of the memory element. In order to accurately sense each storage state, the cathode voltage and the gate voltage are reduced to -1.0V and -0.8V respectively. Thus, the anode-cathode voltage (V AC,R ) and a gate-cathode voltage of 0.2V (V GC,R ) is applied to the memory element. The low resistance state (LRS) maintained after programming can be sensed as a high current level even after 10 seconds by the read voltage pulse.

[0092] Fig.21 FIG. 1 is a schematic diagram of a memory cell array that can be composed of memory elements of one embodiment of the present invention. If a gate-cathode voltage (V GC ), then undesirable operation errors can be prevented. In the array configuration, in order to effectively adjust the gate-cathode voltage (V GC ), the gate and cathode electrodes are set as word lines (WL) and bit lines (BL), respectively, and the anode electrode is set to maintain a low resistance state (LRS: Low Resistance State) in a standby state. AC,ST ) and is fixed at 1.3V.

[0093] Fig. 22TABLE 1 is a table showing the operating voltage conditions (anode, gate, cathode voltage) of the selected cells and the unselected cells in each operating mode (standby, programming, erasing, reading) of the device of one embodiment of the present invention. In order to maintain a stable impedance state in the standby state, the gate voltage (V G ), cathode voltage (V C ) are set to 0.0V.

[0094] Figure 23 to Figure 25 The figure shows the storage characteristics caused by array disturbance pulses that may occur in various operation modes of a device according to an embodiment of the present invention.

[0095] Fig.23 is Fig. 22 Energy band diagram of one embodiment storage element due to a program disturbance pulse applied to unselected cells during a programming operation. A 2.3V programming anode-cathode voltage (V AC,P ) and 0.0V gate-cathode voltage (V GC ). When the gate-cathode voltage (V GC ) is kept below 0.0V, there is no change in the energy band before and after the programming disturbance pulse, thus preventing errors caused by programming disturbance.

[0096] Fig.24 Shown in Fig. 22 In an embodiment, the hole concentration (N) stored in the storage element is reduced due to the repeated application of the erase disturbance pulse to the unselected cells in the erase operation. P ). Apply an anode-cathode voltage (V ) of 0.3 V to the selected word line (WL) and the unselected bit line (BL). AC ) and a gate-to-cathode voltage of 0.0V (V GC ). Gate-cathode voltage (V GC ) is kept below 0.0 V, so that even if the erase disturbance pulse is repeated, the storage hole concentration of the programmed cell remains unchanged, and errors caused by erase disturbance can be prevented.

[0097] Fig.25 is Fig. 22 After the erase operation, 10 repeated application of read pulses resulted in an operating voltage and anode current of a storage element in an embodiment. The anode-cathode voltage (V AC,R ) and a gate-cathode voltage of 0.2V (V GC,R) even if a read pulse is repeatedly applied to the erased storage element, the read current level does not change, so the high resistance state (HRS: High Resistance State) of the erased memory can be kept stable, preventing programming errors caused by the read operation.

[0098] Fig.26 is a schematic diagram of a memory element array including a memory element of one of the above-mentioned embodiments as a unit device. Fig.26 , it is possible to realize a storage element array that uses the storage element of one of the above embodiments as a unit device, which all falls within the scope of the present invention.

[0099] In addition, the present invention provides a driving method for a storage element including a double PN junction and a control gate. The driving method includes: a step of selectively applying a programming voltage to a storage element including at least one double PN junction; a step of lowering the potential barrier of the semiconductor layer by means of the programming voltage, moving carriers to the semiconductor layer, and lowering the impedance of the semiconductor layer; a step of selectively applying an erasing voltage to the storage element; a step of erasing the carriers of the semiconductor layer by means of the erasing voltage, thereby returning the impedance of the semiconductor layer to an initial level; and a step of reading the impedance of the semiconductor layer.

[0100] That is, the present invention can apply a programming voltage to a storage element including a double PN junction and a control gate to change the impedance value of the semiconductor layer from high impedance to low impedance, and apply an erase voltage to change the impedance value of the semiconductor layer from low impedance to high impedance, thereby performing a data write operation. In addition, after the programming operation, the low impedance value of the semiconductor layer can maintain a low resistance state (LRS) after programming by applying a standby anode-cathode voltage (V AC,ST , 1.3V), so that it can be stably maintained, a read voltage can be applied, and the low impedance state of the semiconductor layer can be confirmed. That is, the data of the storage element can be confirmed.

[0101] The above storage element driving method can effectively perform data writing, erasing, reading, and holding without using additional complicated structures such as capacitors.

Claims

1. A storage element comprising a double PN junction, characterized in that: include: A semiconductor layer having at least one double PN junction; as well as an anode and a cathode both in contact with the semiconductor layer; The semiconductor layer is connected to the anode through a Schottky junction, and connected to the cathode through an Ohmic junction. The semiconductor layer is of NPN type, one of the N-type semiconductor layers in the semiconductor layer has a low concentration, and the other has a high concentration.

2. The storage element comprising a double PN junction according to claim 1, characterized in that: The low-concentration N-type semiconductor layer is connected to the anode, and the high-concentration N-type semiconductor layer is connected to the cathode.

3. The storage element comprising a double PN junction according to claim 2, characterized in that: The junction between the anode and the low-concentration N-type semiconductor layer is a Schottky junction, and the junction between the high-concentration N-type semiconductor layer and the cathode is an Ohmic junction.

4. A memory element array comprising the memory element according to any one of claims 1 to 3 as a unit device.

5. A method for driving a storage element including a double PN junction, as a method for driving a storage element including a double PN junction, characterized in that: include: The step of applying a programming voltage to the memory element; A step of reducing the potential barrier of the double PN junction by means of the programming voltage, so that carriers move to the semiconductor layer and reduce the impedance of the semiconductor layer; as well as The step of reading the impedance of the semiconductor layer; The storage element including the double PN junction includes: a semiconductor layer having at least one double PN junction; and an anode and a cathode both in contact with the semiconductor layer; The semiconductor layer is connected to the anode through a Schottky junction, and connected to the cathode through an Ohmic junction. The semiconductor layer is of NPN type, one of the N-type semiconductor layers in the semiconductor layer has a low concentration, and the other has a high concentration.

6. The driving method of the storage element comprising a double PN junction according to claim 5, characterized in that: The method for driving the storage element further includes: after the step of reducing the impedance of the semiconductor layer, the step of selectively applying an erase voltage to the storage element to increase the impedance of the semiconductor layer.

7. The driving method of the storage element comprising a double PN junction according to claim 6, characterized in that: The method further includes: after applying the programming voltage, selectively applying a refresh voltage to the storage element again to reduce the impedance of the semiconductor layer again.

8. A capacitor-free storage element comprising a double PN junction and a control gate, characterized in that: include: A semiconductor layer having at least one double PN junction; a control gate connected to the semiconductor layer; as well as an anode and a cathode both in contact with the semiconductor layer; The semiconductor layer is connected to the anode through a Schottky junction, and connected to the cathode through an Ohmic junction. The semiconductor layer is of NPN type, one of the N-type semiconductor layers in the semiconductor layer has a low concentration, and the other has a high concentration.

9. The capacitor-less storage element comprising a double PN junction and a control gate according to claim 8, characterized in that: The low-concentration N-type semiconductor layer is connected to the anode, and the high-concentration N-type semiconductor layer is connected to the cathode.

10. The capacitor-less storage element comprising a double PN junction and a control gate according to claim 9, characterized in that: The low-concentration N-type semiconductor layer is connected to the anode, and the high-concentration N-type semiconductor layer is connected to the cathode.

11. A memory element array comprising the memory element according to any one of claims 8 to 10 as a unit device.

12. A method for driving a capacitor-free storage element including a double PN junction and a control gate, as a method for driving a capacitor-free storage element including a double PN junction and a control gate, characterized in that: include: The step of applying a programming voltage to the memory element; A step of reducing the potential barrier of the double PN junction by means of the programming voltage, so that carriers move to the semiconductor layer and reduce the impedance of the semiconductor layer; as well as The step of reading the impedance of the semiconductor layer; The capacitor-free storage element including a double PN junction and a control gate includes: a semiconductor layer having at least one double PN junction; and an anode and a cathode both in contact with the semiconductor layer; The semiconductor layer is connected to the anode through a Schottky junction, and connected to the cathode through an Ohmic junction. The semiconductor layer is of NPN type, one of the N-type semiconductor layers in the semiconductor layer has a low concentration, and the other has a high concentration.

13. The driving method of the capacitor-less storage element including a double PN junction and a control gate according to claim 12, characterized in that: The low-concentration N-type semiconductor layer is connected to the anode, and the high-concentration N-type semiconductor layer is connected to the cathode.

14. The driving method of the capacitor-less storage element including a double PN junction and a control gate according to claim 13, characterized in that: The method for driving the storage element further includes: after the step of reducing the impedance of the semiconductor layer, selectively applying an erase voltage to the storage element to increase the impedance of the semiconductor layer.

15. The driving method of the capacitor-less storage element including a double PN junction and a control gate according to claim 13, characterized in that: The method further includes the step of suppressing operation errors of unselected cells in a memory cell array that can be composed of memory elements by using a control gate.

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