Semiconductor structure and method for forming the same

Abstract

The technical solution of the present application provides a semiconductor structure and a method for forming the same, wherein the semiconductor structure comprises: a substrate, the substrate comprising a first epitaxial layer; doped columns, discretely located in the first epitaxial layer; a first JFET region, located on part of the doped columns; a second JFET region, located on part of the first epitaxial layer between adjacent doped columns; a well region, located on the first JFET region and the second JFET region; a source region, extending from the surface of the well region to the well region; a doped region, located between adjacent source regions and extending to the surface of the doped columns; a gate structure, located in the source region and the well region and extending between the first JFET region and the second JFET region, and the entire or partial bottom of the gate structure is adjacent to the doped columns. The technical solution of the present application can reduce the electric field at the bottom of the gate structure, reduce gate-drain charge, and reduce substrate resistance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the continuous development of power MOSFET technology, trench MOSFET has emerged. The biggest advantage of trench MOSFET is that it can increase the channel density of planar devices to improve the current handling capability of the device. However, the bottom of the gate structure of current trench MOSFET is subjected to a high electric field, and the gate-drain charge (Qgd) is large, and the substrate resistance is high. Summary of the invention

[0003] The technical problem to be solved by the present application is to provide a semiconductor structure and a method for forming the same, which can reduce the electric field at the bottom of the gate structure, reduce the gate leakage charge, and also reduce the substrate resistance.

[0004] To solve the above technical problems, the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a first epitaxial layer; a doped column, discretely located in the first epitaxial layer and coplanar with the surface of the first epitaxial layer, wherein the thickness of the doped column is less than or equal to the thickness of the first epitaxial layer, and the thickness difference is 0μm to 1μm; a first JFET region, located on part of the doped column; a second JFET region, located on part of the first epitaxial layer between adjacent doped columns; a well region, located on the first JFET region and the second JFET region; a source region, extending from the surface of the well region to the well region; a doped region, located between adjacent source regions and extending to the surface of the doped column; a gate structure, located in the source region and the well region and extending between the first JFET region and the second JFET region, and the entire or partial bottom of the gate structure is adjacent to the doped column.

[0005] In an embodiment of the present application, the doped columns are distributed along the extension direction of the gate structure and perpendicular to the extension direction of the gate structure, the first JFET region spans or does not span the doped columns in the extension direction of the gate structure, and the second JFET region has the same extension direction as the gate structure.

[0006] In the embodiment of the present application, surfaces of the first JFET region and the second JFET region are coplanar.

[0007] In the embodiment of the present application, the depth of the source region is 0.2μm-0.4μm; the depth of the doping region is 1.2μm-1.5μm; the depth of the well region is 0.8μm-1.0μm; the thickness of the first JFET region and the second JFET region is 0.3μm-0.4μm.

[0008] In an embodiment of the present application, the gate structure includes a gate oxide layer and a gate layer located on a surface of the gate oxide layer.

[0009] In the embodiment of the present application, the depth of the gate layer is 1.1 μm-1.5 μm.

[0010] In an embodiment of the present application, the first epitaxial layer, the first JFET region, the second JFET region and the source region have the same doping type; the doping column, the doping region and the well region have the same doping type; wherein the doping concentration of the first JFET region is greater than or equal to the doping concentration of the second JFET region.

[0011] In the embodiment of the present application, the doping concentration of the first epitaxial layer and the doping column is 5×10 15 / cm 3 Up to 2.5×10 16 / cm 3 , the doping concentration of the first JFET region and the second JFET region is 3×10 16 / cm 3 Up to 2×10 17 / cm 3 .

[0012] In an embodiment of the present application, the semiconductor structure also includes: an interlayer dielectric layer, located on the surface of the gate structure and a portion of the source region; a source contact layer, located between the interlayer dielectric layers, and the surfaces of the source contact layer and the interlayer dielectric layer are coplanar; and a source metal, located on the surfaces of the interlayer dielectric layer and the source contact layer.

[0013] The present application also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first epitaxial layer, a discrete doped column formed in the first epitaxial layer, and the surface of the doped column and the first epitaxial layer are coplanar, wherein the thickness of the doped column is less than or equal to the thickness of the first epitaxial layer, and the thickness difference is 0 μm to 11 μm; forming a second epitaxial layer on the surface of the first epitaxial layer and the doped column; forming a first JFET region in the second epitaxial layer, and the first JFET region is located on part of the doped column; forming a second JFET region in the second epitaxial layer, and the The second JFET region is located on the first epitaxial layer between adjacent doped columns; a well region is formed in the second epitaxial layer higher than the first JFET region and the second JFET region; a source region is formed extending from the surface of the well region on the first JFET region and the second JFET region to the well region; a doped region is formed extending from the surface of the well region between adjacent source regions to the surface of the doped column; the source region, the well region, the first JFET region and the second JFET region are partially etched, and a gate structure is formed at a corresponding position, and the entire or partial bottom of the gate structure is adjacent to the doped column.

[0014] In an embodiment of the present application, the doped columns are distributed along the extension direction of the gate structure and perpendicular to the extension direction of the gate structure, the first JFET region spans or does not span the doped columns in the extension direction of the gate structure, and the second JFET region has the same extension direction as the gate structure.

[0015] In an embodiment of the present application, the substrate also includes a silicon carbide substrate; when the thickness of the first epitaxial layer and the doped column are equal, the formation method includes: providing a silicon carbide substrate; forming a graphic mask of the doped column on a portion of the silicon carbide substrate; forming the first epitaxial layer on the silicon carbide substrate not covered by the graphic mask; removing the graphic mask, and forming the doped column at a corresponding position; or, the formation method includes: providing a silicon carbide substrate; forming the first epitaxial layer on the silicon carbide substrate; etching the first epitaxial layer to form a first groove, and the first groove passes through the first epitaxial layer; forming the doped column in the first groove.

[0016] In an embodiment of the present application, the substrate also includes a silicon carbide substrate; when the thickness of the first epitaxial layer is less than the thickness of the doped column, the formation method includes: providing a silicon carbide substrate; forming a first portion of the first epitaxial layer on the silicon carbide substrate; forming a graphic mask of the doped column on a portion of the first portion of the first epitaxial layer; forming a second portion of the first epitaxial layer on the first portion of the first epitaxial layer not covered by the graphic mask; removing the graphic mask, and forming the doped column at a corresponding position; or, the formation method includes: providing a silicon carbide substrate; forming the first epitaxial layer on the silicon carbide substrate; etching the first epitaxial layer to form a second trench, and the second trench does not penetrate the first epitaxial layer; forming the doped column in the second trench.

[0017] In an embodiment of the present application, an ion implantation process is used to form the first JFET region, the second JFET region, the well region, the source region and the doped region; wherein the temperature of the ion implantation process for forming the well region, the source region and the doped region is 500°C-600°C, and the temperature of the ion implantation process for forming the first JFET region and the second JFET region is 20°C-40°C or 500°C-600°C.

[0018] In an embodiment of the present application, the first epitaxial layer, the second epitaxial layer, the first JFET region, the second JFET region and the source region have the same doping type; the doping column, the doping region and the well region have the same doping type; wherein the doping concentration of the first JFET region is greater than or equal to the doping concentration of the second JFET region.

[0019] In the embodiment of the present application, the doping concentration of the first epitaxial layer and the doping column is 5×10 15 / cm 3 Up to 2.5×10 16 / cm 3 , the doping concentration of the first JFET region and the second JFET region is 3×10 16 / cm 3 Up to 2×10 17 / cm 3 .

[0020] In an embodiment of the present application, before forming the gate structure, it also includes: forming a carbon layer on the surface of the source region and the doping region; performing annealing to activate doped ions under the protection of the carbon layer; and removing the carbon layer.

[0021] In an embodiment of the present application, the method for forming the gate structure includes: etching part of the source region, the well region, the first JFET region and the second JFET region, stopping at the surface of the first epitaxial layer and the doped column to form a third trench; forming a gate oxide layer on the sidewall and bottom of the third trench; and forming a gate layer filling the third trench on the surface of the gate oxide layer.

[0022] In an embodiment of the present application, the method for forming the semiconductor structure also includes: forming an interlayer dielectric layer on the surface of the gate structure and a portion of the source region; forming a source contact layer between the interlayer dielectric layers, and the surfaces of the source contact layer and the interlayer dielectric layer are coplanar; and forming a source metal on the surfaces of the interlayer dielectric layer and the source contact layer.

[0023] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0024] The technical solution of the present application forms a doped column in the first epitaxial layer, and forms a first JFET region on part of the doped region, forms a second JFET region on part of the epitaxial layer between adjacent doped columns, forms a doped region extending to the surface of the doped column between adjacent source regions, and the doped column is adjacent to the entire or partial bottom of the gate structure, wherein the first JFET region and the second JFET region can improve the drain-source on-resistance RDS(on), and the doped column can reduce the electric field of the gate oxide layer, thereby improving the reliability of the gate oxide layer and reducing the gate-drain charge.

[0025] The doped columns are discrete and distributed along the extension direction of the gate structure and perpendicular to the extension direction of the gate structure, which can prevent the diffusion of basal plane dislocation defects and improve conductivity. At the same time, the doped columns can form a super junction in the first epitaxial layer, thereby increasing the doping concentration of the first epitaxial layer and thus improving the substrate conductivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only used for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0027] Figure 1 A schematic diagram of the structure of a trench MOSFET;

[0028] Figures 2 to 26 Schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0030] refer to Figure 1 A trench MOSFET includes an epitaxial layer 10, a gate structure 20 is formed in the epitaxial layer 10, a well region 30 is formed between adjacent gate structures 20, an active region 40 is formed in the well region 30, the source region 40 is adjacent to the sidewall of the gate structure 20, and a doping region 50 is formed in the source region 40 and the well region 30, and both the source region 40 and the doping region 50 extend from the surface of the well region 30 to the well region 30. Although this trench MOSFET can improve the current handling capability of the device, it has a higher electric field at the bottom of the gate structure 20, and the gate-drain charge Qgd is large.

[0031] Based on this, the semiconductor structure and formation method of the technical solution of the present application form doped columns in the first epitaxial layer, and form a first JFET region on part of the doped columns, and form a second JFET region on part of the first epitaxial layer between adjacent doped columns, and the doped columns are adjacent to the entire or partial bottom of the gate structure, wherein the first JFET region and the second JFET region can further improve the drain-source on-resistance RDS(on); the doped columns can reduce the electric field of the gate oxide layer, thereby improving the reliability of the gate oxide layer, and at the same time can prevent the diffusion of basal plane dislocation (BPD) defects and improve conductivity; the presence of the doped columns can form a super junction effect, so the substrate resistance can be reduced by increasing the doping concentration of the first epitaxial layer.

[0032] The semiconductor structure of the technical solution of the present application is described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0033] refer to Fig.23 The present invention provides a semiconductor structure, including a substrate, wherein the substrate includes a first epitaxial layer 100. The first epitaxial layer 100 may be doped with impurity ions. For example, nitrogen, arsenic, antimony or phosphorus ions may be implanted. The first epitaxial layer 100 may be N-type silicon carbide, and the doping concentration may be 5×10 15 / cm 3 Up to 2.5×10 16 / cm 3The doping concentration of the first epitaxial layer 100 in the embodiment of the present application is relatively high, so the substrate resistance can be reduced. For different devices, the requirements for the thickness and doping concentration of the first epitaxial layer 100 are different. As an example, for a 650V device, the thickness of the first epitaxial layer 100 can be 5μm to 7μm, and the doping concentration is 1.2×10 16 / cm 3 Up to 2.5×10 16 / cm 3 For a 1200V device, the thickness of the first epitaxial layer 100 may be 9.5 μm to 12.5 μm, and the doping concentration may be 8×10 15 / cm 3 to 1.1×10 16 / cm 3 For a 1700V device, the thickness of the first epitaxial layer 100 may be 13 μm to 16 μm, and the doping concentration may be 5×10 15 / cm 3 Up to 7×10 15 / cm 3 For other devices, the thickness and doping concentration of the first epitaxial layer 100 may also be determined according to actual conditions. In some embodiments, the substrate may further include a silicon carbide substrate 110 located below the first epitaxial layer 100 .

[0034] The doping column 210 is discretely disposed in the first epitaxial layer 100. The doping type of the doping column 210 is different from the doping type of the first epitaxial layer 100. In some embodiments, the first epitaxial layer 100 is N-type doped, and the doping column 210 is P-type doped. The doping concentrations of the doping column 210 and the first epitaxial layer 100 are close to form a super junction. The doping concentration of the doping column 210 can be 5×10 15 / cm 3 Up to 2.5×10 16 / cm 3 The thickness of the doped column 210 is less than or equal to the thickness of the first epitaxial layer 100, and the thickness difference is 0 μm to 11 μm. Figure 2 The doping columns 210 are distributed along the extension direction of the gate structure (y direction) and perpendicular to the extension direction of the gate structure (x direction). This distribution method can prevent the expansion of BPD defects and thus improve the conductivity of the device.

[0035] refer to Fig.23 and Fig.24 , Fig.24 for Fig.23The semiconductor structure further includes a first JFET region 220, which is located on a portion of the doped column 210. The first JFET region 220 is a continuous structure and crosses the doped column 210 in the extension direction of the gate structure, that is, a portion of the first JFET region 220 is located on the doped column 210, and the remaining portion is located on the first epitaxial layer 100 between adjacent doped columns 210. At this time, the first JFET region 220 is adjacent to the first epitaxial layer 100 through the bottom.

[0036] refer to Fig.25 In some other embodiments, the first JFET region 220 is a discontinuous discrete structure and is only located on a portion of the doped column 210. The widths of the first JFET region 220 and the doped column 210 in the extension direction of the gate structure are equal. At this time, the first JFET region 220 is adjacent to the first epitaxial layer 100 through the sidewall.

[0037] The first JFET region 220 has the same doping type as the first epitaxial layer 100 and is opposite to the doping type of the doping column 210. As an example, the first JFET region 220 is N-type doped and has a doping concentration of 3×10 16 / cm 3 Up to 2×10 17 / cm 3 In some embodiments, the thickness of the first JFET region 220 may be 0.3 μm-0.4 μm.

[0038] Continue to refer Fig.23, a second JFET region 230 is further included on a portion of the first epitaxial layer 100 between the adjacent doping columns 210. The arrangement of the first JFET region 220 and the second JFET region 230 can further improve RDS(on). The extension direction of the second JFET region 230 is the same as the extension direction of the gate structure. The second JFET region 230 is a continuous structure, for example, in the shape of a long strip. The surfaces of the first JFET region 220 and the second JFET region 230 are coplanar. As an example, the thickness of the second JFET region 230 is 0.3μm-0.4μm. The second JFET region 230 has the same doping type as the first JFET region 220, and the doping concentration of the first JFET region 220 can be equal to the doping concentration of the second JFET region 230. Since the first JFET region 220 and the first epitaxial layer 100 are blocked by the doping column 210, the doping of the first JFET region 220 can also be greater than the doping concentration of the second JFET region 230, so as to further improve the improvement effect on RDS(on). As an example, the second JFET region 230 is N-type doped, and the doping concentration of the second JFET region 230 is 3×10 16 / cm 3 Up to 2×10 17 / cm 3 .

[0039] The first JFET region 220 and the second JFET region 230 include a well region 240. The depth of the well region 240 may be 0.8 μm-1.0 μm. The well region 240 may be lightly doped with a P-type. For example, the well region 240 may be doped with aluminum ions to make the doping concentration of the well region 240 be 5×10 16 / cm 3 Up to 5×10 20 / cm 3 .

[0040] The source region 250 extends from the surface of the well region 240 to the well region 240, and the doping type of the source region 250 is opposite to that of the well region 240, and the doping type of the first JFET region 220 and the second JFET region 230 is the same. As an example, the source region 250 is N-type doped, and the doping concentration is 1×10 18 / cm 3 Up to 1×10 21 / cm 3In some embodiments, the depth of the source region 250 is 0.2 μm-0.4 μm, wherein the depth of the source region 250 refers to the distance from the surface of the well region 240 to the bottom of the source region 250. Since the surfaces of the source region 250 and the well region 240 are coplanar, the depth of the source region 250 is also the distance from the surface of the source region 250 to the bottom of the source region 250, and the depth of the well region 240 may also refer to the distance from the surface of the source region 250 to the bottom of the well region 240.

[0041] The semiconductor structure of the embodiment of the present application further includes a doping region 260. The doping region 260 is located between the adjacent source regions 250 and extends to the surface of the doping column 210, and the doping region 260 is coplanar with the surface of the source region 250. Extending the doping region 260 to the surface of the doping column 210 can prevent the doping column 210 from becoming a floating junction. The doping region 260 has the same doping type as the doping column 210 and the well region 240, for example, P-type doping. In some embodiments, the doping concentration of the doping region 260 is 3×10 17 / cm 3 Up to 1×10 21 / cm 3 The depth of the doping region 260 is 1.2 μm-1.5 μm, wherein the depth of the doping region 260 refers to the distance from the surface of the doping region 260 to the bottom of the doping region 260 , that is, the distance from the surface of the doping region 260 to the surface of the doping column 210 .

[0042] Continue to refer Fig.23 , the semiconductor structure also includes a gate structure, the gate structure is located in the source region 240 and the well region 240 and extends between the first JFET region 220 and the second JFET region 230, and the entire bottom of the gate structure is adjacent to the doped column 210, or part of the bottom of the gate structure is adjacent to the doped column 210. The gate structure may include a gate oxide layer 310 and a gate layer 320 located on the surface of the gate oxide layer 310. The material of the gate oxide layer 310 may include oxide, oxynitride, etc. The thickness of the gate oxide layer 310 may be between 350 angstroms and 550 angstroms. The material of the gate layer 320 may include polysilicon, and the depth of the gate layer 320 may be 1.1μm-1.5μm. The depth of the gate layer 320 refers to the distance from the surface of the gate layer 320 to the bottom surface of the gate layer 320.

[0043] In the embodiment of the present application, since the doped column 210 covers part or all of the bottom of the gate structure, the electric field of the gate oxide layer is reduced, so the reliability of the gate oxide layer can be significantly improved. Further, since the doped column 210 forms a super junction in the first epitaxial layer 100, the doping concentration of the first epitaxial layer 100 can be increased, thereby significantly reducing the substrate resistance.

[0044] refer to Fig.26 The semiconductor structure may further include: an interlayer dielectric layer 330, wherein the interlayer dielectric layer 330 is located on the surface of the gate structure and a portion of the source region 250; a source contact layer 410, which is located between the interlayer dielectric layers 330, and the surfaces of the source contact layer 410 and the interlayer dielectric layer 330 are coplanar; and a source metal 420, which is located on the surfaces of the interlayer dielectric layer 330 and the source contact layer 410.

[0045] The method for forming a semiconductor structure according to an embodiment of the present application is described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0046] The method for forming a semiconductor structure according to an embodiment of the present application comprises the following steps:

[0047] Step S1: providing a substrate, the substrate comprising a first epitaxial layer, wherein discrete doped columns are formed in the first epitaxial layer, and the surfaces of the doped columns and the first epitaxial layer are coplanar, wherein the thickness of the doped columns is less than or equal to the thickness of the first epitaxial layer, and the thickness difference is 0 μm to 11 μm;

[0048] Step s2: forming a second epitaxial layer on the surfaces of the first epitaxial layer and the doped pillars;

[0049] Step S3: forming a first JFET region in the second epitaxial layer, wherein the first JFET region is located on a portion of the doped column;

[0050] Step S4: forming a second JFET region in the second epitaxial layer, wherein the second JFET region is located on a portion of the first epitaxial layer between adjacent doped columns;

[0051] Step S5: forming a well region in the second epitaxial layer higher than the first JFET region and the second JFET region;

[0052] Step s6: forming a source region extending from the surface of the well region on the first JFET region and the second JFET region to the well region;

[0053] Step S7: forming a doped region extending from the surface of the well region between the adjacent source regions to the surface of the doped column;

[0054] Step S8: etching a portion of the source region, the well region, the first JFET region and the second JFET region, and forming a gate structure at a corresponding position, wherein the entire or a portion of the bottom of the gate structure is adjacent to the doped column.

[0055] refer to Figure 2 and Figure 3 ,in Figure 2 is a top view of the semiconductor structure obtained in step S1, Figure 3 Figure (a) and (b) are Figure 2 Two cross-sectional schematic diagrams at AA. In step S1, a substrate is provided including a first epitaxial layer 100. The material of the first epitaxial layer 100 may include N-type silicon carbide, wherein the doping ions may be nitrogen, arsenic, antimony or phosphorus, etc., and the doping concentration may be 5×10 15 / cm 3 Up to 2.5×10 16 / cm 3 In some embodiments, a silicon carbide substrate 110 is further formed below the first epitaxial layer 100 .

[0056] Discrete doping columns 210 are formed in the first epitaxial layer 100, and the doping columns 210 are distributed along the extension direction of the gate structure (y direction) and perpendicular to the extension direction of the gate structure (x direction). Compared with a continuous structure, this discrete structure can prevent the diffusion of BPD defects and improve conductivity. The doping concentration of the doping column 210 is very close to that of the first epitaxial layer 100, which is conducive to forming a super junction. In some embodiments, the doping column 210 is P-type silicon carbide, and the doping concentration can be 5×10 15 / cm 3 Up to 2.5×10 16 / cm 3 .

[0057] refer to Figure 3 , the surfaces of the doped column 210 and the first epitaxial layer 100 are coplanar, wherein the thickness of the doped column 210 is equal to the thickness of the first epitaxial layer 100 (as shown in Figure a), or the thickness of the doped column 210 is less than the thickness of the first epitaxial layer 100 (as shown in Figure b). The difference in thickness between the doped column 210 and the first epitaxial layer 100 is 0μm to 11μm. By using a thicker doped column 210, a superjunction structure can be formed in the first epitaxial layer 100, and the substrate resistance can be reduced by increasing the doping concentration of the first epitaxial layer 100. Generally speaking, the doping concentration of the first epitaxial layer 100 can be 1×10 14 / cm 3 Up to 1×10 16 / cm 3By introducing the doping column 210, the doping concentration of the first epitaxial layer 100 can be increased to 5×10 15 / cm 3 Up to 2.5×10 16 / cm 3 , thereby significantly reducing the substrate resistance.

[0058] refer to Figure 4 When the thickness of the first epitaxial layer 100 and the doped column 210 are equal, the method for forming the first epitaxial layer 100 and the doped column 210 may include: providing a silicon carbide substrate 110; forming a graphic mask 200 of the doped column 210 on a portion of the silicon carbide substrate 110; forming the first epitaxial layer 100 on the silicon carbide substrate 110 not covered by the graphic mask; removing the graphic mask 200, and forming the doped column 210 at a corresponding position.

[0059] refer to Figure 5 In some other embodiments, when the thicknesses of the first epitaxial layer 100 and the doped pillar 210 are equal, the method for forming the first epitaxial layer 100 and the doped pillar 210 may include: providing a silicon carbide substrate 110; forming the first epitaxial layer 100 on the silicon carbide substrate 110; etching the first epitaxial layer 100 to form a first trench 120, and the first trench 120 penetrates the first epitaxial layer 100; and forming the doped pillar 210 in the first trench 120. The doped pillar 210 may be formed by epitaxially growing P-type silicon carbide.

[0060] refer to Figure 6 When the thickness of the first epitaxial layer 100 is less than the thickness of the doped column 210, the method for forming the first epitaxial layer 100 and the doped column 210 may include: providing a silicon carbide substrate 110; forming a first portion 100a of the first epitaxial layer 100 on the silicon carbide substrate 110; forming a graphic mask 200 of the doped column 210 on part of the first portion 100a of the first epitaxial layer 100; forming a second portion 100b of the first epitaxial layer 100 on the first portion 100a of the first epitaxial layer 100 not covered by the graphic mask 200; removing the graphic mask 200, and forming the doped column 210 at a corresponding position.

[0061] refer to Figure 7When the thickness of the first epitaxial layer 100 is less than the thickness of the doped pillar 210, the first epitaxial layer 100 and the doped pillar 210 may also be formed by the following method: providing a silicon carbide substrate 110; forming the first epitaxial layer 100 on the silicon carbide substrate 110; etching the first epitaxial layer 100 to form a second trench 120, and the second trench 120 does not penetrate the first epitaxial layer 100; forming the doped pillar 210 in the second trench 120. The doped pillar 210 may be formed by epitaxially growing P-type silicon carbide.

[0062] refer to Figure 8 and Fig. 9 , Fig. 9 for Figure 8 A second epitaxial layer 120 is formed on the surface of the first epitaxial layer 100 and the doping column 210 . The thickness, material and doping concentration of the second epitaxial layer 120 may refer to the first epitaxial layer 100 .

[0063] refer to Figures 10 to 12 ,in Fig.10 and Fig.11 This is a schematic diagram of a top view of the structure. In order to illustrate the film layer changes in the second epitaxial layer 120, the Fig.10 and Fig.11 The second epitaxial layer 120 in the embodiment of the present invention. Fig.12 for Fig.10 and Fig.11 The cross-sectional view is taken at CC, and shows the second epitaxial layer 120 . A first JFET region 220 is formed in the second epitaxial layer 120 , and the first JFET region 220 is located on a portion of the doped column 210 .

[0064] refer to Fig.10 In some embodiments, the first JFET region 220 crosses the doped column 210 in the extension direction (y direction) of the gate structure, that is, part of the first JFET region 220 is located on the doped column 210, and the rest of the first JFET region 220 is located on the first epitaxial layer 100 between adjacent doped columns 210. Fig.11 In other embodiments, the first JFET region 220 does not cross the doped column 210 in the extension direction (y direction) of the gate structure, that is, the first JFET region 220 is separately located on the doped column 210, and the first JFET region 220 and the doped column 210 have the same width in the extension direction (y direction) of the gate structure. The sidewall of one side of the first JFET region 220 and the doped column 210 may be coplanar or non-coplanar.

[0065] The formation process of the first JFET region 220 may include: forming a patterned first oxide layer (not shown) on the surface of the first epitaxial layer 100, wherein the first oxide layer exposes the area to be ion implanted and acts as a mask, and the thickness of the first oxide layer may be 1.2 μm-2.0 μm; performing an ion implantation process, wherein the ion implantation temperature may be controlled at 20° C.-40° C. or 500° C.-600° C., and the implanted ion type may be the same as the doping ion type of the first epitaxial layer 100, for example, N-type ions may be implanted, and the doping concentration may be 3×10 16 / cm 3 Up to 2×10 17 / cm 3 ; removing the first oxide layer.

[0066] Fig.13 is Fig.10 A schematic diagram of the structure obtained by adding a second JFET region 230 on the basis of FIG. Fig.14 yes Fig.13 The cross-sectional view at DD in the figure is shown in Figure 1. Fig.14 The second epitaxial layer 120 is shown. A second JFET region 230 is formed in the second epitaxial layer 120, and the second JFET region 230 is located on the first epitaxial layer 100 between adjacent doping columns 210. The formation method may include: forming a patterned second oxide layer (not shown) on the surface of the second epitaxial layer 120, the second oxide layer exposing an ion implantation region, and the second oxide layer may have the same thickness as the first oxide layer; performing ion implantation, the ion implantation temperature may be 20°C-40°C or 500°C-600°C, the implanted ion type may be the same as the doping ion type of the first epitaxial layer 100, for example, N-type ions may be implanted, and the doping concentration of the ion implantation is less than or equal to the doping concentration of the first JFET region 220, for example, 3×10 16 / cm 3 Up to 2×10 17 / cm 3 ; removing the second oxide layer.

[0067] The second JFET region 230 is formed in the same extension direction as the gate structure and is coplanar with the surface of the first JFET region 220 .

[0068] refer to Fig.15 and Fig.16 ,in Fig.16 for Fig.15A cross-sectional view at EE in FIG. A well region 240 is formed in the second epitaxial layer 120 which is higher than the first JFET region 220 and the second JFET region 230. The method for forming the well region 240 may include: forming a third oxide layer (not shown) on the surface of the second epitaxial layer 120, wherein the thickness of the third oxide layer is 1.6 μm-2.0 μm; performing ion implantation on the surface of the third oxide layer, wherein the temperature during ion implantation may be 500° C.-600° C., wherein the type of implanted ions is the same as the doping type of the doping column 210, for example, the type of implanted ions is P type, and the doping ions are, for example, aluminum ions, and the doping concentration may be 3×10 17 / cm 3 Up to 1×10 21 / cm 3 ; removing the third oxide layer.

[0069] refer to Fig.17 and Fig.18 ,in Fig.18 for Fig.17 A cross-sectional view at FF in FIG. A source region 250 is formed extending from the surface of the well region 240 on the first JFET region 220 and the second JFET region 230 to the well region 240. The method for forming the source region 250 comprises: forming a patterned fourth oxide layer (not shown) on the surface of the well region 240, wherein the fourth oxide layer exposes an ion implantation region, and the thickness of the fourth oxide layer may be, for example, 1 μm; performing ion implantation, wherein the temperature during ion implantation may be 500° C.-600° C., and the type of implanted ions is the same as the type of doped ions of the first epitaxial layer 100, the second epitaxial layer 120, the first JFET region 220, and the second JFET region 230, and the concentration of the ion implantation is 3×10 16 / cm 3 Up to 2×10 17 / cm 3 ; removing the fourth oxide layer.

[0070] refer to Fig.19 and Fig. 20 ,in Fig. 20 for Fig.19A cross-sectional view at GG in FIG. A doping region 260 is formed extending from the surface of the well region 240 between the adjacent source regions 250 to the surface of the doping column 210. The formation process of the doping region 260 may include: forming a fifth oxide layer (not shown) on the surface of the source region 250, the thickness of the fifth oxide layer may be 1.2 μm-1.6 μm; using the fifth oxide layer as a mask, ion implantation is performed, the ion implantation temperature may be 500°C-600°C, the type of ion implantation may be the same as the doping type of the doping column 210 and the well region 260, the doping ions may be, for example, aluminum ions, and the doping concentration may be 3×10 17 / cm 3 Up to 1×10 21 / cm 3 ; removing the fifth oxide layer.

[0071] Before forming the gate structure, the following process may also be performed: forming a carbon layer on the surface of the source region 250 and the doping region 260 by processes such as carbonizing photoresist or depositing carbon powder; annealing is performed at 1600°C-1800°C in an argon atmosphere to activate all previously doped ions. Since the surfaces of the source region 250 and the doping region 260 react with trace oxygen or nitrogen oxides in the atmosphere during the annealing process, the carbon layer can play an isolation and protection role; and then the carbon layer is removed.

[0072] refer to Fig.21 and Fig. 22 ,in Fig. 22 for Fig.21 The source region 250, the well region 240, the first JFET region 220 and the second JFET region 230 are partially etched, and the etching stops at the surface of the first epitaxial layer 100 and the doped column 210 to form a third trench 301. In some embodiments, the inner wall of the third trench 301 may be repaired, for example, a dielectric layer may be deposited on the inner wall of the third trench 301 for repair.

[0073] refer to Fig.23, a gate oxide layer 310 is formed on the sidewall and bottom of the third trench 301, and the process of forming the gate oxide layer 310 can be a deposition process such as high temperature oxidation, chemical vapor deposition, physical vapor deposition, etc. The material of the gate oxide layer 310 can include at least one of silicon oxide, silicon nitride and oxynitride, such as a combination of SiO2, Si3N4, etc. After the gate oxide layer 310 is formed, a high temperature annealing can be performed at 1200°C-1350°C in a gas such as NO or N2O. Then, a gate layer 320 filling the third trench 301 is formed on the surface of the gate oxide layer 310. The process of forming the gate layer 320 can include: forming a gate material layer in the third trench 301 and on the surface of the source region 250 and the doping region 260 by a deposition process; grinding the gate material layer by a process such as chemical mechanical grinding or physical mechanical grinding, so that the gate material layer is coplanar with the surface of the source region 250 and the doping region 260 to form the gate layer 320.

[0074] refer to Fig.26 , the method for forming the semiconductor structure may further include: forming an interlayer dielectric layer 330 on the surface of the gate structure and part of the source region 250. The process of forming the interlayer dielectric layer 330 may include: depositing an interlayer dielectric material on the surface of the gate structure, the source region 250 and the doping region 260 by a deposition process such as chemical vapor deposition, physical vapor deposition or atomic layer deposition; etching the interlayer dielectric material to expose the surface of the doping region 260 and part of the source region 250 adjacent to the doping region 260 to form the interlayer dielectric layer 330. The material of the interlayer dielectric layer 330 may include phosphosilicate glass material (PSG), plasma enhanced tetraethyl orthosilicate material (PE-TEOS) or borophosphosilicate glass material (BPSG), etc. The thickness of the interlayer dielectric layer 330 may be 0.5μm-1.5μm.

[0075] In some embodiments, the method for forming the semiconductor structure may further include: forming a source contact layer 410 between the interlayer dielectric layers 330. The source contact layer 410 may form an ohmic contact. The method for forming the source contact region 410 may include: forming a source contact material layer on the surface of the interlayer dielectric layer 330, the source region 250 and the doping region 260 by a deposition process such as physical vapor deposition, chemical vapor deposition or atomic layer deposition; then performing a first annealing treatment at 700°C-850°C; etching and removing the source contact material layer on the surface of the interlayer dielectric layer 330, leaving only the source contact material layer on the surface of the source region 250 and the doping region 260; performing a second annealing treatment at 1000°C-1100°C to form the source contact layer 410, and the surface of the source contact layer 410 is coplanar with the top surface of the interlayer dielectric layer 330. The material of the source contact layer 410 may include nickel. The thickness of the source contact layer 410 may be 500 angstroms-1000 angstroms.

[0076] In some embodiments, after forming the source contact layer 410 , a contact hole may be further formed.

[0077] Continue to refer Fig.26 The method for forming the semiconductor structure may further include: forming a source metal 420 on the surface of the interlayer dielectric layer 330 and the source contact layer 410. The source metal 420 includes aluminum, for example. The thickness of the source metal 420 may be 2.5 μm-4.5 μm.

[0078] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0079] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can also be intermediate elements.

[0080] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0081] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0082] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, characterized in that: include: a substrate comprising a first epitaxial layer; a doped column, discretely located in the first epitaxial layer and coplanar with a surface of the first epitaxial layer, wherein the thickness of the doped column is less than or equal to the thickness of the first epitaxial layer, and the thickness difference is 0 μm to 11 μm, and the doping type of the doped column is different from the doping type of the first epitaxial layer; A first JFET region is located on a portion of the doped column; A second JFET region is located on a portion of the first epitaxial layer between adjacent doped columns; a well region located on the first JFET region and the second JFET region; A source region extending from the surface of the well region into the well region; a doped region, located between adjacent source regions and extending to the surface of the doped column; A gate structure is located in the source region and the well region and extends between the first JFET region and the second JFET region, and the entire or a portion of the bottom of the gate structure is adjacent to the doped column.

2. The semiconductor structure according to claim 1, characterized in that: The doped columns are distributed along the extension direction of the gate structure and perpendicular to the extension direction of the gate structure, the first JFET region crosses or does not cross the doped columns in the extension direction of the gate structure, and the second JFET region has the same extension direction as the gate structure.

3. The semiconductor structure according to claim 1, characterized in that: Surfaces of the first JFET region and the second JFET region are coplanar.

4. The semiconductor structure according to claim 1, characterized in that: The depth of the source region is 0.2 μm-0.4 μm; the depth of the doping region is 1.2 μm-1.5 μm; the depth of the well region is 0.8 μm-1.0 μm; and the thickness of the first JFET region and the second JFET region is 0.3 μm-0.4 μm.

5. The semiconductor structure according to claim 1, characterized in that: The gate structure includes a gate oxide layer and a gate layer located on the surface of the gate oxide layer.

6. The semiconductor structure according to claim 5, characterized in that: The depth of the gate layer is 1.1 μm-1.5 μm.

7. The semiconductor structure according to claim 1, characterized in that: The first epitaxial layer, the first JFET region, the second JFET region and the source region have the same doping type; the doping column, the doping region and the well region have the same doping type; wherein the doping concentration of the first JFET region is greater than or equal to the doping concentration of the second JFET region.

8. The semiconductor structure according to claim 1, characterized in that: The doping concentration of the first epitaxial layer and the doped column is 5×10 15 / cm 3 Up to 2.5×10 16 / cm 3 , the doping concentration of the first JFET region and the second JFET region is 3×10 16 / cm 3 Up to 2×10 17 / cm 3 .

9. The semiconductor structure according to claim 1, characterized in that: Also includes: An interlayer dielectric layer, located on the surface of the gate structure and part of the source region; A source contact layer, located between the interlayer dielectric layers, and the surfaces of the source contact layer and the interlayer dielectric layer are coplanar; The source metal is located on the surface of the interlayer dielectric layer and the source contact layer.

10. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first epitaxial layer, wherein discrete doping columns are formed in the first epitaxial layer, and the surfaces of the doping columns and the first epitaxial layer are coplanar, wherein the thickness of the doping columns is less than or equal to the thickness of the first epitaxial layer, and the thickness difference is 0 μm to 11 μm, and the doping type of the doping columns is different from the doping type of the first epitaxial layer; forming a second epitaxial layer on surfaces of the first epitaxial layer and the doped pillars; forming a first JFET region in the second epitaxial layer, wherein the first JFET region is located on a portion of the doped column; forming a second JFET region in the second epitaxial layer, wherein the second JFET region is located on the first epitaxial layer between adjacent doped columns; forming a well region in a second epitaxial layer higher than the first JFET region and the second JFET region; A source region formed extending from a surface of a well region on the first JFET region and the second JFET region to the well region; forming a doped region extending from the surface of the well region between adjacent source regions to the surface of the doped column; Part of the source region, the well region, the first JFET region and the second JFET region are etched, and a gate structure is formed at a corresponding position, and the entire or a part of the bottom of the gate structure is adjacent to the doped column.

11. The method for forming a semiconductor structure according to claim 10, characterized in that: The doped columns are distributed along the extension direction of the gate structure and perpendicular to the extension direction of the gate structure, the first JFET region crosses or does not cross the doped columns in the extension direction of the gate structure, and the second JFET region has the same extension direction as the gate structure.

12. The method for forming a semiconductor structure according to claim 10, wherein: The substrate further comprises a silicon carbide substrate; when the thickness of the first epitaxial layer and the doped column are equal, the forming method comprises: Providing a silicon carbide substrate; forming a pattern mask of the doped column on a portion of the silicon carbide substrate; forming the first epitaxial layer on the silicon carbide substrate not covered by the pattern mask; removing the pattern mask and forming the doped column at a corresponding position; Alternatively, the forming method comprises: Providing a silicon carbide substrate; forming the first epitaxial layer on the silicon carbide substrate; Etching the first epitaxial layer to form a first trench, wherein the first trench penetrates the first epitaxial layer; The doped column is formed in the first trench.

13. The method for forming a semiconductor structure according to claim 10, wherein: The substrate further comprises a silicon carbide substrate; when the thickness of the first epitaxial layer is less than the thickness of the doped column, the forming method comprises: providing a silicon carbide substrate; forming a first portion of the first epitaxial layer on the silicon carbide substrate; forming a pattern mask of the doped pillar on a first portion of the first epitaxial layer; forming a second portion of the first epitaxial layer on the first portion of the first epitaxial layer not covered by the pattern mask; removing the pattern mask and forming the doped column at a corresponding position; Alternatively, the forming method comprises: Providing a silicon carbide substrate; forming the first epitaxial layer on the silicon carbide substrate; The first epitaxial layer is etched to form a second trench, wherein the second trench does not penetrate the first epitaxial layer; and the doped column is formed in the second trench.

14. The method for forming a semiconductor structure according to claim 10, wherein: The first JFET region, the second JFET region, the well region, the source region and the doped region are formed by an ion implantation process; wherein the temperature of the ion implantation process for forming the well region, the source region and the doped region is 500°C-600°C, and the temperature of the ion implantation process for forming the first JFET region and the second JFET region is 20°C-40°C or 500°C-600°C.

15. The method for forming a semiconductor structure according to claim 10, wherein: The first epitaxial layer, the second epitaxial layer, the first JFET region, the second JFET region and the source region have the same doping type; the doping column, the doping region and the well region have the same doping type; wherein the doping concentration of the first JFET region is greater than or equal to the doping concentration of the second JFET region.

16. The method for forming a semiconductor structure according to claim 15, characterized in that: The doping concentration of the first epitaxial layer and the doped column is 5×10 15 / cm 3 Up to 2.5×10 16 / cm 3 , the doping concentration of the first JFET region and the second JFET region is 3×10 16 / cm 3 Up to 2×10 17 / cm 3 .

17. The method for forming a semiconductor structure according to claim 10, wherein: Before forming the gate structure, the method further includes: forming a carbon layer on the surfaces of the source region and the doping region; Under the protection of the carbon layer, annealing is performed to activate doping ions; The carbon layer is removed.

18. The method for forming a semiconductor structure according to claim 10, wherein: The method of forming the gate structure includes: Etching a portion of the source region, the well region, the first JFET region, and the second JFET region, stopping at the surfaces of the first epitaxial layer and the doped column, to form a third trench; forming a gate oxide layer on the sidewalls and bottom of the third trench; A gate layer filling the third trench is formed on the surface of the gate oxide layer.

19. The method for forming a semiconductor structure according to claim 10, wherein: Also includes: forming an interlayer dielectric layer on the surface of the gate structure and a portion of the source region; forming a source contact layer between the interlayer dielectric layers, wherein the surfaces of the source contact layer and the interlayer dielectric layer are coplanar; A source metal is formed on surfaces of the interlayer dielectric layer and the source contact layer.

Images