Semiconductor structure and method for manufacturing the same

Abstract

An embodiment of the present invention provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises: a substrate and a first conductive layer located on the substrate; a second conductive layer, the second conductive layer being located on a surface of the first conductive layer away from the substrate; and a third conductive layer, the third conductive layer covering a side wall of the first conductive layer and contacting the second conductive layer, wherein the contact resistance between the third conductive layer and the second conductive layer is less than the contact resistance between the first conductive layer and the second conductive layer. The present invention is conducive to improving the signal transmission performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Memory is a memory component used to store programs and various data information. It can be divided into read-only memory and random access memory according to the type of memory used. Memory usually includes capacitors and transistors connected to the capacitors. The capacitors are used to store charges representing stored information, and the transistors are switches that control the flow and release of charges in the capacitors. Among them, the transistors are formed with a source, a drain, and a gate, and the drain is connected to the bit line.

[0003] However, as process nodes continue to shrink, the problem of obstructed memory signal transmission becomes more and more serious. How to solve this problem has become an important direction for memory process optimization. Summary of the invention

[0004] The embodiments of the present invention provide a semiconductor structure and a manufacturing method thereof, which are beneficial to improving the signal transmission performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate and a first conductive layer located on the substrate; a second conductive layer, the second conductive layer is located on the surface of the first conductive layer away from the substrate; a third conductive layer, the third conductive layer covers the side wall of the first conductive layer and contacts with the second conductive layer, and the contact resistance between the third conductive layer and the second conductive layer is smaller than the contact resistance between the first conductive layer and the second conductive layer.

[0006] In addition, the top surface of the third conductive layer contacts the bottom surface of the second conductive layer, which is beneficial to reducing the contact resistance between the bottom surface of the second conductive layer and other active areas, so that the current signal flowing through the bottom surface of the second conductive layer has a better transmission effect.

[0007] In addition, the sidewall of the first conductive layer includes a first sub-sidewall and a second sub-sidewall extending upward from the bottom of the first conductive layer, the first sub-sidewall is located between the second sub-sidewall and the bottom of the first conductive layer, and the third conductive layer covers the second sub-sidewall.

[0008] In addition, in a direction perpendicular to the substrate surface, the ratio of the height of the second sub-sidewall to the height of the first sub-sidewall is 5 to 10. This is beneficial to ensure that the semiconductor structure has a good signal transmission effect, and to avoid signal crosstalk between the substrate and the second conductive layer caused by the third conductive layer being too close to the substrate.

[0009] In addition, in a direction perpendicular to the surface of the substrate, the first conductive layer is also located between the third conductive layer and the substrate.

[0010] In addition, in a direction parallel to the surface of the substrate, the top width of the third conductive layer is greater than the bottom width of the third conductive layer. This is conducive to making the active area between the substrate and the second conductive layer have a lower resistance on the side close to the second conductive layer and a higher resistance on the side close to the substrate, so that the current signal is more likely to be transmitted from the second conductive layer to the substrate, and is not easy to be transmitted from the substrate to the second conductive layer, thereby avoiding the current signal in the substrate interfering with the current signal in the second conductive layer.

[0011] In addition, in a direction parallel to the surface of the substrate, a top width of the first conductive layer is smaller than a bottom width of the first conductive layer.

[0012] In addition, the side wall surface of the first conductive layer is an arc surface, and in the direction from the second conductive layer toward the substrate, the width of the first conductive layer in a direction parallel to the surface of the substrate increases gradually.

[0013] In addition, the substrate has an active area, the first conductive layer is in contact with the active area, and the active area includes an N-type doped semiconductor layer.

[0014] In addition, the semiconductor structure also includes: a metal conductive layer and a top dielectric layer, the metal conductive layer is located on the side of the second conductive layer away from the first conductive layer, and the top dielectric layer is located on the side of the metal conductive layer away from the substrate; the first conductive layer, the second conductive layer, the third conductive layer, the metal conductive layer, and the top dielectric layer constitute a bit line structure.

[0015] In addition, the material of the first conductive layer includes polysilicon, and the materials of the second conductive layer and the third conductive layer include metal compounds. The bit line structure contacts the active area through polysilicon, which can avoid the junction stress and junction leakage problems of the active area generated by the metal-silicon contact interface.

[0016] In addition, the material of the second conductive layer includes titanium nitride, and the material of the third conductive layer includes cobalt silicide or titanium silicide.

[0017] Correspondingly, an embodiment of the present invention also provides a method for manufacturing a semiconductor structure, comprising: providing a substrate and a bit line structure located on the substrate, the bit line structure comprising a first conductive layer, a second conductive layer, a metal conductive layer and a top dielectric layer stacked in sequence; forming a third conductive layer covering the side wall of the first conductive layer and contacting the second conductive layer, the contact resistance between the third conductive layer and the second conductive layer being smaller than the contact resistance between the first conductive layer and the second conductive layer.

[0018] In addition, the bit line structure may be formed through a self-aligned double patterning process (SADP) and a self-aligned quadruple patterning process (SAQP).

[0019] In addition, before forming the third conductive layer, an etching process is performed on the first conductive layer so that a top width of the first conductive layer in a direction parallel to the substrate surface is smaller than a bottom width.

[0020] In addition, the material of the first conductive layer includes polysilicon, and the materials of the second conductive layer and the third conductive layer include metal compounds.

[0021] In addition, the process steps of forming the third conductive layer include: forming a metal layer covering the sidewalls of the first conductive layer; and converting the metal layer into a metal silicide layer to form the third conductive layer.

[0022] In addition, the process steps for forming the metal silicide layer include: performing a high temperature process to make the first conductive layer react with the metal layer to form the metal silicide layer.

[0023] In addition, the process steps for forming a metal layer covering the side walls of the first conductive layer include: forming a metal film, the metal film covering the exposed surfaces of the substrate and the bit line structure; removing the metal film on the surface of the substrate to form a metal layer, the metal layer covering at least part of the side walls of the first conductive layer, the side walls of the second conductive layer, and the side walls of the metal conductive layer.

[0024] In addition, after forming the third conductive layer, the method further includes: removing the unreacted metal layer on the sidewall of the bit line structure.

[0025] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0026] In the above technical solution, by setting a third conductive layer with a smaller contact resistance with the second conductive layer, the total contact resistance between the second conductive layer and other active areas is reduced, thereby reducing the resistance on the current transmission path between the second conductive layer and the substrate, thereby ensuring that the current signal flowing from the second conductive layer to the substrate has a better signal transmission effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0028] Figures 1 to 5 Schematic diagram of cross-sectional structures of different semiconductor structures provided by embodiments of the present invention;

[0029] Figures 6 to 9 A schematic cross-sectional structure diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0030] Fig.10 A schematic cross-sectional structure diagram corresponding to a step in a method for manufacturing a semiconductor structure provided by another embodiment of the present invention;

[0031] Fig.11 A schematic cross-sectional structure diagram corresponding to a step in a method for manufacturing a semiconductor structure provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0033] refer to Figure 1 The semiconductor structure includes: a substrate 10 and a first conductive layer 11 located on the substrate 10; a second conductive layer 12, the second conductive layer 12 is located on the surface of the first conductive layer 11 away from the substrate 10; a third conductive layer 13, the third conductive layer 13 covers the side wall of the first conductive layer 11 and contacts the second conductive layer 12, and the contact resistance between the third conductive layer 13 and the second conductive layer 12 is less than the contact resistance between the first conductive layer 11 and the second conductive layer 12.

[0034] In this embodiment, the substrate 10 has an active region 101, and isolation structures 102 are provided on both sides of the active region 101. Since the top width of the isolation structure 102 is generally greater than the bottom width in the direction perpendicular to the surface of the substrate 10, the top width of the active region 101 between adjacent isolation structures 102 is generally less than the bottom width. In order to allow a larger contact area between the first conductive layer 11 and the active region 101, the exposed area of ​​the active region 101 can be increased by etching the substrate 10, thereby reducing the contact resistance between the first conductive layer 11 and the active region 101 and improving the current transmission effect.

[0035] In this embodiment, the setting of the third conductive layer 13 is equivalent to connecting a resistor in parallel between the second conductive layer 12 and the substrate 10. The parallel connection of resistors will reduce the total resistance on the conductive path between the second conductive layer 12 and the substrate 10, thereby improving the current transmission rate and increasing the current margin; in addition, the contact resistance between the third conductive layer 13 and the second conductive layer 12 is small, and the setting of the third conductive layer 13 is equivalent to connecting a resistor with a smaller resistance in parallel. Since the total resistance of multiple resistors after parallel connection is less than the smallest resistance of the multiple resistors, the setting of the third conductive layer 13 is conducive to further reducing the total resistance of the conductive path, thereby achieving a better current transmission effect.

[0036] In this embodiment, the top surface of the third conductive layer 13 contacts the bottom surface of the second conductive layer 12, which is beneficial to reduce the contact resistance in the direction perpendicular to the bottom surface of the second conductive layer 12, so that the current signal flowing through the bottom surface of the second conductive layer 12 has a better signal transmission effect; in other embodiments, refer to Figure 2 The third conductive layer 23 contacts the side wall of the second conductive layer 22. Due to the increase in contact area, the contact between the third conductive layer 23 and the side wall of the second conductive layer 22 can also reduce the total resistance of the conductive path.

[0037] In this embodiment, in a direction parallel to the surface of the substrate 10, the third conductive layer 13 partially protrudes relative to the second conductive layer 12; Figure 3 In the direction perpendicular to the surface of the substrate 30, the orthographic projection of the third conductive layer 33 coincides with the orthographic projection boundary of the second conductive layer 32; in another embodiment, the orthographic projection of the third conductive layer may also be located within the orthographic projection of the second conductive layer.

[0038] In this embodiment, the sidewall of the first conductive layer 11 includes a first sub-sidewall (not labeled) and a second sub-sidewall (not labeled) extending upward from the bottom of the first conductive layer 11, the first sub-sidewall is located between the second sub-sidewall and the bottom of the first conductive layer 11, and the third conductive layer 13 covers the second sub-sidewall. The third conductive layer 13 only covers part of the sidewall of the first conductive layer 11, which is conducive to preventing the third conductive layer 13 from contacting with the substrate 10 to form a new interface, thereby preventing the formation of the new interface from destroying the signal transmission characteristics between the first conductive layer 11 and the substrate 10.

[0039] In this embodiment, in the direction perpendicular to the surface of the substrate 10, the ratio of the height of the second sub-sidewall to the height of the first sub-sidewall is 5 to 10, for example, 6, 8 or 9. The height of the first sub-sidewall ranges from 2 nm to 10 nm, and the height of the second sub-sidewall ranges from 10 nm to 50 nm. The use of a ratio within this range is beneficial to ensure that the third conductive layer 13 has a larger contact area with the first conductive layer 11, so that the third conductive layer 13 has a better effect of reducing the total resistance, and is also beneficial to avoid the third conductive layer 13 being too close to the substrate 10, causing signal crosstalk between the substrate 10 and the third conductive layer 13, thereby avoiding the signal in the substrate 10 from interfering with the signal in the second conductive layer 12.

[0040] In this embodiment, in a direction perpendicular to the surface of the substrate 10 , the first conductive layer 11 is also located between the third conductive layer 13 and the substrate 10 , so as to block the third conductive layer 13 and the substrate 10 .

[0041] In this embodiment, the active region 101 includes an N-type doped semiconductor layer.

[0042] In this embodiment, the active area 101 is a drain, the first conductive layer 11 is a bit line contact, the second conductive layer 12 is a blocking layer, and the signal in the bit line structure needs to be transmitted to the drain through the second conductive layer 12 and the first conductive layer 11 to achieve data storage.

[0043] The material of the active area 101 may be single crystal silicon, and the material of the first conductive layer 11 may be polycrystalline silicon; in addition, the material of the first conductive layer 11 may be N-type doped polycrystalline silicon, and the ion doping in the first conductive layer 11 may be heavily doped, which is conducive to making the first conductive layer 11 have good conductivity. The bit line structure contacts the active area through polycrystalline silicon, which can avoid the junction stress and junction leakage problems of the active area caused by the contact interface formed by the direct contact between metal and silicon.

[0044] In this embodiment, the thickness of the third conductive layer 13 at different positions of the sidewall of the first conductive layer 11 is equal in the direction parallel to the surface of the substrate 10. It should be noted that the expression "equal" does not refer to absolute equality in value. Due to the limitation of the process level, the thickness can be considered "equal" when the difference between the two is within a preset range and does not affect the structural performance.

[0045] In other embodiments, reference Figure 4 , in a direction parallel to the surface of the substrate 40 , the top width of the third conductive layer 43 is greater than the bottom width.

[0046] Since the flow of current has a tendency, the current tends to flow in the direction of lower resistance. In the direction parallel to the surface of the substrate 40, the larger the width of the third conductive layer 43, the larger the cross-sectional area of ​​the conductive path between the substrate 40 and the second conductive layer 42, and the smaller the resistance of the conductive path.

[0047] By controlling the top width of the third conductive layer 43 to be larger than the bottom width, the conductive path can have a lower resistance on the side close to the second conductive layer 42 and a higher resistance on the side close to the substrate 40. This helps ensure that the current signal in the second conductive layer 42 can be transmitted to the substrate 40, and helps prevent the signal in the substrate 40 from being transmitted to the second conductive layer 42, thereby preventing the current signal in the substrate 40 from interfering with the current signal in the second conductive layer 42.

[0048] It should be noted that, since the third conductive layer 43 is not in contact with the active region 401 , the junction stress and junction leakage problems in the active region are avoided.

[0049] In addition, in a direction parallel to the surface of the substrate 40, the top width of the first conductive layer 41 is smaller than the bottom width. In this way, part of the third conductive layer 43 can be placed between the first conductive layer 41 and the second conductive layer 42, thereby reducing the protrusion of the third conductive layer 43 relative to the second conductive layer 42, so that the overall structure occupies a smaller space, which is conducive to reserving more space for other structures located between adjacent bit line structures and reducing the size of the semiconductor structure. In another embodiment of the present invention, reference Figure 5 The side wall surface of the first conductive layer 51 is an arc surface, and in the direction from the second conductive layer 52 to the substrate 50, the width of the first conductive layer 51 in the direction parallel to the surface of the substrate 50 increases gradually; correspondingly, in the direction from the second conductive layer 52 to the substrate 50, the width of the third conductive layer 53 in the direction parallel to the surface of the substrate 50 decreases gradually.

[0050] In this embodiment, the semiconductor structure also includes: a metal conductive layer 14 and a top dielectric layer 15. The metal conductive layer 14 is located on the side of the second conductive layer 12 away from the first conductive layer 11. The second conductive layer 12 is used to block the metal diffusion in the metal conductive layer 14. The top dielectric layer 15 is located on the side of the metal conductive layer 14 away from the substrate 10. The top dielectric layer 15 plays a role of electrical isolation.

[0051] In this embodiment, the first conductive layer 11, the second conductive layer 12, the third conductive layer 13, the metal conductive layer 14 and the top dielectric layer 15 together constitute a bit line structure, wherein the first conductive layer 11 serves as a bit line contact, the second conductive layer 12 serves as a barrier layer, the metal conductive layer 14 serves as a bit line conductive layer, and the top dielectric layer 15 serves as a bit line protection layer.

[0052] In this embodiment, the material of the first conductive layer 11 is polysilicon, and the materials of the second conductive layer 12 and the third conductive layer 13 include metal compounds. The third conductive layer 13 is selected to have a material type consistent with the material type of the second conductive layer 12, so that the second conductive layer 12 and the third conductive layer 13 have a smaller contact resistance. In other embodiments, the material of the first conductive layer can also be other conductive materials. The signal in the metal conductive layer 14 needs to be transmitted to the active area through the first conductive layer 11 and the second conductive layer 12 to realize data storage. Due to the reduction of contact resistance, the read and write performance of the memory can be improved.

[0053] In addition, the contact resistance between the third conductive layer 13 and the first conductive layer 11 is smaller than the contact resistance between the second conductive layer 12 and the first conductive layer 11. This is beneficial to further improve the signal transmission effect between the second conductive layer 12 and the substrate 10.

[0054] Specifically, the material of the second conductive layer 12 includes titanium nitride, and the material of the third conductive layer 13 includes metal silicide, and the metal silicide includes cobalt silicide or titanium silicide.

[0055] In this embodiment, by providing a third conductive layer having a smaller contact resistance with the second conductive layer, the total contact resistance between the second conductive layer and other active areas is reduced, thereby reducing the resistance on the conductive path between the second conductive layer and the substrate, thereby ensuring that the current signal flowing from the second conductive layer to the substrate has a better signal transmission effect.

[0056] Correspondingly, an embodiment of the present invention further provides a method for manufacturing a semiconductor structure, which can be used to manufacture the above-mentioned semiconductor structure.

[0057] Figures 6 to 9 A schematic diagram of the cross-sectional structure corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention.

[0058] refer to Figure 6A substrate 10 and a first conductive layer 11 and a second conductive layer 12 sequentially stacked on the substrate 10 are provided, and the second conductive layer 12 is located on a surface of the first conductive layer 11 away from the substrate 10 .

[0059] The semiconductor structure also includes a metal conductive layer 14 located on the second conductive layer 12 away from the surface of the substrate 10, and a top dielectric layer 15 located on the metal conductive layer 14 away from the surface of the substrate 10. The metal conductive layer 14 is used to transmit bit line signals and can be a metal material such as tungsten, titanium, tantalum, etc. The top dielectric layer 15 is used to play an electrical isolation role and can be a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, etc. The first conductive layer 11, the second conductive layer 12, the metal conductive layer 14, the top dielectric layer 15 and the third conductive layer formed subsequently constitute a bit line structure.

[0060] In this embodiment, the substrate 10 has isolation structures 102 and active regions 101 between adjacent isolation structures 102, and the first conductive layer 11 is electrically connected to the active regions 101. The first conductive layer 11 may be N-type doped polysilicon, and the active regions 101 may be N-type doped single crystal silicon.

[0061] In this embodiment, according to the difference in sidewall morphology at different positions of the first conductive layer 11, the first conductive layer 11 can be divided into a bottom conductive layer 111 and a top conductive layer 112, the bottom conductive layer 111 is in contact with the active area 101, and the top conductive layer 112 is in contact with the second conductive layer 12. In the direction perpendicular to the surface of the substrate 10, the orthographic projection of the top conductive layer 112 coincides with the orthographic projection boundary of the second conductive layer 12 or is located within the orthographic projection of the second conductive layer 12, and the orthographic projection of the top conductive layer 112 is located within the orthographic projection of the bottom conductive layer 111.

[0062] The bottom conductive layer 111 completely covers the exposed surface of the active area 101, thereby blocking the subsequently formed third conductive layer and the active area 101, and avoiding direct contact between the third conductive layer and the active area 101; accordingly, since the bottom conductive layer 111 can play an isolation role, the top conductive layer 112 can have a narrower width, thereby achieving a size reduction of the bit line structure and reserving more space for other structures located between adjacent bit line structures.

[0063] The reasons for the formation of the bottom conductive layer 111 include: the etching components are reduced during the etching process and the etching components are gathered toward the etching center, resulting in that part of the material of the first conductive layer 11 is not etched.

[0064] refer to Figure 7 , forming a metal film 131 to be etched.

[0065] The metal film 131 covers the surface of the substrate 10, the sidewalls of the first conductive layer 11, the sidewalls of the second conductive layer 12, the sidewalls of the metal conductive layer 14, and the sidewalls and top surface of the top dielectric layer 15. The metal film 131 can be formed by an atomic layer deposition process to better control the thickness of the metal film 131 located on the sidewalls of the first conductive layer 11, thereby controlling the thickness of the subsequently formed third conductive layer in a direction parallel to the surface of the substrate 10.

[0066] In other embodiments, reference Figure 8 , before forming the metal film, the first conductive layer 51 is etched to form a curved sidewall, and in the direction from the second conductive layer 52 to the substrate 50, the width of the first conductive layer 51 in the direction parallel to the surface of the substrate 50 decreases. In this way, the first conductive layer 51 can accommodate part of the third conductive layer formed subsequently, thereby reducing the width of the bit line structure in the direction parallel to the surface of the substrate 50 and the space occupied by the bit line structure.

[0067] refer to Fig. 9 , etching the metal film 131 (reference Figure 7 ) to form a metal layer 132 to be reacted.

[0068] In this embodiment, a dry etching process may be used to remove the metal film 131 on the surface of the substrate 10 to form a metal layer 132. The etched metal layer 132 at least covers a portion of the sidewalls of the first conductive layer 11, the sidewalls of the second conductive layer 12, and the sidewalls of the metal conductive layer 14. This helps to avoid damage to the second conductive layer 12 and the metal conductive layer 14 by the etching process, and avoid damage to the second conductive layer 12 and the metal conductive layer 14 by the subsequent third conductive layer forming process, so that the bit line signal has a better transmission effect.

[0069] In addition, part of the metal film 131 on the bottom side wall of the first conductive layer 11 can be removed to prevent the metal film at this position from reacting with the first conductive layer 11 located between the metal layer 132 and the substrate 10 in subsequent process steps, thereby preventing the third conductive layer from contacting the active area 101 due to the consumption of the first conductive layer 11.

[0070] refer to Fig.10 , a high temperature process is performed to convert the metal layer 132 covering the sidewall of the first conductive layer 11 into a metal silicide layer to form a third conductive layer 13.

[0071] In this embodiment, the material of the metal layer 132 includes cobalt or titanium, and the high-temperature process causes the metal layer 132 covering the first conductive layer 11 to react with the silicon atoms in the first conductive layer 11 to generate metal silicide, thereby forming the third conductive layer 13; in other embodiments, an ion implantation process can be used to implant silicon atoms or other atoms into the metal layer to convert part or all of the metal layer into the third conductive layer.

[0072] Compared with the ion implantation process, the high temperature process is used to form the third conductive layer, which is beneficial for the third conductive layer 13 to contact the bottom surface of the second conductive layer 12, and then by etching the third conductive layer 13, the orthographic projection of the third conductive layer 13 is located within the orthographic projection of the second conductive layer 12 in the direction perpendicular to the surface of the substrate 10.

[0073] After the high temperature process, the unreacted metal layer 132 on the sidewall of the bit line structure is removed to form Figure 1 The structure shown.

[0074] In other embodiments, reference Figure 8 If the first conductive layer 51 is etched before forming the metal film, the final Figure 5 or Fig.11 The structure shown, Fig.11 and Figure 5 The difference is that in the direction from the second conductive layer 62 to the substrate 60, the width of the third conductive layer 63 at different positions is equal, and in the direction parallel to the surface of the substrate 60, the third conductive layer 63 has a portion protruding relative to the second conductive layer 62. If this portion is removed, the third conductive layer 63 is the same as the second conductive layer 62. Figure 5 The structures shown are the same.

[0075] In this embodiment, by providing a third conductive layer having a smaller contact resistance with the second conductive layer, the total contact resistance between the second conductive layer and other active areas is reduced, thereby reducing the resistance on the conductive path between the second conductive layer and the substrate, thereby ensuring that the current signal flowing from the second conductive layer to the substrate has a better signal transmission effect.

[0076] Those skilled in the art will appreciate that the above embodiments are specific examples of the present invention, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: a substrate and a first conductive layer located on the substrate; a second conductive layer, wherein the second conductive layer is located on a surface of the first conductive layer away from the substrate; A third conductive layer, wherein the third conductive layer covers the side wall of the first conductive layer and contacts the second conductive layer, the contact resistance between the third conductive layer and the second conductive layer is smaller than the contact resistance between the first conductive layer and the second conductive layer, and in a direction parallel to the surface of the substrate, the top width of the third conductive layer is larger than the bottom width of the third conductive layer.

2. The semiconductor structure according to claim 1, characterized in that: The top surface of the third conductive layer contacts the bottom surface of the second conductive layer.

3. The semiconductor structure according to claim 1, characterized in that: The sidewall of the first conductive layer includes a first sub-sidewall and a second sub-sidewall extending upward from the bottom of the first conductive layer, the first sub-sidewall is located between the second sub-sidewall and the bottom of the first conductive layer, and the third conductive layer covers the second sub-sidewall.

4. The semiconductor structure according to claim 3, characterized in that: In a direction perpendicular to the substrate surface, a ratio of a height of the second sub-sidewall to a height of the first sub-sidewall is 5-10.

5. The semiconductor structure according to claim 3, characterized in that: In a direction perpendicular to the surface of the substrate, the first conductive layer is also located between the third conductive layer and the substrate.

6. The semiconductor structure according to claim 1, characterized in that In a direction parallel to the surface of the substrate, a top width of the first conductive layer is smaller than a bottom width of the first conductive layer.

7. The semiconductor structure according to claim 1, characterized in that: The side wall surface of the first conductive layer is an arc surface, and in the direction from the second conductive layer toward the substrate, the width of the first conductive layer in a direction parallel to the surface of the substrate increases gradually.

8. The semiconductor structure according to claim 1, characterized in that: The substrate has an active area therein, the first conductive layer is in contact with the active area, and the active area includes an N-type doped semiconductor layer.

9. The semiconductor structure according to claim 1, characterized in that: Also includes: A metal conductive layer and a top dielectric layer, wherein the metal conductive layer is located on a side of the second conductive layer away from the first conductive layer, and the top dielectric layer is located on a side of the metal conductive layer away from the substrate; the first conductive layer, the second conductive layer, the third conductive layer, the metal conductive layer, and the top dielectric layer constitute a bit line structure.

10. The semiconductor structure according to claim 1 or 9, characterized in that: The material of the first conductive layer includes polysilicon, and the materials of the second conductive layer and the third conductive layer include metal compounds.

11. The semiconductor structure according to claim 10, characterized in that: The material of the second conductive layer includes titanium nitride, and the material of the third conductive layer includes cobalt silicide or titanium silicide.

12. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate and a bit line structure located on the substrate, wherein the bit line structure comprises a first conductive layer, a second conductive layer, a metal conductive layer and a top dielectric layer stacked in sequence; A third conductive layer is formed covering the side wall of the first conductive layer and contacting the second conductive layer, wherein the contact resistance between the third conductive layer and the second conductive layer is smaller than the contact resistance between the first conductive layer and the second conductive layer, and in a direction parallel to the surface of the substrate, the top width of the third conductive layer is larger than the bottom width of the third conductive layer.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: Before forming the third conductive layer, an etching process is performed on the first conductive layer to make the top width of the first conductive layer in a direction parallel to the substrate surface smaller than the bottom width.

14. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: The material of the first conductive layer includes polysilicon, and the materials of the second conductive layer and the third conductive layer include metal compounds.

15. The method for manufacturing a semiconductor structure according to claim 12 or 14, characterized in that: The process steps for forming the third conductive layer include: forming a metal layer covering the sidewalls of the first conductive layer; and converting the metal layer into a metal silicide layer to form the third conductive layer.

16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that: The process steps for forming the metal silicide layer include: performing a high temperature process to make the first conductive layer react with the metal layer to form the metal silicide layer.

17. The method for manufacturing a semiconductor structure according to claim 15, characterized in that: The process steps for forming a metal layer covering the side walls of the first conductive layer include: forming a metal film, the metal film covering the exposed surfaces of the substrate and the bit line structure; removing the metal film on the surface of the substrate to form a metal layer, the metal layer covering at least part of the side walls of the first conductive layer, the side walls of the second conductive layer, and the side walls of the metal conductive layer.

18. The method for manufacturing a semiconductor structure according to claim 17, characterized in that: After forming the third conductive layer, the method further includes: removing the unreacted metal layer on the sidewall of the bit line structure.

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