Semiconductor packaging for improved reliability

Abstract

The semiconductor package includes: a chip-level unit including a semiconductor chip; an intermediate-level unit; and a solder ball unit. The solder ball unit will be connected to a circuit substrate. The intermediate-level unit includes: a wiring pad layer on a first protective layer; a second protective layer on the first protective layer and including a pad exposure hole; a terminal post layer in the pad exposure hole on the wiring pad layer; and a third protective layer on the second protective layer and including a terminal post exposure hole. The width or diameter of the terminal post exposure hole is smaller than the width or diameter of the pad exposure hole; and a barrier layer is disposed on the terminal post layer in the terminal post exposure hole. The solder ball unit includes a solder ball on the barrier layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0106427 filed on August 24, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package for improving its own reliability. Background Art

[0004] A semiconductor package may include solder balls for electrically connecting a semiconductor chip to a circuit substrate. When the semiconductor chip is physically and electrically connected to the circuit substrate by using the solder balls, cracks may be formed, for example, in a redistribution layer of the circuit substrate. Therefore, it would be beneficial to improve the reliability of the semiconductor package by reducing the stress applied to the semiconductor chip. Summary of the invention

[0005] Aspects of the inventive concept provide a semiconductor package capable of improving reliability thereof by reducing stress applied to a semiconductor chip.

[0006] A semiconductor package according to an embodiment of the present invention includes: a chip-level portion including a semiconductor chip; an intermediate-level portion on the chip-level portion; and a solder ball portion on the intermediate-level portion, wherein the solder ball portion is configured to be connected to a circuit substrate. The intermediate-level portion includes: a wiring pad layer on a first protective layer, the first protective layer being an inner protective layer among a plurality of protective layers and being directly adjacent to the chip-level portion; a second protective layer on the first protective layer and including a pad exposure hole exposing the wiring pad layer, the second protective layer being an intermediate protective layer among a plurality of protective layers; a post layer (post layer), in the pad exposure hole on the wiring pad layer; a third protective layer on the second protective layer and including a post exposure hole, the post exposure hole exposing the post layer, the third protective layer corresponding to an outer protective layer among a plurality of protective layers, wherein the width of the post exposure hole is or is directly smaller than the width or diameter of the pad exposure hole; and a barrier layer, in the post exposure hole on the post layer. The solder ball portion includes solder balls on the barrier layer.

[0007] According to one aspect of the inventive concept, a semiconductor package includes: a semiconductor chip; a first protective layer on the semiconductor chip; a redistribution pad layer on the first protective layer; a second protective layer on the redistribution pad layer and including a pad exposure hole, the pad exposure hole exposing the redistribution pad layer; a terminal layer, in the pad exposure hole on the redistribution pad layer; a third protective layer on the terminal layer and including a terminal exposure hole, the terminal exposure hole exposing the terminal layer, wherein the terminal exposure hole is smaller than the pad exposure hole; a barrier layer in the terminal exposure hole on the terminal layer; and a solder layer on the barrier layer. The elastic modulus of the second protective layer may be greater than the elastic modulus of the third protective layer.

[0008] According to another aspect of the inventive concept, a semiconductor package includes: a redistribution structure including a redistribution layer, the redistribution layer including a first portion penetrating a first protective layer and connected to a chip pad and a second portion at an end portion of the redistribution layer, the first portion extending from the chip pad in a horizontal direction on the first protective layer; a second protective layer on the redistribution structure and including a pad exposure hole, the pad exposure hole exposing the second portion of the redistribution layer; a terminal layer on the redistribution structure in the pad exposure hole; a third protective layer on the terminal layer and including a terminal exposure hole, the terminal exposure hole exposing the terminal layer, wherein the terminal exposure hole is smaller than the pad exposure hole; a barrier layer on the terminal layer in the terminal exposure hole; and a solder layer on the barrier layer. The maximum width or diameter of the terminal layer is equal to or smaller than the minimum width or diameter of the barrier layer, and the elastic modulus of the second protective layer is greater than the elastic modulus of the third protective layer.

[0009] The width (or diameter) of the terminal layer may be equal to or smaller than the width (or diameter) of the barrier layer, and the elastic modulus of the second protective layer may be greater than the elastic modulus of the third protective layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept;

[0012] Figure 2 According to an example embodiment Figure 1 The planar layout diagram of the wiring pad layer and the terminal layer in the figure;

[0013] Figure 3 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept;

[0014] Figure 4 According to an example embodiment Figure 3The planar layout diagram of the wiring pad layer and the terminal layer in the figure;

[0015] Figure 5 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept;

[0016] Figure 6 According to an example embodiment Figure 5 The planar layout diagram of the wiring pad layer and the terminal layer in the figure;

[0017] Figure 7 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept;

[0018] Figure 8 According to an example embodiment Figure 7 The planar layout diagram of the wiring pad layer and the terminal layer in the figure;

[0019] Fig. 9 is a cross-sectional view of a semiconductor package product including a semiconductor package according to an embodiment of the inventive concept;

[0020] Fig.10 According to an example embodiment Fig. 9 A cross-sectional view of a semiconductor package in FIG.

[0021] Fig.11 yes Fig.10 A planar layout diagram of a redistribution structure and a terminal layer of a semiconductor package;

[0022] Fig.12 According to an example embodiment Fig. 9 A plan cross-sectional view of a semiconductor package in FIG.

[0023] Fig.13 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept;

[0024] Fig.14 According to an example embodiment Fig.13 A planar layout diagram of a redistribution structure and a terminal layer of a semiconductor package;

[0025] Fig.15 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept;

[0026] Fig.16 According to an example embodiment Fig.15 A planar layout diagram of a redistribution structure and a terminal layer of a semiconductor package;

[0027] Fig.17 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept;

[0028] Fig.18According to an example embodiment Fig.17 A planar layout diagram of a redistribution structure and a terminal layer of a semiconductor package;

[0029] Fig.19 is a cross-sectional view of a semiconductor package product including a semiconductor package according to an embodiment of the inventive concept;

[0030] Fig. 20 is a cross-sectional view of a semiconductor package product according to an embodiment of the inventive concept;

[0031] Fig.21 is a cross-sectional view of a semiconductor package product according to an embodiment of the inventive concept;

[0032] Fig. 22 is a cross-sectional view of a semiconductor package product according to an embodiment of the inventive concept;

[0033] Fig.23 is a schematic diagram of a configuration of a card using a semiconductor package according to the inventive concept; and

[0034] Fig.24 is a schematic diagram of a configuration of an electronic system using a semiconductor package according to the inventive concept. DETAILED DESCRIPTION

[0035] Below, the inventive concept will be described more fully with reference to the accompanying drawings showing exemplary embodiments. The inventive concept can be implemented by any one of the various embodiments or by combining one or more of the various embodiments. Therefore, the technical idea of ​​the inventive concept is not limited to one embodiment.

[0036] In this specification, unless the context clearly indicates otherwise, description of a component in the singular may include a plurality of components having the structure of the described component in a single form. In this specification, the drawings may be enlarged in order to clarify various aspects of the inventive concept.

[0037] Figure 1 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept, and Figure 2 yes Figure 1 The plan layout of the wiring pad layer and the terminal layer in .

[0038] exist Figure 1 and Figure 2 In the embodiment, the X-axis direction and the Y-axis direction may be directions parallel to the surface of the semiconductor chip 20 (or the semiconductor substrate), and the Z-axis direction may be a direction perpendicular to the surface of the semiconductor chip 20 (or the semiconductor substrate).

[0039] The semiconductor package 1 (only a portion of which is shown) may include a wafer-level package. In a cross-sectional view (e.g., a cross-sectional view in the Z-axis direction), the semiconductor package 1 may include a chip-level unit LE1, an intermediate-level unit LE2, and a solder ball unit LE3. In the following, for convenience, the downward direction (e.g., the Z-axis direction) of the chip-level unit LE1 is referred to as the vertical direction. The chip-level unit LE1 may be referred to as a chip-level portion, a chip portion, or simply a semiconductor chip. The intermediate-level unit LE2 may be referred to as an intermediate-level portion, or an intermediate-level structure, or an intermediate structure. The solder ball unit LE3 may be referred to as a solder ball portion, or a solder ball structure, or an external connection terminal portion. Different portions may also be referred to as top, middle, and bottom (for reference, the chip is at the top, and the solder ball is at the bottom). For ease of description, spatial relative terms such as "below ...", "below ...", "below ...", "above ...", "above ...", etc. may be used herein to describe positional relationships, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms cover different orientations of the device.

[0040] The chip-level unit LE1 may include a semiconductor chip 20. The semiconductor chip 20 may include a semiconductor layer, such as a silicon layer. The intermediate-level unit LE2 may be on the chip-level unit LE1 (e.g., below the chip-level unit LE1). The intermediate-level unit LE2 may include a wiring pad layer 26, a terminal layer 28, a barrier layer 32, and a plurality of protective layers 34. The barrier layer 32 may also be referred to as a lower barrier metal layer. The barrier layer 32 may also be referred to as a pad. It will be understood that when a reference is made to an element being "connected" or "coupled" to another element or "on top of" another element, the element may be directly connected or coupled to the other element or directly on the other element, or there may be an intervening element. In contrast, when a reference is made to an element being "directly connected" or "directly coupled" to another element or "contacting" another element or "contacting" another element, there is no intervening element at the contact point.

[0041] The solder ball unit LE3 may be on the intermediate level unit LE2 (e.g., below the intermediate level unit LE2). The solder ball unit LE3 may include a solder ball 36 to be physically or electrically connected to a circuit substrate (or board substrate). The solder ball 36 may include or be formed of a low-strength solder component including, for example, Sn as a base metal and Ag and Cu as auxiliary metals. Alternatively, the solder ball 36 may include or be formed of a high-strength solder component including, for example, Sn as a base metal and Ag, Cu, and Bi as auxiliary metals.

[0042] The structure of the semiconductor package 1 conceived by the present invention is described in detail based on the intermediate-level unit LE2. The intermediate-level unit LE2 may include a plurality of protective layers 34 on the chip-level unit LE1. The wiring pad layer 26 may be disposed on the first protective layer 22, and the first protective layer 22 corresponds to the lowermost portion of the protective layer 34. The first protective layer 22 may include an epoxy layer or a polyimide layer, or may be an epoxy layer or a polyimide layer. For example, the wiring pad layer 26 may be directly on the first protective layer 22 and may contact the first protective layer 22. In some embodiments, when the first protective layer 22 includes an epoxy layer, its elastic modulus may be approximately 15 GPa to approximately 30 GPa, and when the first protective layer 22 includes a polyimide layer, its elastic modulus may be approximately 1 GPa to approximately 10 GPa. Figure 2 As shown, in a plan view, the wiring pad layer 26 may be circular. The wiring pad layer 26 may have a width (or diameter) W1. The wiring pad layer 26 may include, for example, a copper layer.

[0043] The intermediate level unit LE2 may include a second protective layer 24 on the first protective layer 22, and the second protective layer 24 includes a pad exposure hole H1. The pad exposure hole H1 may expose the wiring pad layer 26 relative to the second protective layer 24. The pad exposure hole H1 may have a width (or diameter) W2H. The second protective layer 24 may correspond to the middle protective layer of the protective layer 34. The elastic modulus of the material of the second protective layer 24 may be the same as or greater than the elastic modulus of the material of the first protective layer 22. The second protective layer 24 may include an upper surface 24f and a lower surface 24r. The second protective layer 24 may include an epoxy resin layer, or may be an epoxy resin layer. In some embodiments, when the second protective layer 24 is an epoxy resin layer, the elastic modulus of the second protective layer 24 may be about 15GPa to about 30GPa.

[0044] The intermediate level unit LE2 may include a post layer 28 formed in the pad exposing hole H1 on the wiring pad layer 26. Figure 2 As shown, in plan view, the terminal layer 28 may be circular. Figure 2 As shown, in a plan view, the terminal post layer 28 may be inside the wiring pad layer 26. The terminal post layer 28 may have a single post (e.g., a single continuous integral structure formed of a single material without any grain boundaries), which has the same upper width (or diameter) and lower width (or diameter) as a whole, and as shown in FIG. Figure 1 As shown, in a plan view, it has a circular shape. The terminal layer 28 may have a terminal shape.

[0045] The terminal post layer 28 may have a width (or diameter) (e.g., an outer width or diameter) W2. The width (or diameter) W2 of the terminal post layer 28 may be smaller than the width (or diameter) W1 of the wiring pad layer 26. The terminal post layer 28 may have a single integral structure in which the upper width (or diameter) and the lower width (or diameter) W2 are the same. For example, the terminal post layer 28 may have a single integral structure in which the upper width (or diameter) and the lower width (or diameter) W2 in the upper and lower parts of the terminal post layer 28 are the same. The terminal post layer 28 may include a metal layer, or may be a metal layer.

[0046] The terminal post layer 28 may include a lower surface 28r connected to the first protective layer 22 (e.g., through the wiring pad layer 26), and an upper surface 28f in contact with the barrier layer 32 and the third protective layer 30. Note that the "upper" surface and the "lower" surface here are described in the context of the intermediate level unit LE2. If described as part of the semiconductor package 1, the opposite designation (e.g., lower surface 28f and upper surface 28r) may be used. In general, terms such as "first" and "second" can be used to describe different surfaces. Ordinals such as "first", "second", and "third" can be used only as labels for certain elements to distinguish these elements from each other. Terms that are not described using "first", "second", etc. in the specification can still be referred to as "first" or "second" in the claims. In addition, terms cited with a specific ordinal number (e.g., "first" in a specific claim) can be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim). The upper surface 28f of the terminal post layer 28 can be a flat surface. The upper surface 28f of the terminal layer 28 can be coplanar with the upper surface 24f of the second protective layer 24. After the metal material is filled into the pad exposure hole H1 in the second protective layer 24, the terminal layer 28 can be formed by using a planarization process. Terms such as "same", "equal", "planar" or "coplanar" as used herein cover the sameness or the near sameness including changes that may occur, for example, due to the manufacturing process. Unless otherwise indicated by the context or other statements, the term "substantially" may be used herein to emphasize this meaning.

[0047] The intermediate level unit LE2 may include a third protective layer 30 including a post exposure hole H2 exposing the post layer 28 in the second protective layer 24. The post exposure hole H2 may have a width (or diameter) W4H. The third protective layer 30 may correspond to the uppermost portion of the protective layer 34.

[0048] The width (or diameter) W4H of the terminal post exposure hole H2 (for example, the minimum width of the terminal post exposure hole H2, or the width of the terminal post exposure hole H2 at a position where it is adjacent to the terminal post layer 28) may be smaller than the width (or diameter) W2H of the pad exposure hole H1. The lower width (or diameter) W4H of the terminal post exposure hole H2 may be smaller than the upper width (or diameter) W4H' of the terminal post exposure hole H2. The third protective layer 30 may include a material having a lower elastic modulus than the elastic modulus of the material of the second protective layer 24 or may be formed of the material. The third protective layer 30 may include a polyimide layer or may be a polyimide layer. In some embodiments, when the third protective layer 30 is formed using a polyimide layer, the third protective layer 30 may have an elastic modulus of approximately 1 GPa to approximately 10 GPa. Unless otherwise stated, the width described herein is in the X or Y horizontal direction. Unless otherwise stated, the thickness described herein is in the Z vertical direction (which is perpendicular to the X horizontal direction).

[0049] The intermediate level unit LE2 may include a barrier layer 32 formed in the terminal post exposure hole H2 on the terminal post layer 28. The barrier layer 32 may extend outward from the terminal post exposure hole H2 in the third protective layer 30. The barrier layer 32 may have a width (or diameter) W3. The barrier layer 32 may include or may be, for example, a copper layer, a nickel layer, or a gold layer. A lower width (or lower diameter) W4 of the barrier layer 32 may be smaller than an upper width (or upper diameter) W3 of the barrier layer 32. The entire barrier layer 32 may be considered as part of the intermediate level unit LE2, even if a portion of the barrier layer 32 vertically extends beyond Figure 1 Dotted line shown.

[0050] like Figure 1 As shown, in the middle level unit LE2, the width (or diameter) W2 of the terminal layer 28 may be the same as the width (or diameter) W3 of the barrier layer 32. Figure 1 Unlike the case shown in FIG. 1 , in the intermediate level unit LE2 , the width (or diameter) W2 of the terminal layer 28 may be smaller than the width (or diameter) W3 of the barrier layer 32 . In addition, the thickness T1 of the terminal layer 28 may be smaller than the maximum thickness T2 of the solder ball 36 .

[0051] In some embodiments, the value of the width (or diameter) W2 of the terminal layer 28 may be in the range of about 70% to about 100% of the width (or diameter) W3 of the barrier layer 32. In some embodiments, the value of the width (or diameter) W4H (e.g., the minimum width) of the terminal exposure hole H2 may be about 65% of the width (or diameter) W3 of the barrier layer 32. In some embodiments, the value of the thickness T1 of the terminal layer 28 may be about 10% to about 50% of the thickness T2 of the solder ball 36. Here, the thickness is in the Z direction and the width is in the X direction perpendicular to the Z direction.

[0052] In some embodiments, the width (or diameter) W2 of the terminal layer 28 can be about 100 μm to about 300 μm. In some embodiments, the thickness T1 of the terminal layer 28 can be about 10 μm to about 90 μm. The thickness T2 of the solder ball (e.g., the maximum thickness in the Z direction) can be about 100 μm to about 180 μm. The width (or diameter) W3 of the barrier layer 32 (e.g., the outermost width) can be about 180 μm to about 200 μm. Terms such as "approximately" or "substantially" can reflect only the quantity, size, orientation, or layout that varies in a small relative manner and / or in a manner that does not significantly change the operation, function, or structure of certain elements. For example, a range of "about 0.1 to about 1" can cover a range such as a 0%-5% deviation around 0.1 and a 0%-5% deviation around 1, particularly where such a deviation maintains the same effect as the listed range.

[0053] The semiconductor package 1 configured as described above according to the example embodiment of the inventive concept may include the intermediate level unit LE2 having the plurality of protection layers 34, and the elastic modulus of the second protection layer 24 among the protection layers 34 may be greater than the elastic modulus of the third protection layer 30. In addition, the semiconductor package 1 according to the embodiment of the inventive concept may include the post layer 28, the width W2 of the post layer 28 being greater than the width (or diameter) W4H of the post exposure hole H2 and being equal to or less than the width (or diameter) W3 of the barrier layer 32.

[0054] Therefore, the semiconductor package 1 according to aspects of the present inventive concept can improve its reliability by reducing stress applied to the semiconductor chip 20 when or after the semiconductor chip 20 is physically or electrically connected to the circuit board by using the solder balls 36 (for example, by reducing mechanical shock stress or thermal shock stress).

[0055] Furthermore, the semiconductor package 1 according to aspects of the inventive concept can reduce stress (such as the stress applied to the edges near the both ends of the wiring pad layer 26 constituting the semiconductor chip 20) by Figure 1As shown in the figure mark 38 in the figure, for example, mechanical shock stress or thermal shock stress) is used to improve its reliability. The mechanical shock stress may include a drop shock stress.

[0056] Figure 3 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept, and Figure 4 yes Figure 3 The plan layout of the wiring pad layer and the terminal layer in .

[0057] In addition to the structure of the terminal layer 28-1 and the barrier layer 32-1 Figure 1 and Figure 2 In addition to the difference in structure of the terminal layer and the barrier layer in the semiconductor package 1, Figure 3 and Figure 4 The semiconductor package 3 can be used with Figure 1 and Figure 2 The semiconductor package 1 is the same as that of FIG. Figure 3 and Figure 4 In, with Figure 1 and Figure 2 The same or similar reference numerals in the figure may represent the same or similar components. Figure 3 and Figure 4 For the sake of convenience, the following are briefly given or omitted. Figure 1 and Figure 2 The description given is the same or similar to the description.

[0058] The semiconductor package 3 may include a chip-level unit LE1, an intermediate-level unit LE2, and a solder ball unit LE3. The intermediate-level unit LE2 may include a plurality of protective layers 34 on the chip-level unit LE1. The wiring pad layer 26 may be on the first protective layer 22, and the first protective layer 22 corresponds to the lowermost portion of the protective layer 34. Figure 4 As shown, in a plan view, the wiring pad layer 26 may be circular. The wiring pad layer 26 may have a width (or diameter) W1.

[0059] The intermediate level unit LE2 may include a second protective layer 24, and the second protective layer 24 includes a plurality of pad exposure holes H1a and H1b that expose the wiring pad layer 26 on the first protective layer 22. The pad exposure holes H1a and H1b may be separated from each other. The pad exposure holes H1a and H1b may have widths W2aH and W2bH, respectively. W2aH and W2bH may have the same width as each other. The pad exposure holes H1a and H1b are shown in a cross-sectional view, and when viewed in a plan view or a perspective view, a single groove having a ring shape may be formed. The width of the groove may be W2aH or W2bH (may be the same width). The outer width of the ring formed by the groove may be W2.

[0060] The intermediate level unit LE2 may include a terminal post layer 28-1 formed in the pad exposing holes H1a and H1b on the wiring pad layer 26. When viewed from a cross-sectional view, as shown in FIG. Figure 3 As shown, the terminal post layer 28-1 may include a first terminal post portion 28a and a second terminal post portion 28b formed in the pad exposure holes H1a and H1b, respectively. When viewed in a plan view or a perspective view, the terminal post layer 28-1 may be an annular (e.g., circular) post with a hollow center in the vertical direction. The terminal post layer 28-1 may be a single continuous structure in the form of an annular shape formed by a single continuous material. When viewed in a plan view, the terminal post layer 28-1 may be within the outer diameter of the wiring pad layer 26.

[0061] The first terminal portion 28a may have a width W2a. The second terminal portion 28b may have a width W2b. W2a and W2b may be the same width. The terminal layer 28-1 may have an outer width (outer diameter) W2 (e.g., an outer diameter of a ring). The outer width (or outer diameter) W2 of the terminal layer 28-1 may be less than the width (or diameter) W1 of the wiring pad layer 26.

[0062] The intermediate level unit LE2 may include a third protective layer 30, which includes a terminal post exposure hole H2-1 that exposes the terminal post layer 28-1 in the second protective layer 24. The terminal post exposure hole H2-1 may also expose the second protective layer 24, and may gradually taper in the direction toward the terminal post layer 28-1 and the second protective layer 24. The terminal post exposure hole H2-1 may have a width (or diameter) W4H-1 (e.g., the minimum width or the width of the terminal post exposure hole H2-1 at a position where it is adjacent to the terminal post layer 28-1). The width (or diameter) W4H-1 of the terminal post exposure hole H2-1 may be smaller than the outer width (or outer diameter) W2 of the terminal post layer 28-1. The lower width (or lower diameter) W4H-1 of the terminal post exposure hole H2-1 may be smaller than the upper width (or upper diameter) W4H'-1 of the terminal post exposure hole H2-1. The upper width W4H'-1 (e.g., the maximum width) may also be smaller than the outer width (or outer diameter) W2 of the terminal layer 28-1. In this way, the terminal exposure hole H2-1 may include a first opening (e.g., at a position where it is adjacent to the terminal layer 28-1) and a second opening (opposite to the first opening), and the widths of both the first opening and the second opening may be smaller than the outer width W2 of the terminal layer 28-1.

[0063] The intermediate level unit LE2 may include a barrier layer 32-1, which is formed in the terminal post exposure hole H2-1 on the terminal post layer 28-1. The barrier layer 32-1 may also contact the second protective layer 24 and may extend into the recesses in the terminal post layer 28-1 and the second protective layer 24. In one embodiment, the upper surface 26f-1 of the terminal post layer 28-1 may be a curved surface (or a non-flat surface). The barrier layer 32-1 may have a width (or diameter) W4-1. The lower width (or lower diameter) W4-1 of the barrier layer 32-1 may be less than the upper width (or upper diameter) W3 of the barrier layer 32-1.

[0064] like Figure 3 As shown, in the intermediate level unit LE2, the outer width (or outer diameter) W2 of the terminal layer 28-1 may be smaller than the width (or diameter) W3 of the barrier layer 32-1. In addition, the thickness T1 of the terminal layer 28-1 may be smaller than the maximum thickness T2 of the solder ball 36.

[0065] In some embodiments, the outer width (or outer diameter) W2 of the terminal layer 28-1 may be in the range of about 70% to about 100% of the width (or diameter) W3 of the barrier layer 32-1. In some embodiments, the width (or diameter) W4H-1 of the terminal exposure hole H2-1 may be about 65% of the width (or diameter) W3 of the barrier layer 32-1. In some embodiments, the thickness T1 of the terminal layer 28-1 (e.g., in the Z direction) may be about 10% to about 50% of the maximum thickness T2 of the solder ball 36.

[0066] As described above, the semiconductor package 3 according to some embodiments of the present inventive concept can reduce the stress applied to the edges near the both ends of the wiring pad layer 26 constituting the semiconductor chip 20 (such as Figure 3 As shown in the figure mark 38, for example, mechanical shock stress or thermal shock stress) to improve reliability.

[0067] Figure 5 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept, and Figure 6 yes Figure 5 The plan layout of the wiring pad layer and the terminal layer in .

[0068] In addition to the structure of the terminal layer 28-2 and the second protection layer 24-1 Figure 3 and Figure 4 In addition to the difference in structure between the terminal layer and the second protective layer in the semiconductor package 3, Figure 5 and Figure 6 The semiconductor package 5 can be connected with Figure 3 and Figure 4 The semiconductor package 3 is the same. Figure 5 and Figure 6 In, with Figures 1 to 4 The same or similar reference numerals in the figure may represent the same or similar components. Figure 5 and Figure 6 For the sake of convenience, the following are briefly given or omitted. Figures 1 to 4 The description given is the same or similar to the description.

[0069] The semiconductor package 5 may include a chip-level unit LE1, an intermediate-level unit LE2, and a solder ball unit LE3. The intermediate-level unit LE2 may include a plurality of protective layers 34-1 on the chip-level unit LE1. The wiring pad layer 26 may be on the first protective layer 22, and the first protective layer 22 corresponds to the lowermost portion of the protective layer 34-1. Figure 5 As shown, in a plan view, the wiring pad layer 26 may be circular. The wiring pad layer 26 may have a width (or diameter) W1.

[0070] The intermediate level unit LE2 may include a second protective layer 24-1 including, in a plan view, a plurality of pad exposure holes H1c and H1d exposing the wiring pad layer 26 on the first protective layer 22. The pad exposure holes H1c and H1d may be separated from each other in a cross-sectional view and may be a part of a ring-shaped groove in a plan view or a perspective view.

[0071] The pad exposure holes H1c and H1d may have widths (or diameters) W2cH and W2dH, respectively. The widths (or diameters) W2cH and W2dH of the pad exposure holes H1c and H1d may be respectively Figure 3 The widths (or diameters) W2aH and W2cH of the pad exposure holes H1a and H1b are different. The widths (or diameters) W2cH and W2dH of the pad exposure holes H1c and H1d may be larger than Figure 3 The pad exposure holes H1a and H1b in FIG. 1 may have widths (or diameters) W2aH and W2cH. From a plan view or a perspective view, the pad exposure holes H1c and H1d may be, for example, Figure 6 A portion of the circular holes formed in a square pattern as shown in FIG. Figure 4 Although four circular holes are shown, other arrangements may be used, such as 3, 5, 6, or other numbers of holes.

[0072] The intermediate level unit LE2 may include a post layer 28-2 formed in the pad exposure holes H1c and H1d on the wiring pad layer 26. Figure 5 As shown, the post layer 28 - 2 may include sub-post layers 28 c and 28 d formed in the pad exposing holes H1 c and H1 d , respectively.

[0073] The terminal layer 28-2 may include a plurality of sub-terminal layers 28c and 28d, each of which is arranged in a circular shape. Figure 6 As shown. Figure 6 In the figure, the terminal post layer 28-2 is shown as including 4 sub-terminal post layers 28c and 28d, but more or less than 4 sub-terminal post layers can be included as needed. In the plan view, each of the sub-terminal post layers 28c and 28d can have a single circular structure. Each of the sub-terminal post layers 28c and 28d can be a circular column. When observed in the plan view, the terminal post layer 28-2 can be within the outer diameter of the wiring pad layer 26.

[0074] Sub-post layer 28c may have a width (or diameter) W2c. Sub-post layer 28d may have a width (or diameter) W2d. W2c and W2d may be the same width. Post layer 28-2 may have an outer width (or outer diameter) W2 (e.g., a maximum width). The outer width (or outer diameter) W2 of post layer 28-2 may be less than the width (or diameter) W1 of wiring pad layer 26.

[0075] The intermediate level unit LE2 may include a third protective layer 30, and the third protective layer 30 includes a terminal post exposure hole H2-2 that exposes the terminal post layer 28-2 in the second protective layer 24-1. The terminal post exposure hole H2-2 may also expose the second protective layer 24-1, and may gradually become thinner in a direction toward the terminal post layer 28-2 and the second protective layer 24-1. The terminal post exposure hole H2-2 may have a width (or diameter) W4H-2.

[0076] The width (or diameter) W4H-2 of the terminal post exposure hole H2-2 may be smaller than the outer width (or outer diameter) W2 of the terminal post layer 28-2. The lower width (or lower diameter) W4H-2 of the terminal post exposure hole H2-2 may be smaller than the upper width (or upper diameter) W4H′-2 of the terminal post exposure hole H2-2. Figure 6 As shown, the post layer 28 - 2 may include a plurality of sub-post layers 28 c and 28 d arranged in a circular or ring shape along the edge of the post exposure hole H2 - 2 .

[0077] The intermediate level unit LE2 may include a barrier layer 32-1 formed in the terminal post exposure hole H2-2 on the terminal post layer 28-2. The barrier layer 32-1 may also contact the second protective layer 24-1 and may be recessed into the terminal post layer 28-2 and the second protective layer 24-1. The barrier layer 32-1 may have a width (or diameter) W4-2. The lower width (or lower diameter) W4-2 of the barrier layer 32-1 may be smaller than the upper width (or upper diameter) W3 of the barrier layer 32-1.

[0078] like Figure 5As shown, in the intermediate level unit LE2, the outer width (or outer diameter) W2 of the terminal layer 28-2 may be the same as the width (or diameter) W3 of the barrier layer 32-1. In addition, the thickness T1 of the terminal layer 28-2 may be smaller than the maximum thickness T2 of the solder ball 36.

[0079] In some embodiments, the outer width (or outer diameter) W2 of the terminal layer 28-2 may be in the range of about 70% to about 100% of the width (or diameter) W3 of the barrier layer 32-1. In some embodiments, the width (or diameter) W4H-2 of the terminal exposure hole H2-2 may be at a level of about 65% of the width (or diameter) W3 of the barrier layer 32-1. In some embodiments, the thickness T1 of the terminal layer 28-2 may be about 10% to about 50% of the maximum thickness T2 of the solder ball 36.

[0080] As described above, the semiconductor package 5 according to the embodiment of the inventive concept configured as described above can reduce the stress applied to the edges near the both ends of the wiring pad layer 26 constituting the semiconductor chip 20 (such as Figure 5 As shown in the figure mark 38, for example, mechanical shock stress or thermal shock stress) to improve its reliability.

[0081] Figure 7 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept, and Figure 8 yes Figure 7 The plan layout of the wiring pad layer and the terminal layer in .

[0082] In addition to the structure of the terminal layer 28-3 and the second protection layer 24-2 Figure 1 and Figure 2 In addition to the difference in structure of the terminal layer and the protective layer in the semiconductor package 1, Figure 7 and Figure 8 The semiconductor package 7 can be used with Figure 1 and Figure 2 The semiconductor package 1 is the same as that of FIG. Figure 7 and Figure 8 In, with Figure 1 and Figure 2 The same or similar reference numerals in the figure may represent the same or similar components. Figure 7 and Figure 8 For the sake of convenience, the following are briefly given or omitted. Figure 1 and Figure 2 The description given is the same or similar to the description.

[0083] The semiconductor package 7 may include a chip-level unit LE1, an intermediate-level unit LE2, and a solder ball unit LE3. The intermediate-level unit LE2 may include a plurality of protective layers 34-2 on the chip-level unit LE1. The wiring pad layer 26 may be on the first protective layer 22, and the first protective layer 22 corresponds to the lowermost portion of the protective layer 34-2. Figure 8 As shown, in a plan view, the wiring pad layer 26 may be circular. The wiring pad layer 26 may have a width (or diameter) W1.

[0084] The intermediate level unit LE2 may include a second protective layer 24-2 including a pad exposure hole H1e exposing the wiring pad layer 26 on the first protective layer 22. The pad exposure hole H1e may have a width (or diameter) W2H'. The lower width (or diameter) W2H' of the pad exposure hole H1e may be greater than the upper width (or diameter) W2H of the pad exposure hole H1e.

[0085] The intermediate level unit LE2 may include a post layer 28-3 formed in the pad exposure hole H1e on the wiring pad layer 26. Figure 8 As shown, in a plan view, the terminal layer 28-3 may be circular. Figure 8 As shown, in a plan view, the terminal layer 28-3 may be within the outer circumference of the wiring pad layer 26. Figure 8 As shown, the terminal layer 28 - 3 may have a circular shape.

[0086] The terminal post layer 28-3 may have a lower width (or diameter) W2f and an upper width (or diameter) W2e. The lower width (or diameter) W2f of the terminal post layer 28-3 may be greater than the upper width (or diameter) W2e of the terminal post layer 28-3. The terminal post layer 28-3 may be a single continuous structure having an upper width (or diameter) W2e and a lower width (or diameter) W2f that are different from each other.

[0087] The width (or diameter) W2e and W2f of the terminal post layer 28-3 may be smaller than the width (or diameter) W1 of the wiring pad layer 26. The upper surface 28f of the terminal post layer 28-3 may be a flat surface. The upper surface 28f of the terminal post layer 28-3 may be coplanar with the upper surface of the second protective layer 24-2.

[0088] The intermediate level unit LE2 may include a third protective layer 30 including a stud exposure hole H2-3 exposing the stud layer 28-3 in the second protective layer 24-2. The stud exposure hole H2-3 may have a width (or diameter) W4H.

[0089] The width (or diameter) W4H of the terminal post exposure hole H2-3 may be smaller than the widths (or diameters) W2H and W2H' of the pad exposure hole H1e. For example, the maximum width of the terminal post exposure hole H2-3 may be smaller than the minimum width of the pad exposure hole H1e. The lower width (or lower diameter) W4H of the terminal post exposure hole H2-3 may be smaller than the upper width (or upper diameter) W4H' of the terminal post exposure hole H2-3.

[0090] The intermediate level unit LE2 may include a barrier layer 32 formed in the terminal post exposure hole H2-3 on the terminal post layer 28-3. The barrier layer 32 may have a width (or diameter) W3. The lower width W4 (or lower diameter) at the bottommost surface of the barrier layer 32 may be smaller than the upper width (or upper diameter) W3 at the uppermost surface of the barrier layer 32.

[0091] like Figure 7 As shown, in the intermediate level unit LE2, the widths (or diameters) W2e and W2f of the post layer 28-3 may be smaller than the width (or diameter) W3 of the barrier layer 32. In addition, the thickness T1 of the post layer 28-3 may be smaller than the maximum thickness T2 of the solder ball 36.

[0092] In some embodiments, the outer widths (or outer diameters) W2e and W2f of the post layer 28-3 may be in the range of about 70% to about 100% of the width (or diameter) W3 of the barrier layer 32. In some embodiments, the width (or diameter) W4H of the post exposure hole H2-3 may be about 65% of the width (or diameter) W3 of the barrier layer 32. In some embodiments, the thickness T1 of the post layer 28-3 may be about 10% to about 50% of the maximum thickness T2 of the solder ball 36.

[0093] As described above, the semiconductor package 7 according to the embodiment of the inventive concept configured as described above can reduce the stress applied to the edges near the both ends of the wiring pad layer 26 constituting the semiconductor chip 20 (such as Figure 7 As shown in the figure mark 38, for example, mechanical shock stress or thermal shock stress) to improve its reliability.

[0094] Fig. 9 is a cross-sectional view of a semiconductor package product including a semiconductor package according to an embodiment of the inventive concept, Fig.10 yes Fig. 9 A cross-sectional view of a semiconductor package in FIG. Fig.11 yes Fig.10 The redistribution structure and the planar layout of the terminal layer of the semiconductor package in Fig.12 yes Fig. 9 A plan cross-sectional view of a semiconductor package in FIG.

[0095] The semiconductor package 200 included in the semiconductor package product 300 may be formed using Figure 1 The semiconductor package 1. In this way, Figures 9 to 12 The semiconductor package 200 may be configured as Figure 1 The semiconductor package product 300 may be, for example, a semiconductor package, or may be a memory module. For example, the semiconductor package product 300 may be a memory module (e.g., a single in-line memory module (SIMM)), or may be part of a dual in-line memory module (DIMM).

[0096] In addition to Figure 1 and Figure 2 The semiconductor package 1 also includes a semiconductor chip 20 and a redistribution structure 27 in detail. Figures 9 to 12 The semiconductor package 200 may be Figure 1 and Figure 2 The semiconductor package 1 is the same as that of FIG. Fig. 9 and Fig.12 In, with Figure 1 and Figure 2 The same or similar reference numerals in the figure may represent the same or similar components. Fig. 9 and Fig.12 For the sake of convenience, the following are briefly given or omitted. Figure 1 and Figure 2 The description given is the same or similar to the description.

[0097] like Fig. 9 As shown, the semiconductor package product 300 may include a circuit substrate 150 and a semiconductor package 200. The circuit substrate 150 may include a printed circuit board. The connection pads 152 may be on the circuit substrate 150. The solder balls 36 of the semiconductor package 200 may be connected to the connection pads 152. The solder balls 36 of the semiconductor package 200 may be mechanically and electrically connected to the circuit substrate 150 via the connection pads 152.

[0098] like Fig.10 As shown in the cross-sectional view, the semiconductor package 200 may include a chip-level unit LE1-1, an intermediate-level unit LE2-1, and a solder ball unit LE3-1. The chip-level unit LE1-1, the intermediate-level unit LE2-1, and the solder ball unit LE3-1 may correspond to Figure 1 The chip-level unit LE1, the intermediate-level unit LE2 and the solder ball unit LE3.

[0099] The chip-level unit LE1-1 may include a semiconductor chip 20. The semiconductor chip 20 may include a chip circuit layer 12 on a semiconductor substrate 10 (e.g., a silicon layer (or silicon substrate)). The chip circuit layer 12 may be at an active surface of the semiconductor chip 20. For convenience, the chip circuit layer 12 may be shown as a single layer on the semiconductor substrate 10, but an integrated circuit layer including a plurality of transistors, capacitors, and / or resistor elements may be formed on the semiconductor substrate 10. The semiconductor chip 20 may include a passivation layer 14 and a chip pad 15 formed on the chip circuit layer 12. The chip pad 15 may be insulated from other chip pads 15 by the passivation layer 14 and may be connected to the chip circuit layer 12. The passivation layer 14 may include, for example, a silicon nitride layer.

[0100] The intermediate level unit LE2-1 may include a redistribution structure 27, a stud layer 28, a barrier layer 32, and a plurality of protection layers 34. A solder ball unit LE3-1 including a solder ball 36 may be on the intermediate level unit LE2-1. The intermediate level unit LE2-1 is described in detail.

[0101] The intermediate level unit LE2-1 may include a plurality of protective layers 34 formed on the passivation layer 14 and the chip pad 15. The first protective layer 22 may be formed on the passivation layer 14 and the chip pad 15. The first protective layer 22 may be formed on the chip circuit layer 12 and the chip pad 15. The first protective layer 22 may include, for example, an epoxy layer or a polyimide layer. A redistribution structure 27 connected to the chip pad 15 may be formed on the first protective layer 22.

[0102] The redistribution structure 27 may include a redistribution layer 25 extending from the chip pad 15 in a specific direction (e.g., in the X direction (i.e., the horizontal direction)) and extending to a wiring pad layer 26 (or a redistribution pad layer) at one end of the redistribution layer 25. The wiring pad layer 26 and the redistribution layer 25 may be a single layer (including a terminal post pad portion formed on the terminal post layer 28 and a chip pad portion formed on the chip pad 15), and may be described as a redistribution layer. The redistribution layer 25 may penetrate the first passivation layer 22, be connected to the chip pad 15, and extend from the chip pad 15 on the first passivation layer 22 in a horizontal direction. Fig.12 As shown, the redistribution layer 25 extending from the chip pad 15 may extend in the X direction and / or the Y direction (eg, in the horizontal direction) to be connected to the solder ball 36 .

[0103] The pitch of the solder balls 36 (eg, the pitch between the solder balls formed on the semiconductor package 200) may be a first pitch P1 in the X direction and a second pitch P2 in the Y direction. In some embodiments, the value of the pitch may be about 0.2 mm to about 0.5 mm. Fig.12, the solder balls 36 are shown as being formed in the peripheral portion of the semiconductor package 200 , but the solder balls 36 may also be formed in the central portion of the semiconductor package 200 .

[0104] In the following description, since the wiring pad layer 26 is included in the redistribution structure 27, the wiring pad layer 26 may be referred to as the redistribution pad layer 26. The redistribution structure 27 may be separated into a redistribution layer region RD1 in which the redistribution layer 25 is arranged and a redistribution pad region RD2 in which the redistribution pad layer 26 is formed, as shown in FIG. Fig.10 and Fig.11 shown.

[0105] The redistribution pad region RD2 may have a width (or diameter) W5 in the Y-axis direction and a width (or diameter) W1 in the X-axis direction. In other words, the redistribution pad layer 26 may have a width (or diameter) W1 in the X-axis direction. The width (or length) W6 of the redistribution layer region RD1 in the Y-axis direction (described as the longitudinal direction) may be less than the width (or diameter) W5 of the redistribution pad region RD2 in the Y-axis direction. An item, layer, or portion of an item or layer described as extending "longitudinally" in a particular direction has a length in that particular direction and a width in a direction perpendicular to that direction, where the length is greater than the width.

[0106] The intermediate level unit LE2-1 may include a second protective layer 24 including a pad exposure hole H1 exposing a redistribution pad layer 26 on the first protective layer 22. The second protective layer 24 may be formed on a redistribution structure 27 including a redistribution layer 25 and a redistribution pad layer 26, and may be formed on the first protective layer 22. The elastic modulus of the material of the second protective layer 24 may be the same as or greater than the elastic modulus of the material of the first protective layer 22. The second protective layer 24 may include an epoxy resin layer. The pad exposure hole H1 may have a width (or diameter) W2H.

[0107] The intermediate level unit LE2-1 may include a post layer 28 formed in the pad exposure hole H1 on the redistribution pad layer 26. The post layer 28 may have a width (or diameter) W2. The outer width (or outer diameter) W2 of the post layer 28 may be smaller than the width (or diameter) W1 of the redistribution pad layer 26. The post layer 28 may have a single structure having the same upper width (or diameter) and lower width (or diameter) W2. The post layer 28 may include a metal layer.

[0108] The upper surface 28f of the post layer 28 may be a flat surface. The upper surface 28f of the post layer 28 may be coplanar with the upper surface of the second protective layer 24. After the metal material is filled into the pad exposure hole H1 in the second protective layer 24, the post layer 28 may be formed by using a planarization process.

[0109] The intermediate level unit LE2-1 may include a third protective layer 30, which includes a terminal post exposure hole H2 that exposes the terminal post layer 28 in the second protective layer 24. The terminal post exposure hole H2 may have a width (or diameter) W4H. The width (or diameter) W4H of the terminal post exposure hole H2 may be smaller than the width (or diameter) W2H of the pad exposure hole H1. The lower width (or lower diameter) W4H of the terminal post exposure hole H2 may be smaller than the upper width (or upper diameter) W4H' of the terminal post exposure hole H2. The elastic modulus of the third protective layer 30 may be smaller than the elastic modulus of the second protective layer 24. The third protective layer 30 may include, for example, a polyimide layer.

[0110] The intermediate level unit LE2-1 may include a barrier layer 32 formed in the terminal post exposure hole H2 on the terminal post layer 28. The barrier layer 32 may have a width (or diameter) W3. The lower width (or lower diameter) W4 of the barrier layer 32 may be smaller than the upper width (or upper diameter) W3 of the barrier layer 32. In the intermediate level unit LE2-1, the width (or diameter) W2 of the terminal post layer 28 may be smaller than the width (or diameter) W3 of the barrier layer 32. The thickness T1 of the terminal post layer 28 may be smaller than the thickness T2 of the solder ball 36 (e.g., the maximum thickness in the Z direction).

[0111] As described above, the semiconductor package 200 according to the embodiment of the inventive concept configured as described above can improve its reliability by reducing stress (such as the stress of the redistribution pad layer 26) applied to the edges at both ends of the semiconductor chip 20 when or after the semiconductor chip 20 is physically or electrically connected to the circuit substrate 150 by using the solder balls 36. Fig.10 38 in the figure) or stress applied to the redistribution layer 25 (eg, mechanical shock stress or thermal shock stress).

[0112] Fig.13 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept, and Fig.14 yes Fig.13 Figure 2. Planar layout of the redistribution structure and terminal layer of the semiconductor package.

[0113] Fig.13 and Fig.14 The semiconductor package 210 may be applied to Fig. 9 300 semiconductor packaging products. Fig.13 and Fig.14 The semiconductor package 210 may be implemented using Figure 3 and Figure 4 semiconductor package 3. In addition to Figure 3 and Figure 4 The semiconductor package 3 also includes a detailed configuration of the semiconductor chip 20 and the redistribution structure 27. Fig.13 and Fig.14 The semiconductor package 210 may be Figure 3 and Figure 4 The semiconductor package 3 is the same.

[0114] exist Fig.13 and Fig.14 In, with Figure 3 , Figure 4 and Figures 9 to 12 The same or similar reference numerals in the figure may represent the same or similar components. Fig.13 and Fig.14 For the sake of convenience, the following are briefly given or omitted. Figure 3 , Figure 4 and Figures 9 to 12 The description given is the same or similar to the description.

[0115] like Fig.13 As shown, in the cross-sectional view, the semiconductor package 210 may include a chip-level unit LE1-1, an intermediate-level unit LE2-1, and a solder ball unit LE3-1. The chip-level unit LE1-1 may include a semiconductor chip 20. The semiconductor chip 20 may include a passivation layer 14 and a chip pad 15 formed on a chip circuit layer 12 of a semiconductor substrate 10.

[0116] The intermediate level unit LE2-1 may include a redistribution structure 27, a stud layer 28-1, a barrier layer 32-1, and a plurality of protection layers 34. A solder ball unit LE3-1 including a solder ball 36 may be on the intermediate level unit LE2-1. The intermediate level unit LE2-1 is described in detail.

[0117] The intermediate level unit LE2-1 may include a plurality of protective layers 34 formed on the passivation layer 14 and the chip pad 15. The first protective layer 22 may be formed on the passivation layer 14 and the chip pad 15. A redistribution structure 27 connected to the chip pad 15 may be formed on the first protective layer 22. The redistribution structure 27 may include a redistribution layer 25 extending from the chip pad 15 in a specific direction (e.g., in the X direction (e.g., horizontal direction)), and a wiring pad layer 26 at one end of the redistribution layer 25.

[0118] The redistribution structure 27 may be separated into a redistribution layer region RD1 in which the redistribution layer 25 is arranged and a redistribution pad region RD2 in which the redistribution pad layer 26 is formed. Fig.13and Fig.14 For convenience of explanation, these regions as well as the regions described in the previous embodiments may be described as the first region and the second region of the redistribution structure 27 .

[0119] The redistribution pad region RD2 may have a width (or diameter) W5 in the Y-axis direction and a width (or diameter) W1 in the X-axis direction. In other words, the redistribution pad layer 26 may have a width (or diameter) W1 in the X-axis direction. The value of W1 may be the same as the value of W5. The width (or length) W6 of the redistribution layer region RD1 in the Y-axis direction may be less than the width (or diameter) W5 of the redistribution pad region RD2 in the Y-axis direction.

[0120] The intermediate level unit LE2-1 may include a second protective layer 24, the second protective layer 24 includes a plurality of pad exposure holes H1a and H1b, and from a cross-sectional view, the plurality of pad exposure holes H1a and H1b expose the wiring pad layer 26 on the first protective layer 22. From a plan view, the pad exposure holes H1a and H1b may have widths W2aH and W2bH, respectively, and may form a ring together. The intermediate level unit LE2-1 may include a post layer 28-1, and the post layer 28-1 is formed on the wiring pad layer 26 in the pad exposure holes H1a and H1b.

[0121] From the cross-sectional view, the terminal post layer 28-1 may include a first terminal post portion 28a and a second terminal post portion 28b. The terminal post layer 28-1 may be a circular post with an empty middle in the vertical direction, so it may have a donut shape. In a plan view, the terminal post layer 28-1 may be a single continuous structure in an annular shape. In a plan view, the terminal post layer 28-1 may be within the outer circumference of the wiring pad layer 26.

[0122] The first terminal portion 28a may have a width W2a. The second terminal portion 28b may have a width W2b. The terminal layer 28-1 may have an outer width (or outer diameter) W2. The outer width (or outer diameter) W2 of the terminal layer 28-1 may be smaller than the width (or diameter) W1 of the wiring pad layer 26.

[0123] The intermediate level unit LE2-1 may include a third protective layer 30, and the third protective layer 30 includes a terminal post exposure hole H2-1 that exposes the terminal post layer 28-1 in the second protective layer 24. The terminal post exposure hole H2-1 may also expose the second protective layer 24, and may gradually become thinner in the direction toward the terminal post layer 28-1 and the second protective layer 24. The terminal post exposure hole H2-1 may have a width (or diameter) W4H-1. The width (or diameter) W4H-1 of the terminal post exposure hole H2-1 may be smaller than the outer width (or outer diameter) W2 of the terminal post layer 28-1. The lower width (or lower diameter) W4H-1 of the terminal post exposure hole H2-1 may be smaller than the upper width (or upper diameter) W4H'-1 of the terminal post exposure hole H2-1.

[0124] The intermediate level unit LE2-1 may include a barrier layer 32-1 formed in the terminal post exposure hole H2-1 on the terminal post layer 28-1. The barrier layer 32-1 may also contact the second protective layer 24 and may be recessed into the terminal post layer 28-1 and the second protective layer 24. The barrier layer 32-1 may have a width (or diameter) W4-1. The lower width (or lower diameter) W4-1 of the barrier layer 32-1 may be smaller than the upper width (or upper diameter) W3 of the barrier layer 32-1.

[0125] like Fig.13 As shown, in the intermediate level unit LE2-1, the outer width (or outer diameter) W2 of the terminal layer 28-1 may be smaller than the width (or diameter) W3 of the barrier layer 32. In addition, the thickness T1 of the terminal layer 28-1 may be smaller than the thickness T2 of the solder ball 36.

[0126] As described above, the semiconductor package 210 according to the embodiment of the inventive concept configured as described above can improve its reliability by operating as follows: when the semiconductor chip 20 is physically or electrically connected to the circuit substrate 150 (refer to Fig. 9 ), reducing the stress applied to the vicinity of the edges at both ends of the redistribution pad layer 26 constituting the semiconductor chip 20 (eg Fig.13 38 in the figure) or stress applied to the redistribution layer 25 (eg, mechanical shock stress or thermal shock stress).

[0127] Fig.15 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept, and Fig.16 yes Fig.15 Figure 2. Planar layout of the redistribution structure and terminal layer of the semiconductor package.

[0128] Fig.15 and Fig.16 The semiconductor package 220 can be applied to Fig. 9 300 semiconductor packaging products. Fig.15 and Fig.16 The semiconductor package 220 may be implemented using Figure 5 and Figure 6 semiconductor package 5. In addition to Figure 5 and Figure 6 The semiconductor package 5 also includes a detailed configuration of the semiconductor chip 20 and the redistribution structure 27. Fig.15 and Fig.16 The semiconductor package 220 may be Figure 5 and Figure 6 The semiconductor package 5 is the same.

[0129] exist Fig.15 and Fig.16 In, with Figure 5 , Figure 6 and Figures 9 to 12 The same or similar reference numerals in the figure may represent the same or similar components. Fig.15 and Fig.16 For the sake of convenience, the following are briefly given or omitted. Figure 5 , Figure 6 and Figures 9 to 12 The description given is the same or similar to the description.

[0130] like Fig.15 As shown, in the cross-sectional view, the semiconductor package 220 may include a chip-level unit LE1-1, an intermediate-level unit LE2-1, and a solder ball unit LE3-1. The chip-level unit LE1-1 may include a semiconductor chip 20. The semiconductor chip 20 may include a passivation layer 14 and a chip pad 15 formed on a chip circuit layer 12 of a semiconductor substrate 10.

[0131] The intermediate level unit LE2-1 may include a redistribution structure 27, a stud layer 28-2, a barrier layer 32-1, and a plurality of protection layers 34. A solder ball unit LE3-1 including a solder ball 36 may be on the intermediate level unit LE2-1. The intermediate level unit LE2-1 is described in detail.

[0132] The intermediate level unit LE2-1 may include a plurality of protective layers 34-1 formed on the passivation layer 14 and the chip pad 15. The first protective layer 22 may be formed on the passivation layer 14 and the chip pad 15. A redistribution structure 27 connected to the chip pad 15 may be formed on the first protective layer 22. The redistribution structure 27 may include a redistribution layer 25 extending from the chip pad 15 in a specific direction (e.g., in the X direction (e.g., horizontal direction)), and a wiring pad layer 26 at one end of the redistribution layer 25.

[0133] The redistribution structure 27 may be separated into a redistribution layer region RD1 in which the redistribution layer 25 is arranged and a redistribution pad region RD2 in which the redistribution pad layer 26 is formed. Fig.15 and Fig.16 shown.

[0134] The redistribution pad region RD2 may have a width (or diameter) W5 in the Y-axis direction and a width (or diameter) W1 in the X-axis direction. In other words, the redistribution pad layer 26 may have a width (or diameter) W1 in the X-axis direction. The width (or length) W6 of the redistribution layer region RD1 in the Y-axis direction may be smaller than the width (or diameter) W5 of the redistribution pad region RD2 in the Y-axis direction.

[0135] The intermediate level unit LE2-1 may include a second protective layer 24-1 including a plurality of pad exposure holes H1c and H1d exposing the wiring pad layer 26 on the first protective layer 22. The pad exposure holes H1c and H1d may be separated from each other.

[0136] The pad exposure holes H1c and H1d may have widths (or diameters) W2cH and W2dH, respectively. The widths (or diameters) W2cH and W2dH of the pad exposure holes H1c and H1d may be respectively Figure 3 The widths W2aH and W2cH of the pad exposure holes H1a and H1b in the embodiment are different. The widths (or diameters) W2cH and W2dH of the pad exposure holes H1c and H1d may be larger than Figure 3 The pad exposure holes H1a and H1b have widths W2aH and W2cH.

[0137] The intermediate level unit LE2-1 may include a post layer 28-2 formed in the pad exposing holes H1c and H1d on the wiring pad layer 26. Fig.15 As shown, the post layer 28 - 2 may include sub-post layers 28 c and 28 d formed in the pad exposing holes H1 c and H1 d , respectively.

[0138] The terminal layer 28-2 may include a plurality of sub-terminal layers 28c and 28d arranged in a circular shape (eg, a circular pattern), such as Fig.16 As shown. In a plan view, each of the sub-post layers 28c and 28d may have a single circular structure. Each of the sub-post layers 28c and 28d may be a circular post. In a plan view, the post layer 28-2 may be within the outer diameter of the wiring pad layer 26.

[0139] Sub-post layer 28c may have a width (or diameter) W2c. Sub-post layer 28d may have a width (or diameter) W2d. Post layer 28-2 may have an outer width (or outer diameter) W2. The outer width (or outer diameter) W2 of post layer 28-2 may be smaller than the width (or diameter) W1 of wiring pad layer 26.

[0140] The intermediate level unit LE2-1 may include a third protective layer 30, and the third protective layer 30 includes a terminal post exposure hole H2-2 that exposes the terminal post layer 28-2 in the second protective layer 24-1. The terminal post exposure hole H2-2 may also expose the second protective layer 24-1, and may gradually become thinner in the direction toward the terminal post layer 28-2 and the second protective layer 24-1. The terminal post exposure hole H2-2 may have a width (or diameter) W4H-2.

[0141] The width (or diameter) W4H-2 of the terminal post exposure hole H2-2 may be smaller than the outer width (or outer diameter) W2 of the terminal post layer 28-2. The lower width (or lower diameter) W4H-2 of the terminal post exposure hole H2-2 may be smaller than the upper width (or upper diameter) W4H′-2 of the terminal post exposure hole H2-2. Fig.16 As shown, the post layer 28 - 2 may include a plurality of sub-post layers 28 c and 28 d arranged in a circular shape along the edge of the post exposing hole H2 - 2 .

[0142] The intermediate level unit LE2-1 may include a barrier layer 32-1 formed in the terminal post exposure hole H2-2 on the terminal post layer 28-2. The barrier layer 32-1 may also contact the second protective layer 24-1 and may be recessed into the terminal post layer 28-2 and the second protective layer 24-1. The barrier layer 32-1 may have a width (or diameter) W4-2 at a position where it intersects with the interface, where the third protective layer 30 intersects with the second protective layer 24-1 at the interface. The lower width (or lower diameter) W4-2 of the barrier layer 32-1 (e.g., at a position where the barrier layer 32-1 intersects with the interface, where the third protective layer 30 intersects with the second protective layer 24-1 at the interface) may be less than the upper width (or upper diameter) W3 of the barrier layer 32-1 (e.g., at a position where the barrier layer 32-1 intersects with the surface of the third protective layer 30 facing the solder ball 36).

[0143] like Fig.15 As shown, in the intermediate level unit LE2-1, the outer width (or outer diameter) W2 of the terminal layer 28-2 can be the same as the width (or diameter) W3 (e.g., the outermost width) of the barrier layer 32-1. In addition, the thickness T1 of the terminal layer 28-2 can be less than the thickness T2 of the solder ball 36.

[0144] As described above, the semiconductor package 220 according to the embodiment of the inventive concept configured as described above can improve its reliability by operating as follows: when the semiconductor chip 20 is physically or electrically connected to the circuit substrate 150 (refer to Fig. 9 ), reducing the stress applied to the vicinity of the edges at both ends of the redistribution pad layer 26 constituting the semiconductor chip 20 (eg Fig.15 38 in the figure) or stress applied to the redistribution layer 25 (eg, mechanical shock stress or thermal shock stress).

[0145] Fig.17 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept, and Fig.18 yes Fig.17 Figure 2. Planar layout of the redistribution structure and terminal layer of the semiconductor package.

[0146] Fig.17 and Fig.18 The semiconductor package 230 can be applied to Fig. 9 300 semiconductor packaging products. Fig.17 and Fig.18 The semiconductor package 230 may be implemented using Figure 7 and Figure 8 Semiconductor package 7. In addition to Figure 7 and Figure 8 The semiconductor package 7 also includes a semiconductor chip 20 and a redistribution structure 27 in detail. Fig.17 and Fig.18 The semiconductor package 230 may be Figure 7 and Figure 8 The semiconductor package 7 is the same.

[0147] exist Fig.17 and Fig.18 In, with Figure 7 , Figure 8 and Figures 9 to 12 The same or similar reference numerals in the figure may represent the same or similar components. Fig.17 and Fig.18 For the sake of convenience, the following are briefly given or omitted. Figure 7 , Figure 8 and Figures 9 to 12 The description given is the same or similar to the description.

[0148] like Fig.17As shown, in the cross-sectional view, the semiconductor package 230 may include a chip-level unit LE1-1, an intermediate-level unit LE2-1, and a solder ball unit LE3-1. The chip-level unit LE1-1 may include a semiconductor chip 20. The semiconductor chip 20 may include a passivation layer 14 and a chip pad 15 formed on a chip circuit layer 12 of a semiconductor substrate 10.

[0149] The intermediate level unit LE2-1 may include a redistribution structure 27, a stud layer 28-3, a barrier layer 32, and a plurality of protection layers 34-2. A solder ball unit LE3-1 including a solder ball 36 may be on the intermediate level unit LE2-1. The intermediate level unit LE2-1 is described in detail.

[0150] The intermediate level unit LE2-1 may include a plurality of protective layers 34-2 formed on the passivation layer 14 and the chip pad 15. The first protective layer 22 may be formed on the passivation layer 14 and the chip pad 15. A redistribution structure 27 connected to the chip pad 15 may be formed on the first protective layer 22. The redistribution structure 27 may include a redistribution layer 25 extending from the chip pad 15 in an arbitrary direction (e.g., in the X direction (i.e., horizontal direction)), and a redistribution pad layer 26 at one end of the redistribution layer 25.

[0151] The redistribution structure 27 may be separated into a redistribution layer region RD1 in which the redistribution layer 25 is arranged and a redistribution pad region RD2 in which the redistribution pad layer 26 is formed. Fig.17 and Fig.18 shown.

[0152] The redistribution pad region RD2 may have a width (or diameter) W5 in the Y-axis direction and a width (or diameter) W1 in the X-axis direction. In other words, the redistribution pad layer 26 may have a width (or diameter) W1 in the X-axis direction. The width (or length) W6 of the redistribution layer region RD1 in the Y-axis direction may be smaller than the width (or diameter) W5 of the redistribution pad region RD2 in the Y-axis direction.

[0153] The intermediate level unit LE2-1 may include a second protective layer 24-2 including a pad exposure hole H1e exposing the redistribution pad layer 26 on the first protective layer 22. The pad exposure hole H1e may have a width (or diameter) W2H'. The lower width (or diameter) W2H' of the pad exposure hole H1e may be greater than the upper width (or diameter) W2H of the pad exposure hole H1e.

[0154] The intermediate level unit LE2-1 may include a post layer 28-3 formed in the pad exposing hole H1e on the wiring pad layer 26. Fig.18 As shown, in a plan view, the terminal layer 28-3 may be circular. Fig.18 As shown, in a plan view, the terminal layer 28-3 may be inside the wiring pad layer 26. Fig.18 As shown, the terminal post layer 28 - 3 may have vertical circular posts.

[0155] The terminal post layer 28-3 may have a lower width (or diameter) W2f and an upper width (or diameter) W2e. The lower width (or diameter) W2f of the terminal post layer 28-3 may be greater than the upper width (or diameter) W2e of the terminal post layer 28-3. In other words, the terminal post layer 28-3 may be a single structure having an upper width (or diameter) W2e and a lower width (or diameter) W2f that are different from each other.

[0156] The width (or diameter) W2e and W2f of the terminal post layer 28-3 may be smaller than the width (or diameter) W1 of the wiring pad layer 26. The upper surface 28f of the terminal post layer 28-3 may be a flat surface. The upper surface 28f of the terminal post layer 28-3 may be coplanar with the upper surface of the second protective layer 24-2.

[0157] The intermediate level unit LE2-1 may include a third protective layer 30 including a stud exposure hole H2-3 exposing the stud layer 28-3 in the second protective layer 24-2. The stud exposure hole H2-3 may have a width (or diameter) W4H.

[0158] The width (or diameter) W4H of the stud exposure hole H2-3 may be smaller than the widths (or diameters) W2H and W2H' of the pad exposure hole H1e. The lower width (or lower diameter) W4H of the stud exposure hole H2-3 may be smaller than the upper width (or upper diameter) W4H' of the stud exposure hole H2-3.

[0159] The intermediate level unit LE2-1 may include a barrier layer 32 formed in the terminal post exposure hole H2-3 on the terminal post layer 28-3. The barrier layer 32 may have a width (or diameter) W4, for example, at a position where it intersects with an interface where the third protective layer 30 intersects with the second protective layer 24-2. The lower width (or lower diameter) W4 of the barrier layer 32 (for example, at a position where the barrier layer 32 intersects with a surface of the third protective layer 30 facing the solder ball 36) may be smaller than the upper width (or upper diameter) W3 of the barrier layer 32.

[0160] like Fig.17 As shown, in the intermediate level unit LE2-1, the width (or diameter) W2e and W2f of the terminal layer 28-3 may be smaller than the width (or diameter) W3 of the barrier layer 32. In addition, the thickness T1 of the terminal layer 28-3 may be smaller than the thickness T2 of the solder ball 36 (e.g., the maximum thickness in the Z direction).

[0161] As described above, the semiconductor package 230 according to the embodiment of the inventive concept configured as described above can improve its reliability by operating as follows: when the semiconductor chip 20 is physically or electrically connected to the circuit substrate 150 (refer to Fig. 9 ), reducing the stress applied to the vicinity of the edges at both ends of the redistribution pad layer 26 constituting the semiconductor chip 20 (eg Fig.17 38 in the figure) or stress applied to the redistribution layer 25 (eg, mechanical shock stress or thermal shock stress).

[0162] Fig.19 300 is a cross-sectional view of a semiconductor package product including a semiconductor package according to an embodiment of the inventive concept. The semiconductor package product 300 may be, for example, a semiconductor package, or may be a memory module. For example, the semiconductor package product 300 may be a memory module (e.g., a single in-line memory module (SIMM)), or may be part of a dual in-line memory module (DIMM).

[0163] In addition to the upper semiconductor package 200U and the lower semiconductor package 200L being arranged on both sides of the circuit substrate, the semiconductor package product 400 may be Fig. 9 Each of the upper semiconductor package 200U and the lower semiconductor package 200L may correspond to Fig. 9 A semiconductor package 200 is provided.

[0164] As the semiconductor package 200, each of the upper semiconductor package 200U and the lower semiconductor package 200L may adopt Figure 1 Semiconductor packaging 1. Fig.19 In, with Fig. 9 The same or similar reference numerals as those in the drawings may represent the same or similar components.

[0165] The semiconductor package product 400 may include a circuit substrate 150 and upper and lower semiconductor packages 200U and 200L. The circuit substrate 150 may include a printed circuit board. Upper and lower connection pads 152U and 152L may be on the upper and lower surfaces of the circuit substrate 150, respectively.

[0166] The solder balls 36 of the upper semiconductor package 200U may be connected to the upper connection pads 152U. The solder balls 36 of the lower semiconductor package 200L may be connected to the lower connection pads 152L. The solder balls 36 of the upper semiconductor package 200U and the lower semiconductor package 200L may be mechanically and electrically connected to each other via the circuit substrate 150 and the upper connection pads 152U and the lower connection pads 152L. The semiconductor package product 400 as described above may include the upper semiconductor package 200U and the lower semiconductor package 200L on the upper surface and the lower surface of the circuit substrate 150, respectively, and may increase capacity (e.g., storage capacity).

[0167] Fig. 20 is a cross-sectional view of a semiconductor package product according to an embodiment of the inventive concept.

[0168] In addition to Fig. 9 Compared with the semiconductor package product 300, in addition to forming a mold layer 160 on the circuit substrate 150, the semiconductor package product 500 can be Fig. 9 The semiconductor package product 300 is the same as the semiconductor package product 300. The semiconductor package 200 may correspond to Fig. 9 A semiconductor package 200 is provided. Fig. 20 The illustrated semiconductor package 200 may include a fan-in wafer level package.

[0169] The semiconductor package 200 may be implemented using Figure 1 The semiconductor package product 500 may be, for example, a semiconductor package, and in one embodiment, a stacked package device. Fig. 20 In, with Fig. 9 The same or similar reference numerals as those in the drawings may represent the same or similar components.

[0170] The semiconductor package product 500 may include a circuit substrate 150 and a molded semiconductor package 200. The connection pads 152 may be on the circuit substrate 150. The connection terminals 162 may be below the circuit substrate 150. The solder balls 36 of the semiconductor package 200 may be mechanically and electrically connected to the connection pads 152. The semiconductor package 200 on the circuit substrate 150 may be molded by a molding layer 160. The molding layer 160 may include a resin layer, such as an epoxy resin. The semiconductor package product 500 as described above may improve its reliability by molding the semiconductor package 200 using the molding layer 160.

[0171] Fig.21 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0172] In addition to Fig. 9Compared with the semiconductor package 200 of FIG. 1 , the semiconductor package 550 further includes a mold layer 160 a and solder balls 36 are formed under the mold layer 160 a. Fig. 9 The semiconductor package 550 may be similar to the semiconductor package 200. Fig. 9 The semiconductor package 200 may be a semiconductor package 200 of the embodiment of the present invention. Figure 1 A semiconductor package 1. Fig.21 The semiconductor package 200 shown may include a fan-in wafer level package. Fig.21 In, with Fig. 9 The same or similar reference numerals as those in the drawings may represent the same or similar components.

[0173] The semiconductor package 550 may include a mold layer 160a on the opposite outer sides of the semiconductor chip 20. The semiconductor package 550 may further extend the redistribution structure 27 including the redistribution layer 25 and the redistribution pad layer 26 under the mold layer 160a.

[0174] In other words, the semiconductor package 550 can extend the redistribution pad layer 26 further below the mold layer 160a. The mold layer 160a may include a resin layer, such as an epoxy resin. The solder balls 36 may be below the mold layer 160a. The solder balls 36 of the semiconductor package 550 may be additionally connected to the circuit substrate 150. The semiconductor package 550 as described above can increase the degree of design freedom by extending the redistribution layer 25 below the mold layer 160a.

[0175] Fig. 22 is a cross-sectional view of a semiconductor package product according to an embodiment of the inventive concept.

[0176] In addition to Fig. 20 Compared with the semiconductor package 500, the semiconductor package 600 may include semiconductor packages 200A and 200B on the circuit substrate 150. Fig. 20 The same as the semiconductor package 500. Note that Figures 19 to 22 The dashed lines in the figure depict interruptions in the diagram and do not indicate individual devices. However, Fig. 22 An example of two separate semiconductor packages 200A and 200B is shown.

[0177] Each of the semiconductor packages 200A and 200B may correspond to Fig. 9 Each of the semiconductor packages 200A and 200B (two semiconductor packages are shown, but the semiconductor package 600 may include more than two semiconductor packages) may adopt Figure 1 The semiconductor package 1 or the semiconductor package in other figures discussed above. Fig. 22 In, with Fig. 9 The same or similar reference numerals as those in the drawings may represent the same or similar components.

[0178] The semiconductor package 600 may include semiconductor packages 200A and 200B molded on a circuit substrate 150. The connection pads 152 may be on the circuit substrate 150. The connection terminals 162 may be below the circuit substrate 150. The solder balls 36 of the semiconductor packages 200A and 200B may be mechanically and electrically connected to the connection pads 152.

[0179] The semiconductor packages 200A and 200B on the circuit substrate 150 may be molded by the mold layer 160. The mold layer 160 may include a resin layer such as epoxy resin. The semiconductor package 600 as described above may increase capacity by mounting two different types of semiconductor packages 200A and 200B on the circuit substrate 150.

[0180] Fig.23 is a schematic diagram of a configuration of a card using a semiconductor package according to aspects of the inventive concept.

[0181] The semiconductor package or in some cases the semiconductor package product as described above may be applied to the card 700. The card 700 may include a multimedia card (MMC), a secure digital (SD) card, etc. The card 700 may include a controller 710 and a memory 720.

[0182] The memory 720 may include a flash memory, a phase change random access memory (PRAM), or other types of nonvolatile memory. The controller 710 may send a control signal to the memory 720, and data may be exchanged between the controller 710 and the memory 720.

[0183] One or both of the controller 710 and the memory 720 constituting the card 700 may adopt the semiconductor package or semiconductor package product of the inventive concept as described above. In this way, the reliability of the card 700 may be improved.

[0184] Fig.24 is a schematic diagram of a configuration of an electronic system using a semiconductor package according to aspects of the inventive concept.

[0185] The electronic system 800 according to aspects of the inventive concept may be a computer, a mobile phone, an MPEG audio layer 3 (MP3) player, a navigator, etc. The electronic system 800 may include a controller 810, an input / output device 820, a memory 830, and an interface 840. Control signals or data may be exchanged between the controller 810 and the input / output device 820, the memory 830, and the interface 840 by using a communication channel 850.

[0186] According to aspects of the inventive concept, the semiconductor package or semiconductor package product described above may be employed in the controller 810 and the memory 830 in the electronic system 800. In this case, the electronic system 800 according to aspects of the inventive concept may implement various functions and improve its reliability.

[0187] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: The chip-level part includes semiconductor chips; an intermediate-level portion, on the chip-level portion; as well as a solder ball portion on the intermediate stage portion, wherein the solder ball portion is configured to be connected to a circuit substrate, Wherein, the intermediate stage part comprises: a wiring pad layer extending in a horizontal direction on a first protection layer, the first protection layer being an inner protection layer among a plurality of protection layers and being directly adjacent to the chip-level portion; a second protective layer on the first protective layer and including a pad exposing hole exposing the wiring pad layer, the second protective layer being an intermediate protective layer among the plurality of protective layers; A terminal layer, located in the pad exposure hole on the wiring pad layer; a third protective layer on the second protective layer and including a terminal post exposure hole, the terminal post exposure hole exposing the terminal post layer, the third protective layer corresponding to an outer protective layer among the plurality of protective layers, wherein a width or a diameter of the terminal post exposure hole is smaller than a width or a diameter of the pad exposure hole; and a barrier layer, on the terminal layer, in the terminal exposure hole, The solder ball portion includes solder balls on the barrier layer.

2. The semiconductor package according to claim 1, wherein The width or diameter of the terminal layer is smaller than the width or diameter of the barrier layer.

3. The semiconductor package according to claim 1, wherein: The first width or the first diameter of the terminal exposure hole at the terminal layer is smaller than the second width or the second diameter of the terminal exposure hole at a position adjacent to the solder ball, and the first width or the first diameter of the barrier layer at the first surface of the barrier layer is smaller than the second width or the second diameter of the barrier layer at the second surface of the barrier layer opposite to the first surface.

4. The semiconductor package according to claim 1, wherein: The elastic modulus of the second protective layer is greater than the elastic modulus of the third protective layer.

5. The semiconductor package according to claim 1, wherein In a plan view, the terminal layer has a single continuous structure in a circular or ring shape.

6. The semiconductor package according to claim 1, wherein The post layer has a single continuous structure in which a width of a first surface of the post layer is the same as a width of a second surface of the post layer opposite to the first surface.

7. The semiconductor package according to claim 1, wherein: The post layer has a single continuous structure in which a width of a first surface of the post layer is greater than a width of a second surface of the post layer opposite to the first surface.

8. The semiconductor package according to claim 1, wherein The post layer includes a plurality of sub-post layers having a circular shape in a plan view and arranged along edges of the post exposing holes.

9. The semiconductor package according to claim 1, wherein: A surface of the terminal layer in contact with the barrier layer is coplanar with a surface of the second protective layer.

10. A semiconductor package, comprising: Semiconductor chips; a first protective layer on the semiconductor chip; A redistribution pad layer extending in a horizontal direction on the first protection layer; a second protection layer on the redistribution pad layer and comprising a pad exposure hole, wherein the pad exposure hole exposes the redistribution pad layer; A terminal layer, located in the pad exposure hole on the redistribution pad layer; a third protective layer on the terminal post layer and comprising a terminal post exposure hole, the terminal post exposure hole exposing the terminal post layer, wherein the terminal post exposure hole is smaller than the pad exposure hole; A barrier layer, on the terminal layer, in the terminal exposure hole; as well as a solder layer, on the barrier layer, Wherein, the elastic modulus of the second protective layer is greater than the elastic modulus of the third protective layer.

11. The semiconductor package according to claim 10, wherein: The barrier layer extends outward from the terminal post exposing hole in the third protective layer, and a maximum width or diameter of the terminal post layer is equal to or smaller than a minimum width or diameter of the barrier layer on the third protective layer.

12. The semiconductor package according to claim 10, wherein: The second protective layer includes a material having an elastic modulus greater than or equal to an elastic modulus of a material of the first protective layer.

13. The semiconductor package according to claim 10, wherein: The post layer has a circular shape in a plan view, and the post layer has a single post in which widths or diameters of an upper portion and a lower portion are the same as each other.

14. The semiconductor package according to claim 10, wherein: The post layer includes a plurality of sub-post layers, and in a plan view, the plurality of sub-post layers are arranged in a circular shape along edges of the post exposing holes.

15. The semiconductor package according to claim 10, wherein The post layer has a circular shape in a plan view, and an upper surface of the post layer is a curved surface.

16. A semiconductor package, comprising: A semiconductor chip, comprising a chip circuit layer on a semiconductor substrate, and a chip pad connected to the chip circuit layer; A first protective layer, on the chip circuit layer and the chip pad; a redistribution structure, comprising a redistribution layer, the redistribution layer comprising a first portion penetrating the first protection layer and connected to the chip pad and a second portion at one end of the redistribution layer, the first portion extending from the chip pad in a horizontal direction on the first protection layer; a second protection layer on the redistribution structure and comprising a pad exposure hole, wherein the pad exposure hole exposes the second portion of the redistribution layer; A terminal layer, located in the pad exposure hole on the redistribution structure; a third protective layer on the terminal post layer and comprising a terminal post exposure hole, the terminal post exposure hole exposing the terminal post layer, wherein the terminal post exposure hole is smaller than the pad exposure hole; A barrier layer, on the terminal layer, in the terminal exposure hole; as well as a solder layer, on the barrier layer, The maximum width or diameter of the terminal layer is equal to or smaller than the minimum width or diameter of the barrier layer, and the elastic modulus of the second protective layer is greater than the elastic modulus of the third protective layer.

17. The semiconductor package according to claim 16, wherein: A first surface of the post layer contacting the barrier layer is a flat surface, and a thickness of the post layer is smaller than a maximum thickness of the solder layer.

18. The semiconductor package according to claim 17, wherein: In a plan view, the terminal post layer has a circular shape, and the terminal post layer has a single post in which the width or diameter of the lower portion corresponding to the second surface is greater than the width or diameter of the upper portion corresponding to the first surface, and the second surface is opposite to the first surface.

19. The semiconductor package according to claim 16, wherein: In a plan view, the terminal layer has a single continuous structure in a circular or ring shape.

20. The semiconductor package according to claim 16, wherein The post layer includes a plurality of sub-post layers, and the plurality of sub-post layers are arranged in a circular shape along edges of the post exposing holes.

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